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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 982
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T793 /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1976390416 Jul 29 07:33:06 PM PDT 24 Jul 29 07:33:07 PM PDT 24 16662814 ps
T794 /workspace/coverage/default/23.clkmgr_clk_status.3664791882 Jul 29 07:33:08 PM PDT 24 Jul 29 07:33:09 PM PDT 24 16592571 ps
T795 /workspace/coverage/default/44.clkmgr_regwen.295519743 Jul 29 07:34:08 PM PDT 24 Jul 29 07:34:11 PM PDT 24 820292380 ps
T796 /workspace/coverage/default/10.clkmgr_smoke.3540634886 Jul 29 07:32:45 PM PDT 24 Jul 29 07:32:46 PM PDT 24 20001276 ps
T797 /workspace/coverage/default/18.clkmgr_peri.321406907 Jul 29 07:33:02 PM PDT 24 Jul 29 07:33:03 PM PDT 24 18049964 ps
T798 /workspace/coverage/default/41.clkmgr_extclk.2191979223 Jul 29 07:33:52 PM PDT 24 Jul 29 07:33:53 PM PDT 24 26654269 ps
T799 /workspace/coverage/default/29.clkmgr_smoke.1081030297 Jul 29 07:33:29 PM PDT 24 Jul 29 07:33:31 PM PDT 24 58766446 ps
T800 /workspace/coverage/default/24.clkmgr_alert_test.3535965045 Jul 29 07:33:07 PM PDT 24 Jul 29 07:33:18 PM PDT 24 14026027 ps
T801 /workspace/coverage/default/24.clkmgr_extclk.4257491480 Jul 29 07:33:15 PM PDT 24 Jul 29 07:33:16 PM PDT 24 46550154 ps
T802 /workspace/coverage/default/25.clkmgr_smoke.1121425526 Jul 29 07:33:17 PM PDT 24 Jul 29 07:33:18 PM PDT 24 70195082 ps
T803 /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2832161494 Jul 29 07:33:45 PM PDT 24 Jul 29 07:33:46 PM PDT 24 24041916 ps
T804 /workspace/coverage/default/5.clkmgr_frequency_timeout.512481568 Jul 29 07:32:25 PM PDT 24 Jul 29 07:32:27 PM PDT 24 264412456 ps
T805 /workspace/coverage/default/32.clkmgr_clk_status.1808193730 Jul 29 07:33:42 PM PDT 24 Jul 29 07:33:43 PM PDT 24 54159899 ps
T806 /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3456844453 Jul 29 07:33:20 PM PDT 24 Jul 29 07:33:22 PM PDT 24 15000015 ps
T807 /workspace/coverage/default/8.clkmgr_frequency.2529941351 Jul 29 07:32:29 PM PDT 24 Jul 29 07:32:40 PM PDT 24 2132008766 ps
T808 /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3594416969 Jul 29 07:32:33 PM PDT 24 Jul 29 07:32:34 PM PDT 24 20235967 ps
T809 /workspace/coverage/default/4.clkmgr_extclk.3617826108 Jul 29 07:32:30 PM PDT 24 Jul 29 07:32:31 PM PDT 24 64167063 ps
T810 /workspace/coverage/default/39.clkmgr_alert_test.1616777568 Jul 29 07:34:06 PM PDT 24 Jul 29 07:34:07 PM PDT 24 18622519 ps
T811 /workspace/coverage/default/0.clkmgr_alert_test.863236479 Jul 29 07:32:23 PM PDT 24 Jul 29 07:32:24 PM PDT 24 23801391 ps
T812 /workspace/coverage/default/30.clkmgr_stress_all.3025771401 Jul 29 07:33:27 PM PDT 24 Jul 29 07:33:47 PM PDT 24 4941817893 ps
T813 /workspace/coverage/default/34.clkmgr_regwen.3850747476 Jul 29 07:33:34 PM PDT 24 Jul 29 07:33:40 PM PDT 24 1455203904 ps
T814 /workspace/coverage/default/1.clkmgr_alert_test.657723456 Jul 29 07:32:19 PM PDT 24 Jul 29 07:32:20 PM PDT 24 59643961 ps
T815 /workspace/coverage/default/15.clkmgr_peri.2515727974 Jul 29 07:32:47 PM PDT 24 Jul 29 07:32:47 PM PDT 24 29266670 ps
T816 /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3879066148 Jul 29 07:32:53 PM PDT 24 Jul 29 07:32:54 PM PDT 24 32879164 ps
T817 /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.316719514 Jul 29 07:34:35 PM PDT 24 Jul 29 07:34:36 PM PDT 24 20976990 ps
T818 /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.3079462587 Jul 29 07:33:04 PM PDT 24 Jul 29 07:33:05 PM PDT 24 25967154 ps
T819 /workspace/coverage/default/15.clkmgr_trans.639805333 Jul 29 07:32:53 PM PDT 24 Jul 29 07:32:54 PM PDT 24 51984061 ps
T111 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4191410346 Jul 29 07:06:07 PM PDT 24 Jul 29 07:06:09 PM PDT 24 28737888 ps
T112 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.504675059 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:20 PM PDT 24 46490601 ps
T820 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3078355565 Jul 29 07:03:04 PM PDT 24 Jul 29 07:03:05 PM PDT 24 11766857 ps
T58 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2455624167 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:28 PM PDT 24 1102648084 ps
T83 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.537455890 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:10 PM PDT 24 574300637 ps
T144 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1819484413 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:24 PM PDT 24 47065864 ps
T106 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2190111701 Jul 29 07:06:13 PM PDT 24 Jul 29 07:06:15 PM PDT 24 115181542 ps
T821 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3248568839 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:17 PM PDT 24 21079444 ps
T822 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1232093124 Jul 29 07:06:31 PM PDT 24 Jul 29 07:06:31 PM PDT 24 25569551 ps
T823 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2238988502 Jul 29 07:03:05 PM PDT 24 Jul 29 07:03:06 PM PDT 24 30874602 ps
T84 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3122393255 Jul 29 07:05:56 PM PDT 24 Jul 29 07:05:57 PM PDT 24 86841118 ps
T59 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2178774990 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:11 PM PDT 24 441762016 ps
T60 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.4150531969 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:07 PM PDT 24 86264346 ps
T61 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3245378073 Jul 29 07:05:50 PM PDT 24 Jul 29 07:05:56 PM PDT 24 1728894333 ps
T824 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2055002450 Jul 29 07:05:59 PM PDT 24 Jul 29 07:06:00 PM PDT 24 143795658 ps
T62 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3580476841 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:01 PM PDT 24 135739422 ps
T85 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1340503216 Jul 29 07:06:07 PM PDT 24 Jul 29 07:06:09 PM PDT 24 262328123 ps
T825 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2381345601 Jul 29 07:06:32 PM PDT 24 Jul 29 07:06:33 PM PDT 24 14368654 ps
T826 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1954577182 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 155161705 ps
T63 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.858143586 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:19 PM PDT 24 454291718 ps
T86 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1530175345 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:17 PM PDT 24 32185044 ps
T827 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.382281658 Jul 29 07:06:09 PM PDT 24 Jul 29 07:06:10 PM PDT 24 48324998 ps
T828 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1789012709 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:24 PM PDT 24 11854277 ps
T107 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.710713407 Jul 29 07:06:01 PM PDT 24 Jul 29 07:06:03 PM PDT 24 156227137 ps
T829 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1740423653 Jul 29 07:05:49 PM PDT 24 Jul 29 07:05:56 PM PDT 24 482250739 ps
T830 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2673708853 Jul 29 07:06:31 PM PDT 24 Jul 29 07:06:31 PM PDT 24 26946088 ps
T831 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.7596747 Jul 29 07:03:07 PM PDT 24 Jul 29 07:03:09 PM PDT 24 234859744 ps
T832 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.197383715 Jul 29 07:06:28 PM PDT 24 Jul 29 07:06:29 PM PDT 24 16748199 ps
T87 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.345779274 Jul 29 07:06:26 PM PDT 24 Jul 29 07:06:28 PM PDT 24 67136028 ps
T64 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.597700335 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:15 PM PDT 24 55600583 ps
T833 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1820186590 Jul 29 07:03:14 PM PDT 24 Jul 29 07:03:21 PM PDT 24 278609399 ps
T834 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3890083846 Jul 29 07:03:05 PM PDT 24 Jul 29 07:03:06 PM PDT 24 19894003 ps
T65 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1833203136 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:32 PM PDT 24 265192995 ps
T131 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2191189702 Jul 29 07:03:01 PM PDT 24 Jul 29 07:03:03 PM PDT 24 288533027 ps
T108 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.4142748213 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:26 PM PDT 24 103387203 ps
T835 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1692954083 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:24 PM PDT 24 13161894 ps
T132 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.696751439 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:12 PM PDT 24 771378549 ps
T836 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1892063363 Jul 29 07:05:59 PM PDT 24 Jul 29 07:06:00 PM PDT 24 39953591 ps
T88 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1908117692 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:19 PM PDT 24 100393265 ps
T837 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3812904161 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:25 PM PDT 24 69253912 ps
T838 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2917635132 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 21467056 ps
T89 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2399961471 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:19 PM PDT 24 130463638 ps
T839 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.756496514 Jul 29 07:03:01 PM PDT 24 Jul 29 07:03:01 PM PDT 24 22692061 ps
T840 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3361312608 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:01 PM PDT 24 83404674 ps
T841 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.824724415 Jul 29 07:03:13 PM PDT 24 Jul 29 07:03:14 PM PDT 24 21843824 ps
T842 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2538053379 Jul 29 07:06:31 PM PDT 24 Jul 29 07:06:32 PM PDT 24 28762329 ps
T843 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1434215361 Jul 29 07:06:26 PM PDT 24 Jul 29 07:06:28 PM PDT 24 97002118 ps
T844 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.997758912 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 45955084 ps
T845 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4048923397 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:20 PM PDT 24 103255501 ps
T846 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4249667920 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 78575836 ps
T847 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3960574988 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:24 PM PDT 24 18914173 ps
T848 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2008257464 Jul 29 07:03:15 PM PDT 24 Jul 29 07:03:15 PM PDT 24 12859775 ps
T849 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.599024850 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:14 PM PDT 24 34872630 ps
T850 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3949688739 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:01 PM PDT 24 627766916 ps
T851 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2554777893 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:19 PM PDT 24 686689386 ps
T852 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4013013730 Jul 29 07:03:01 PM PDT 24 Jul 29 07:03:02 PM PDT 24 44469134 ps
T853 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2123418638 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:23 PM PDT 24 19812575 ps
T854 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3586167443 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 32989587 ps
T855 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3325972123 Jul 29 07:05:48 PM PDT 24 Jul 29 07:05:50 PM PDT 24 83313422 ps
T856 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1419700800 Jul 29 07:03:06 PM PDT 24 Jul 29 07:03:08 PM PDT 24 98443435 ps
T857 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3955016649 Jul 29 07:06:05 PM PDT 24 Jul 29 07:06:06 PM PDT 24 46476703 ps
T109 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1567548578 Jul 29 07:03:12 PM PDT 24 Jul 29 07:03:15 PM PDT 24 124464215 ps
T858 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2672715010 Jul 29 07:03:13 PM PDT 24 Jul 29 07:03:18 PM PDT 24 504408752 ps
T133 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1425395860 Jul 29 07:05:59 PM PDT 24 Jul 29 07:06:02 PM PDT 24 128787556 ps
T859 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.715963673 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:31 PM PDT 24 15177456 ps
T860 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3871781328 Jul 29 07:06:34 PM PDT 24 Jul 29 07:06:35 PM PDT 24 57047497 ps
T861 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3797654624 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:21 PM PDT 24 278851947 ps
T862 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.981996051 Jul 29 07:03:02 PM PDT 24 Jul 29 07:03:03 PM PDT 24 25735743 ps
T863 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3904935536 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:18 PM PDT 24 30620892 ps
T864 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3676667089 Jul 29 07:05:58 PM PDT 24 Jul 29 07:05:59 PM PDT 24 28149004 ps
T865 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3110038663 Jul 29 07:02:59 PM PDT 24 Jul 29 07:03:00 PM PDT 24 11303329 ps
T866 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.499228883 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:30 PM PDT 24 10857180 ps
T867 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.110294229 Jul 29 07:03:05 PM PDT 24 Jul 29 07:03:07 PM PDT 24 131387823 ps
T868 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3834838759 Jul 29 07:06:01 PM PDT 24 Jul 29 07:06:02 PM PDT 24 19074894 ps
T143 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1077712359 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 439498694 ps
T869 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3373803442 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:07 PM PDT 24 685610049 ps
T136 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3454383447 Jul 29 07:03:14 PM PDT 24 Jul 29 07:03:16 PM PDT 24 159709975 ps
T870 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1009576843 Jul 29 07:05:57 PM PDT 24 Jul 29 07:05:58 PM PDT 24 42895286 ps
T871 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3458167565 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:19 PM PDT 24 23441850 ps
T872 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1199512269 Jul 29 07:03:13 PM PDT 24 Jul 29 07:03:16 PM PDT 24 475628040 ps
T873 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2188498248 Jul 29 07:03:05 PM PDT 24 Jul 29 07:03:06 PM PDT 24 25108511 ps
T874 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3658522905 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:01 PM PDT 24 76508600 ps
T875 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.378618906 Jul 29 07:06:28 PM PDT 24 Jul 29 07:06:29 PM PDT 24 11268728 ps
T876 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.763414972 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:07 PM PDT 24 18062678 ps
T134 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2104613507 Jul 29 07:06:12 PM PDT 24 Jul 29 07:06:15 PM PDT 24 279197453 ps
T877 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1016053504 Jul 29 07:06:01 PM PDT 24 Jul 29 07:06:03 PM PDT 24 33537498 ps
T878 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3380412577 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:17 PM PDT 24 54784766 ps
T879 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.603651322 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:31 PM PDT 24 84576582 ps
T137 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2365108161 Jul 29 07:03:08 PM PDT 24 Jul 29 07:03:10 PM PDT 24 269271987 ps
T880 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1660242389 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 20747971 ps
T881 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3581179611 Jul 29 07:06:00 PM PDT 24 Jul 29 07:06:02 PM PDT 24 41267079 ps
T882 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1296883939 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:23 PM PDT 24 29834559 ps
T883 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.4153415094 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:23 PM PDT 24 32096683 ps
T884 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3758742731 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 50605325 ps
T885 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3579520688 Jul 29 07:03:04 PM PDT 24 Jul 29 07:03:12 PM PDT 24 263925400 ps
T886 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1834356622 Jul 29 07:05:57 PM PDT 24 Jul 29 07:05:59 PM PDT 24 94896871 ps
T138 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1522621759 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:02 PM PDT 24 336522154 ps
T887 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.4203534612 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:29 PM PDT 24 31735389 ps
T888 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2149824614 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:07 PM PDT 24 12941981 ps
T889 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2727928198 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:18 PM PDT 24 37680051 ps
T142 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1104185554 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:02 PM PDT 24 79585224 ps
T113 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.162012656 Jul 29 07:06:01 PM PDT 24 Jul 29 07:06:08 PM PDT 24 1715546076 ps
T890 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.345493027 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:30 PM PDT 24 16824471 ps
T139 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2403998193 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:16 PM PDT 24 228229221 ps
T891 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1431148971 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:29 PM PDT 24 20220358 ps
T892 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.415095962 Jul 29 07:05:52 PM PDT 24 Jul 29 07:05:53 PM PDT 24 17285580 ps
T893 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3947073573 Jul 29 07:03:14 PM PDT 24 Jul 29 07:03:16 PM PDT 24 65990528 ps
T894 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4052603723 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:19 PM PDT 24 51711056 ps
T114 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2379018594 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 287554113 ps
T895 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.560167449 Jul 29 07:03:14 PM PDT 24 Jul 29 07:03:16 PM PDT 24 131812714 ps
T896 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4013142593 Jul 29 07:06:13 PM PDT 24 Jul 29 07:06:15 PM PDT 24 47201878 ps
T897 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3210413772 Jul 29 07:03:06 PM PDT 24 Jul 29 07:03:08 PM PDT 24 183009097 ps
T898 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.265102962 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:19 PM PDT 24 59556669 ps
T899 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2718158592 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:30 PM PDT 24 13920305 ps
T900 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.4200708567 Jul 29 07:06:15 PM PDT 24 Jul 29 07:06:16 PM PDT 24 26773758 ps
T901 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4020056447 Jul 29 07:05:58 PM PDT 24 Jul 29 07:05:59 PM PDT 24 37874059 ps
T140 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.849831168 Jul 29 07:05:48 PM PDT 24 Jul 29 07:05:50 PM PDT 24 195077184 ps
T902 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3769353554 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:18 PM PDT 24 95037032 ps
T903 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2015531980 Jul 29 07:03:11 PM PDT 24 Jul 29 07:03:13 PM PDT 24 105043094 ps
T904 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3122805685 Jul 29 07:02:59 PM PDT 24 Jul 29 07:03:01 PM PDT 24 127939455 ps
T905 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3236102925 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:03 PM PDT 24 136893147 ps
T906 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.508517496 Jul 29 07:06:28 PM PDT 24 Jul 29 07:06:29 PM PDT 24 15617597 ps
T907 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2604393664 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:08 PM PDT 24 43493981 ps
T115 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3803640889 Jul 29 07:06:07 PM PDT 24 Jul 29 07:06:14 PM PDT 24 1737176716 ps
T908 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2170277443 Jul 29 07:06:04 PM PDT 24 Jul 29 07:06:06 PM PDT 24 229049694 ps
T141 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2475643948 Jul 29 07:03:09 PM PDT 24 Jul 29 07:03:11 PM PDT 24 103239155 ps
T135 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2939704580 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:24 PM PDT 24 108861381 ps
T909 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1098647417 Jul 29 07:03:15 PM PDT 24 Jul 29 07:03:16 PM PDT 24 55659784 ps
T910 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.4144778830 Jul 29 07:06:26 PM PDT 24 Jul 29 07:06:27 PM PDT 24 63339066 ps
T911 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.122980304 Jul 29 07:05:57 PM PDT 24 Jul 29 07:06:01 PM PDT 24 457863134 ps
T912 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1981396946 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:30 PM PDT 24 13749641 ps
T913 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.492250640 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:24 PM PDT 24 25410345 ps
T914 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3858528988 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:23 PM PDT 24 13401523 ps
T915 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3131268215 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:18 PM PDT 24 108303732 ps
T916 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1026531119 Jul 29 07:06:04 PM PDT 24 Jul 29 07:06:06 PM PDT 24 96859323 ps
T917 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3233823722 Jul 29 07:03:02 PM PDT 24 Jul 29 07:03:04 PM PDT 24 77026174 ps
T918 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.505663015 Jul 29 07:06:15 PM PDT 24 Jul 29 07:06:16 PM PDT 24 40799910 ps
T919 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2398353705 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:25 PM PDT 24 149454777 ps
T167 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1731521528 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:21 PM PDT 24 336368771 ps
T920 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.426787839 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:01 PM PDT 24 110512040 ps
T921 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3956140676 Jul 29 07:06:13 PM PDT 24 Jul 29 07:06:13 PM PDT 24 18965191 ps
T922 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3293695949 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:26 PM PDT 24 158342327 ps
T923 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.153870254 Jul 29 07:03:13 PM PDT 24 Jul 29 07:03:14 PM PDT 24 30556277 ps
T924 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4197265937 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:17 PM PDT 24 103295659 ps
T925 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3070253872 Jul 29 07:03:14 PM PDT 24 Jul 29 07:03:17 PM PDT 24 620992706 ps
T926 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2206219929 Jul 29 07:06:09 PM PDT 24 Jul 29 07:06:09 PM PDT 24 12897621 ps
T927 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2243578415 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:26 PM PDT 24 209686676 ps
T928 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2299600576 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:11 PM PDT 24 743592549 ps
T929 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.93012437 Jul 29 07:05:59 PM PDT 24 Jul 29 07:06:00 PM PDT 24 29484092 ps
T930 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3303095512 Jul 29 07:06:05 PM PDT 24 Jul 29 07:06:06 PM PDT 24 17255556 ps
T931 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3444518865 Jul 29 07:05:57 PM PDT 24 Jul 29 07:05:58 PM PDT 24 38516723 ps
T932 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2455289276 Jul 29 07:03:04 PM PDT 24 Jul 29 07:03:09 PM PDT 24 268450681 ps
T933 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1496133387 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:08 PM PDT 24 31167506 ps
T934 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2726627236 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:30 PM PDT 24 19850712 ps
T935 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3390840585 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:08 PM PDT 24 389872253 ps
T936 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3038478946 Jul 29 07:05:58 PM PDT 24 Jul 29 07:05:59 PM PDT 24 14578509 ps
T116 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2385029534 Jul 29 07:06:21 PM PDT 24 Jul 29 07:06:24 PM PDT 24 188932694 ps
T937 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1043472968 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:16 PM PDT 24 137629371 ps
T938 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.728607217 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:03 PM PDT 24 139444601 ps
T939 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3051866825 Jul 29 07:06:05 PM PDT 24 Jul 29 07:06:06 PM PDT 24 73016627 ps
T940 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1369718997 Jul 29 07:05:48 PM PDT 24 Jul 29 07:05:50 PM PDT 24 126571013 ps
T941 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3538458028 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:31 PM PDT 24 25790414 ps
T942 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1750776407 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:18 PM PDT 24 101959465 ps
T943 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2024920816 Jul 29 07:03:05 PM PDT 24 Jul 29 07:03:06 PM PDT 24 114170107 ps
T944 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1419284761 Jul 29 07:06:00 PM PDT 24 Jul 29 07:06:01 PM PDT 24 96667735 ps
T945 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3712477876 Jul 29 07:06:14 PM PDT 24 Jul 29 07:06:15 PM PDT 24 69178636 ps
T946 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.615100335 Jul 29 07:05:59 PM PDT 24 Jul 29 07:06:01 PM PDT 24 126496413 ps
T947 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1460240430 Jul 29 07:05:58 PM PDT 24 Jul 29 07:06:00 PM PDT 24 136419466 ps
T948 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.777985962 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:31 PM PDT 24 23490187 ps
T949 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.426726058 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:10 PM PDT 24 198006213 ps
T950 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2869485823 Jul 29 07:06:28 PM PDT 24 Jul 29 07:06:29 PM PDT 24 18146024 ps
T951 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2106639619 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:18 PM PDT 24 18008794 ps
T952 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2076161764 Jul 29 07:06:00 PM PDT 24 Jul 29 07:06:02 PM PDT 24 95931192 ps
T953 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3097447518 Jul 29 07:06:09 PM PDT 24 Jul 29 07:06:10 PM PDT 24 13497768 ps
T954 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3025974779 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:23 PM PDT 24 59107486 ps
T955 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2986482736 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:19 PM PDT 24 13832705 ps
T956 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2418737785 Jul 29 07:06:12 PM PDT 24 Jul 29 07:06:13 PM PDT 24 16280909 ps
T110 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.4004395470 Jul 29 07:06:18 PM PDT 24 Jul 29 07:06:20 PM PDT 24 229899255 ps
T957 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4033881179 Jul 29 07:06:22 PM PDT 24 Jul 29 07:06:23 PM PDT 24 17522735 ps
T958 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1688308227 Jul 29 07:05:49 PM PDT 24 Jul 29 07:05:51 PM PDT 24 32139411 ps
T959 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3556099705 Jul 29 07:05:58 PM PDT 24 Jul 29 07:05:59 PM PDT 24 46654427 ps
T960 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1974726464 Jul 29 07:06:06 PM PDT 24 Jul 29 07:06:08 PM PDT 24 98488263 ps
T961 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1625308658 Jul 29 07:06:04 PM PDT 24 Jul 29 07:06:04 PM PDT 24 17135775 ps
T962 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.4168085382 Jul 29 07:06:30 PM PDT 24 Jul 29 07:06:31 PM PDT 24 25642409 ps
T963 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1502170000 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 19704622 ps
T964 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.716800866 Jul 29 07:05:48 PM PDT 24 Jul 29 07:05:49 PM PDT 24 19007542 ps
T965 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2217286023 Jul 29 07:05:51 PM PDT 24 Jul 29 07:05:51 PM PDT 24 20592032 ps
T966 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3745914467 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 186625932 ps
T967 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.476089849 Jul 29 07:06:29 PM PDT 24 Jul 29 07:06:30 PM PDT 24 36783727 ps
T968 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3662729685 Jul 29 07:06:12 PM PDT 24 Jul 29 07:06:15 PM PDT 24 236825940 ps
T969 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3395827192 Jul 29 07:03:02 PM PDT 24 Jul 29 07:03:06 PM PDT 24 275829267 ps
T970 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2208492742 Jul 29 07:06:23 PM PDT 24 Jul 29 07:06:25 PM PDT 24 236595044 ps
T971 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2903957284 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:09 PM PDT 24 53997977 ps
T972 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.901365304 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:25 PM PDT 24 34102763 ps
T973 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.747476204 Jul 29 07:03:09 PM PDT 24 Jul 29 07:03:10 PM PDT 24 32553633 ps
T974 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1083870605 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:02 PM PDT 24 155484155 ps
T975 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1414659628 Jul 29 07:06:17 PM PDT 24 Jul 29 07:06:18 PM PDT 24 29889736 ps
T976 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1609866267 Jul 29 07:06:31 PM PDT 24 Jul 29 07:06:32 PM PDT 24 35976063 ps
T977 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.4180093109 Jul 29 07:06:04 PM PDT 24 Jul 29 07:06:07 PM PDT 24 352170034 ps
T978 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1524260709 Jul 29 07:05:57 PM PDT 24 Jul 29 07:05:58 PM PDT 24 25495773 ps
T979 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3788474245 Jul 29 07:06:26 PM PDT 24 Jul 29 07:06:30 PM PDT 24 119306808 ps
T980 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1473002822 Jul 29 07:06:08 PM PDT 24 Jul 29 07:06:09 PM PDT 24 118607727 ps
T117 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.721907628 Jul 29 07:06:16 PM PDT 24 Jul 29 07:06:18 PM PDT 24 217050213 ps
T981 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1323848546 Jul 29 07:03:00 PM PDT 24 Jul 29 07:03:02 PM PDT 24 105833365 ps
T982 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2640582939 Jul 29 07:06:24 PM PDT 24 Jul 29 07:06:27 PM PDT 24 83727955 ps

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.1107884736
Short name T5
Test name
Test status
Simulation time 428678463 ps
CPU time 2.11 seconds
Started Jul 29 07:33:03 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201144 kb
Host smart-815a856c-4cc4-4f50-8fc3-9a5dc8cf067b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107884736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.1107884736
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.4204534271
Short name T1
Test name
Test status
Simulation time 3478865551 ps
CPU time 15.52 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:47 PM PDT 24
Peak memory 201464 kb
Host smart-372ba8a9-ec75-458b-9e78-0403050801c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204534271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.4204534271
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.4206890154
Short name T17
Test name
Test status
Simulation time 52018514665 ps
CPU time 548.76 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:42:39 PM PDT 24
Peak memory 217844 kb
Host smart-fa78e503-9e28-483c-9656-aa7e8ebbf91c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4206890154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.4206890154
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2178774990
Short name T59
Test name
Test status
Simulation time 441762016 ps
CPU time 3.53 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:11 PM PDT 24
Peak memory 209000 kb
Host smart-f36c6857-f41a-44ce-8977-647ce067ab7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178774990 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2178774990
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.2078168242
Short name T4
Test name
Test status
Simulation time 838230712 ps
CPU time 4.74 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201280 kb
Host smart-0ab0add1-6ec2-4df3-8e79-b4f567a2a5ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078168242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2078168242
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.3864594885
Short name T8
Test name
Test status
Simulation time 15440659 ps
CPU time 0.79 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 200212 kb
Host smart-554c3048-c920-4ba1-a840-0d072dc9c225
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864594885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3864594885
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.3484888610
Short name T44
Test name
Test status
Simulation time 655663652 ps
CPU time 3.31 seconds
Started Jul 29 07:32:36 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 216584 kb
Host smart-64cdc4f9-aa2f-4154-b9f8-a80ef2bd49aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484888610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.3484888610
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1194297288
Short name T13
Test name
Test status
Simulation time 11947662141 ps
CPU time 83.26 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201452 kb
Host smart-a1d170c6-b0df-4932-bf22-cc97850e8fee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194297288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1194297288
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.587019627
Short name T19
Test name
Test status
Simulation time 95915974 ps
CPU time 1.12 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201080 kb
Host smart-81dec38c-6f9b-4466-9bd5-863b94706b32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587019627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_idle_intersig_mubi.587019627
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1567548578
Short name T109
Test name
Test status
Simulation time 124464215 ps
CPU time 2.66 seconds
Started Jul 29 07:03:12 PM PDT 24
Finished Jul 29 07:03:15 PM PDT 24
Peak memory 200788 kb
Host smart-4ff7ea1c-702d-4134-b001-32474b9f1756
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567548578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.1567548578
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2455624167
Short name T58
Test name
Test status
Simulation time 1102648084 ps
CPU time 4.35 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:28 PM PDT 24
Peak memory 200880 kb
Host smart-d109978e-c284-4f55-8d64-8104072940ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455624167 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.2455624167
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.2739686970
Short name T32
Test name
Test status
Simulation time 33390616706 ps
CPU time 531.79 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:41:51 PM PDT 24
Peak memory 209740 kb
Host smart-45d2c21e-1a8a-456f-ae5e-200762215990
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2739686970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.2739686970
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2659916859
Short name T252
Test name
Test status
Simulation time 31393552 ps
CPU time 0.83 seconds
Started Jul 29 07:32:51 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201024 kb
Host smart-1be66eda-80b5-48a0-b6c2-a726d397aed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659916859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2659916859
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1926981304
Short name T38
Test name
Test status
Simulation time 70936874 ps
CPU time 0.95 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201084 kb
Host smart-15f28dac-c0ca-4ffd-ab8e-7a33f72e73f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926981304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.1926981304
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2403998193
Short name T139
Test name
Test status
Simulation time 228229221 ps
CPU time 1.78 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:16 PM PDT 24
Peak memory 216956 kb
Host smart-60db280f-6dbe-469b-af17-358a09fa6ddf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403998193 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.2403998193
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.162012656
Short name T113
Test name
Test status
Simulation time 1715546076 ps
CPU time 6.8 seconds
Started Jul 29 07:06:01 PM PDT 24
Finished Jul 29 07:06:08 PM PDT 24
Peak memory 200628 kb
Host smart-7d17fb24-ffe7-46b4-9be5-8dfcc9b25ecf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162012656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_tl_intg_err.162012656
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1750776407
Short name T942
Test name
Test status
Simulation time 101959465 ps
CPU time 1.8 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 201004 kb
Host smart-2ce11044-41da-4358-9d53-2116821c21d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750776407 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.1750776407
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.4039297939
Short name T66
Test name
Test status
Simulation time 223955929066 ps
CPU time 847.89 seconds
Started Jul 29 07:32:48 PM PDT 24
Finished Jul 29 07:46:56 PM PDT 24
Peak memory 209816 kb
Host smart-ce7902f9-00c1-4284-a3f7-8cacbbcb384e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4039297939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.4039297939
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1611832922
Short name T100
Test name
Test status
Simulation time 17249066 ps
CPU time 0.8 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201048 kb
Host smart-ba9b4a21-6be1-4550-9d6f-5616df39dc3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611832922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1611832922
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2939704580
Short name T135
Test name
Test status
Simulation time 108861381 ps
CPU time 1.87 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 216608 kb
Host smart-828830d3-ecf0-408a-bf4b-91fc4c8b7249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939704580 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2939704580
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.1447429502
Short name T676
Test name
Test status
Simulation time 985933485 ps
CPU time 4.7 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:25 PM PDT 24
Peak memory 201348 kb
Host smart-e365d005-60ae-468c-a6d7-83494abb5ef5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447429502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.1447429502
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.426726058
Short name T949
Test name
Test status
Simulation time 198006213 ps
CPU time 2.05 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:10 PM PDT 24
Peak memory 200600 kb
Host smart-b53c7639-d089-44ea-aeb5-49120bf1dc08
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426726058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_tl_intg_err.426726058
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.721907628
Short name T117
Test name
Test status
Simulation time 217050213 ps
CPU time 2.52 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 200616 kb
Host smart-0a02ac06-6a9b-4a56-8b26-221ee969349f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721907628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_tl_intg_err.721907628
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1323848546
Short name T981
Test name
Test status
Simulation time 105833365 ps
CPU time 1.76 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 200560 kb
Host smart-96fcaf95-2316-4d5a-b141-fb4ef1eb52d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323848546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.1323848546
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3373803442
Short name T869
Test name
Test status
Simulation time 685610049 ps
CPU time 7.23 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:07 PM PDT 24
Peak memory 200536 kb
Host smart-2b89fa31-027c-4701-a424-eded88df7bf8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373803442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.3373803442
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.981996051
Short name T862
Test name
Test status
Simulation time 25735743 ps
CPU time 0.91 seconds
Started Jul 29 07:03:02 PM PDT 24
Finished Jul 29 07:03:03 PM PDT 24
Peak memory 200396 kb
Host smart-98ce582a-e7ed-4882-bd22-e97294878ebd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981996051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_hw_reset.981996051
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.4013013730
Short name T852
Test name
Test status
Simulation time 44469134 ps
CPU time 1.38 seconds
Started Jul 29 07:03:01 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 200496 kb
Host smart-18a69459-3a04-4fa7-a5a6-767d65f2fd2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013013730 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.4013013730
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3658522905
Short name T874
Test name
Test status
Simulation time 76508600 ps
CPU time 1 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:01 PM PDT 24
Peak memory 200376 kb
Host smart-4f88d210-2712-479d-8c44-be001b4b3073
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658522905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.3658522905
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.756496514
Short name T839
Test name
Test status
Simulation time 22692061 ps
CPU time 0.72 seconds
Started Jul 29 07:03:01 PM PDT 24
Finished Jul 29 07:03:01 PM PDT 24
Peak memory 198956 kb
Host smart-5010596c-3b22-4a55-88ee-05f949dee1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756496514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm
gr_intr_test.756496514
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1083870605
Short name T974
Test name
Test status
Simulation time 155484155 ps
CPU time 1.61 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 200524 kb
Host smart-87fe2eca-bf07-48bd-b2a6-859538c52492
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083870605 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1083870605
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1522621759
Short name T138
Test name
Test status
Simulation time 336522154 ps
CPU time 1.99 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 200592 kb
Host smart-7b899de7-2253-44e8-a9a7-64b2b5a8fb83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522621759 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.1522621759
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3122805685
Short name T904
Test name
Test status
Simulation time 127939455 ps
CPU time 1.74 seconds
Started Jul 29 07:02:59 PM PDT 24
Finished Jul 29 07:03:01 PM PDT 24
Peak memory 208984 kb
Host smart-fe91aa57-6bcd-4b49-aa27-4a1120c2c640
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122805685 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3122805685
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.3395827192
Short name T969
Test name
Test status
Simulation time 275829267 ps
CPU time 3.52 seconds
Started Jul 29 07:03:02 PM PDT 24
Finished Jul 29 07:03:06 PM PDT 24
Peak memory 200592 kb
Host smart-4939be3d-34bd-4b60-8820-5915e0f551de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395827192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.3395827192
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3233823722
Short name T917
Test name
Test status
Simulation time 77026174 ps
CPU time 1.78 seconds
Started Jul 29 07:03:02 PM PDT 24
Finished Jul 29 07:03:04 PM PDT 24
Peak memory 200568 kb
Host smart-7ae66966-2559-4260-8e43-24463da424a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233823722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3233823722
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.110294229
Short name T867
Test name
Test status
Simulation time 131387823 ps
CPU time 1.47 seconds
Started Jul 29 07:03:05 PM PDT 24
Finished Jul 29 07:03:07 PM PDT 24
Peak memory 200388 kb
Host smart-ed9f0789-d9e2-4271-b225-817fb8fb064a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110294229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.110294229
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3579520688
Short name T885
Test name
Test status
Simulation time 263925400 ps
CPU time 7.53 seconds
Started Jul 29 07:03:04 PM PDT 24
Finished Jul 29 07:03:12 PM PDT 24
Peak memory 200584 kb
Host smart-12c64c51-5c6b-4b7e-b2d7-6c52964cc43c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579520688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3579520688
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2024920816
Short name T943
Test name
Test status
Simulation time 114170107 ps
CPU time 1.02 seconds
Started Jul 29 07:03:05 PM PDT 24
Finished Jul 29 07:03:06 PM PDT 24
Peak memory 200360 kb
Host smart-04a0dd88-f5ae-4f9b-bc07-4d7716fcaf9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024920816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2024920816
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.2238988502
Short name T823
Test name
Test status
Simulation time 30874602 ps
CPU time 1.45 seconds
Started Jul 29 07:03:05 PM PDT 24
Finished Jul 29 07:03:06 PM PDT 24
Peak memory 200856 kb
Host smart-8de8b47b-86e8-4492-9fe2-8e14bf5acfad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238988502 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.2238988502
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.747476204
Short name T973
Test name
Test status
Simulation time 32553633 ps
CPU time 0.85 seconds
Started Jul 29 07:03:09 PM PDT 24
Finished Jul 29 07:03:10 PM PDT 24
Peak memory 200348 kb
Host smart-3b5b34f3-48e2-4b47-80e5-344251178a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747476204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.747476204
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3110038663
Short name T865
Test name
Test status
Simulation time 11303329 ps
CPU time 0.66 seconds
Started Jul 29 07:02:59 PM PDT 24
Finished Jul 29 07:03:00 PM PDT 24
Peak memory 199040 kb
Host smart-a76b53d2-65eb-4944-9d01-6dcbbdcaae64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110038663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3110038663
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.1419700800
Short name T856
Test name
Test status
Simulation time 98443435 ps
CPU time 1.55 seconds
Started Jul 29 07:03:06 PM PDT 24
Finished Jul 29 07:03:08 PM PDT 24
Peak memory 200568 kb
Host smart-8f2982d4-bec1-416b-9606-b084e31260f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419700800 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.1419700800
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2191189702
Short name T131
Test name
Test status
Simulation time 288533027 ps
CPU time 2.42 seconds
Started Jul 29 07:03:01 PM PDT 24
Finished Jul 29 07:03:03 PM PDT 24
Peak memory 200792 kb
Host smart-b3b3acf9-895a-40cc-8ebd-8e495bd083a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191189702 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2191189702
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.1104185554
Short name T142
Test name
Test status
Simulation time 79585224 ps
CPU time 1.74 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:02 PM PDT 24
Peak memory 209024 kb
Host smart-9e229867-2c62-4deb-acdf-b97d718932b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104185554 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.1104185554
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3236102925
Short name T905
Test name
Test status
Simulation time 136893147 ps
CPU time 3.71 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:03 PM PDT 24
Peak memory 200588 kb
Host smart-15a59ea4-e97f-461e-b483-28356c8cc43f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236102925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3236102925
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.728607217
Short name T938
Test name
Test status
Simulation time 139444601 ps
CPU time 2.82 seconds
Started Jul 29 07:03:00 PM PDT 24
Finished Jul 29 07:03:03 PM PDT 24
Peak memory 200592 kb
Host smart-5dd53af6-b188-430c-b888-01680068ab1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728607217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_tl_intg_err.728607217
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2170277443
Short name T908
Test name
Test status
Simulation time 229049694 ps
CPU time 1.8 seconds
Started Jul 29 07:06:04 PM PDT 24
Finished Jul 29 07:06:06 PM PDT 24
Peak memory 200464 kb
Host smart-c13e45ee-e2ec-4b83-bfc4-6fffe9f1c242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170277443 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2170277443
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2149824614
Short name T888
Test name
Test status
Simulation time 12941981 ps
CPU time 0.8 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:07 PM PDT 24
Peak memory 200368 kb
Host smart-be685318-894b-4481-8c05-bf61a3d5b3e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149824614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.2149824614
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.763414972
Short name T876
Test name
Test status
Simulation time 18062678 ps
CPU time 0.69 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:07 PM PDT 24
Peak memory 198980 kb
Host smart-4555a53c-d989-467d-978f-c1a31d1bda14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763414972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_intr_test.763414972
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.537455890
Short name T83
Test name
Test status
Simulation time 574300637 ps
CPU time 2.66 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:10 PM PDT 24
Peak memory 200548 kb
Host smart-6e05ab84-e861-476a-8150-e22800b2cc3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537455890 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.537455890
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.4150531969
Short name T60
Test name
Test status
Simulation time 86264346 ps
CPU time 1.46 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:07 PM PDT 24
Peak memory 200628 kb
Host smart-4da8f575-f959-4927-bc0f-274cb0149980
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150531969 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.4150531969
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.382281658
Short name T827
Test name
Test status
Simulation time 48324998 ps
CPU time 1.67 seconds
Started Jul 29 07:06:09 PM PDT 24
Finished Jul 29 07:06:10 PM PDT 24
Peak memory 200528 kb
Host smart-d1b8b460-8ac8-45af-a3c0-0e234c3c011c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382281658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_tl_errors.382281658
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.4180093109
Short name T977
Test name
Test status
Simulation time 352170034 ps
CPU time 2.77 seconds
Started Jul 29 07:06:04 PM PDT 24
Finished Jul 29 07:06:07 PM PDT 24
Peak memory 200596 kb
Host smart-340cc42b-3d12-46d0-9ad1-16dd0116d414
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180093109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.4180093109
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1026531119
Short name T916
Test name
Test status
Simulation time 96859323 ps
CPU time 1.18 seconds
Started Jul 29 07:06:04 PM PDT 24
Finished Jul 29 07:06:06 PM PDT 24
Peak memory 200348 kb
Host smart-56fdb428-35ac-4786-9349-db91aabdba43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026531119 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1026531119
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1625308658
Short name T961
Test name
Test status
Simulation time 17135775 ps
CPU time 0.8 seconds
Started Jul 29 07:06:04 PM PDT 24
Finished Jul 29 07:06:04 PM PDT 24
Peak memory 200320 kb
Host smart-078f9420-7a38-4179-a5de-4b98d4a1f2d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625308658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.1625308658
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3097447518
Short name T953
Test name
Test status
Simulation time 13497768 ps
CPU time 0.68 seconds
Started Jul 29 07:06:09 PM PDT 24
Finished Jul 29 07:06:10 PM PDT 24
Peak memory 198972 kb
Host smart-69dac0f9-96e3-4358-baab-0b477887e695
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097447518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.3097447518
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2903957284
Short name T971
Test name
Test status
Simulation time 53997977 ps
CPU time 1.28 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:09 PM PDT 24
Peak memory 200384 kb
Host smart-53e80440-6afa-4e3e-88cc-ebe116d26751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903957284 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.2903957284
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.696751439
Short name T132
Test name
Test status
Simulation time 771378549 ps
CPU time 3.55 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:12 PM PDT 24
Peak memory 200800 kb
Host smart-ebbb9941-039d-4909-afc5-9db4b4a279e9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696751439 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.clkmgr_shadow_reg_errors.696751439
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2299600576
Short name T928
Test name
Test status
Simulation time 743592549 ps
CPU time 4.61 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:11 PM PDT 24
Peak memory 209264 kb
Host smart-184c93cc-e69c-46ed-98be-c95bd2334c2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299600576 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2299600576
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2604393664
Short name T907
Test name
Test status
Simulation time 43493981 ps
CPU time 1.62 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:08 PM PDT 24
Peak memory 200548 kb
Host smart-751793d1-0068-44a2-80c1-d7a4853aa3fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604393664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2604393664
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.504675059
Short name T112
Test name
Test status
Simulation time 46490601 ps
CPU time 1.49 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:20 PM PDT 24
Peak memory 200400 kb
Host smart-42f10322-641c-40ee-8c72-cb989d275a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504675059 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.504675059
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.2986482736
Short name T955
Test name
Test status
Simulation time 13832705 ps
CPU time 0.75 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200284 kb
Host smart-effbb17a-aa31-48c6-b328-fc9cf939b7bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986482736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.2986482736
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.599024850
Short name T849
Test name
Test status
Simulation time 34872630 ps
CPU time 0.7 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:14 PM PDT 24
Peak memory 198984 kb
Host smart-9719be2e-8b91-457e-ae5c-de87ff01ade5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599024850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.599024850
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1414659628
Short name T975
Test name
Test status
Simulation time 29889736 ps
CPU time 0.98 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 200340 kb
Host smart-fea15af3-3d49-45fb-8bb3-d642e32a4fdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414659628 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1414659628
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.597700335
Short name T64
Test name
Test status
Simulation time 55600583 ps
CPU time 1.33 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 200632 kb
Host smart-db3bdd71-bc11-4ad2-9b0b-d6be341242db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597700335 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.clkmgr_shadow_reg_errors.597700335
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3662729685
Short name T968
Test name
Test status
Simulation time 236825940 ps
CPU time 2.11 seconds
Started Jul 29 07:06:12 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 217180 kb
Host smart-3ff8a6da-2b9c-45d7-b5c1-a82a5c89591b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662729685 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3662729685
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.2554777893
Short name T851
Test name
Test status
Simulation time 686689386 ps
CPU time 4.68 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200544 kb
Host smart-4315be6b-78ab-4cc5-87ad-d0cae358d794
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554777893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.2554777893
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.4004395470
Short name T110
Test name
Test status
Simulation time 229899255 ps
CPU time 2.66 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:20 PM PDT 24
Peak memory 200596 kb
Host smart-66ea0a8e-2c7e-4532-bd5b-7bc5379ea121
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004395470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.4004395470
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3904935536
Short name T863
Test name
Test status
Simulation time 30620892 ps
CPU time 1.03 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 200268 kb
Host smart-361f17f9-5ff8-45a5-8143-d9c5e1b80103
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904935536 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3904935536
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.2418737785
Short name T956
Test name
Test status
Simulation time 16280909 ps
CPU time 0.82 seconds
Started Jul 29 07:06:12 PM PDT 24
Finished Jul 29 07:06:13 PM PDT 24
Peak memory 200380 kb
Host smart-1b3298b2-f493-465b-916f-5238fd53fc66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418737785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.2418737785
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3956140676
Short name T921
Test name
Test status
Simulation time 18965191 ps
CPU time 0.67 seconds
Started Jul 29 07:06:13 PM PDT 24
Finished Jul 29 07:06:13 PM PDT 24
Peak memory 198960 kb
Host smart-df6b63fb-d43c-4a2e-a828-f0af4040565e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956140676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.3956140676
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3458167565
Short name T871
Test name
Test status
Simulation time 23441850 ps
CPU time 0.98 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200380 kb
Host smart-feda64f4-92b5-4e85-93bb-77f7aa0e561d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458167565 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3458167565
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.858143586
Short name T63
Test name
Test status
Simulation time 454291718 ps
CPU time 2.14 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200620 kb
Host smart-8acae25f-5499-4c5e-b38e-31857f6d176d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858143586 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.clkmgr_shadow_reg_errors.858143586
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.3131268215
Short name T915
Test name
Test status
Simulation time 108303732 ps
CPU time 1.74 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 209188 kb
Host smart-16a493e9-bb9c-42b5-8eae-adfe4ec8086f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131268215 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.3131268215
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4197265937
Short name T924
Test name
Test status
Simulation time 103295659 ps
CPU time 2.72 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:17 PM PDT 24
Peak memory 200556 kb
Host smart-073be55d-7285-4a43-a192-c1e217f7f038
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197265937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.4197265937
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.265102962
Short name T898
Test name
Test status
Simulation time 59556669 ps
CPU time 1.53 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200492 kb
Host smart-e0b66c40-a912-406f-90a0-361279775fc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265102962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.265102962
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4013142593
Short name T896
Test name
Test status
Simulation time 47201878 ps
CPU time 1.41 seconds
Started Jul 29 07:06:13 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 200452 kb
Host smart-acdfb042-7df7-47d6-8168-28144234ab5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013142593 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.4013142593
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.4200708567
Short name T900
Test name
Test status
Simulation time 26773758 ps
CPU time 0.87 seconds
Started Jul 29 07:06:15 PM PDT 24
Finished Jul 29 07:06:16 PM PDT 24
Peak memory 200368 kb
Host smart-b66b783d-436f-4de7-8dc2-c7ab0020192e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200708567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.4200708567
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3248568839
Short name T821
Test name
Test status
Simulation time 21079444 ps
CPU time 0.7 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:17 PM PDT 24
Peak memory 198940 kb
Host smart-d33b2011-d52f-48ce-b564-914ac12b7b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248568839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.3248568839
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3712477876
Short name T945
Test name
Test status
Simulation time 69178636 ps
CPU time 0.99 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 200352 kb
Host smart-e216a6ee-5f86-4dfc-a50c-5ba178bb372a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712477876 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.3712477876
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1908117692
Short name T88
Test name
Test status
Simulation time 100393265 ps
CPU time 2.54 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 209056 kb
Host smart-2a9b6c11-16fb-4b1b-a866-4570eb5ccde0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908117692 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1908117692
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3769353554
Short name T902
Test name
Test status
Simulation time 95037032 ps
CPU time 1.75 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 200560 kb
Host smart-65ec43bb-1752-439d-8e35-eb5dd2fb4e10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769353554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.3769353554
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2190111701
Short name T106
Test name
Test status
Simulation time 115181542 ps
CPU time 1.85 seconds
Started Jul 29 07:06:13 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 200628 kb
Host smart-d8e87ec1-c5a2-44ac-bb39-7046135f083c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190111701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.2190111701
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.505663015
Short name T918
Test name
Test status
Simulation time 40799910 ps
CPU time 1.33 seconds
Started Jul 29 07:06:15 PM PDT 24
Finished Jul 29 07:06:16 PM PDT 24
Peak memory 200616 kb
Host smart-a595bc83-af20-4c0d-a7e6-28550d76abcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505663015 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.505663015
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4052603723
Short name T894
Test name
Test status
Simulation time 51711056 ps
CPU time 0.9 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 200284 kb
Host smart-9967971a-68c7-464b-a375-3a86a622d45c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052603723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.4052603723
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3380412577
Short name T878
Test name
Test status
Simulation time 54784766 ps
CPU time 0.73 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:17 PM PDT 24
Peak memory 199032 kb
Host smart-16aa9b19-d608-44db-b843-27ae8f20dc7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380412577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.3380412577
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2727928198
Short name T889
Test name
Test status
Simulation time 37680051 ps
CPU time 1.17 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 200136 kb
Host smart-a6705d12-26b3-415b-8bcb-71f81d220503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727928198 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.2727928198
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2104613507
Short name T134
Test name
Test status
Simulation time 279197453 ps
CPU time 2.92 seconds
Started Jul 29 07:06:12 PM PDT 24
Finished Jul 29 07:06:15 PM PDT 24
Peak memory 209000 kb
Host smart-1c3b24e9-f32e-4ae4-94c4-8c26f674c852
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104613507 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.2104613507
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4048923397
Short name T845
Test name
Test status
Simulation time 103255501 ps
CPU time 1.84 seconds
Started Jul 29 07:06:18 PM PDT 24
Finished Jul 29 07:06:20 PM PDT 24
Peak memory 200512 kb
Host smart-7e06e522-493e-4ba5-a287-45dffd84bf47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048923397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.4048923397
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1731521528
Short name T167
Test name
Test status
Simulation time 336368771 ps
CPU time 3.22 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:21 PM PDT 24
Peak memory 200540 kb
Host smart-2fbd65c8-d7d9-47f4-a6e5-d6a26a7c8e22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731521528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1731521528
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.2917635132
Short name T838
Test name
Test status
Simulation time 21467056 ps
CPU time 1.16 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200420 kb
Host smart-e96848de-075a-4ebd-a305-1f976250455d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917635132 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.2917635132
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1530175345
Short name T86
Test name
Test status
Simulation time 32185044 ps
CPU time 0.84 seconds
Started Jul 29 07:06:16 PM PDT 24
Finished Jul 29 07:06:17 PM PDT 24
Peak memory 200540 kb
Host smart-8f336368-87e3-4448-a882-394633fd1989
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530175345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1530175345
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2106639619
Short name T951
Test name
Test status
Simulation time 18008794 ps
CPU time 0.69 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:18 PM PDT 24
Peak memory 198988 kb
Host smart-dc28547e-e08f-4573-92f9-49f8707aff38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106639619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2106639619
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1434215361
Short name T843
Test name
Test status
Simulation time 97002118 ps
CPU time 1.46 seconds
Started Jul 29 07:06:26 PM PDT 24
Finished Jul 29 07:06:28 PM PDT 24
Peak memory 200596 kb
Host smart-b02c3f7a-d451-4671-834d-6d6831cbdcdf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434215361 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.1434215361
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1043472968
Short name T937
Test name
Test status
Simulation time 137629371 ps
CPU time 1.88 seconds
Started Jul 29 07:06:14 PM PDT 24
Finished Jul 29 07:06:16 PM PDT 24
Peak memory 210064 kb
Host smart-efa99569-404d-4210-ab13-3584f9fc012a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043472968 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.1043472968
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2399961471
Short name T89
Test name
Test status
Simulation time 130463638 ps
CPU time 1.78 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:19 PM PDT 24
Peak memory 209012 kb
Host smart-b2d85f2b-ada3-4e6d-b032-892a55b2b03d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399961471 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2399961471
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3797654624
Short name T861
Test name
Test status
Simulation time 278851947 ps
CPU time 3.68 seconds
Started Jul 29 07:06:17 PM PDT 24
Finished Jul 29 07:06:21 PM PDT 24
Peak memory 200544 kb
Host smart-4e454012-b5cb-49a6-ab59-bde392327f92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797654624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.3797654624
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3812904161
Short name T837
Test name
Test status
Simulation time 69253912 ps
CPU time 1.24 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200484 kb
Host smart-7cb0b884-3ffc-4730-ac85-2c4250ae1429
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812904161 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3812904161
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.1502170000
Short name T963
Test name
Test status
Simulation time 19704622 ps
CPU time 0.79 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200368 kb
Host smart-46b29e20-b14a-4077-9b11-5c8d3d855dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502170000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.1502170000
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3960574988
Short name T847
Test name
Test status
Simulation time 18914173 ps
CPU time 0.68 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 199156 kb
Host smart-2d4fbeef-72bf-4f93-b0eb-9d000d703000
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960574988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3960574988
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3758742731
Short name T884
Test name
Test status
Simulation time 50605325 ps
CPU time 1.44 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200568 kb
Host smart-bfaa82f9-be1d-48e9-a264-0385a55fb0c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758742731 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.3758742731
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1833203136
Short name T65
Test name
Test status
Simulation time 265192995 ps
CPU time 3.22 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 201116 kb
Host smart-06bda65a-dbbf-4747-a423-4d950e7883ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833203136 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1833203136
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2640582939
Short name T982
Test name
Test status
Simulation time 83727955 ps
CPU time 2.49 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:27 PM PDT 24
Peak memory 200556 kb
Host smart-d0c86ead-73ba-46d6-bcc6-ed7fb4440e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640582939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2640582939
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2243578415
Short name T927
Test name
Test status
Simulation time 209686676 ps
CPU time 1.93 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:26 PM PDT 24
Peak memory 200572 kb
Host smart-08d47d0e-ef9e-430f-a156-c1955d628b3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243578415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.2243578415
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.492250640
Short name T913
Test name
Test status
Simulation time 25410345 ps
CPU time 0.91 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 200464 kb
Host smart-6c9e6699-2074-4739-8d63-df4cf6f11451
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492250640 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.492250640
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.4153415094
Short name T883
Test name
Test status
Simulation time 32096683 ps
CPU time 0.81 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 200476 kb
Host smart-bf8c60e3-2581-4114-9a10-87af17f30af3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153415094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.4153415094
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3025974779
Short name T954
Test name
Test status
Simulation time 59107486 ps
CPU time 0.78 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 198952 kb
Host smart-156d569c-c7c6-4452-a1a1-d78b9702c64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025974779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.3025974779
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3745914467
Short name T966
Test name
Test status
Simulation time 186625932 ps
CPU time 1.52 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200380 kb
Host smart-832bd9a3-995d-4b2d-a025-89ddcdccfc4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745914467 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.3745914467
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.2398353705
Short name T919
Test name
Test status
Simulation time 149454777 ps
CPU time 2.17 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 217140 kb
Host smart-3094bed0-3c80-4d80-9fb5-ec0443438a05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398353705 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.2398353705
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3788474245
Short name T979
Test name
Test status
Simulation time 119306808 ps
CPU time 3.17 seconds
Started Jul 29 07:06:26 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 200528 kb
Host smart-4d3f4173-0be6-4dbb-abcb-3add57ecf646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788474245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3788474245
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2385029534
Short name T116
Test name
Test status
Simulation time 188932694 ps
CPU time 2.86 seconds
Started Jul 29 07:06:21 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 200520 kb
Host smart-4424348b-ab88-457c-86aa-abf7f10b9300
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385029534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.2385029534
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1819484413
Short name T144
Test name
Test status
Simulation time 47065864 ps
CPU time 1.42 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 200460 kb
Host smart-cc7f0034-46a1-4e85-b94a-28a92bc0586d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819484413 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1819484413
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.508517496
Short name T906
Test name
Test status
Simulation time 15617597 ps
CPU time 0.76 seconds
Started Jul 29 07:06:28 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 200212 kb
Host smart-8df102b8-af12-449a-a16b-ec9d2dc5866b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508517496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.508517496
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2869485823
Short name T950
Test name
Test status
Simulation time 18146024 ps
CPU time 0.69 seconds
Started Jul 29 07:06:28 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 198928 kb
Host smart-2e0f1b80-9ffd-4ab3-8961-a2fac75ff9bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869485823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2869485823
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3586167443
Short name T854
Test name
Test status
Simulation time 32989587 ps
CPU time 1.1 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200280 kb
Host smart-12676cd7-99d4-49ef-a883-b9085dd439c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586167443 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3586167443
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3293695949
Short name T922
Test name
Test status
Simulation time 158342327 ps
CPU time 1.59 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:26 PM PDT 24
Peak memory 200568 kb
Host smart-ca547d6e-0879-4d4c-b2ad-57a03c3a72a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293695949 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3293695949
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.345779274
Short name T87
Test name
Test status
Simulation time 67136028 ps
CPU time 1.83 seconds
Started Jul 29 07:06:26 PM PDT 24
Finished Jul 29 07:06:28 PM PDT 24
Peak memory 208988 kb
Host smart-503c1277-dbba-46f7-9559-f8f258af529e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345779274 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.345779274
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2208492742
Short name T970
Test name
Test status
Simulation time 236595044 ps
CPU time 2.26 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 200596 kb
Host smart-70346c38-0a72-4c1a-8638-c6a4b493fd6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208492742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.2208492742
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.4142748213
Short name T108
Test name
Test status
Simulation time 103387203 ps
CPU time 2.49 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:26 PM PDT 24
Peak memory 200588 kb
Host smart-b2e3c17d-ec6a-4ab3-8415-8e9eedfe6d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142748213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.4142748213
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1098647417
Short name T909
Test name
Test status
Simulation time 55659784 ps
CPU time 1.21 seconds
Started Jul 29 07:03:15 PM PDT 24
Finished Jul 29 07:03:16 PM PDT 24
Peak memory 200336 kb
Host smart-2ac23dd3-d098-4d6c-974f-a3a70ba06970
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098647417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1098647417
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.2455289276
Short name T932
Test name
Test status
Simulation time 268450681 ps
CPU time 4.72 seconds
Started Jul 29 07:03:04 PM PDT 24
Finished Jul 29 07:03:09 PM PDT 24
Peak memory 200496 kb
Host smart-f6857449-abe3-4601-aceb-579f047290b5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455289276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.2455289276
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3890083846
Short name T834
Test name
Test status
Simulation time 19894003 ps
CPU time 0.8 seconds
Started Jul 29 07:03:05 PM PDT 24
Finished Jul 29 07:03:06 PM PDT 24
Peak memory 200324 kb
Host smart-8622b184-c28d-4b16-9e11-00ba668daeaa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890083846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.3890083846
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.560167449
Short name T895
Test name
Test status
Simulation time 131812714 ps
CPU time 1.61 seconds
Started Jul 29 07:03:14 PM PDT 24
Finished Jul 29 07:03:16 PM PDT 24
Peak memory 200508 kb
Host smart-fd28ea97-e362-47a0-b52f-ab3de864b747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560167449 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.560167449
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2188498248
Short name T873
Test name
Test status
Simulation time 25108511 ps
CPU time 0.86 seconds
Started Jul 29 07:03:05 PM PDT 24
Finished Jul 29 07:03:06 PM PDT 24
Peak memory 200356 kb
Host smart-bf6c5f65-c112-4b9c-ab37-370e30520038
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188498248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2188498248
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3078355565
Short name T820
Test name
Test status
Simulation time 11766857 ps
CPU time 0.65 seconds
Started Jul 29 07:03:04 PM PDT 24
Finished Jul 29 07:03:05 PM PDT 24
Peak memory 198968 kb
Host smart-11a1765c-c299-44c5-bb50-9573b7251368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078355565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.3078355565
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3947073573
Short name T893
Test name
Test status
Simulation time 65990528 ps
CPU time 1.34 seconds
Started Jul 29 07:03:14 PM PDT 24
Finished Jul 29 07:03:16 PM PDT 24
Peak memory 200536 kb
Host smart-0919a702-5fbc-40d3-a3af-ef0cbd7db5cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947073573 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.3947073573
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.2365108161
Short name T137
Test name
Test status
Simulation time 269271987 ps
CPU time 1.77 seconds
Started Jul 29 07:03:08 PM PDT 24
Finished Jul 29 07:03:10 PM PDT 24
Peak memory 200628 kb
Host smart-92a2b1ae-6a2e-4cc8-82da-61d4d8a0401c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365108161 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.2365108161
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2475643948
Short name T141
Test name
Test status
Simulation time 103239155 ps
CPU time 2.54 seconds
Started Jul 29 07:03:09 PM PDT 24
Finished Jul 29 07:03:11 PM PDT 24
Peak memory 217188 kb
Host smart-67aaa586-b814-4720-934a-9b6f9ed88d0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475643948 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2475643948
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.7596747
Short name T831
Test name
Test status
Simulation time 234859744 ps
CPU time 2.33 seconds
Started Jul 29 07:03:07 PM PDT 24
Finished Jul 29 07:03:09 PM PDT 24
Peak memory 200508 kb
Host smart-5d9b5681-dfd6-4aa8-9f38-a31cacac95aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7596747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=
clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr
_tl_errors.7596747
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3210413772
Short name T897
Test name
Test status
Simulation time 183009097 ps
CPU time 1.84 seconds
Started Jul 29 07:03:06 PM PDT 24
Finished Jul 29 07:03:08 PM PDT 24
Peak memory 200524 kb
Host smart-7842d4f3-c314-48b3-9388-c02349ab0525
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210413772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3210413772
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1296883939
Short name T882
Test name
Test status
Simulation time 29834559 ps
CPU time 0.71 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 198972 kb
Host smart-190b8d87-b8a0-4267-8709-3716f5a6de56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296883939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.1296883939
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2718158592
Short name T899
Test name
Test status
Simulation time 13920305 ps
CPU time 0.68 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 198976 kb
Host smart-5ed4f0be-7e8c-431e-a8d3-3d76f51fb336
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718158592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.2718158592
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1692954083
Short name T835
Test name
Test status
Simulation time 13161894 ps
CPU time 0.69 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 198952 kb
Host smart-23c2011e-6ad1-4e2b-9e80-fd691c0d0897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692954083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.1692954083
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.197383715
Short name T832
Test name
Test status
Simulation time 16748199 ps
CPU time 0.69 seconds
Started Jul 29 07:06:28 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 199004 kb
Host smart-1f68ab98-d461-49c9-b335-74781f2cc517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197383715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.197383715
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2726627236
Short name T934
Test name
Test status
Simulation time 19850712 ps
CPU time 0.68 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 198976 kb
Host smart-970d881a-6e29-459c-b284-97249d8f07b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726627236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.2726627236
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.1660242389
Short name T880
Test name
Test status
Simulation time 20747971 ps
CPU time 0.69 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 199136 kb
Host smart-da81b831-47ec-4a1d-91af-02941fb3ee24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660242389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.1660242389
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3858528988
Short name T914
Test name
Test status
Simulation time 13401523 ps
CPU time 0.69 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 198960 kb
Host smart-6aa6d70a-eb06-4f77-a9d7-645836b9bc9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858528988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3858528988
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2123418638
Short name T853
Test name
Test status
Simulation time 19812575 ps
CPU time 0.71 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 199040 kb
Host smart-eca17bb5-f6b1-42a4-bdb8-5de95c8d5add
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123418638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.2123418638
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.4144778830
Short name T910
Test name
Test status
Simulation time 63339066 ps
CPU time 0.78 seconds
Started Jul 29 07:06:26 PM PDT 24
Finished Jul 29 07:06:27 PM PDT 24
Peak memory 198940 kb
Host smart-9d796f99-5e48-419d-b33f-bb96920b6c8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144778830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.4144778830
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.4033881179
Short name T957
Test name
Test status
Simulation time 17522735 ps
CPU time 0.67 seconds
Started Jul 29 07:06:22 PM PDT 24
Finished Jul 29 07:06:23 PM PDT 24
Peak memory 199044 kb
Host smart-3e2b0239-b58e-4fdf-afee-7b7c6af9b70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033881179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.4033881179
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1199512269
Short name T872
Test name
Test status
Simulation time 475628040 ps
CPU time 2.27 seconds
Started Jul 29 07:03:13 PM PDT 24
Finished Jul 29 07:03:16 PM PDT 24
Peak memory 200264 kb
Host smart-3fdf6e38-005a-428a-ae63-49856e6736c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199512269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.1199512269
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.1820186590
Short name T833
Test name
Test status
Simulation time 278609399 ps
CPU time 6.87 seconds
Started Jul 29 07:03:14 PM PDT 24
Finished Jul 29 07:03:21 PM PDT 24
Peak memory 200560 kb
Host smart-c1595695-ad56-401a-8f8a-52a593588406
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820186590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.1820186590
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.153870254
Short name T923
Test name
Test status
Simulation time 30556277 ps
CPU time 0.78 seconds
Started Jul 29 07:03:13 PM PDT 24
Finished Jul 29 07:03:14 PM PDT 24
Peak memory 200248 kb
Host smart-3aa762da-5537-4a93-9e26-001f42bd6b90
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153870254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.153870254
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1688308227
Short name T958
Test name
Test status
Simulation time 32139411 ps
CPU time 1.57 seconds
Started Jul 29 07:05:49 PM PDT 24
Finished Jul 29 07:05:51 PM PDT 24
Peak memory 200624 kb
Host smart-a5bae980-41ad-4643-8458-3dbde8910d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688308227 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1688308227
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.824724415
Short name T841
Test name
Test status
Simulation time 21843824 ps
CPU time 0.88 seconds
Started Jul 29 07:03:13 PM PDT 24
Finished Jul 29 07:03:14 PM PDT 24
Peak memory 200368 kb
Host smart-550eae1e-644d-45cb-a1ec-e3ad02b8dac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824724415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.c
lkmgr_csr_rw.824724415
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2008257464
Short name T848
Test name
Test status
Simulation time 12859775 ps
CPU time 0.67 seconds
Started Jul 29 07:03:15 PM PDT 24
Finished Jul 29 07:03:15 PM PDT 24
Peak memory 198972 kb
Host smart-46b837f3-b44e-4bee-acba-b1c5b150e397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008257464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.2008257464
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3070253872
Short name T925
Test name
Test status
Simulation time 620992706 ps
CPU time 2.83 seconds
Started Jul 29 07:03:14 PM PDT 24
Finished Jul 29 07:03:17 PM PDT 24
Peak memory 200664 kb
Host smart-56e4b381-f6ff-4573-8325-0db05beff093
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070253872 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.3070253872
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3454383447
Short name T136
Test name
Test status
Simulation time 159709975 ps
CPU time 1.51 seconds
Started Jul 29 07:03:14 PM PDT 24
Finished Jul 29 07:03:16 PM PDT 24
Peak memory 200616 kb
Host smart-04e669e1-beba-467a-aed5-874760e10ab0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454383447 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3454383447
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2015531980
Short name T903
Test name
Test status
Simulation time 105043094 ps
CPU time 1.88 seconds
Started Jul 29 07:03:11 PM PDT 24
Finished Jul 29 07:03:13 PM PDT 24
Peak memory 209060 kb
Host smart-4ed927e7-2a00-48eb-b110-000e038fcea9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015531980 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.2015531980
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2672715010
Short name T858
Test name
Test status
Simulation time 504408752 ps
CPU time 4.35 seconds
Started Jul 29 07:03:13 PM PDT 24
Finished Jul 29 07:03:18 PM PDT 24
Peak memory 200516 kb
Host smart-100312f0-535f-47a0-9423-7be8b29199b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672715010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2672715010
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.378618906
Short name T875
Test name
Test status
Simulation time 11268728 ps
CPU time 0.66 seconds
Started Jul 29 07:06:28 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 198932 kb
Host smart-1f9c0b2b-ef86-44d5-9726-c6194f341f2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378618906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clk
mgr_intr_test.378618906
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1789012709
Short name T828
Test name
Test status
Simulation time 11854277 ps
CPU time 0.66 seconds
Started Jul 29 07:06:23 PM PDT 24
Finished Jul 29 07:06:24 PM PDT 24
Peak memory 198900 kb
Host smart-f85a9e0d-cc26-435e-9b63-62e8575bd1b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789012709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1789012709
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.901365304
Short name T972
Test name
Test status
Simulation time 34102763 ps
CPU time 0.7 seconds
Started Jul 29 07:06:24 PM PDT 24
Finished Jul 29 07:06:25 PM PDT 24
Peak memory 198968 kb
Host smart-1108f1e0-8378-4711-b778-decd5d04ea66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901365304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.901365304
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.4203534612
Short name T887
Test name
Test status
Simulation time 31735389 ps
CPU time 0.68 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 198972 kb
Host smart-9a2f186f-0adf-4490-8ee7-94bd2b5249ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203534612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.4203534612
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.4168085382
Short name T962
Test name
Test status
Simulation time 25642409 ps
CPU time 0.69 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 199048 kb
Host smart-2d0cf67a-eb5f-42e9-a050-e9a759a248ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168085382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.4168085382
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.603651322
Short name T879
Test name
Test status
Simulation time 84576582 ps
CPU time 0.84 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 198996 kb
Host smart-550db5e9-cc2d-452c-a294-a6c365193788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603651322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk
mgr_intr_test.603651322
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.476089849
Short name T967
Test name
Test status
Simulation time 36783727 ps
CPU time 0.72 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 198972 kb
Host smart-62fc2bf5-5859-486d-8280-f04bc2b9780e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476089849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk
mgr_intr_test.476089849
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2381345601
Short name T825
Test name
Test status
Simulation time 14368654 ps
CPU time 0.69 seconds
Started Jul 29 07:06:32 PM PDT 24
Finished Jul 29 07:06:33 PM PDT 24
Peak memory 199012 kb
Host smart-2d98a0de-b2bf-41a5-ab7a-6d3c20e45fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381345601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.2381345601
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.345493027
Short name T890
Test name
Test status
Simulation time 16824471 ps
CPU time 0.66 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 198972 kb
Host smart-253d7585-cc90-49c0-a5d2-c03d77051888
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345493027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clk
mgr_intr_test.345493027
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1232093124
Short name T822
Test name
Test status
Simulation time 25569551 ps
CPU time 0.75 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 199012 kb
Host smart-ca7eafc2-8d8e-404d-814e-32cf14e67641
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232093124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.1232093124
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3122393255
Short name T84
Test name
Test status
Simulation time 86841118 ps
CPU time 1.67 seconds
Started Jul 29 07:05:56 PM PDT 24
Finished Jul 29 07:05:57 PM PDT 24
Peak memory 200592 kb
Host smart-bfecdbf8-b7bd-4bde-b7ca-3115a060e555
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122393255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3122393255
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1740423653
Short name T829
Test name
Test status
Simulation time 482250739 ps
CPU time 7.38 seconds
Started Jul 29 07:05:49 PM PDT 24
Finished Jul 29 07:05:56 PM PDT 24
Peak memory 200540 kb
Host smart-2ff5b8ae-c673-4799-b3d0-d02d954223e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740423653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1740423653
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.415095962
Short name T892
Test name
Test status
Simulation time 17285580 ps
CPU time 0.8 seconds
Started Jul 29 07:05:52 PM PDT 24
Finished Jul 29 07:05:53 PM PDT 24
Peak memory 200340 kb
Host smart-4c243f7b-6ede-4e94-9c5f-1569ed84d14d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415095962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.415095962
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1954577182
Short name T826
Test name
Test status
Simulation time 155161705 ps
CPU time 1.73 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 216904 kb
Host smart-db23ca87-c7db-41e5-a919-7a9b66567656
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954577182 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1954577182
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.2217286023
Short name T965
Test name
Test status
Simulation time 20592032 ps
CPU time 0.78 seconds
Started Jul 29 07:05:51 PM PDT 24
Finished Jul 29 07:05:51 PM PDT 24
Peak memory 200316 kb
Host smart-7656f964-c85e-438a-9871-df29363fdde2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217286023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.2217286023
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.716800866
Short name T964
Test name
Test status
Simulation time 19007542 ps
CPU time 0.68 seconds
Started Jul 29 07:05:48 PM PDT 24
Finished Jul 29 07:05:49 PM PDT 24
Peak memory 198968 kb
Host smart-e8488901-52ce-4654-a079-4eda13f799e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716800866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_intr_test.716800866
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.997758912
Short name T844
Test name
Test status
Simulation time 45955084 ps
CPU time 1.24 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200372 kb
Host smart-47f54304-3405-473a-8b9d-a3048be924ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997758912 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.clkmgr_same_csr_outstanding.997758912
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.849831168
Short name T140
Test name
Test status
Simulation time 195077184 ps
CPU time 1.58 seconds
Started Jul 29 07:05:48 PM PDT 24
Finished Jul 29 07:05:50 PM PDT 24
Peak memory 200628 kb
Host smart-eda1a33c-994a-41fc-8e3e-25b31757c347
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849831168 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.849831168
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3245378073
Short name T61
Test name
Test status
Simulation time 1728894333 ps
CPU time 6.66 seconds
Started Jul 29 07:05:50 PM PDT 24
Finished Jul 29 07:05:56 PM PDT 24
Peak memory 217172 kb
Host smart-d2e8fe01-674d-42c9-ae72-fe318ddf7896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245378073 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3245378073
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3325972123
Short name T855
Test name
Test status
Simulation time 83313422 ps
CPU time 1.62 seconds
Started Jul 29 07:05:48 PM PDT 24
Finished Jul 29 07:05:50 PM PDT 24
Peak memory 200568 kb
Host smart-4e53eb12-ec0f-4a20-b703-cdde27ca668c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325972123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3325972123
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1369718997
Short name T940
Test name
Test status
Simulation time 126571013 ps
CPU time 2.58 seconds
Started Jul 29 07:05:48 PM PDT 24
Finished Jul 29 07:05:50 PM PDT 24
Peak memory 200536 kb
Host smart-902871c3-4e6f-4315-8fa2-c91d1748a0cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369718997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1369718997
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.2538053379
Short name T842
Test name
Test status
Simulation time 28762329 ps
CPU time 0.69 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 198928 kb
Host smart-ef14b939-034b-46a8-b064-c692f2fc7cc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538053379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.2538053379
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1981396946
Short name T912
Test name
Test status
Simulation time 13749641 ps
CPU time 0.7 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 198968 kb
Host smart-0c5f3fb3-d5e1-4c62-b631-7fc6ea53aa34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981396946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.1981396946
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.2673708853
Short name T830
Test name
Test status
Simulation time 26946088 ps
CPU time 0.7 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 198900 kb
Host smart-0f4221e9-d6c3-414a-bf65-b274b8f73441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673708853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.2673708853
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.1431148971
Short name T891
Test name
Test status
Simulation time 20220358 ps
CPU time 0.65 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:29 PM PDT 24
Peak memory 199000 kb
Host smart-0fb73158-60a3-439a-a827-18af816baa11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431148971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.1431148971
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3538458028
Short name T941
Test name
Test status
Simulation time 25790414 ps
CPU time 0.68 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 198952 kb
Host smart-54968c93-46bd-4db1-8941-3b32c9b4d0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538458028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.3538458028
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3871781328
Short name T860
Test name
Test status
Simulation time 57047497 ps
CPU time 0.77 seconds
Started Jul 29 07:06:34 PM PDT 24
Finished Jul 29 07:06:35 PM PDT 24
Peak memory 198948 kb
Host smart-f27485c1-a2b8-4c5b-9a99-ebd0d99f5496
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871781328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.3871781328
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1609866267
Short name T976
Test name
Test status
Simulation time 35976063 ps
CPU time 0.7 seconds
Started Jul 29 07:06:31 PM PDT 24
Finished Jul 29 07:06:32 PM PDT 24
Peak memory 199040 kb
Host smart-80952b9a-230f-41a9-a88e-abe60cf3abbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609866267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.1609866267
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.715963673
Short name T859
Test name
Test status
Simulation time 15177456 ps
CPU time 0.68 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 198940 kb
Host smart-bc8c35a9-48c9-424f-a0ab-3dd603891a8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715963673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.715963673
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.777985962
Short name T948
Test name
Test status
Simulation time 23490187 ps
CPU time 0.68 seconds
Started Jul 29 07:06:30 PM PDT 24
Finished Jul 29 07:06:31 PM PDT 24
Peak memory 199012 kb
Host smart-55ef61a9-ceba-4e35-b50b-5fbcaadf266f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777985962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.777985962
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.499228883
Short name T866
Test name
Test status
Simulation time 10857180 ps
CPU time 0.68 seconds
Started Jul 29 07:06:29 PM PDT 24
Finished Jul 29 07:06:30 PM PDT 24
Peak memory 199012 kb
Host smart-da1150d2-2e98-4831-b096-847d57ac4c44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499228883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clk
mgr_intr_test.499228883
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3444518865
Short name T931
Test name
Test status
Simulation time 38516723 ps
CPU time 1.24 seconds
Started Jul 29 07:05:57 PM PDT 24
Finished Jul 29 07:05:58 PM PDT 24
Peak memory 200460 kb
Host smart-67a32ed8-4fef-468e-8efe-9271d2d7a702
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444518865 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.3444518865
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3556099705
Short name T959
Test name
Test status
Simulation time 46654427 ps
CPU time 0.83 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:05:59 PM PDT 24
Peak memory 200380 kb
Host smart-40b7cf08-8062-4b4f-89cf-1c11db4fe116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556099705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.3556099705
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4020056447
Short name T901
Test name
Test status
Simulation time 37874059 ps
CPU time 0.71 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:05:59 PM PDT 24
Peak memory 198900 kb
Host smart-b534c5a3-5a87-430e-9a74-82407c48ecc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020056447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.4020056447
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2076161764
Short name T952
Test name
Test status
Simulation time 95931192 ps
CPU time 1.4 seconds
Started Jul 29 07:06:00 PM PDT 24
Finished Jul 29 07:06:02 PM PDT 24
Peak memory 200560 kb
Host smart-366ffb88-6e8e-4409-918a-3e9683f350a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076161764 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2076161764
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1460240430
Short name T947
Test name
Test status
Simulation time 136419466 ps
CPU time 1.88 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200804 kb
Host smart-eeb5c5a4-e266-4405-87b9-d51103cacc52
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460240430 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1460240430
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1834356622
Short name T886
Test name
Test status
Simulation time 94896871 ps
CPU time 2.38 seconds
Started Jul 29 07:05:57 PM PDT 24
Finished Jul 29 07:05:59 PM PDT 24
Peak memory 201128 kb
Host smart-1d436035-73ce-4b5e-a83b-37ae34e9c77a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834356622 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1834356622
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.1016053504
Short name T877
Test name
Test status
Simulation time 33537498 ps
CPU time 2.02 seconds
Started Jul 29 07:06:01 PM PDT 24
Finished Jul 29 07:06:03 PM PDT 24
Peak memory 200596 kb
Host smart-ea1c2765-227d-44d4-bf18-57b9cdf14a35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016053504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.1016053504
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3676667089
Short name T864
Test name
Test status
Simulation time 28149004 ps
CPU time 1.34 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:05:59 PM PDT 24
Peak memory 200620 kb
Host smart-547d4628-abc0-4a68-9a4b-4101ed703c30
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676667089 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3676667089
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.3834838759
Short name T868
Test name
Test status
Simulation time 19074894 ps
CPU time 0.94 seconds
Started Jul 29 07:06:01 PM PDT 24
Finished Jul 29 07:06:02 PM PDT 24
Peak memory 200392 kb
Host smart-0b207827-c675-463f-9486-0891342b593e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834838759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.3834838759
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1009576843
Short name T870
Test name
Test status
Simulation time 42895286 ps
CPU time 0.7 seconds
Started Jul 29 07:05:57 PM PDT 24
Finished Jul 29 07:05:58 PM PDT 24
Peak memory 198928 kb
Host smart-7dd08e0c-f229-49a4-98c9-bdd02eb7e24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009576843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.1009576843
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.3581179611
Short name T881
Test name
Test status
Simulation time 41267079 ps
CPU time 1.31 seconds
Started Jul 29 07:06:00 PM PDT 24
Finished Jul 29 07:06:02 PM PDT 24
Peak memory 200584 kb
Host smart-7dac618c-3ccd-4a64-9f11-08979435260f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581179611 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.3581179611
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1077712359
Short name T143
Test name
Test status
Simulation time 439498694 ps
CPU time 2.23 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200536 kb
Host smart-a15be53b-ff6b-46bc-943c-e580c71a46a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077712359 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1077712359
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.122980304
Short name T911
Test name
Test status
Simulation time 457863134 ps
CPU time 3.42 seconds
Started Jul 29 07:05:57 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 208948 kb
Host smart-992b7df5-436d-45c2-80cb-ae5362f361ba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122980304 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.122980304
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.3361312608
Short name T840
Test name
Test status
Simulation time 83404674 ps
CPU time 2.81 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 200564 kb
Host smart-f94bf1df-e595-4cc6-8bb2-515b9f450269
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361312608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.3361312608
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.710713407
Short name T107
Test name
Test status
Simulation time 156227137 ps
CPU time 1.92 seconds
Started Jul 29 07:06:01 PM PDT 24
Finished Jul 29 07:06:03 PM PDT 24
Peak memory 200512 kb
Host smart-fd4f6e95-5d3e-48c8-9292-ac0a3bf447dc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710713407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_tl_intg_err.710713407
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2055002450
Short name T824
Test name
Test status
Simulation time 143795658 ps
CPU time 1.32 seconds
Started Jul 29 07:05:59 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200372 kb
Host smart-5f00aeae-288c-4cf7-a5bc-eb9b76136f4b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055002450 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.2055002450
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.93012437
Short name T929
Test name
Test status
Simulation time 29484092 ps
CPU time 0.86 seconds
Started Jul 29 07:05:59 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200372 kb
Host smart-80a09761-0a03-4d48-a66a-59066804c7c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93012437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.cl
kmgr_csr_rw.93012437
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1524260709
Short name T978
Test name
Test status
Simulation time 25495773 ps
CPU time 0.65 seconds
Started Jul 29 07:05:57 PM PDT 24
Finished Jul 29 07:05:58 PM PDT 24
Peak memory 198980 kb
Host smart-1a380712-089f-4e22-8b13-f6bc86b439f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524260709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.1524260709
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1419284761
Short name T944
Test name
Test status
Simulation time 96667735 ps
CPU time 1.47 seconds
Started Jul 29 07:06:00 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 200532 kb
Host smart-a86795b6-17cf-4c8a-ba92-fd5c2be8b309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419284761 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.1419284761
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3580476841
Short name T62
Test name
Test status
Simulation time 135739422 ps
CPU time 2.11 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 200816 kb
Host smart-35ed7794-0f5f-4a2a-a2ac-e5d9c32bf572
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580476841 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3580476841
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.615100335
Short name T946
Test name
Test status
Simulation time 126496413 ps
CPU time 1.91 seconds
Started Jul 29 07:05:59 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 209012 kb
Host smart-eaece021-dd5f-4f30-8bea-e4f6f8526a96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615100335 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.615100335
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3949688739
Short name T850
Test name
Test status
Simulation time 627766916 ps
CPU time 2.91 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 200448 kb
Host smart-36bae115-7aa3-48a7-8d00-cae7e4e67a84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949688739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.3949688739
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4249667920
Short name T846
Test name
Test status
Simulation time 78575836 ps
CPU time 1.63 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200632 kb
Host smart-4070cb58-8f0b-489d-b92d-92d37ab09de6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249667920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.4249667920
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4191410346
Short name T111
Test name
Test status
Simulation time 28737888 ps
CPU time 1.6 seconds
Started Jul 29 07:06:07 PM PDT 24
Finished Jul 29 07:06:09 PM PDT 24
Peak memory 200608 kb
Host smart-a340794b-d078-423c-98ed-e32a35684ff9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191410346 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.4191410346
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3303095512
Short name T930
Test name
Test status
Simulation time 17255556 ps
CPU time 0.83 seconds
Started Jul 29 07:06:05 PM PDT 24
Finished Jul 29 07:06:06 PM PDT 24
Peak memory 200356 kb
Host smart-282c34cf-131c-4b84-a3c1-c8d1cd58776d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303095512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3303095512
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3038478946
Short name T936
Test name
Test status
Simulation time 14578509 ps
CPU time 0.67 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:05:59 PM PDT 24
Peak memory 199056 kb
Host smart-d6c08c14-ebf6-4154-8eba-aeb5655940f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038478946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.3038478946
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.1974726464
Short name T960
Test name
Test status
Simulation time 98488263 ps
CPU time 1.39 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:08 PM PDT 24
Peak memory 200488 kb
Host smart-30ed945b-8ab4-4fd0-885b-bf8ca0c7827d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974726464 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.1974726464
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1425395860
Short name T133
Test name
Test status
Simulation time 128787556 ps
CPU time 2.21 seconds
Started Jul 29 07:05:59 PM PDT 24
Finished Jul 29 07:06:02 PM PDT 24
Peak memory 200800 kb
Host smart-f1154f01-099a-4e3f-9fa2-144b37dc2bdf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425395860 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1425395860
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.426787839
Short name T920
Test name
Test status
Simulation time 110512040 ps
CPU time 2.66 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:01 PM PDT 24
Peak memory 217220 kb
Host smart-1248c0f0-956b-4d94-9685-3a32574cc41b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426787839 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.426787839
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1892063363
Short name T836
Test name
Test status
Simulation time 39953591 ps
CPU time 1.23 seconds
Started Jul 29 07:05:59 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200372 kb
Host smart-7b91cd17-d4b0-4043-95e6-8291d122f3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892063363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.1892063363
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2379018594
Short name T114
Test name
Test status
Simulation time 287554113 ps
CPU time 2.16 seconds
Started Jul 29 07:05:58 PM PDT 24
Finished Jul 29 07:06:00 PM PDT 24
Peak memory 200544 kb
Host smart-3680d01f-364c-45ca-9859-b0bfb85075d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379018594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.2379018594
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.1473002822
Short name T980
Test name
Test status
Simulation time 118607727 ps
CPU time 1.44 seconds
Started Jul 29 07:06:08 PM PDT 24
Finished Jul 29 07:06:09 PM PDT 24
Peak memory 200676 kb
Host smart-1748ee56-4ab5-49c2-aaba-9f9787689ad9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473002822 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.1473002822
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3955016649
Short name T857
Test name
Test status
Simulation time 46476703 ps
CPU time 0.85 seconds
Started Jul 29 07:06:05 PM PDT 24
Finished Jul 29 07:06:06 PM PDT 24
Peak memory 200236 kb
Host smart-c2e7ddf0-fbe9-492b-a677-3bda8d0c6bf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955016649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3955016649
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2206219929
Short name T926
Test name
Test status
Simulation time 12897621 ps
CPU time 0.67 seconds
Started Jul 29 07:06:09 PM PDT 24
Finished Jul 29 07:06:09 PM PDT 24
Peak memory 199044 kb
Host smart-fd7c18f2-217d-441b-82f1-d650986d4e99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206219929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2206219929
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3390840585
Short name T935
Test name
Test status
Simulation time 389872253 ps
CPU time 2.27 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:08 PM PDT 24
Peak memory 200596 kb
Host smart-aee166cc-b113-4bd3-9328-86a865e2b575
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390840585 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.3390840585
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.3051866825
Short name T939
Test name
Test status
Simulation time 73016627 ps
CPU time 1.27 seconds
Started Jul 29 07:06:05 PM PDT 24
Finished Jul 29 07:06:06 PM PDT 24
Peak memory 200616 kb
Host smart-2cd51b36-dfb9-46b3-ae63-a30e744c8373
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051866825 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.3051866825
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1340503216
Short name T85
Test name
Test status
Simulation time 262328123 ps
CPU time 2.34 seconds
Started Jul 29 07:06:07 PM PDT 24
Finished Jul 29 07:06:09 PM PDT 24
Peak memory 209044 kb
Host smart-3a8c96bb-3d5c-4c08-8c2c-6a9cc580a96e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340503216 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1340503216
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1496133387
Short name T933
Test name
Test status
Simulation time 31167506 ps
CPU time 1.89 seconds
Started Jul 29 07:06:06 PM PDT 24
Finished Jul 29 07:06:08 PM PDT 24
Peak memory 200536 kb
Host smart-497fb480-b2aa-4621-864f-e091a0320965
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496133387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.1496133387
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3803640889
Short name T115
Test name
Test status
Simulation time 1737176716 ps
CPU time 7.09 seconds
Started Jul 29 07:06:07 PM PDT 24
Finished Jul 29 07:06:14 PM PDT 24
Peak memory 200616 kb
Host smart-96871623-8259-4b32-8d6a-0b3cb277e1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803640889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.3803640889
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.863236479
Short name T811
Test name
Test status
Simulation time 23801391 ps
CPU time 0.79 seconds
Started Jul 29 07:32:23 PM PDT 24
Finished Jul 29 07:32:24 PM PDT 24
Peak memory 200744 kb
Host smart-cbcc70fe-c8af-49c4-a118-f55847a31f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863236479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.863236479
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.2816573640
Short name T735
Test name
Test status
Simulation time 61856729 ps
CPU time 0.93 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201116 kb
Host smart-4a1d3096-776d-42d2-b11b-c86fae753d13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816573640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.2816573640
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2276648244
Short name T417
Test name
Test status
Simulation time 23052267 ps
CPU time 0.72 seconds
Started Jul 29 07:32:17 PM PDT 24
Finished Jul 29 07:32:18 PM PDT 24
Peak memory 200288 kb
Host smart-b6d0d5f5-ed30-4c10-aba8-d5895ef1a43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276648244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2276648244
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.3761529895
Short name T121
Test name
Test status
Simulation time 23618726 ps
CPU time 0.84 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201084 kb
Host smart-50327099-f65b-4abe-a321-055eab0e8f5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761529895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.3761529895
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.1472707190
Short name T431
Test name
Test status
Simulation time 16851117 ps
CPU time 0.77 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201060 kb
Host smart-0df881e5-96e0-4134-9760-8198f6151e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472707190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.1472707190
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.4277883852
Short name T778
Test name
Test status
Simulation time 2114177904 ps
CPU time 15.96 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 201244 kb
Host smart-87074f02-ed72-4095-babf-c47e0801f214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277883852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.4277883852
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.3340829976
Short name T634
Test name
Test status
Simulation time 1820597201 ps
CPU time 13.45 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201180 kb
Host smart-78c15eca-01cf-4850-8016-a81eae174bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340829976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.3340829976
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.169132466
Short name T787
Test name
Test status
Simulation time 103922331 ps
CPU time 1.18 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201080 kb
Host smart-481ddf33-a3ab-41ca-9c28-27eec9ad1939
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169132466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.169132466
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1878343779
Short name T189
Test name
Test status
Simulation time 18789075 ps
CPU time 0.77 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201096 kb
Host smart-13d6e65b-1c24-460b-9d1a-42a8116df5c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878343779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1878343779
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.729623657
Short name T92
Test name
Test status
Simulation time 36181816 ps
CPU time 0.73 seconds
Started Jul 29 07:32:17 PM PDT 24
Finished Jul 29 07:32:18 PM PDT 24
Peak memory 201080 kb
Host smart-43ce62cc-4704-4526-93e5-cddc0a50bd0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729623657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.729623657
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.2079041860
Short name T462
Test name
Test status
Simulation time 16649818 ps
CPU time 0.79 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201192 kb
Host smart-dd340482-1efa-4959-8eaf-e399ddf87f7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079041860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2079041860
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.2546024963
Short name T118
Test name
Test status
Simulation time 250491319 ps
CPU time 1.46 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201160 kb
Host smart-751d6652-c840-436b-9bea-fb39c29f5aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546024963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2546024963
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.685972189
Short name T57
Test name
Test status
Simulation time 346335576 ps
CPU time 2.35 seconds
Started Jul 29 07:32:18 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 216360 kb
Host smart-3c7848bc-79ba-4671-84d6-07eecd576f2f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685972189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.685972189
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.424169444
Short name T549
Test name
Test status
Simulation time 21209474 ps
CPU time 0.87 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201040 kb
Host smart-84591f67-a81a-4d2f-ab8e-4a290fcc9315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424169444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.424169444
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.911113297
Short name T309
Test name
Test status
Simulation time 2955310909 ps
CPU time 16.68 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:44 PM PDT 24
Peak memory 201420 kb
Host smart-b5fad75d-9e9a-4f17-a75b-14e92920343e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911113297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.911113297
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all_with_rand_reset.2069547904
Short name T765
Test name
Test status
Simulation time 65959611022 ps
CPU time 775.03 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:45:20 PM PDT 24
Peak memory 209752 kb
Host smart-66fe2321-a347-4e53-8075-9224411b097a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2069547904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.2069547904
Directory /workspace/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.clkmgr_trans.404448832
Short name T174
Test name
Test status
Simulation time 49091132 ps
CPU time 0.96 seconds
Started Jul 29 07:32:17 PM PDT 24
Finished Jul 29 07:32:18 PM PDT 24
Peak memory 201024 kb
Host smart-ec0bea3a-7057-4c0d-9cbe-9b0bac1fdc97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404448832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.404448832
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.657723456
Short name T814
Test name
Test status
Simulation time 59643961 ps
CPU time 0.86 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201080 kb
Host smart-cb6d03a0-ed45-4d1d-9542-6f33538cf552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657723456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_alert_test.657723456
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.204191644
Short name T631
Test name
Test status
Simulation time 86129657 ps
CPU time 1.03 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201080 kb
Host smart-8c6df811-94d6-4744-929c-b5c609e5276d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204191644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.204191644
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.3993813701
Short name T535
Test name
Test status
Simulation time 27036355 ps
CPU time 0.75 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 200272 kb
Host smart-ecd1e094-0caf-4bd4-b8da-c8d4a453d0d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993813701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3993813701
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2224759586
Short name T589
Test name
Test status
Simulation time 20210236 ps
CPU time 0.83 seconds
Started Jul 29 07:32:18 PM PDT 24
Finished Jul 29 07:32:19 PM PDT 24
Peak memory 201012 kb
Host smart-2c93825c-ecff-4848-80b3-48ad60f9677f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224759586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.2224759586
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.2566464688
Short name T612
Test name
Test status
Simulation time 24405334 ps
CPU time 0.82 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201088 kb
Host smart-943cff28-e7a6-46e3-842a-00ab84c44761
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566464688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.2566464688
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1797693324
Short name T464
Test name
Test status
Simulation time 1659197933 ps
CPU time 7.9 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201064 kb
Host smart-15604f53-a552-4ed2-8229-edd1bfd68def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797693324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1797693324
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.2447695540
Short name T395
Test name
Test status
Simulation time 859612182 ps
CPU time 5.68 seconds
Started Jul 29 07:32:18 PM PDT 24
Finished Jul 29 07:32:24 PM PDT 24
Peak memory 201140 kb
Host smart-081349f1-e513-4ba6-86a2-762662d5b907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447695540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.2447695540
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3217350162
Short name T259
Test name
Test status
Simulation time 81142777 ps
CPU time 0.96 seconds
Started Jul 29 07:32:22 PM PDT 24
Finished Jul 29 07:32:23 PM PDT 24
Peak memory 201080 kb
Host smart-9cf3dcf5-3398-41a9-9ff3-87ddb76082cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217350162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.3217350162
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.2991116139
Short name T491
Test name
Test status
Simulation time 242904210 ps
CPU time 1.49 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:22 PM PDT 24
Peak memory 201164 kb
Host smart-67c5c4f3-2e08-4dea-9048-8177f5fdfe1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991116139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.2991116139
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3590545555
Short name T486
Test name
Test status
Simulation time 23243200 ps
CPU time 0.83 seconds
Started Jul 29 07:32:23 PM PDT 24
Finished Jul 29 07:32:24 PM PDT 24
Peak memory 201152 kb
Host smart-c8cd7545-0ff4-4e93-9f6c-385225bec7be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590545555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.3590545555
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.596703049
Short name T284
Test name
Test status
Simulation time 19404917 ps
CPU time 0.8 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201088 kb
Host smart-aadbb629-6417-4e75-b6d3-eaa9a901a33c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596703049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.596703049
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.3898364878
Short name T784
Test name
Test status
Simulation time 537236576 ps
CPU time 2.36 seconds
Started Jul 29 07:32:17 PM PDT 24
Finished Jul 29 07:32:19 PM PDT 24
Peak memory 201060 kb
Host smart-23b48459-9d8c-4c42-b849-fd34923566ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898364878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3898364878
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.1845176666
Short name T45
Test name
Test status
Simulation time 298233397 ps
CPU time 3.2 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:24 PM PDT 24
Peak memory 221864 kb
Host smart-c1603efe-7e10-40dd-a58a-54b1891a6f8e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845176666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.1845176666
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.3821773038
Short name T317
Test name
Test status
Simulation time 20786947 ps
CPU time 0.85 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201016 kb
Host smart-16dd83a8-cc56-4ea6-8996-13ae1111dd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821773038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.3821773038
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_trans.3808849095
Short name T335
Test name
Test status
Simulation time 30008696 ps
CPU time 0.95 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201028 kb
Host smart-706e4d0f-c6f0-44b6-8077-4a71397f5634
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808849095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.3808849095
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.2244147181
Short name T383
Test name
Test status
Simulation time 34789772 ps
CPU time 0.8 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201292 kb
Host smart-60ab4f12-01fe-4ac4-86fa-b24cc9380e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244147181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.2244147181
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.1857337057
Short name T400
Test name
Test status
Simulation time 16916886 ps
CPU time 0.72 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 200260 kb
Host smart-d918b893-fc44-4927-92d4-92d335bb093c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857337057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.1857337057
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1671718148
Short name T467
Test name
Test status
Simulation time 38398516 ps
CPU time 0.91 seconds
Started Jul 29 07:32:42 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 201072 kb
Host smart-d6b9940f-b342-420a-b953-3919f1c23b9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671718148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1671718148
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.3531532769
Short name T621
Test name
Test status
Simulation time 42705495 ps
CPU time 0.83 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201068 kb
Host smart-e9d15753-26fe-43ff-8800-f9daefd8d792
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531532769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.3531532769
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3899858827
Short name T243
Test name
Test status
Simulation time 233808718 ps
CPU time 1.6 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 201132 kb
Host smart-c23831cf-74bb-499e-9cf2-bff1f3e6b42f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899858827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3899858827
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1146319485
Short name T292
Test name
Test status
Simulation time 616896828 ps
CPU time 4.94 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201212 kb
Host smart-6243cc97-be07-4788-8c6c-39c36cd17957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146319485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1146319485
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1958132083
Short name T231
Test name
Test status
Simulation time 110843408 ps
CPU time 1.03 seconds
Started Jul 29 07:32:50 PM PDT 24
Finished Jul 29 07:32:51 PM PDT 24
Peak memory 201032 kb
Host smart-c9b11c98-fafd-4bc8-9661-ed69737b4464
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958132083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.1958132083
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.809553407
Short name T596
Test name
Test status
Simulation time 33945770 ps
CPU time 0.78 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201052 kb
Host smart-d9e4610e-407f-486e-8b5b-d6922cf77dff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809553407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_clk_byp_req_intersig_mubi.809553407
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.202737809
Short name T371
Test name
Test status
Simulation time 17334077 ps
CPU time 0.77 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201108 kb
Host smart-6b855800-b74d-4031-80b6-4a57c7cd2e9b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202737809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.202737809
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.805273650
Short name T251
Test name
Test status
Simulation time 22668495 ps
CPU time 0.74 seconds
Started Jul 29 07:32:50 PM PDT 24
Finished Jul 29 07:32:51 PM PDT 24
Peak memory 201000 kb
Host smart-7bbb8945-4092-4a08-9689-89967b403554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805273650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.805273650
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.2015464313
Short name T152
Test name
Test status
Simulation time 821993196 ps
CPU time 3.57 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:44 PM PDT 24
Peak memory 201296 kb
Host smart-a66cdb5a-901e-4c6b-bfb0-4198372d43f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015464313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.2015464313
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.3540634886
Short name T796
Test name
Test status
Simulation time 20001276 ps
CPU time 0.83 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201064 kb
Host smart-c27071da-3dca-4057-9024-08c15b1b8d8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540634886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.3540634886
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.3608271142
Short name T470
Test name
Test status
Simulation time 10416449018 ps
CPU time 32.71 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:33:14 PM PDT 24
Peak memory 201476 kb
Host smart-e666c9c4-4bf4-43ea-a6b6-2b188dbb3a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608271142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.3608271142
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2054201181
Short name T227
Test name
Test status
Simulation time 116806118 ps
CPU time 1.23 seconds
Started Jul 29 07:32:51 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201024 kb
Host smart-762d33e3-0ecb-4fc8-a8cc-746db548e240
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054201181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2054201181
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1616855924
Short name T384
Test name
Test status
Simulation time 18987781 ps
CPU time 0.72 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201036 kb
Host smart-20a5d1eb-c6fe-4edf-9f8f-f69fff9eeb79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616855924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1616855924
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2782456962
Short name T277
Test name
Test status
Simulation time 83376121 ps
CPU time 1.06 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201072 kb
Host smart-93da1823-55e3-4e5d-8235-6406a58858bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782456962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2782456962
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.1392523025
Short name T166
Test name
Test status
Simulation time 25364094 ps
CPU time 0.72 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 200288 kb
Host smart-260f504e-2bda-4cbd-841e-1842fffc80b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392523025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1392523025
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3632462469
Short name T257
Test name
Test status
Simulation time 83663830 ps
CPU time 1.08 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201084 kb
Host smart-8d7bfc24-ebb7-4cbe-a866-e88709d3b8cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632462469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.3632462469
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2073398396
Short name T412
Test name
Test status
Simulation time 26492070 ps
CPU time 0.77 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201100 kb
Host smart-6ed096ab-d758-4661-8b25-1c9feb1d9ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073398396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2073398396
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1459882242
Short name T2
Test name
Test status
Simulation time 2002026966 ps
CPU time 15.99 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201424 kb
Host smart-47b9fdf5-76ab-4fec-a82a-ad2dceb86dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459882242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1459882242
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.868892296
Short name T536
Test name
Test status
Simulation time 2296061878 ps
CPU time 15.95 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:56 PM PDT 24
Peak memory 201328 kb
Host smart-f8a095f9-ceff-40b8-ba1a-3a39ab7202d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868892296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti
meout.868892296
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.1180512630
Short name T728
Test name
Test status
Simulation time 91309289 ps
CPU time 1.14 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201028 kb
Host smart-975b9d15-69fb-4b3b-86d8-b4ef40bb7708
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180512630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.1180512630
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.3719960485
Short name T742
Test name
Test status
Simulation time 61815588 ps
CPU time 0.9 seconds
Started Jul 29 07:32:42 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 201068 kb
Host smart-4f5af7e7-e3b8-42cb-961b-d18b276bdbe4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719960485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.3719960485
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2395801603
Short name T274
Test name
Test status
Simulation time 108116963 ps
CPU time 1.13 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201020 kb
Host smart-b783333d-b44b-4cb0-ab83-54085606b082
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395801603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.2395801603
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.1169057055
Short name T7
Test name
Test status
Simulation time 12460095 ps
CPU time 0.71 seconds
Started Jul 29 07:32:51 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201000 kb
Host smart-adb8c586-6987-4e45-9687-dad70b71664d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169057055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1169057055
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2841828122
Short name T36
Test name
Test status
Simulation time 133370565 ps
CPU time 1.33 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201092 kb
Host smart-5118f4d8-c668-4c05-ae30-e26f0c8e9428
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841828122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2841828122
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.666465940
Short name T29
Test name
Test status
Simulation time 42844679 ps
CPU time 0.93 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201060 kb
Host smart-3dabee05-4872-4253-8427-ce0e51e5436a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666465940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.666465940
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.949426356
Short name T565
Test name
Test status
Simulation time 8216472957 ps
CPU time 32.08 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201440 kb
Host smart-e8f2aad9-c0f5-461f-98a4-35ecef237256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949426356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.949426356
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.311438905
Short name T512
Test name
Test status
Simulation time 103376412 ps
CPU time 1.14 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201044 kb
Host smart-6d54c6ec-6b09-4bcc-8e0d-b288f585d851
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311438905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.311438905
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3879066148
Short name T816
Test name
Test status
Simulation time 32879164 ps
CPU time 0.89 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201096 kb
Host smart-e3b8aa53-1500-4004-b86b-81df94ce88fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879066148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3879066148
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.3576941663
Short name T324
Test name
Test status
Simulation time 21282364 ps
CPU time 0.7 seconds
Started Jul 29 07:32:43 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 200288 kb
Host smart-1d15501c-4bbd-4843-ad73-85cec1d6c0e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576941663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3576941663
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.824281739
Short name T306
Test name
Test status
Simulation time 77507393 ps
CPU time 1.03 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201132 kb
Host smart-7ef7e572-36ea-45cf-bbdb-bb74f843bd95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824281739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_div_intersig_mubi.824281739
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.890674471
Short name T739
Test name
Test status
Simulation time 53690359 ps
CPU time 0.98 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201140 kb
Host smart-f8534587-ee50-4413-8311-6b30a6ba8991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890674471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.890674471
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.3577564259
Short name T382
Test name
Test status
Simulation time 1400036497 ps
CPU time 11.12 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201140 kb
Host smart-884cc703-2cc4-4214-9463-20836df5d173
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577564259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3577564259
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2301796232
Short name T441
Test name
Test status
Simulation time 1990016781 ps
CPU time 7.45 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201136 kb
Host smart-ec5d7944-3d0b-4fac-bc1d-420f4f2ceec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301796232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2301796232
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.4090479143
Short name T714
Test name
Test status
Simulation time 34618518 ps
CPU time 1.04 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201080 kb
Host smart-a1feeca3-d1c0-4532-bab0-09d3761c15f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090479143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.4090479143
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.258671474
Short name T610
Test name
Test status
Simulation time 30594297 ps
CPU time 0.91 seconds
Started Jul 29 07:32:42 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 201064 kb
Host smart-b57be077-014b-465e-aa2b-a122cfea74e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258671474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.258671474
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3435488077
Short name T623
Test name
Test status
Simulation time 74960312 ps
CPU time 1.03 seconds
Started Jul 29 07:32:48 PM PDT 24
Finished Jul 29 07:32:49 PM PDT 24
Peak memory 201096 kb
Host smart-cfd5991c-b85b-4b36-bc16-1107599df2f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435488077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3435488077
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.2796374096
Short name T20
Test name
Test status
Simulation time 22775365 ps
CPU time 0.75 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201032 kb
Host smart-d453b23b-bed4-4be1-87a6-85391747a4b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796374096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2796374096
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.1295123824
Short name T566
Test name
Test status
Simulation time 843438425 ps
CPU time 5.03 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:51 PM PDT 24
Peak memory 201320 kb
Host smart-1a8bba75-2eb7-4eff-8566-f84a968e4874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295123824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1295123824
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.3032440597
Short name T354
Test name
Test status
Simulation time 24394614 ps
CPU time 0.91 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201036 kb
Host smart-4bdaba2f-7315-4d6b-af6c-fcae2d35dbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032440597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3032440597
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.587540506
Short name T217
Test name
Test status
Simulation time 8186138184 ps
CPU time 34.8 seconds
Started Jul 29 07:32:50 PM PDT 24
Finished Jul 29 07:33:25 PM PDT 24
Peak memory 201384 kb
Host smart-8d535ac9-8028-4791-91d5-512eca365d63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587540506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.587540506
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1074375872
Short name T628
Test name
Test status
Simulation time 40003914 ps
CPU time 0.98 seconds
Started Jul 29 07:32:44 PM PDT 24
Finished Jul 29 07:32:45 PM PDT 24
Peak memory 201096 kb
Host smart-36169dce-8d23-4024-a1de-a3b167dfd910
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074375872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1074375872
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.1705830261
Short name T672
Test name
Test status
Simulation time 32418642 ps
CPU time 0.89 seconds
Started Jul 29 07:32:52 PM PDT 24
Finished Jul 29 07:32:53 PM PDT 24
Peak memory 201096 kb
Host smart-8168259d-a0db-4935-8943-66bbe5be373b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705830261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.1705830261
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.687105166
Short name T520
Test name
Test status
Simulation time 86959659 ps
CPU time 1.07 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:49 PM PDT 24
Peak memory 201136 kb
Host smart-8ad332f2-e4ca-431c-a0b2-494dbd43a716
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687105166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.687105166
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.1945356470
Short name T18
Test name
Test status
Simulation time 15400638 ps
CPU time 0.73 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201012 kb
Host smart-6619b3e4-f753-4fcc-8201-965e5dc1340a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945356470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1945356470
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.4153042376
Short name T550
Test name
Test status
Simulation time 33163366 ps
CPU time 0.85 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201048 kb
Host smart-9a226f07-8dd6-439c-ae44-fa4937f70dab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153042376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.4153042376
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.705922681
Short name T246
Test name
Test status
Simulation time 18119522 ps
CPU time 0.81 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201044 kb
Host smart-87f3d982-8f57-4831-b9aa-2da3a47cc802
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705922681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.705922681
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.358721889
Short name T229
Test name
Test status
Simulation time 2393390988 ps
CPU time 9.93 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:57 PM PDT 24
Peak memory 201392 kb
Host smart-96b0d7ab-9a1b-4aad-ad46-2cc41daef627
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358721889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.358721889
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.4017642325
Short name T656
Test name
Test status
Simulation time 1597129268 ps
CPU time 6.62 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:53 PM PDT 24
Peak memory 201216 kb
Host smart-ac89d9e2-b1de-4107-a255-192e86a07251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017642325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.4017642325
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2990223021
Short name T518
Test name
Test status
Simulation time 72770476 ps
CPU time 0.91 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 200332 kb
Host smart-cf5eb5aa-a5d7-4aeb-940b-527ef74e1988
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990223021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.2990223021
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.508836061
Short name T574
Test name
Test status
Simulation time 63264616 ps
CPU time 0.95 seconds
Started Jul 29 07:32:54 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201072 kb
Host smart-5a6c8dc1-819a-4d8e-98c7-de2584b3bdcd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508836061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.508836061
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1226057370
Short name T422
Test name
Test status
Simulation time 38314848 ps
CPU time 0.8 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201052 kb
Host smart-20a502c6-2625-4989-a904-f300e6cf35ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226057370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1226057370
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.254220676
Short name T418
Test name
Test status
Simulation time 14424086 ps
CPU time 0.76 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201052 kb
Host smart-361024aa-02ec-4fb7-853d-25ab74537fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254220676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.254220676
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.818173397
Short name T709
Test name
Test status
Simulation time 497293872 ps
CPU time 2.62 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:56 PM PDT 24
Peak memory 201092 kb
Host smart-03f0bc90-7ef7-40c5-9d06-144cae56a9f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818173397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.818173397
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1820733359
Short name T587
Test name
Test status
Simulation time 17892965 ps
CPU time 0.86 seconds
Started Jul 29 07:32:44 PM PDT 24
Finished Jul 29 07:32:45 PM PDT 24
Peak memory 201040 kb
Host smart-9bde0cb0-1327-4c8f-837f-0715392be15b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820733359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1820733359
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.3311995332
Short name T344
Test name
Test status
Simulation time 2591357742 ps
CPU time 11.09 seconds
Started Jul 29 07:32:54 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201396 kb
Host smart-160097f7-803a-4047-acec-ec5fdda922da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311995332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.3311995332
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.98856241
Short name T370
Test name
Test status
Simulation time 52088257 ps
CPU time 1.14 seconds
Started Jul 29 07:32:55 PM PDT 24
Finished Jul 29 07:32:56 PM PDT 24
Peak memory 200952 kb
Host smart-38fcc44c-fc3f-4d0b-acbb-58e219cc513f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98856241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.98856241
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.4204856246
Short name T242
Test name
Test status
Simulation time 121365349 ps
CPU time 1.12 seconds
Started Jul 29 07:32:48 PM PDT 24
Finished Jul 29 07:32:49 PM PDT 24
Peak memory 201008 kb
Host smart-2937bd82-297b-468d-9cfc-a31ce1613c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204856246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.4204856246
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3616331663
Short name T346
Test name
Test status
Simulation time 40814338 ps
CPU time 0.98 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201088 kb
Host smart-4d34f955-4176-44b4-a413-16357568a687
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616331663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.3616331663
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.613808999
Short name T485
Test name
Test status
Simulation time 39811881 ps
CPU time 0.75 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 200296 kb
Host smart-cbded199-3004-4158-a897-7e092a3723f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613808999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.613808999
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.1829844626
Short name T261
Test name
Test status
Simulation time 113003909 ps
CPU time 1.12 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201096 kb
Host smart-36a8c23c-d3e9-47ba-af63-0784da2d3a1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829844626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.1829844626
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.2274284816
Short name T322
Test name
Test status
Simulation time 93659936 ps
CPU time 1.01 seconds
Started Jul 29 07:32:50 PM PDT 24
Finished Jul 29 07:32:51 PM PDT 24
Peak memory 200980 kb
Host smart-0cc8fa3e-62a9-444a-8d51-cdfc09a7a2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274284816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2274284816
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.4063491800
Short name T214
Test name
Test status
Simulation time 2592321134 ps
CPU time 11.83 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:57 PM PDT 24
Peak memory 201336 kb
Host smart-cb91e0a9-2d37-4016-b5a5-0c0e2ff97517
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063491800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.4063491800
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.4256457711
Short name T361
Test name
Test status
Simulation time 1579472604 ps
CPU time 11.73 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201216 kb
Host smart-e077f37e-31d4-4e3a-b0d2-249be1041dda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256457711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.4256457711
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.1397332571
Short name T705
Test name
Test status
Simulation time 51644057 ps
CPU time 1.08 seconds
Started Jul 29 07:32:55 PM PDT 24
Finished Jul 29 07:32:56 PM PDT 24
Peak memory 200940 kb
Host smart-aabdf50e-9aba-4d7e-b0fa-8b71eacce6e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397332571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.1397332571
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.4161573621
Short name T432
Test name
Test status
Simulation time 93562205 ps
CPU time 0.94 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201076 kb
Host smart-c113444d-c46a-40d7-a45f-7692f68b1f9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161573621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.4161573621
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3446907968
Short name T205
Test name
Test status
Simulation time 22092609 ps
CPU time 0.76 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201004 kb
Host smart-b0c74ad5-9d10-41de-aef5-9ae46efb231b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446907968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3446907968
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.948216521
Short name T268
Test name
Test status
Simulation time 17792613 ps
CPU time 0.81 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 200992 kb
Host smart-b4f6acdc-f267-4a1c-b2a1-63e8f28e253d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948216521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.948216521
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.2885120473
Short name T583
Test name
Test status
Simulation time 54898359 ps
CPU time 0.98 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201056 kb
Host smart-6e98813e-91f0-4969-bb11-e49f196a67ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885120473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.2885120473
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2598300781
Short name T347
Test name
Test status
Simulation time 7738627589 ps
CPU time 56.65 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 201484 kb
Host smart-4f989f69-13ec-41c0-bee8-1753e1adfbad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598300781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2598300781
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.4106193041
Short name T625
Test name
Test status
Simulation time 38010021 ps
CPU time 0.85 seconds
Started Jul 29 07:32:54 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201044 kb
Host smart-7ef8dfa8-91a0-46a8-8d1f-58f1b5c88e23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106193041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.4106193041
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1898696654
Short name T667
Test name
Test status
Simulation time 15652376 ps
CPU time 0.75 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201096 kb
Host smart-248cdc6f-8a53-43d3-8ee1-ae60b8ed938a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898696654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1898696654
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.801513363
Short name T754
Test name
Test status
Simulation time 37044890 ps
CPU time 0.93 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201112 kb
Host smart-6703bd1a-be90-4fe7-a6a8-bf2e3da45507
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801513363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.801513363
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.2015081868
Short name T258
Test name
Test status
Simulation time 36533249 ps
CPU time 0.83 seconds
Started Jul 29 07:32:55 PM PDT 24
Finished Jul 29 07:32:56 PM PDT 24
Peak memory 200872 kb
Host smart-4c785864-a64d-4e0c-96c9-9054d548c7dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015081868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2015081868
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.2036490936
Short name T411
Test name
Test status
Simulation time 75525774 ps
CPU time 0.91 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 200936 kb
Host smart-014bde2d-b4f6-401c-998d-4d1388d764f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036490936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.2036490936
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1212793866
Short name T232
Test name
Test status
Simulation time 24308968 ps
CPU time 0.84 seconds
Started Jul 29 07:32:51 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201120 kb
Host smart-195ead82-8c17-473e-ad75-821471c518db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212793866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1212793866
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.2057815354
Short name T645
Test name
Test status
Simulation time 2545441767 ps
CPU time 11.19 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201412 kb
Host smart-f65edb7b-adb0-4102-863e-8825e55e796a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057815354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2057815354
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.2157091213
Short name T387
Test name
Test status
Simulation time 1345715731 ps
CPU time 7.3 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201224 kb
Host smart-f28c20ce-59bc-4bd7-b51d-84b8312e22e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157091213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.2157091213
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.3855652955
Short name T776
Test name
Test status
Simulation time 40553652 ps
CPU time 0.97 seconds
Started Jul 29 07:32:54 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201088 kb
Host smart-c484b7fa-e123-4d68-af94-c2485bcce380
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855652955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.3855652955
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1608375087
Short name T454
Test name
Test status
Simulation time 20582497 ps
CPU time 0.83 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201064 kb
Host smart-ea0f5651-4a15-4b6a-aaa7-d97b4e724894
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608375087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.1608375087
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.168454936
Short name T703
Test name
Test status
Simulation time 43581297 ps
CPU time 0.95 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201036 kb
Host smart-fc9ca200-97cc-4bb6-9858-d89fa0ba526a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168454936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_ctrl_intersig_mubi.168454936
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.2515727974
Short name T815
Test name
Test status
Simulation time 29266670 ps
CPU time 0.8 seconds
Started Jul 29 07:32:47 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 200324 kb
Host smart-ac9d8c1b-3594-49d4-baa9-73be54fd1d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515727974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2515727974
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.918269135
Short name T542
Test name
Test status
Simulation time 911823840 ps
CPU time 4.39 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:57 PM PDT 24
Peak memory 201260 kb
Host smart-f75e39a6-ae83-4833-8423-da921a5f2a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918269135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.918269135
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1698476092
Short name T523
Test name
Test status
Simulation time 33897143 ps
CPU time 0.91 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201064 kb
Host smart-d3903262-dc2e-4040-a0d3-ba5976de3960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698476092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1698476092
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.584477603
Short name T640
Test name
Test status
Simulation time 5818462642 ps
CPU time 18.2 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:18 PM PDT 24
Peak memory 201460 kb
Host smart-71f1807f-a6d3-4a5e-bbdc-442cc596c636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584477603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.584477603
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.639805333
Short name T819
Test name
Test status
Simulation time 51984061 ps
CPU time 0.93 seconds
Started Jul 29 07:32:53 PM PDT 24
Finished Jul 29 07:32:54 PM PDT 24
Peak memory 201068 kb
Host smart-1d2902b8-46a3-475f-a67c-e5ad6085f109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639805333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.639805333
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.2092892210
Short name T601
Test name
Test status
Simulation time 19722657 ps
CPU time 0.75 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201100 kb
Host smart-fb8a04b7-8136-4ea0-aa3a-b97cac3d25f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092892210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.2092892210
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1195627488
Short name T580
Test name
Test status
Simulation time 81951032 ps
CPU time 0.97 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 201048 kb
Host smart-13e5eccd-5782-46e5-b6c8-e3b3ddc1dcf4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195627488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.1195627488
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2452079560
Short name T772
Test name
Test status
Simulation time 23540803 ps
CPU time 0.84 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 200948 kb
Host smart-3162f956-a289-4676-9fee-3a7fa04fefdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452079560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2452079560
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.2988531875
Short name T597
Test name
Test status
Simulation time 17914822 ps
CPU time 0.78 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 201068 kb
Host smart-9bcdfe17-4d9a-4bc9-abb3-2aab1bf242d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988531875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.2988531875
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.864948545
Short name T262
Test name
Test status
Simulation time 18344447 ps
CPU time 0.79 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 201072 kb
Host smart-bbad118c-d467-4bb0-bf91-2b895cf422f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864948545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.864948545
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.2949811150
Short name T318
Test name
Test status
Simulation time 968327402 ps
CPU time 4.88 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201144 kb
Host smart-1eaaa1a2-b95e-4e84-8c43-46890c5e4349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949811150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2949811150
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.4092811607
Short name T603
Test name
Test status
Simulation time 635447483 ps
CPU time 3.18 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201164 kb
Host smart-9cf05236-0407-4a22-b9b5-101630ca7c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092811607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.4092811607
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2283385577
Short name T30
Test name
Test status
Simulation time 49374892 ps
CPU time 0.98 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:01 PM PDT 24
Peak memory 201088 kb
Host smart-be565208-ba77-450c-a24c-9fceef14b4e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283385577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2283385577
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.3079462587
Short name T818
Test name
Test status
Simulation time 25967154 ps
CPU time 0.8 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201068 kb
Host smart-0fb8bc63-f3ea-4219-b309-bd170a9b40ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079462587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.3079462587
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.2690661756
Short name T177
Test name
Test status
Simulation time 63060891 ps
CPU time 1 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:01 PM PDT 24
Peak memory 201040 kb
Host smart-69c468e1-93fe-4d2c-bede-87a0e103cb68
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690661756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.2690661756
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.1069501336
Short name T171
Test name
Test status
Simulation time 19616253 ps
CPU time 0.79 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201072 kb
Host smart-390ca7a0-78e6-40d8-a48f-d1e5adcb9309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069501336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1069501336
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.1278469322
Short name T617
Test name
Test status
Simulation time 1361682785 ps
CPU time 5.32 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201280 kb
Host smart-9a9ae9f3-aa82-47ca-b183-b86aae514ffc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278469322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1278469322
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.4220980023
Short name T294
Test name
Test status
Simulation time 18285348 ps
CPU time 0.8 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 200996 kb
Host smart-2fcfcbea-34fd-4223-83bd-d0282b8a7f68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220980023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.4220980023
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.2823661652
Short name T490
Test name
Test status
Simulation time 11449455920 ps
CPU time 42.46 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201492 kb
Host smart-2744c9f2-c2b5-4d5f-9a8a-7788fb450005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823661652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.2823661652
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.1720285668
Short name T209
Test name
Test status
Simulation time 37159253 ps
CPU time 0.77 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 200984 kb
Host smart-c0c99e83-456d-401f-8458-9c4e60eb1b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720285668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1720285668
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.369372465
Short name T320
Test name
Test status
Simulation time 14643517 ps
CPU time 0.71 seconds
Started Jul 29 07:32:57 PM PDT 24
Finished Jul 29 07:32:58 PM PDT 24
Peak memory 201084 kb
Host smart-dff8e8cd-2b0d-467d-889d-2436ae84f952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369372465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkm
gr_alert_test.369372465
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3039509510
Short name T101
Test name
Test status
Simulation time 388366264 ps
CPU time 2.01 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201088 kb
Host smart-1a96a54c-2c88-4a07-bb6e-d2276b49c74c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039509510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.3039509510
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1544487812
Short name T158
Test name
Test status
Simulation time 17863858 ps
CPU time 0.7 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 200184 kb
Host smart-efdb22c6-422f-434e-a015-e7b543a02180
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544487812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1544487812
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.2859862707
Short name T510
Test name
Test status
Simulation time 21231897 ps
CPU time 0.81 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 201084 kb
Host smart-72e7739c-09a9-4b8b-88a3-2c9b5aee0c8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859862707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.2859862707
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.2758158079
Short name T595
Test name
Test status
Simulation time 20305474 ps
CPU time 0.78 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201060 kb
Host smart-5fc2b25e-7430-47ae-a01d-62c162744849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758158079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2758158079
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3615986414
Short name T578
Test name
Test status
Simulation time 197911595 ps
CPU time 2.36 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201124 kb
Host smart-7bc665f6-292d-4412-b226-a8d26a7ca394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615986414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3615986414
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.90567752
Short name T399
Test name
Test status
Simulation time 31071214 ps
CPU time 1.01 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:02 PM PDT 24
Peak memory 201080 kb
Host smart-65eacdc2-3352-4090-a2e2-b93a26b64514
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90567752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.clkmgr_idle_intersig_mubi.90567752
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1860079691
Short name T553
Test name
Test status
Simulation time 33797209 ps
CPU time 0.88 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201020 kb
Host smart-973cc245-13c4-489d-a6a1-77b2c4a8aa7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860079691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.1860079691
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1765256198
Short name T150
Test name
Test status
Simulation time 89429191 ps
CPU time 1.09 seconds
Started Jul 29 07:33:02 PM PDT 24
Finished Jul 29 07:33:04 PM PDT 24
Peak memory 201004 kb
Host smart-a089a85c-be5e-4116-b5d2-821bbe8135ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765256198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.1765256198
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.3201464440
Short name T385
Test name
Test status
Simulation time 13883892 ps
CPU time 0.73 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201136 kb
Host smart-62e78896-fbd7-497b-8243-112d14601a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201464440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3201464440
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.3172592076
Short name T192
Test name
Test status
Simulation time 1043016323 ps
CPU time 5.78 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:33:04 PM PDT 24
Peak memory 201276 kb
Host smart-71accdae-6022-46ec-a102-469d015a63c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172592076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3172592076
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.1198034557
Short name T527
Test name
Test status
Simulation time 46069953 ps
CPU time 0.89 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201040 kb
Host smart-c779947a-a85d-4441-a6c4-50513e673520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198034557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1198034557
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2551237915
Short name T3
Test name
Test status
Simulation time 10045526388 ps
CPU time 71.45 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:34:09 PM PDT 24
Peak memory 201472 kb
Host smart-c4d325b9-1a49-4d94-8e56-707bfef7304b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551237915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2551237915
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.3191068491
Short name T331
Test name
Test status
Simulation time 22250521 ps
CPU time 0.87 seconds
Started Jul 29 07:33:02 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201024 kb
Host smart-5746e8f5-d38e-479f-bd26-c057ebe5081e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191068491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3191068491
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2768149204
Short name T341
Test name
Test status
Simulation time 28189266 ps
CPU time 0.86 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201100 kb
Host smart-c08ead44-78ce-45ae-a471-c474c07762ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768149204 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2768149204
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.568685891
Short name T22
Test name
Test status
Simulation time 19137555 ps
CPU time 0.82 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:01 PM PDT 24
Peak memory 201040 kb
Host smart-047936f2-1c16-4ae4-8fab-a9a2483078a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568685891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.568685891
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.3443772539
Short name T469
Test name
Test status
Simulation time 31061303 ps
CPU time 0.72 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 200148 kb
Host smart-d73f610a-0e28-4bb3-bfb8-a08f1a3822be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443772539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.3443772539
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.99813927
Short name T544
Test name
Test status
Simulation time 19243092 ps
CPU time 0.78 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201004 kb
Host smart-553a60e7-1e58-48b5-8169-d3311de31eab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99813927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.clkmgr_div_intersig_mubi.99813927
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.4149072079
Short name T722
Test name
Test status
Simulation time 14511820 ps
CPU time 0.82 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201260 kb
Host smart-982d9ae8-2e7d-481c-8f63-2e28edf13069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149072079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.4149072079
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1113269733
Short name T586
Test name
Test status
Simulation time 2362228856 ps
CPU time 17.58 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:19 PM PDT 24
Peak memory 201324 kb
Host smart-a61b918e-59f4-4208-a9b6-efd186c3889c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113269733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1113269733
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.3688160011
Short name T34
Test name
Test status
Simulation time 376260692 ps
CPU time 3.18 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:15 PM PDT 24
Peak memory 201056 kb
Host smart-6b781d4a-4cd9-4e0a-8750-d12bf0ec93ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688160011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.3688160011
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.3608567215
Short name T694
Test name
Test status
Simulation time 29943454 ps
CPU time 0.99 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201012 kb
Host smart-236c1af3-c8ad-489a-a68d-e521f7fa2187
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608567215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.3608567215
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.278785523
Short name T414
Test name
Test status
Simulation time 103992745 ps
CPU time 1.19 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201120 kb
Host smart-0b2e9575-9c19-40f8-89cc-bbaa727aba20
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278785523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.clkmgr_lc_clk_byp_req_intersig_mubi.278785523
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3494927942
Short name T273
Test name
Test status
Simulation time 20568235 ps
CPU time 0.78 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 201280 kb
Host smart-a8287ac9-7650-40e8-a8b0-12b8e02bc0ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494927942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.3494927942
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.321406907
Short name T797
Test name
Test status
Simulation time 18049964 ps
CPU time 0.8 seconds
Started Jul 29 07:33:02 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 200992 kb
Host smart-ddc41a9b-e5ab-4b0a-808a-b0e7ee11b4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321406907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.321406907
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.1932321041
Short name T342
Test name
Test status
Simulation time 148880400 ps
CPU time 1.22 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201000 kb
Host smart-d1620a2a-5a16-4f43-8abb-4574751c9f5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932321041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.1932321041
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2517097093
Short name T126
Test name
Test status
Simulation time 22246825 ps
CPU time 0.88 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:00 PM PDT 24
Peak memory 201060 kb
Host smart-c249c986-ebed-4509-b2f9-b4c8ba963368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517097093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2517097093
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.4235338310
Short name T768
Test name
Test status
Simulation time 4112419504 ps
CPU time 16.88 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201464 kb
Host smart-c618459f-4a6f-499c-a0e2-7ff339fd7c75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235338310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.4235338310
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.343687998
Short name T235
Test name
Test status
Simulation time 54753148 ps
CPU time 1.07 seconds
Started Jul 29 07:32:59 PM PDT 24
Finished Jul 29 07:33:01 PM PDT 24
Peak memory 201252 kb
Host smart-564ae35b-cb1d-4eda-b918-10336271a279
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343687998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.343687998
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3657660612
Short name T757
Test name
Test status
Simulation time 17420623 ps
CPU time 0.8 seconds
Started Jul 29 07:33:07 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 201076 kb
Host smart-4f350e67-1161-4d01-bef9-f0016e3cac50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657660612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3657660612
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2077529610
Short name T201
Test name
Test status
Simulation time 27123596 ps
CPU time 0.94 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201088 kb
Host smart-fc3636f1-d6fc-4a60-8763-33d0b3e9b86b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077529610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.2077529610
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.2899566817
Short name T522
Test name
Test status
Simulation time 13733088 ps
CPU time 0.71 seconds
Started Jul 29 07:32:58 PM PDT 24
Finished Jul 29 07:32:59 PM PDT 24
Peak memory 200320 kb
Host smart-3e3e65b6-7dc6-41ed-8031-ac56654dcb8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899566817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.2899566817
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1523176848
Short name T641
Test name
Test status
Simulation time 44031067 ps
CPU time 0.99 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201080 kb
Host smart-3d97f5d8-7d0e-465f-8e68-1dbdf0cb16c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523176848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1523176848
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.3874602155
Short name T452
Test name
Test status
Simulation time 79053900 ps
CPU time 1.06 seconds
Started Jul 29 07:33:06 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201068 kb
Host smart-771ffc70-a305-4e7e-90ba-fe03c57a0db6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874602155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3874602155
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.391998261
Short name T267
Test name
Test status
Simulation time 486386531 ps
CPU time 2.69 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201172 kb
Host smart-5cf7ff89-ea73-4b18-b649-d1be0910c493
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391998261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.391998261
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1048955944
Short name T627
Test name
Test status
Simulation time 1291679729 ps
CPU time 5.19 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201132 kb
Host smart-b4104636-56d2-41db-8984-d3945c636d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048955944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1048955944
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2325870417
Short name T473
Test name
Test status
Simulation time 27217480 ps
CPU time 0.9 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201012 kb
Host smart-d84b1def-310e-435d-894f-a547fb19d89b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325870417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.2325870417
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2763855666
Short name T290
Test name
Test status
Simulation time 13347729 ps
CPU time 0.75 seconds
Started Jul 29 07:33:03 PM PDT 24
Finished Jul 29 07:33:04 PM PDT 24
Peak memory 201076 kb
Host smart-d182831e-0b05-4adf-8c04-ed949b7abe4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763855666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2763855666
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3552628433
Short name T653
Test name
Test status
Simulation time 97614414 ps
CPU time 1.04 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201076 kb
Host smart-eb79e209-1935-4b21-91a6-fb4f54d68837
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552628433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.3552628433
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1694911609
Short name T647
Test name
Test status
Simulation time 19103108 ps
CPU time 0.78 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201008 kb
Host smart-b499db9d-8cd8-4791-a6e2-a3aa537fb038
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694911609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1694911609
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2145773976
Short name T607
Test name
Test status
Simulation time 944428961 ps
CPU time 3.77 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 201264 kb
Host smart-176f1914-6c2d-4b44-8a3c-6b408be1b082
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145773976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2145773976
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2507518761
Short name T148
Test name
Test status
Simulation time 40139866 ps
CPU time 0.89 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:02 PM PDT 24
Peak memory 201032 kb
Host smart-033a84bb-45ac-4950-aa4c-78c666cf28a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507518761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2507518761
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.2941082968
Short name T208
Test name
Test status
Simulation time 4667589217 ps
CPU time 20.48 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:29 PM PDT 24
Peak memory 201428 kb
Host smart-36553cff-1b13-4e4c-bf51-a755d698b153
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941082968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.2941082968
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.1357598776
Short name T67
Test name
Test status
Simulation time 116334617411 ps
CPU time 716.48 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:45:12 PM PDT 24
Peak memory 217776 kb
Host smart-11cde145-8080-4bf0-adfc-96f5581e9001
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1357598776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.1357598776
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.4067831653
Short name T298
Test name
Test status
Simulation time 30571784 ps
CPU time 0.97 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201012 kb
Host smart-f4b3fff5-a8f4-410b-8a0a-ffffb2c17290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067831653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.4067831653
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.1091103187
Short name T442
Test name
Test status
Simulation time 41304246 ps
CPU time 0.8 seconds
Started Jul 29 07:32:17 PM PDT 24
Finished Jul 29 07:32:18 PM PDT 24
Peak memory 201036 kb
Host smart-0ae6ca90-91d8-4a66-9911-a182b682f3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091103187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.1091103187
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1503201961
Short name T278
Test name
Test status
Simulation time 81163364 ps
CPU time 0.98 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201072 kb
Host smart-3fe8421a-0c44-457a-933a-1f57b8b7d567
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503201961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1503201961
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.3576149968
Short name T785
Test name
Test status
Simulation time 20744423 ps
CPU time 0.72 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 200992 kb
Host smart-69961b70-e3c4-4199-b760-988eed5a425a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576149968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.3576149968
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.4157781606
Short name T732
Test name
Test status
Simulation time 31925940 ps
CPU time 0.87 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 200420 kb
Host smart-349cdcd3-4a9e-4753-b518-6c0ba58ffb99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157781606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.4157781606
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.2963560860
Short name T556
Test name
Test status
Simulation time 40392773 ps
CPU time 0.96 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:22 PM PDT 24
Peak memory 201032 kb
Host smart-e8887846-1c8d-49d9-abe6-d011cad8befd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963560860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2963560860
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1064000367
Short name T340
Test name
Test status
Simulation time 1035290098 ps
CPU time 8.43 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201064 kb
Host smart-cffab2c1-6f7f-44cd-9805-5cd3403f8462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064000367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1064000367
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.814011554
Short name T444
Test name
Test status
Simulation time 1337561500 ps
CPU time 9.17 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201396 kb
Host smart-278d1305-04f8-424b-8d98-2b2b855bb6f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814011554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim
eout.814011554
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.614237264
Short name T423
Test name
Test status
Simulation time 50120135 ps
CPU time 0.87 seconds
Started Jul 29 07:32:22 PM PDT 24
Finished Jul 29 07:32:23 PM PDT 24
Peak memory 201084 kb
Host smart-efa58012-c679-42fb-92ee-d73983b78cd2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614237264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_idle_intersig_mubi.614237264
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2308578334
Short name T304
Test name
Test status
Simulation time 31125040 ps
CPU time 0.83 seconds
Started Jul 29 07:32:20 PM PDT 24
Finished Jul 29 07:32:21 PM PDT 24
Peak memory 201164 kb
Host smart-e6c98c34-d86c-434c-b535-5ee92f03a822
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308578334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2308578334
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2330029018
Short name T427
Test name
Test status
Simulation time 18025415 ps
CPU time 0.77 seconds
Started Jul 29 07:32:23 PM PDT 24
Finished Jul 29 07:32:24 PM PDT 24
Peak memory 200592 kb
Host smart-95399c76-710c-4ca7-8b1c-58b3bfbd9fe1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330029018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.2330029018
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2766564460
Short name T397
Test name
Test status
Simulation time 47812846 ps
CPU time 0.8 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 201072 kb
Host smart-32b3c2c8-ede3-4ced-878f-cb28ddcc9f9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766564460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2766564460
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1670926436
Short name T789
Test name
Test status
Simulation time 806830564 ps
CPU time 2.83 seconds
Started Jul 29 07:32:23 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 201264 kb
Host smart-944fef0d-1566-4bb0-8e90-b1c9b1333d16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670926436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1670926436
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.1349058118
Short name T55
Test name
Test status
Simulation time 413392939 ps
CPU time 2.68 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 220620 kb
Host smart-199a0f0a-6c50-480b-b27b-b9a929c02d4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349058118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.1349058118
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.1412823066
Short name T594
Test name
Test status
Simulation time 35143512 ps
CPU time 0.86 seconds
Started Jul 29 07:32:18 PM PDT 24
Finished Jul 29 07:32:19 PM PDT 24
Peak memory 200932 kb
Host smart-37b35462-2468-45c5-9ab2-7d04bbff321c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412823066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.1412823066
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.400334458
Short name T608
Test name
Test status
Simulation time 2646080868 ps
CPU time 19.23 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201388 kb
Host smart-0a9b85b8-81c0-4871-a10b-a560838c9791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400334458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.400334458
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.578707755
Short name T401
Test name
Test status
Simulation time 19330714 ps
CPU time 0.79 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201080 kb
Host smart-9d62980b-c1c7-40a8-81c3-dfc6a1564bc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578707755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.578707755
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.425916648
Short name T555
Test name
Test status
Simulation time 22994604 ps
CPU time 0.76 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:01 PM PDT 24
Peak memory 201044 kb
Host smart-53d6a3fc-153f-4f6a-b457-c4c604a702be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425916648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkm
gr_alert_test.425916648
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3854530207
Short name T93
Test name
Test status
Simulation time 48329010 ps
CPU time 0.97 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201040 kb
Host smart-049abb3a-55c9-4eef-9138-b0c610b0d33a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854530207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.3854530207
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.734962305
Short name T379
Test name
Test status
Simulation time 45484572 ps
CPU time 0.8 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 200680 kb
Host smart-25ffdbee-5907-49a1-9aa0-ec75f05e13ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734962305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.734962305
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.1814838532
Short name T500
Test name
Test status
Simulation time 112589877 ps
CPU time 1.05 seconds
Started Jul 29 07:33:06 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201080 kb
Host smart-d9d56bf1-abbf-41d1-9129-b1d21849abdb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814838532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.1814838532
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3450754917
Short name T333
Test name
Test status
Simulation time 25770400 ps
CPU time 0.83 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:15 PM PDT 24
Peak memory 200916 kb
Host smart-e4eed6c2-1980-464f-a6cc-eb5188c70c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450754917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3450754917
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1309697967
Short name T539
Test name
Test status
Simulation time 678644109 ps
CPU time 3.04 seconds
Started Jul 29 07:33:00 PM PDT 24
Finished Jul 29 07:33:03 PM PDT 24
Peak memory 201148 kb
Host smart-c20c134a-f03b-44e6-aab6-07605c9635f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309697967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1309697967
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.429032398
Short name T175
Test name
Test status
Simulation time 2067352278 ps
CPU time 10.89 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 200948 kb
Host smart-606d87d4-2daf-43b2-a819-77b9e0e0fcbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429032398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti
meout.429032398
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.2102464357
Short name T646
Test name
Test status
Simulation time 20706084 ps
CPU time 0.82 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:05 PM PDT 24
Peak memory 201068 kb
Host smart-eb7abaca-7233-4c7c-bbf3-495662b8d781
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102464357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.2102464357
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.859570782
Short name T367
Test name
Test status
Simulation time 43953074 ps
CPU time 0.79 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201028 kb
Host smart-054ad527-b571-4607-894a-798fddfa39e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859570782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_clk_byp_req_intersig_mubi.859570782
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.979983201
Short name T662
Test name
Test status
Simulation time 21657259 ps
CPU time 0.93 seconds
Started Jul 29 07:33:03 PM PDT 24
Finished Jul 29 07:33:04 PM PDT 24
Peak memory 201044 kb
Host smart-45805438-2dab-410d-8b2d-ffd5eb617433
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979983201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_ctrl_intersig_mubi.979983201
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.2182080117
Short name T254
Test name
Test status
Simulation time 14222686 ps
CPU time 0.72 seconds
Started Jul 29 07:33:01 PM PDT 24
Finished Jul 29 07:33:02 PM PDT 24
Peak memory 201132 kb
Host smart-c22f73bf-b670-4e70-af51-87409a6c1b45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182080117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2182080117
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.2793103811
Short name T484
Test name
Test status
Simulation time 1297766972 ps
CPU time 4.61 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:10 PM PDT 24
Peak memory 201264 kb
Host smart-4f54e3ea-7083-49c7-83b9-d20cbdfb802d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793103811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2793103811
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.3332792435
Short name T478
Test name
Test status
Simulation time 24058338 ps
CPU time 0.85 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 200952 kb
Host smart-5decdd6b-60b4-4e3a-8e96-b3bf94159eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332792435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3332792435
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1257990675
Short name T448
Test name
Test status
Simulation time 6177843629 ps
CPU time 20.25 seconds
Started Jul 29 07:33:04 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201388 kb
Host smart-b09e1fd3-57ba-4ffb-8a40-4a255f75661b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257990675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1257990675
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.3588072360
Short name T125
Test name
Test status
Simulation time 90958386 ps
CPU time 1.07 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201032 kb
Host smart-0a866ac8-342b-4296-90b8-2c52f816cb1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588072360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3588072360
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.924252663
Short name T489
Test name
Test status
Simulation time 99531124 ps
CPU time 1.05 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 201236 kb
Host smart-c61a59db-bcf0-4777-9d7d-6817ae8d2df8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924252663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.924252663
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.336985424
Short name T314
Test name
Test status
Simulation time 38050666 ps
CPU time 0.84 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201096 kb
Host smart-e2383373-b130-4e5f-ac00-d15160e7ac10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336985424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.336985424
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.439864941
Short name T426
Test name
Test status
Simulation time 31268806 ps
CPU time 0.74 seconds
Started Jul 29 07:33:06 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 200276 kb
Host smart-418ab52d-4c3d-4132-adef-da0b3d8740c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439864941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.439864941
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1035860308
Short name T660
Test name
Test status
Simulation time 16215376 ps
CPU time 0.77 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201000 kb
Host smart-8791e314-5f6f-4ac7-854f-891d0826ae31
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035860308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1035860308
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.3672846225
Short name T699
Test name
Test status
Simulation time 22209440 ps
CPU time 0.86 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201068 kb
Host smart-66eaae8b-a93f-49d0-8b20-814bc2cebaf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672846225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3672846225
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.775525329
Short name T129
Test name
Test status
Simulation time 1163510371 ps
CPU time 6.76 seconds
Started Jul 29 07:33:16 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 201140 kb
Host smart-12566025-2be4-4bb8-a452-b05e26064227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775525329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.775525329
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3129546288
Short name T677
Test name
Test status
Simulation time 2409116420 ps
CPU time 8.84 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201436 kb
Host smart-0199d771-303e-4ccf-865d-4093e54085df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129546288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3129546288
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1643620361
Short name T240
Test name
Test status
Simulation time 57688194 ps
CPU time 0.91 seconds
Started Jul 29 07:33:07 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 201076 kb
Host smart-1e212b4f-087c-4f4f-8539-5f7601ccd7bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643620361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1643620361
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.988632636
Short name T288
Test name
Test status
Simulation time 67273665 ps
CPU time 0.95 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:15 PM PDT 24
Peak memory 201036 kb
Host smart-58ee5b7c-949e-4dfa-8417-f069b4c6a48f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988632636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 21.clkmgr_lc_clk_byp_req_intersig_mubi.988632636
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2851953045
Short name T472
Test name
Test status
Simulation time 22400825 ps
CPU time 0.73 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201072 kb
Host smart-4f9b42fd-140d-4518-82c7-a0c4fe304480
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851953045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.2851953045
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.577893700
Short name T244
Test name
Test status
Simulation time 73771845 ps
CPU time 0.99 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 200764 kb
Host smart-3963498e-4e1b-462b-ab18-ffed45cceee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577893700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.577893700
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.3058048770
Short name T338
Test name
Test status
Simulation time 665637057 ps
CPU time 3.07 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201312 kb
Host smart-1ba2d31d-2765-4146-aa22-5416d369bbfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058048770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3058048770
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.4164458132
Short name T123
Test name
Test status
Simulation time 39028203 ps
CPU time 0.86 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201092 kb
Host smart-07819efd-c172-4196-94af-aafa8b68e391
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164458132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.4164458132
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.2693163243
Short name T474
Test name
Test status
Simulation time 7193018739 ps
CPU time 30.51 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201392 kb
Host smart-469e1492-b437-4640-a88f-78b2f85756d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693163243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.2693163243
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.2060109642
Short name T650
Test name
Test status
Simulation time 100705426452 ps
CPU time 627.64 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:43:39 PM PDT 24
Peak memory 217636 kb
Host smart-434b0d25-ada1-4d0f-8467-77db0ef0a8dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2060109642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2060109642
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3411236641
Short name T377
Test name
Test status
Simulation time 80627710 ps
CPU time 0.99 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:10 PM PDT 24
Peak memory 201004 kb
Host smart-819f679e-08e7-48c8-9f41-01ff2c9d4d24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411236641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3411236641
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.348463590
Short name T545
Test name
Test status
Simulation time 18803299 ps
CPU time 0.82 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201036 kb
Host smart-93e6711f-7237-40ad-b833-257727eba833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348463590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkm
gr_alert_test.348463590
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.927045567
Short name T300
Test name
Test status
Simulation time 24386587 ps
CPU time 0.95 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:10 PM PDT 24
Peak memory 201040 kb
Host smart-cababe66-41f6-45e1-bc99-48bba56ae47e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927045567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.927045567
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3229841141
Short name T557
Test name
Test status
Simulation time 51087328 ps
CPU time 0.77 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 200224 kb
Host smart-d4bd27bc-17ce-451a-82ef-07c7c5c6fda0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229841141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3229841141
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2862588411
Short name T210
Test name
Test status
Simulation time 30611345 ps
CPU time 0.81 seconds
Started Jul 29 07:33:13 PM PDT 24
Finished Jul 29 07:33:14 PM PDT 24
Peak memory 201032 kb
Host smart-499bc1e9-9292-42f7-b92d-2e066532a46c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862588411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2862588411
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.679603302
Short name T746
Test name
Test status
Simulation time 94348923 ps
CPU time 1.1 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201056 kb
Host smart-9dcc25ca-7a42-436b-ad5f-79039fae0d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679603302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.679603302
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.4069600817
Short name T783
Test name
Test status
Simulation time 2444505549 ps
CPU time 11.02 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 201300 kb
Host smart-6dc0e2c7-9f5b-4230-8d63-9d2d65ba7f38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069600817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.4069600817
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.319542607
Short name T461
Test name
Test status
Simulation time 1527218307 ps
CPU time 5.46 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201176 kb
Host smart-21ea4cf0-00bb-4c9e-9b8e-aaa4baefc731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319542607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.319542607
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.364837875
Short name T435
Test name
Test status
Simulation time 65950516 ps
CPU time 0.89 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 201080 kb
Host smart-9a01cbd6-50f4-49a3-8c6f-2e7c9418d83a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364837875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_idle_intersig_mubi.364837875
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.414146584
Short name T74
Test name
Test status
Simulation time 62107239 ps
CPU time 0.92 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:10 PM PDT 24
Peak memory 201160 kb
Host smart-2e7def65-404b-496e-a023-d170870e1dc0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414146584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_clk_byp_req_intersig_mubi.414146584
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.2037324377
Short name T763
Test name
Test status
Simulation time 17247292 ps
CPU time 0.79 seconds
Started Jul 29 07:33:22 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 201056 kb
Host smart-469f047c-5776-458f-8c7e-0f444cd22210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037324377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2037324377
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2167144353
Short name T82
Test name
Test status
Simulation time 414675853 ps
CPU time 2.4 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201084 kb
Host smart-0d1cd4aa-f2b2-4c84-b4ec-a4ac2489d58c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167144353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2167144353
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.955526523
Short name T28
Test name
Test status
Simulation time 74996329 ps
CPU time 1 seconds
Started Jul 29 07:33:07 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 201160 kb
Host smart-16d708d7-8ccc-4a10-b70c-77338e5f0b89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955526523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.955526523
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.13407421
Short name T626
Test name
Test status
Simulation time 4673509297 ps
CPU time 21.3 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201160 kb
Host smart-81c8ebdf-c596-408f-af52-52148d2d11d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13407421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_stress_all.13407421
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.1300198860
Short name T551
Test name
Test status
Simulation time 86804951 ps
CPU time 1.13 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201140 kb
Host smart-2cc8e455-c1f4-4af1-a2b3-3560eefc648c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300198860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1300198860
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.2581896008
Short name T528
Test name
Test status
Simulation time 74180274 ps
CPU time 1.02 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:33:13 PM PDT 24
Peak memory 201076 kb
Host smart-ef0ed458-8ebc-4cd0-9a9c-b58031b82e92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581896008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.2581896008
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3129208278
Short name T104
Test name
Test status
Simulation time 38096319 ps
CPU time 1 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201156 kb
Host smart-f8e871b4-fa8f-4cb9-a158-a2a87630e6ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129208278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.3129208278
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3664791882
Short name T794
Test name
Test status
Simulation time 16592571 ps
CPU time 0.73 seconds
Started Jul 29 07:33:08 PM PDT 24
Finished Jul 29 07:33:09 PM PDT 24
Peak memory 200024 kb
Host smart-51895ea5-2317-43df-89f9-7dba41558892
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664791882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3664791882
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2514165377
Short name T702
Test name
Test status
Simulation time 45905064 ps
CPU time 0.8 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201108 kb
Host smart-3b483cc3-e5a0-4ea8-b0d3-3148b64ffcd6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514165377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2514165377
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.1415636755
Short name T326
Test name
Test status
Simulation time 50795508 ps
CPU time 0.92 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:33:13 PM PDT 24
Peak memory 201108 kb
Host smart-86d442b3-e2a6-4ec7-b566-b60771f9a769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415636755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.1415636755
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.3811690095
Short name T560
Test name
Test status
Simulation time 673885377 ps
CPU time 5.94 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201128 kb
Host smart-ab7b6826-ced1-47a5-9384-ae3c8f83d9ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811690095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.3811690095
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2693770872
Short name T190
Test name
Test status
Simulation time 382730699 ps
CPU time 2.74 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201184 kb
Host smart-a6ff78d8-f2d5-442d-84d4-5227b14c32fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693770872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2693770872
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1976390416
Short name T793
Test name
Test status
Simulation time 16662814 ps
CPU time 0.76 seconds
Started Jul 29 07:33:06 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201040 kb
Host smart-5d4a454f-0d1e-42ae-bf11-bffe2cbdd402
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976390416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.1976390416
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.2441373251
Short name T187
Test name
Test status
Simulation time 28523526 ps
CPU time 0.89 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:33:13 PM PDT 24
Peak memory 201104 kb
Host smart-8affe460-c9e9-4ea9-a831-b9d53687b0d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441373251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.2441373251
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3940434926
Short name T786
Test name
Test status
Simulation time 71635149 ps
CPU time 1 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201140 kb
Host smart-d0ac6520-7394-4282-b923-e534f41d26f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940434926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3940434926
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.230274281
Short name T661
Test name
Test status
Simulation time 50777948 ps
CPU time 0.87 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:15 PM PDT 24
Peak memory 201012 kb
Host smart-7c7b405a-1d35-41c1-abe2-313a3ac1269c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230274281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.230274281
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.2753667748
Short name T224
Test name
Test status
Simulation time 111662439 ps
CPU time 1.17 seconds
Started Jul 29 07:33:07 PM PDT 24
Finished Jul 29 07:33:08 PM PDT 24
Peak memory 201020 kb
Host smart-a625ab1b-1abf-4cc5-b42f-04b70fba7109
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753667748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.2753667748
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.1826117351
Short name T159
Test name
Test status
Simulation time 76072736 ps
CPU time 1 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 201092 kb
Host smart-5c5ad414-8e39-4f70-bc0c-dcc3ee711190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826117351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1826117351
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.2791297252
Short name T548
Test name
Test status
Simulation time 4828575991 ps
CPU time 28.05 seconds
Started Jul 29 07:33:14 PM PDT 24
Finished Jul 29 07:33:42 PM PDT 24
Peak memory 201408 kb
Host smart-4ba8b3bf-341c-44b4-a222-e2d31e30e4cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791297252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.2791297252
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2913760015
Short name T503
Test name
Test status
Simulation time 33212493 ps
CPU time 1 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 200772 kb
Host smart-2270b95d-bf60-4029-9839-5b6a39c9fcb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913760015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2913760015
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.3535965045
Short name T800
Test name
Test status
Simulation time 14026027 ps
CPU time 0.74 seconds
Started Jul 29 07:33:07 PM PDT 24
Finished Jul 29 07:33:18 PM PDT 24
Peak memory 200920 kb
Host smart-8565f50b-fab4-4f05-9124-15a8368c64ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535965045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.3535965045
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2012631233
Short name T558
Test name
Test status
Simulation time 64375182 ps
CPU time 1.06 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 201072 kb
Host smart-e58ea50d-d3af-4559-b1d6-137bf7b18127
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012631233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.2012631233
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3395739802
Short name T155
Test name
Test status
Simulation time 40427681 ps
CPU time 0.83 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 200272 kb
Host smart-69496708-9057-4d20-bb71-7f6043f8c9b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395739802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3395739802
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1372637786
Short name T308
Test name
Test status
Simulation time 94100128 ps
CPU time 1.11 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201080 kb
Host smart-f80ce00c-b772-451f-937c-55b043deeed9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372637786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1372637786
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.4257491480
Short name T801
Test name
Test status
Simulation time 46550154 ps
CPU time 0.83 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:16 PM PDT 24
Peak memory 201212 kb
Host smart-04b0d449-c313-48e3-a72b-54d8fbb67d13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257491480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.4257491480
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3936134561
Short name T466
Test name
Test status
Simulation time 1162166555 ps
CPU time 9.58 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:19 PM PDT 24
Peak memory 201328 kb
Host smart-e3a69086-7045-48af-979f-b32d73e830e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936134561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3936134561
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.3424998941
Short name T726
Test name
Test status
Simulation time 495449137 ps
CPU time 3.9 seconds
Started Jul 29 07:33:13 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201116 kb
Host smart-c760c6a8-faa5-4af4-b53f-66bb3cb37f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424998941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.3424998941
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3067014941
Short name T696
Test name
Test status
Simulation time 314221109 ps
CPU time 1.88 seconds
Started Jul 29 07:33:22 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201088 kb
Host smart-8a3503aa-34e4-4fd1-a55c-0097a43eed96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067014941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3067014941
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.778978515
Short name T495
Test name
Test status
Simulation time 56063921 ps
CPU time 0.9 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:11 PM PDT 24
Peak memory 201160 kb
Host smart-cce2f3c6-0d44-402f-8b6d-d209982d0365
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778978515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_clk_byp_req_intersig_mubi.778978515
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.963656805
Short name T197
Test name
Test status
Simulation time 15144464 ps
CPU time 0.79 seconds
Started Jul 29 07:33:05 PM PDT 24
Finished Jul 29 07:33:06 PM PDT 24
Peak memory 201120 kb
Host smart-614994b5-32d5-41b8-9d16-558bdf333031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963656805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.963656805
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.818663816
Short name T463
Test name
Test status
Simulation time 25745768 ps
CPU time 0.76 seconds
Started Jul 29 07:33:09 PM PDT 24
Finished Jul 29 07:33:10 PM PDT 24
Peak memory 201076 kb
Host smart-cd8271dd-deb3-4c4c-a612-74e8037889a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818663816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.818663816
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.820992482
Short name T323
Test name
Test status
Simulation time 861503572 ps
CPU time 5.18 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:20 PM PDT 24
Peak memory 201252 kb
Host smart-dee2a274-0ac7-41a7-95ec-090ba6519c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820992482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.820992482
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.3947718656
Short name T635
Test name
Test status
Simulation time 75913958 ps
CPU time 1 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201028 kb
Host smart-b4a249eb-b627-4c9a-8bef-458a96a9b3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947718656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3947718656
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.1505019143
Short name T643
Test name
Test status
Simulation time 11505316667 ps
CPU time 76.64 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:34:32 PM PDT 24
Peak memory 201316 kb
Host smart-10ce4fc9-7421-4e3f-9e98-4133f229731a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505019143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.1505019143
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.360759690
Short name T43
Test name
Test status
Simulation time 228548548617 ps
CPU time 1341.31 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:55:33 PM PDT 24
Peak memory 217908 kb
Host smart-91fd6dc7-e2ed-4b90-9e4d-79e3c504fa33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=360759690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.360759690
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2588884082
Short name T519
Test name
Test status
Simulation time 24181333 ps
CPU time 0.85 seconds
Started Jul 29 07:33:12 PM PDT 24
Finished Jul 29 07:33:13 PM PDT 24
Peak memory 201220 kb
Host smart-f1ba71d8-d626-4816-b649-05c795ce7e04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588884082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2588884082
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.2611107633
Short name T21
Test name
Test status
Simulation time 12807409 ps
CPU time 0.71 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 200976 kb
Host smart-afeb9be8-7122-4254-8c1b-b3eae12c7bfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611107633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.2611107633
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.361662573
Short name T184
Test name
Test status
Simulation time 24807706 ps
CPU time 0.78 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 201080 kb
Host smart-c3b8f379-1402-46ca-a514-625252ac691e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361662573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.361662573
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.869409101
Short name T230
Test name
Test status
Simulation time 42742100 ps
CPU time 0.74 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:27 PM PDT 24
Peak memory 200232 kb
Host smart-4904250f-8025-4924-88b1-24b955dd7511
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869409101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.869409101
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.225540207
Short name T446
Test name
Test status
Simulation time 99552682 ps
CPU time 1.11 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 201080 kb
Host smart-8f24fdc7-c59d-4f9d-926e-a6500444dd49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225540207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.225540207
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.2434222093
Short name T750
Test name
Test status
Simulation time 65720527 ps
CPU time 0.94 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201016 kb
Host smart-50bb223d-c564-4580-8620-d3a7e58b5b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434222093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2434222093
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.4053219450
Short name T343
Test name
Test status
Simulation time 616166476 ps
CPU time 3.32 seconds
Started Jul 29 07:33:20 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201136 kb
Host smart-e0aba8f7-a783-4562-863c-cdf8f8ba4bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053219450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.4053219450
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3604072233
Short name T760
Test name
Test status
Simulation time 1972177613 ps
CPU time 7.82 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:36 PM PDT 24
Peak memory 201136 kb
Host smart-6204b83c-72d5-4407-8b0d-1c1fedc31e38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604072233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3604072233
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3456844453
Short name T806
Test name
Test status
Simulation time 15000015 ps
CPU time 0.74 seconds
Started Jul 29 07:33:20 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 201084 kb
Host smart-1cf6f13e-d366-4b68-b61a-6d4e809613b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456844453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3456844453
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2082674834
Short name T119
Test name
Test status
Simulation time 124486530 ps
CPU time 1.14 seconds
Started Jul 29 07:33:11 PM PDT 24
Finished Jul 29 07:33:12 PM PDT 24
Peak memory 201004 kb
Host smart-d3f987a7-417d-4363-af32-6d21c99694fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082674834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2082674834
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.927881512
Short name T95
Test name
Test status
Simulation time 51757292 ps
CPU time 0.9 seconds
Started Jul 29 07:33:15 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 200996 kb
Host smart-9b119fbc-30de-4c61-8047-4a8fbe2f5816
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927881512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.927881512
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.2146633203
Short name T775
Test name
Test status
Simulation time 21387676 ps
CPU time 0.79 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201012 kb
Host smart-2f86e863-8a68-4cdf-8c9e-11d2b0ec9729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146633203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2146633203
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.647439198
Short name T220
Test name
Test status
Simulation time 1335035912 ps
CPU time 7.1 seconds
Started Jul 29 07:33:10 PM PDT 24
Finished Jul 29 07:33:17 PM PDT 24
Peak memory 201280 kb
Host smart-961ed796-4ad6-41b7-935b-1394dcd8a685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647439198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.647439198
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.1121425526
Short name T802
Test name
Test status
Simulation time 70195082 ps
CPU time 1.03 seconds
Started Jul 29 07:33:17 PM PDT 24
Finished Jul 29 07:33:18 PM PDT 24
Peak memory 201180 kb
Host smart-8210d3ac-d071-4f10-b718-ab4b6296ac89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121425526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1121425526
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3921147974
Short name T675
Test name
Test status
Simulation time 433383021 ps
CPU time 2.97 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201296 kb
Host smart-4816f302-2710-468b-a3be-1765e27f2e31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921147974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3921147974
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.1685420520
Short name T632
Test name
Test status
Simulation time 31178334 ps
CPU time 0.84 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 201072 kb
Host smart-15b9b6ef-4295-4df5-a705-6c02a6dd1786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685420520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.1685420520
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3806804021
Short name T24
Test name
Test status
Simulation time 35302200 ps
CPU time 0.8 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201076 kb
Host smart-e1380be0-395c-44d5-bb0a-b1af6fcc361a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806804021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3806804021
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.742066094
Short name T707
Test name
Test status
Simulation time 25280776 ps
CPU time 0.88 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 201088 kb
Host smart-dd9cfaae-b9d2-4103-b0ec-d348b4f68fa8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742066094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.742066094
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2264291622
Short name T196
Test name
Test status
Simulation time 15276330 ps
CPU time 0.7 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 200212 kb
Host smart-35e67b26-c078-4558-b3ef-7c970581afc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264291622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2264291622
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.750097919
Short name T457
Test name
Test status
Simulation time 40797511 ps
CPU time 0.9 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201060 kb
Host smart-6a22692b-7892-49df-978a-d35fb14f83b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750097919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_div_intersig_mubi.750097919
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.1198496131
Short name T421
Test name
Test status
Simulation time 21976771 ps
CPU time 0.82 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201072 kb
Host smart-dc61484f-570a-4cb6-805a-11bf13cf6b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198496131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1198496131
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.790994407
Short name T638
Test name
Test status
Simulation time 675769339 ps
CPU time 5.68 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:29 PM PDT 24
Peak memory 201088 kb
Host smart-73c800ca-8b06-41da-8ce6-5ed4751f6b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790994407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.790994407
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.115192373
Short name T771
Test name
Test status
Simulation time 1923834983 ps
CPU time 7.69 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:40 PM PDT 24
Peak memory 201240 kb
Host smart-13743d8e-f225-4a2c-bace-d89017bf7aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115192373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_ti
meout.115192373
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3076271646
Short name T743
Test name
Test status
Simulation time 153595839 ps
CPU time 1.22 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201076 kb
Host smart-95e9132d-ca0e-412c-a544-ab72ce4207ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076271646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3076271646
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3538117947
Short name T758
Test name
Test status
Simulation time 71634771 ps
CPU time 0.99 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 201124 kb
Host smart-64755757-26e5-4896-bd7b-68466482ab19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538117947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.3538117947
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.3253093852
Short name T533
Test name
Test status
Simulation time 22275752 ps
CPU time 0.78 seconds
Started Jul 29 07:33:22 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 201032 kb
Host smart-cc8db64f-28c7-4282-93dc-ebacdc958372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253093852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3253093852
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.2322514357
Short name T329
Test name
Test status
Simulation time 402366579 ps
CPU time 2.27 seconds
Started Jul 29 07:33:25 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 201148 kb
Host smart-6fed8ee1-4ae4-44bb-b69c-680e47421bda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322514357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2322514357
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.2196225567
Short name T145
Test name
Test status
Simulation time 22323055 ps
CPU time 0.87 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 201292 kb
Host smart-20326f88-99a1-4ed4-9ff2-b9e1daf7b496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196225567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2196225567
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_trans.2639743895
Short name T172
Test name
Test status
Simulation time 23310804 ps
CPU time 0.81 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201224 kb
Host smart-210fb75d-6285-4341-b51e-0a85ea43420f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639743895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2639743895
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2511293242
Short name T508
Test name
Test status
Simulation time 11596089 ps
CPU time 0.67 seconds
Started Jul 29 07:33:21 PM PDT 24
Finished Jul 29 07:33:22 PM PDT 24
Peak memory 201076 kb
Host smart-e7e5557b-74d4-4a61-95ca-f236a2dd2a08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511293242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2511293242
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3319702723
Short name T453
Test name
Test status
Simulation time 33905326 ps
CPU time 0.94 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201052 kb
Host smart-14856d87-d3ba-4370-9fa1-388527ce6646
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319702723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3319702723
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.1010152950
Short name T183
Test name
Test status
Simulation time 53309070 ps
CPU time 0.95 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201052 kb
Host smart-8203c2e7-9d6c-4b6d-b997-b67994e39d58
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010152950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.1010152950
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.2699650509
Short name T537
Test name
Test status
Simulation time 101326105 ps
CPU time 1.2 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201028 kb
Host smart-b81ed5cb-5640-4564-8f48-b408efce484b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699650509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2699650509
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.354180756
Short name T236
Test name
Test status
Simulation time 970743001 ps
CPU time 4.3 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201132 kb
Host smart-fbc8fe3f-4873-4fe3-8880-5a3158add909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354180756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.354180756
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.807949141
Short name T649
Test name
Test status
Simulation time 1582815412 ps
CPU time 11.87 seconds
Started Jul 29 07:33:25 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201140 kb
Host smart-1219970c-215a-4834-980c-bbb9a42f066b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807949141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_ti
meout.807949141
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.1561481523
Short name T602
Test name
Test status
Simulation time 82387278 ps
CPU time 1.16 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201112 kb
Host smart-dbc77a17-94cf-4f9f-80d3-97796932fbd6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561481523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.1561481523
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.32672198
Short name T582
Test name
Test status
Simulation time 79364363 ps
CPU time 1.02 seconds
Started Jul 29 07:33:26 PM PDT 24
Finished Jul 29 07:33:27 PM PDT 24
Peak memory 201040 kb
Host smart-674f50ab-ac1a-439f-9a63-e5153ff1ecff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_lc_clk_byp_req_intersig_mubi.32672198
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3679439833
Short name T719
Test name
Test status
Simulation time 84748186 ps
CPU time 1.13 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201088 kb
Host smart-ffd05412-63a1-4f86-8f37-a40d7bd6e03a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679439833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.3679439833
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2708057424
Short name T686
Test name
Test status
Simulation time 37963528 ps
CPU time 0.82 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201068 kb
Host smart-94b66d85-2b3a-4717-ac76-5714c0d0ec33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708057424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2708057424
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.472965651
Short name T35
Test name
Test status
Simulation time 456636124 ps
CPU time 2.07 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201112 kb
Host smart-5a3f3105-79b5-4af0-9be9-e10229e1ccc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472965651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.472965651
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.85256287
Short name T633
Test name
Test status
Simulation time 16256130 ps
CPU time 0.78 seconds
Started Jul 29 07:33:25 PM PDT 24
Finished Jul 29 07:33:26 PM PDT 24
Peak memory 201108 kb
Host smart-7d063819-c388-41c7-a74c-01d9a91e5d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85256287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.85256287
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.1172565011
Short name T759
Test name
Test status
Simulation time 6562576101 ps
CPU time 47.06 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:34:19 PM PDT 24
Peak memory 201456 kb
Host smart-b48301cf-a861-4151-96f0-b96237cb045d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172565011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.1172565011
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.117364649
Short name T515
Test name
Test status
Simulation time 52283958 ps
CPU time 0.99 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:29 PM PDT 24
Peak memory 201068 kb
Host smart-2f3d2cea-0026-46b1-a376-16e1792bae8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117364649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.117364649
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.394572917
Short name T424
Test name
Test status
Simulation time 140336498 ps
CPU time 1.16 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201112 kb
Host smart-c504e7f6-d723-4cc3-a315-29394c64268f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394572917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.394572917
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.3251194070
Short name T576
Test name
Test status
Simulation time 20142053 ps
CPU time 0.82 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201072 kb
Host smart-a6f6d99a-6160-4292-89d2-56a674a45038
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251194070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.3251194070
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3609489813
Short name T334
Test name
Test status
Simulation time 59336458 ps
CPU time 0.83 seconds
Started Jul 29 07:33:25 PM PDT 24
Finished Jul 29 07:33:26 PM PDT 24
Peak memory 200456 kb
Host smart-71c43c7b-36bb-4038-a1f1-b575957321e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609489813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3609489813
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.2680007531
Short name T413
Test name
Test status
Simulation time 20091802 ps
CPU time 0.76 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201108 kb
Host smart-5985092b-5f15-4dca-8bff-702f9aab100f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680007531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.2680007531
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.3461563808
Short name T23
Test name
Test status
Simulation time 23520567 ps
CPU time 0.81 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 200908 kb
Host smart-65b9a051-cebe-4a8d-a9eb-e4a65f907ea8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461563808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.3461563808
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2047866442
Short name T688
Test name
Test status
Simulation time 1043276974 ps
CPU time 5.93 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201136 kb
Host smart-ae5e10e2-dbe1-4f44-ada3-2fe53758d770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047866442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2047866442
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.2346616665
Short name T312
Test name
Test status
Simulation time 1946561495 ps
CPU time 10.36 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201204 kb
Host smart-cd1ce623-9c6c-427f-90fd-2e9108b4afd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346616665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.2346616665
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.1309343238
Short name T169
Test name
Test status
Simulation time 21094789 ps
CPU time 0.82 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201056 kb
Host smart-6e96d735-fa90-408f-afa5-b25f44f10307
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309343238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.1309343238
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1865366973
Short name T679
Test name
Test status
Simulation time 18968790 ps
CPU time 0.83 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201068 kb
Host smart-79940549-fc20-45e6-a0ac-92db6964bf45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865366973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1865366973
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4277775680
Short name T365
Test name
Test status
Simulation time 22301809 ps
CPU time 0.88 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201072 kb
Host smart-b8ef4784-a1ab-41a5-ab25-993c7de7eea0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277775680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.4277775680
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.147175594
Short name T620
Test name
Test status
Simulation time 28723240 ps
CPU time 0.88 seconds
Started Jul 29 07:33:24 PM PDT 24
Finished Jul 29 07:33:25 PM PDT 24
Peak memory 201264 kb
Host smart-39f44afe-3e2c-4688-a373-31183630b19d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147175594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.147175594
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.1043451590
Short name T567
Test name
Test status
Simulation time 144284521 ps
CPU time 1.28 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201044 kb
Host smart-ad993d2c-8463-4817-9363-d75afb6a586f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043451590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.1043451590
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.3478579632
Short name T685
Test name
Test status
Simulation time 23578218 ps
CPU time 0.88 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201092 kb
Host smart-b1d159a4-c1d5-4447-beb9-caf92eb8868d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478579632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.3478579632
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.818993631
Short name T501
Test name
Test status
Simulation time 6191950535 ps
CPU time 26.04 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201480 kb
Host smart-75f04701-91f9-4818-a83c-435e41f3da28
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818993631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.818993631
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3232451137
Short name T222
Test name
Test status
Simulation time 18599075 ps
CPU time 0.79 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201224 kb
Host smart-c5eb5834-ffc4-4eb0-8bdb-839008d14455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232451137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3232451137
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3562869299
Short name T506
Test name
Test status
Simulation time 56514562 ps
CPU time 0.87 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201096 kb
Host smart-287d7d3f-6af0-4af0-bcc1-e85e1f4de82d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562869299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3562869299
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1003799856
Short name T525
Test name
Test status
Simulation time 30092560 ps
CPU time 0.83 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:29 PM PDT 24
Peak memory 201148 kb
Host smart-2de725ec-608c-4056-9a50-10947585ea9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003799856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.1003799856
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2018361988
Short name T156
Test name
Test status
Simulation time 13943187 ps
CPU time 0.75 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 200292 kb
Host smart-f4821af4-8c18-4e78-a187-eefb536fb38b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018361988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2018361988
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.1437848576
Short name T492
Test name
Test status
Simulation time 34513227 ps
CPU time 0.88 seconds
Started Jul 29 07:33:26 PM PDT 24
Finished Jul 29 07:33:27 PM PDT 24
Peak memory 201048 kb
Host smart-d47ac94f-5115-4919-9ca7-c4e90bf126b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437848576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.1437848576
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.949842440
Short name T73
Test name
Test status
Simulation time 24150583 ps
CPU time 0.91 seconds
Started Jul 29 07:33:23 PM PDT 24
Finished Jul 29 07:33:24 PM PDT 24
Peak memory 201244 kb
Host smart-ae1669cd-64dd-4d7c-8745-a6b8037c6a3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949842440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.949842440
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3839480426
Short name T11
Test name
Test status
Simulation time 1771720147 ps
CPU time 8.18 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201328 kb
Host smart-44b1502a-b2b3-4907-b951-756143618879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839480426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3839480426
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.995855368
Short name T337
Test name
Test status
Simulation time 1708923731 ps
CPU time 9 seconds
Started Jul 29 07:33:24 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201232 kb
Host smart-b00f66bd-b50b-4acc-b99d-0b7a7690bb59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995855368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_ti
meout.995855368
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2354725507
Short name T266
Test name
Test status
Simulation time 32374303 ps
CPU time 0.98 seconds
Started Jul 29 07:33:24 PM PDT 24
Finished Jul 29 07:33:26 PM PDT 24
Peak memory 201080 kb
Host smart-4d6eaf9e-f617-47ec-9d03-c6fdf18c9a80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354725507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.2354725507
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1820320798
Short name T25
Test name
Test status
Simulation time 40230395 ps
CPU time 0.91 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201072 kb
Host smart-b1bff2e6-504e-4e81-9230-151e75e79960
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820320798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1820320798
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2654675940
Short name T687
Test name
Test status
Simulation time 48215791 ps
CPU time 0.78 seconds
Started Jul 29 07:33:35 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201068 kb
Host smart-79ce4a2f-07ce-46d5-907c-5b001a3ff156
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654675940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.2654675940
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2772315118
Short name T505
Test name
Test status
Simulation time 17685960 ps
CPU time 0.76 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201072 kb
Host smart-a94ef03c-53b6-4432-bd82-16a497297c73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772315118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2772315118
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.3767050928
Short name T255
Test name
Test status
Simulation time 190366054 ps
CPU time 1.25 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201080 kb
Host smart-8da54841-607d-43fd-9627-2ad238587271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767050928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3767050928
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1081030297
Short name T799
Test name
Test status
Simulation time 58766446 ps
CPU time 0.93 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201040 kb
Host smart-43104f1c-174f-4b1f-9a63-a427955ace69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081030297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1081030297
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.134713493
Short name T41
Test name
Test status
Simulation time 4508812671 ps
CPU time 18.84 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:47 PM PDT 24
Peak memory 201524 kb
Host smart-9c66f818-e831-4295-857c-e120d9bb332f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134713493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.134713493
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.2810468142
Short name T180
Test name
Test status
Simulation time 32189077 ps
CPU time 1.03 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 201112 kb
Host smart-e010ce37-c7c5-4ff9-88b2-7c29166e0bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810468142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2810468142
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.3079869667
Short name T749
Test name
Test status
Simulation time 35938371 ps
CPU time 0.82 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:22 PM PDT 24
Peak memory 201008 kb
Host smart-8b766fda-e142-4213-8442-1219abf20330
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079869667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.3079869667
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1347504577
Short name T204
Test name
Test status
Simulation time 75560231 ps
CPU time 0.9 seconds
Started Jul 29 07:32:19 PM PDT 24
Finished Jul 29 07:32:20 PM PDT 24
Peak memory 201116 kb
Host smart-e0395283-5d0d-4d4a-bfe1-e188bb629ef4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347504577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1347504577
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2487599752
Short name T248
Test name
Test status
Simulation time 42453423 ps
CPU time 0.76 seconds
Started Jul 29 07:32:37 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 200292 kb
Host smart-7a77bb8f-f8c1-48f0-8718-703cd18cf35c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487599752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2487599752
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1925280641
Short name T673
Test name
Test status
Simulation time 57641992 ps
CPU time 0.92 seconds
Started Jul 29 07:32:24 PM PDT 24
Finished Jul 29 07:32:25 PM PDT 24
Peak memory 201088 kb
Host smart-0f49db9f-e3e4-4f5e-bf68-ad326a3ad211
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925280641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.1925280641
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.2582582175
Short name T49
Test name
Test status
Simulation time 108251078 ps
CPU time 1.19 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201060 kb
Host smart-4568bc85-3b29-49e4-8694-e3f92a591e92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582582175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.2582582175
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.3798820253
Short name T513
Test name
Test status
Simulation time 803410673 ps
CPU time 6.84 seconds
Started Jul 29 07:32:24 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201144 kb
Host smart-f325e63d-a6e0-47b0-9e30-77bf6f0a8fb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798820253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3798820253
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.236856529
Short name T600
Test name
Test status
Simulation time 985529754 ps
CPU time 5.39 seconds
Started Jul 29 07:32:23 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 201344 kb
Host smart-6a6258d8-00a5-4158-9d05-4485b6fb4deb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236856529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_tim
eout.236856529
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3883463005
Short name T433
Test name
Test status
Simulation time 148874651 ps
CPU time 1.47 seconds
Started Jul 29 07:32:24 PM PDT 24
Finished Jul 29 07:32:25 PM PDT 24
Peak memory 201088 kb
Host smart-da6b46d0-37b0-48f2-ab4c-39ad683220ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883463005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3883463005
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.2248984492
Short name T406
Test name
Test status
Simulation time 31915787 ps
CPU time 0.84 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:22 PM PDT 24
Peak memory 201012 kb
Host smart-382e38df-c05a-4ba8-9815-b4563ac09501
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248984492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.2248984492
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3091620933
Short name T624
Test name
Test status
Simulation time 29372558 ps
CPU time 0.79 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201076 kb
Host smart-944ed79e-2b6e-4e95-8784-4aeb7f7edbc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091620933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3091620933
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.450167538
Short name T682
Test name
Test status
Simulation time 14477682 ps
CPU time 0.73 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201072 kb
Host smart-14d40503-f03a-4a7c-a9c4-4b296b5c4967
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450167538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.450167538
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.4049591090
Short name T665
Test name
Test status
Simulation time 790972333 ps
CPU time 3.66 seconds
Started Jul 29 07:32:32 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201300 kb
Host smart-003f1714-6604-49fe-ab62-3a2410e3a1e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049591090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.4049591090
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.2493061620
Short name T56
Test name
Test status
Simulation time 651434678 ps
CPU time 3.91 seconds
Started Jul 29 07:32:24 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 217940 kb
Host smart-ccef607c-aff7-49ea-8da1-f487caa9a01e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493061620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.2493061620
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.139756238
Short name T792
Test name
Test status
Simulation time 131104374 ps
CPU time 1.17 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201072 kb
Host smart-74b6c222-6030-42b0-a921-d6e79fe2c604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139756238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.139756238
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.1016786143
Short name T780
Test name
Test status
Simulation time 65091709 ps
CPU time 1.07 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201004 kb
Host smart-43542a91-0316-42de-8bb6-c115a257476a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016786143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.1016786143
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.1522479676
Short name T31
Test name
Test status
Simulation time 115244483840 ps
CPU time 910.14 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:47:38 PM PDT 24
Peak memory 217884 kb
Host smart-41e635a3-0b42-45cb-9f61-90ade9ab8777
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1522479676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.1522479676
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.1476794920
Short name T173
Test name
Test status
Simulation time 25862446 ps
CPU time 0.94 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201084 kb
Host smart-08d320be-0667-4da4-b823-e27a01fe63aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476794920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1476794920
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1426290293
Short name T46
Test name
Test status
Simulation time 28338735 ps
CPU time 0.73 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 201116 kb
Host smart-59528057-adb3-4875-84bd-4c4979c0d0a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426290293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1426290293
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.758484682
Short name T547
Test name
Test status
Simulation time 25778401 ps
CPU time 0.81 seconds
Started Jul 29 07:33:26 PM PDT 24
Finished Jul 29 07:33:27 PM PDT 24
Peak memory 201064 kb
Host smart-a68688b2-c034-42df-b847-cf87b99ef1d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758484682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.758484682
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.1570673056
Short name T416
Test name
Test status
Simulation time 13328082 ps
CPU time 0.73 seconds
Started Jul 29 07:33:22 PM PDT 24
Finished Jul 29 07:33:23 PM PDT 24
Peak memory 200232 kb
Host smart-cba7f371-a4c9-491a-b844-bb42233ed0ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570673056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1570673056
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.1007309240
Short name T75
Test name
Test status
Simulation time 66831363 ps
CPU time 0.93 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201004 kb
Host smart-267c6c0d-d69d-4ad7-a819-ba9b89a6abb0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007309240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.1007309240
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.4010669369
Short name T721
Test name
Test status
Simulation time 44195340 ps
CPU time 0.86 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201008 kb
Host smart-88c490d8-da09-4720-b30f-a4f5f1500b96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010669369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.4010669369
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.3546006754
Short name T12
Test name
Test status
Simulation time 683600902 ps
CPU time 5.99 seconds
Started Jul 29 07:33:35 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201100 kb
Host smart-95faf77c-b46f-46c7-8d41-d3d426dfa027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546006754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3546006754
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.736903864
Short name T767
Test name
Test status
Simulation time 1455632843 ps
CPU time 10.63 seconds
Started Jul 29 07:33:26 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201128 kb
Host smart-b9a54c29-4459-4b21-b6a7-4237154efe9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736903864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti
meout.736903864
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2255415722
Short name T179
Test name
Test status
Simulation time 19598024 ps
CPU time 0.81 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201124 kb
Host smart-0c4a7be3-8568-4056-bdb7-b5b336b2d4c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255415722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2255415722
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.229472899
Short name T571
Test name
Test status
Simulation time 37644773 ps
CPU time 0.79 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 200952 kb
Host smart-7dbb68b8-c08d-4693-92aa-01e993496187
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229472899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.229472899
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.592325015
Short name T178
Test name
Test status
Simulation time 42707005 ps
CPU time 0.8 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201028 kb
Host smart-412071a2-83f3-4225-b08b-b86803fe177b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592325015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_ctrl_intersig_mubi.592325015
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.3637074972
Short name T253
Test name
Test status
Simulation time 26767791 ps
CPU time 0.77 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201020 kb
Host smart-b5ad46fa-a3c0-480f-b4a2-896c59f69305
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637074972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3637074972
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.4074642930
Short name T376
Test name
Test status
Simulation time 1169144836 ps
CPU time 6.82 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201292 kb
Host smart-028a4f41-ee5d-403e-b861-5d151d131a08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074642930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.4074642930
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.2979603348
Short name T328
Test name
Test status
Simulation time 22274050 ps
CPU time 0.85 seconds
Started Jul 29 07:33:28 PM PDT 24
Finished Jul 29 07:33:29 PM PDT 24
Peak memory 201140 kb
Host smart-dc6f2d2b-8e0f-4242-99dc-7faa3ec7283c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979603348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2979603348
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.3025771401
Short name T812
Test name
Test status
Simulation time 4941817893 ps
CPU time 20.01 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:47 PM PDT 24
Peak memory 201380 kb
Host smart-c80cf432-abf1-4a4d-95c9-ba70679e2d75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025771401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.3025771401
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2451071512
Short name T72
Test name
Test status
Simulation time 61629530975 ps
CPU time 586.91 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:43:20 PM PDT 24
Peak memory 209764 kb
Host smart-797acff1-c858-44e2-9072-6e81eaa65768
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2451071512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2451071512
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.1318447863
Short name T706
Test name
Test status
Simulation time 48443826 ps
CPU time 0.84 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201040 kb
Host smart-d3bf93af-e2f4-460d-95ba-1cd2568891fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318447863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1318447863
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1269579166
Short name T449
Test name
Test status
Simulation time 92368906 ps
CPU time 1.09 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201040 kb
Host smart-b67941a8-3652-4766-a1ae-41f30ecb065d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269579166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1269579166
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2441049979
Short name T642
Test name
Test status
Simulation time 68608055 ps
CPU time 1.01 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201032 kb
Host smart-1648f321-1e39-4a78-85f6-fb6474bd7dd8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441049979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2441049979
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.814560507
Short name T591
Test name
Test status
Simulation time 19958182 ps
CPU time 0.7 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:28 PM PDT 24
Peak memory 200312 kb
Host smart-18cb30dd-baf1-4124-affa-13ac71f42132
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814560507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.814560507
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1610292846
Short name T581
Test name
Test status
Simulation time 16536643 ps
CPU time 0.77 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201036 kb
Host smart-43d32008-b30a-4551-b071-0439ad6ffa6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610292846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1610292846
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.1850913424
Short name T494
Test name
Test status
Simulation time 16447361 ps
CPU time 0.78 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201044 kb
Host smart-97dbd0b6-e220-47ae-a22c-8ec04c54770b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850913424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.1850913424
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1628761261
Short name T223
Test name
Test status
Simulation time 1050268168 ps
CPU time 5.91 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201152 kb
Host smart-a787b01c-da0a-4ac7-83d7-577684200d6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628761261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1628761261
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.2871958597
Short name T375
Test name
Test status
Simulation time 754994728 ps
CPU time 3.68 seconds
Started Jul 29 07:33:27 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201128 kb
Host smart-10e3c317-2a77-4ed6-8c2c-d03f76e4c60a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871958597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.2871958597
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1729101531
Short name T681
Test name
Test status
Simulation time 19094397 ps
CPU time 0.87 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201052 kb
Host smart-55df3667-1e98-4584-8648-859eb9629fb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729101531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1729101531
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1012965486
Short name T584
Test name
Test status
Simulation time 16306669 ps
CPU time 0.76 seconds
Started Jul 29 07:33:26 PM PDT 24
Finished Jul 29 07:33:27 PM PDT 24
Peak memory 201044 kb
Host smart-42435d4d-a168-4220-abdc-bf72aaedcb4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012965486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1012965486
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2469818601
Short name T683
Test name
Test status
Simulation time 23764995 ps
CPU time 0.95 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201036 kb
Host smart-4847e263-ff26-400c-8c3a-afe58f05fa28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469818601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2469818601
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.479022475
Short name T410
Test name
Test status
Simulation time 16000367 ps
CPU time 0.76 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201088 kb
Host smart-8ba47f58-c286-4d2f-aed8-bd4e78329c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479022475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.479022475
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.3824939968
Short name T455
Test name
Test status
Simulation time 51367764 ps
CPU time 0.91 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 200976 kb
Host smart-f6ca756f-32fc-4d35-ad9a-deb2920708cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824939968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3824939968
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.841262017
Short name T389
Test name
Test status
Simulation time 26223503 ps
CPU time 0.85 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201092 kb
Host smart-c6bf9f74-b9f2-45f8-b0b4-6f34bd61845e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841262017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.841262017
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.3054761853
Short name T559
Test name
Test status
Simulation time 2114168151 ps
CPU time 8.83 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201380 kb
Host smart-b8ea0ba6-a29c-4ceb-991f-c699d3f6de61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054761853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.3054761853
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2460899305
Short name T162
Test name
Test status
Simulation time 93673338563 ps
CPU time 568.32 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:42:59 PM PDT 24
Peak memory 217924 kb
Host smart-a4c745da-3c06-42d1-8b4d-af8d841825e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2460899305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2460899305
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.1930569643
Short name T570
Test name
Test status
Simulation time 63348950 ps
CPU time 0.95 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201056 kb
Host smart-e476b290-b06d-4d15-8ecf-60761429416e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930569643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1930569643
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.4233940608
Short name T502
Test name
Test status
Simulation time 22056347 ps
CPU time 0.77 seconds
Started Jul 29 07:33:32 PM PDT 24
Finished Jul 29 07:33:33 PM PDT 24
Peak memory 201000 kb
Host smart-13b7eef4-b0ac-4a17-a52d-372c21ced300
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233940608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.4233940608
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.3976357081
Short name T514
Test name
Test status
Simulation time 35431348 ps
CPU time 0.76 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201072 kb
Host smart-e92ce564-1578-4b59-a169-43b03673fb05
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976357081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.3976357081
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1808193730
Short name T805
Test name
Test status
Simulation time 54159899 ps
CPU time 0.81 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 200240 kb
Host smart-6a1e08e4-6f66-4c61-ad22-20a6e0de1347
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808193730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1808193730
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.606419955
Short name T364
Test name
Test status
Simulation time 55755366 ps
CPU time 0.93 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201040 kb
Host smart-25d64acd-fb55-4a26-8319-f37279226e8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606419955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_div_intersig_mubi.606419955
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.1214809390
Short name T788
Test name
Test status
Simulation time 63339951 ps
CPU time 0.88 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201216 kb
Host smart-515c26d6-cdeb-4751-818c-926b2e6dfa27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214809390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1214809390
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.1946381017
Short name T218
Test name
Test status
Simulation time 2007620372 ps
CPU time 10.56 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 201360 kb
Host smart-3d495a14-b72d-4dac-89da-bcf641d25b57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946381017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1946381017
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.4292972133
Short name T428
Test name
Test status
Simulation time 497497193 ps
CPU time 4.07 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201236 kb
Host smart-e38fd0c7-f39b-40c9-a086-4b90fa0983c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292972133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.4292972133
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.152292745
Short name T191
Test name
Test status
Simulation time 64849283 ps
CPU time 0.99 seconds
Started Jul 29 07:33:43 PM PDT 24
Finished Jul 29 07:33:44 PM PDT 24
Peak memory 200864 kb
Host smart-6c914c89-b74e-4262-ba65-2b07312afd89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152292745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_idle_intersig_mubi.152292745
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.614282634
Short name T493
Test name
Test status
Simulation time 56823430 ps
CPU time 0.86 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201088 kb
Host smart-0e02a1f1-b95b-45a5-87d6-74c861932152
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614282634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.614282634
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.563989136
Short name T263
Test name
Test status
Simulation time 21083062 ps
CPU time 0.84 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201112 kb
Host smart-599d51c1-5c1a-4743-adde-6a541b16df36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563989136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.563989136
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.1405521884
Short name T260
Test name
Test status
Simulation time 44123904 ps
CPU time 0.84 seconds
Started Jul 29 07:33:29 PM PDT 24
Finished Jul 29 07:33:30 PM PDT 24
Peak memory 201056 kb
Host smart-49e25021-d7ce-40e1-bc12-e1ae09aaf826
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405521884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1405521884
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3364512359
Short name T81
Test name
Test status
Simulation time 392271376 ps
CPU time 1.97 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 200868 kb
Host smart-79d20d58-d2f5-4b1d-b789-a651d0e8c2c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364512359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3364512359
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.1474600363
Short name T264
Test name
Test status
Simulation time 38475318 ps
CPU time 0.91 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 200932 kb
Host smart-f15f8f80-6527-4caf-a1ee-309f4dedcfdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474600363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1474600363
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.295635743
Short name T79
Test name
Test status
Simulation time 1680698880 ps
CPU time 7.15 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 201344 kb
Host smart-007882fb-f707-4b6f-b20b-9fd17639767c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295635743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.295635743
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.504722663
Short name T352
Test name
Test status
Simulation time 19657708 ps
CPU time 0.8 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:36 PM PDT 24
Peak memory 201088 kb
Host smart-5b5ca083-5634-420c-8ef9-dc1835688bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504722663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.504722663
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.70666157
Short name T791
Test name
Test status
Simulation time 152963817 ps
CPU time 1.18 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 200872 kb
Host smart-bd782768-9767-4aba-aea3-f49041bd3b3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70666157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmg
r_alert_test.70666157
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.126708333
Short name T105
Test name
Test status
Simulation time 20251346 ps
CPU time 0.8 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 200952 kb
Host smart-0fa3b81b-da0f-4e18-86d4-b1a8c35abf45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126708333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.126708333
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.842574643
Short name T221
Test name
Test status
Simulation time 53887495 ps
CPU time 0.8 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:31 PM PDT 24
Peak memory 200288 kb
Host smart-933188d8-5cf2-48be-9648-00b7945be92f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842574643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.842574643
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.1256758160
Short name T176
Test name
Test status
Simulation time 19955581 ps
CPU time 0.81 seconds
Started Jul 29 07:33:33 PM PDT 24
Finished Jul 29 07:33:34 PM PDT 24
Peak memory 201116 kb
Host smart-20bd272d-a07b-4863-baea-2a3504495444
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256758160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.1256758160
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1981244769
Short name T530
Test name
Test status
Simulation time 26343265 ps
CPU time 0.88 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201140 kb
Host smart-9d8f0bea-60aa-41ad-a727-522fb48ed0cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981244769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1981244769
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.3764462631
Short name T14
Test name
Test status
Simulation time 1634631846 ps
CPU time 12.59 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201180 kb
Host smart-3663bac0-5874-4fd6-8f40-2759aba4d981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764462631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3764462631
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1835804785
Short name T226
Test name
Test status
Simulation time 2298781278 ps
CPU time 8.58 seconds
Started Jul 29 07:33:35 PM PDT 24
Finished Jul 29 07:33:44 PM PDT 24
Peak memory 201476 kb
Host smart-4d655ed6-eac2-46a9-8781-2f09986f387a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835804785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1835804785
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.79879093
Short name T381
Test name
Test status
Simulation time 340827107 ps
CPU time 1.87 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:42 PM PDT 24
Peak memory 201124 kb
Host smart-dc1261db-00d2-44c3-aa4d-5532f9938c4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79879093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.clkmgr_idle_intersig_mubi.79879093
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.4186732961
Short name T731
Test name
Test status
Simulation time 36746732 ps
CPU time 0.8 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201096 kb
Host smart-2ca9bd13-e885-468f-aedd-a1e39d457917
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186732961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.4186732961
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1629961243
Short name T351
Test name
Test status
Simulation time 23874410 ps
CPU time 0.86 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 201112 kb
Host smart-f2db611d-1f6e-42bd-bc92-6845d7669aa0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629961243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1629961243
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.524274850
Short name T157
Test name
Test status
Simulation time 12424508 ps
CPU time 0.72 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201020 kb
Host smart-b1137b81-29ec-4538-9dc9-87385df13933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524274850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.524274850
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.2699014738
Short name T516
Test name
Test status
Simulation time 997307905 ps
CPU time 4.09 seconds
Started Jul 29 07:33:43 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201044 kb
Host smart-b0b6ad55-8fa3-4c86-898c-2b2bb453c6f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699014738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2699014738
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.1923676757
Short name T403
Test name
Test status
Simulation time 23770216 ps
CPU time 0.9 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 200832 kb
Host smart-467ae74a-126a-4d15-98e6-e9e9e08069e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923676757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1923676757
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1544261260
Short name T195
Test name
Test status
Simulation time 474736731 ps
CPU time 2.83 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201116 kb
Host smart-9c2892ac-a337-4502-a66b-1df418f1be49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544261260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1544261260
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2312841583
Short name T52
Test name
Test status
Simulation time 17047214 ps
CPU time 0.76 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201036 kb
Host smart-10de4ab8-66a1-41d6-bf6b-b5be10f17006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312841583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2312841583
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.4046907522
Short name T233
Test name
Test status
Simulation time 34897915 ps
CPU time 0.87 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 200892 kb
Host smart-b352f88f-60f5-482a-a182-92bf710e845c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046907522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.4046907522
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2572105896
Short name T359
Test name
Test status
Simulation time 29174299 ps
CPU time 0.93 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201012 kb
Host smart-f01a8015-340d-4f22-86a0-c55d2b4b38b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572105896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.2572105896
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.378694529
Short name T655
Test name
Test status
Simulation time 15441992 ps
CPU time 0.7 seconds
Started Jul 29 07:33:58 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 201028 kb
Host smart-215244ed-9acc-486b-9bd5-d0430afff8ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378694529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.378694529
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.2298637643
Short name T511
Test name
Test status
Simulation time 44361931 ps
CPU time 0.82 seconds
Started Jul 29 07:33:43 PM PDT 24
Finished Jul 29 07:33:44 PM PDT 24
Peak memory 200860 kb
Host smart-ea5f210e-27cb-48ff-8654-e5196c921cef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298637643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.2298637643
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.1953558324
Short name T283
Test name
Test status
Simulation time 30779510 ps
CPU time 1.04 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 200908 kb
Host smart-4fc23ad9-e2c9-4941-bc15-0e4e5d06626a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953558324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1953558324
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.4108332670
Short name T128
Test name
Test status
Simulation time 827017055 ps
CPU time 4.12 seconds
Started Jul 29 07:33:39 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201152 kb
Host smart-ca125e73-bf1c-423c-bbe2-a9ccb5f48682
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108332670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.4108332670
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.2989915625
Short name T521
Test name
Test status
Simulation time 887217189 ps
CPU time 3.83 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201212 kb
Host smart-a9d9c89b-f6df-4e25-bd14-4605975ab244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989915625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.2989915625
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3533495712
Short name T393
Test name
Test status
Simulation time 31736709 ps
CPU time 0.95 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 200868 kb
Host smart-73e542fc-65c7-4efb-8c10-342d82c72820
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533495712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.3533495712
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.4173045965
Short name T362
Test name
Test status
Simulation time 26722925 ps
CPU time 0.98 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201120 kb
Host smart-9f8b6d75-e090-4ba6-a2c1-c00e85f1e266
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173045965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.4173045965
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1218350932
Short name T711
Test name
Test status
Simulation time 42673674 ps
CPU time 0.98 seconds
Started Jul 29 07:33:43 PM PDT 24
Finished Jul 29 07:33:44 PM PDT 24
Peak memory 200856 kb
Host smart-1eef56b9-1f6e-410c-b33c-26d78255789e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218350932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.1218350932
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2260872634
Short name T373
Test name
Test status
Simulation time 21660709 ps
CPU time 0.82 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 200972 kb
Host smart-47eeae50-19f7-4749-bedb-199625f7c23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260872634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2260872634
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.3850747476
Short name T813
Test name
Test status
Simulation time 1455203904 ps
CPU time 5.33 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:40 PM PDT 24
Peak memory 201192 kb
Host smart-be9b62f0-19ad-489f-8603-0962fd2b73c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850747476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.3850747476
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.1484222212
Short name T429
Test name
Test status
Simulation time 25373778 ps
CPU time 0.91 seconds
Started Jul 29 07:33:30 PM PDT 24
Finished Jul 29 07:33:32 PM PDT 24
Peak memory 201108 kb
Host smart-1c371440-2bcb-4da7-8291-5525f429073f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484222212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.1484222212
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.159268188
Short name T319
Test name
Test status
Simulation time 6089884238 ps
CPU time 42.56 seconds
Started Jul 29 07:33:31 PM PDT 24
Finished Jul 29 07:34:13 PM PDT 24
Peak memory 201452 kb
Host smart-2329e6a7-c3f3-42cc-8d21-85f9bca44781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159268188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.159268188
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.3573775217
Short name T293
Test name
Test status
Simulation time 83335999 ps
CPU time 1.04 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201100 kb
Host smart-7cb5d90a-ea60-4406-a616-e6c57985b035
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573775217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.3573775217
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3486552981
Short name T664
Test name
Test status
Simulation time 16631052 ps
CPU time 0.78 seconds
Started Jul 29 07:33:40 PM PDT 24
Finished Jul 29 07:33:41 PM PDT 24
Peak memory 201112 kb
Host smart-e89694c0-6489-4963-aa85-64e0326abef3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486552981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3486552981
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.3098309655
Short name T761
Test name
Test status
Simulation time 28858988 ps
CPU time 0.95 seconds
Started Jul 29 07:33:39 PM PDT 24
Finished Jul 29 07:33:40 PM PDT 24
Peak memory 201120 kb
Host smart-379e5d39-7620-49ad-8821-d9780c9ac40c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098309655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.3098309655
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.97545299
Short name T164
Test name
Test status
Simulation time 14156312 ps
CPU time 0.71 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 200304 kb
Host smart-25fe7ec7-e650-4bc0-b4fc-96ee4a277881
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97545299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.97545299
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.3933808136
Short name T168
Test name
Test status
Simulation time 91275453 ps
CPU time 1.08 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201100 kb
Host smart-8b5693f1-dae5-48bb-af59-eeeec0a9bb3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933808136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.3933808136
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3419109741
Short name T630
Test name
Test status
Simulation time 21259399 ps
CPU time 0.83 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201020 kb
Host smart-d863b18d-827f-4584-90f5-1763912cc9eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419109741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3419109741
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.3192104565
Short name T497
Test name
Test status
Simulation time 1165484649 ps
CPU time 6.88 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 200944 kb
Host smart-0042f147-2464-48f9-8247-10e185ebaa47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192104565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.3192104565
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3990669876
Short name T509
Test name
Test status
Simulation time 2417967887 ps
CPU time 17.19 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201308 kb
Host smart-403bcc8f-76fd-4edb-aa97-ee119f1fd13d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990669876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3990669876
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3155063805
Short name T615
Test name
Test status
Simulation time 119958328 ps
CPU time 1.25 seconds
Started Jul 29 07:33:34 PM PDT 24
Finished Jul 29 07:33:35 PM PDT 24
Peak memory 200876 kb
Host smart-f4229a9c-be45-4406-9cb0-807fd173e530
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155063805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3155063805
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2667918608
Short name T477
Test name
Test status
Simulation time 97771535 ps
CPU time 1 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201080 kb
Host smart-8d328549-7231-4e4b-a13a-55fbb23435cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667918608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2667918608
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3259524905
Short name T526
Test name
Test status
Simulation time 86863204 ps
CPU time 0.92 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201076 kb
Host smart-bed5f421-f226-44a7-95f5-2bce8e4f45e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259524905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3259524905
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.490352816
Short name T476
Test name
Test status
Simulation time 28463173 ps
CPU time 0.73 seconds
Started Jul 29 07:33:43 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201072 kb
Host smart-e8f1e4e7-5ce9-4464-a64f-b0aa5a3bc292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490352816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.490352816
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3793043509
Short name T279
Test name
Test status
Simulation time 1017720714 ps
CPU time 4.73 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:42 PM PDT 24
Peak memory 201176 kb
Host smart-3ffff44e-191f-45ca-a51a-dd7a908b3b11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793043509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3793043509
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.1126043286
Short name T98
Test name
Test status
Simulation time 17685641 ps
CPU time 0.82 seconds
Started Jul 29 07:34:02 PM PDT 24
Finished Jul 29 07:34:03 PM PDT 24
Peak memory 201044 kb
Host smart-987c6fc4-205e-4ad3-97c1-c90a991817fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126043286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1126043286
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.1093650746
Short name T766
Test name
Test status
Simulation time 7892228104 ps
CPU time 31.76 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:34:14 PM PDT 24
Peak memory 201244 kb
Host smart-7040b317-2120-4aaa-9f27-ecbe9d503ae3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093650746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.1093650746
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.1271453825
Short name T161
Test name
Test status
Simulation time 26227235646 ps
CPU time 389.07 seconds
Started Jul 29 07:33:41 PM PDT 24
Finished Jul 29 07:40:10 PM PDT 24
Peak memory 209616 kb
Host smart-e09d2598-8f66-4910-8bdd-196cffec2571
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1271453825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.1271453825
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1067749610
Short name T573
Test name
Test status
Simulation time 68098685 ps
CPU time 1.06 seconds
Started Jul 29 07:33:38 PM PDT 24
Finished Jul 29 07:33:39 PM PDT 24
Peak memory 201096 kb
Host smart-1a117fdc-4525-42d0-a6e3-2259ab4a9c6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067749610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1067749610
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.2507203457
Short name T736
Test name
Test status
Simulation time 18379321 ps
CPU time 0.81 seconds
Started Jul 29 07:34:04 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 201064 kb
Host smart-1e5509cc-79e0-4225-827e-07da3d40f30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507203457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.2507203457
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3618014653
Short name T90
Test name
Test status
Simulation time 28373868 ps
CPU time 0.98 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201000 kb
Host smart-b57b909c-bd86-4742-b430-29fcaf39a9f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618014653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.3618014653
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.2410585363
Short name T579
Test name
Test status
Simulation time 32401214 ps
CPU time 0.75 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 200940 kb
Host smart-d7359fcf-10c1-4f59-ac38-7940a090120b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410585363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2410585363
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.53447291
Short name T487
Test name
Test status
Simulation time 24854411 ps
CPU time 0.91 seconds
Started Jul 29 07:34:03 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 201084 kb
Host smart-63573793-d530-4fb1-953e-ab2c919966f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53447291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.clkmgr_div_intersig_mubi.53447291
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.639251708
Short name T151
Test name
Test status
Simulation time 17922591 ps
CPU time 0.8 seconds
Started Jul 29 07:33:37 PM PDT 24
Finished Jul 29 07:33:38 PM PDT 24
Peak memory 201016 kb
Host smart-b9fbc1bc-7733-441f-9559-029027a92008
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639251708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.639251708
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1742990376
Short name T206
Test name
Test status
Simulation time 1162933730 ps
CPU time 9.51 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 201188 kb
Host smart-1b1b40f1-68bb-4ab3-8b59-dfedbc8567b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742990376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1742990376
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.3497435607
Short name T554
Test name
Test status
Simulation time 984285053 ps
CPU time 5.75 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201172 kb
Host smart-c776fe31-40fd-4368-b208-cca63be66591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497435607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.3497435607
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1967085946
Short name T408
Test name
Test status
Simulation time 51520001 ps
CPU time 1.04 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201044 kb
Host smart-0a03741c-2377-402d-9129-d8ea93c335b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967085946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1967085946
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.371485945
Short name T120
Test name
Test status
Simulation time 22497777 ps
CPU time 0.86 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:47 PM PDT 24
Peak memory 201076 kb
Host smart-21fcc83a-58d4-47de-992a-98115c861324
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371485945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_clk_byp_req_intersig_mubi.371485945
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.867098162
Short name T122
Test name
Test status
Simulation time 56760876 ps
CPU time 0.84 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:43 PM PDT 24
Peak memory 201068 kb
Host smart-4ae4bb38-029f-4439-931e-5b7fd7993cf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867098162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_ctrl_intersig_mubi.867098162
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1635542961
Short name T779
Test name
Test status
Simulation time 17761939 ps
CPU time 0.79 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201084 kb
Host smart-39f5cf04-11eb-4790-9b7f-a8504d3e04de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635542961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1635542961
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.621852329
Short name T481
Test name
Test status
Simulation time 1175152112 ps
CPU time 5.11 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:33:47 PM PDT 24
Peak memory 201312 kb
Host smart-87d04e2f-11e8-42ae-aa95-b3efd0cb2e18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621852329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.621852329
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.1785704351
Short name T289
Test name
Test status
Simulation time 24630628 ps
CPU time 0.82 seconds
Started Jul 29 07:34:04 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 201048 kb
Host smart-46415d56-fd9d-408e-87a2-dd43b859120a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785704351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1785704351
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.3294920786
Short name T563
Test name
Test status
Simulation time 775443378 ps
CPU time 6.09 seconds
Started Jul 29 07:33:39 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 201156 kb
Host smart-3b2e0e77-d7bd-4a37-8947-5743f9158e0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294920786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.3294920786
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2396836688
Short name T154
Test name
Test status
Simulation time 95023534838 ps
CPU time 601.15 seconds
Started Jul 29 07:33:42 PM PDT 24
Finished Jul 29 07:43:43 PM PDT 24
Peak memory 217920 kb
Host smart-602ee9d0-17bf-4140-acfa-0c86f221835d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2396836688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2396836688
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1053056146
Short name T482
Test name
Test status
Simulation time 51901776 ps
CPU time 0.81 seconds
Started Jul 29 07:33:36 PM PDT 24
Finished Jul 29 07:33:37 PM PDT 24
Peak memory 201064 kb
Host smart-3e31a8d9-38e3-4673-81ae-3b629446ac03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053056146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1053056146
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.2682175387
Short name T670
Test name
Test status
Simulation time 21762912 ps
CPU time 0.79 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201084 kb
Host smart-d9762de7-a3b3-4f4a-a00d-3071b4d96d19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682175387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.2682175387
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2832161494
Short name T803
Test name
Test status
Simulation time 24041916 ps
CPU time 0.85 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201072 kb
Host smart-6a64d4f2-5eb1-4acb-97e1-611316d549fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832161494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.2832161494
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2264019305
Short name T238
Test name
Test status
Simulation time 49636920 ps
CPU time 0.77 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 200220 kb
Host smart-cc1a7807-137a-4b89-94c0-040c7d8f6464
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264019305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2264019305
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.3805119501
Short name T282
Test name
Test status
Simulation time 28431637 ps
CPU time 0.79 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201068 kb
Host smart-76df1cf9-8387-4f73-88a3-17e7b43a3752
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805119501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.3805119501
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3386328404
Short name T149
Test name
Test status
Simulation time 137328069 ps
CPU time 1.16 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 200952 kb
Host smart-204661a8-6573-47e0-b2a3-ca5b314b61ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386328404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3386328404
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.3747259687
Short name T225
Test name
Test status
Simulation time 1889056154 ps
CPU time 8.75 seconds
Started Jul 29 07:34:03 PM PDT 24
Finished Jul 29 07:34:12 PM PDT 24
Peak memory 201456 kb
Host smart-aa7787ad-cbf6-4a85-81f3-3b3e55fcb009
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747259687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3747259687
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2283684943
Short name T762
Test name
Test status
Simulation time 1336475444 ps
CPU time 8.15 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 201196 kb
Host smart-01f1b3c2-06f4-4b70-bc45-6b54522bbe1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283684943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2283684943
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.1419235611
Short name T629
Test name
Test status
Simulation time 221888221 ps
CPU time 1.51 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201028 kb
Host smart-6864cd0e-c151-49d4-a512-0ca944cdccca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419235611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.1419235611
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1601655386
Short name T748
Test name
Test status
Simulation time 31674255 ps
CPU time 0.81 seconds
Started Jul 29 07:33:49 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 201064 kb
Host smart-a35ee20d-8609-4ce3-b4d7-0428dfa565d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601655386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1601655386
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.3368725962
Short name T213
Test name
Test status
Simulation time 50680227 ps
CPU time 0.81 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 201008 kb
Host smart-cab13129-cd6c-466b-a01e-56a612ee390f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368725962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.3368725962
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.528626835
Short name T275
Test name
Test status
Simulation time 40772559 ps
CPU time 0.91 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201056 kb
Host smart-c6e9362c-fbd4-43c7-9628-b109dee5fe52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528626835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.528626835
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.533053539
Short name T691
Test name
Test status
Simulation time 881628570 ps
CPU time 3.42 seconds
Started Jul 29 07:34:03 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 201236 kb
Host smart-3f330552-8893-46e3-ab9d-ab31d1362ef3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533053539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.533053539
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.2172387995
Short name T529
Test name
Test status
Simulation time 266206587 ps
CPU time 1.53 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201160 kb
Host smart-7238d7ef-42bd-4cce-af9d-5e1ca5ffe5b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172387995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2172387995
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1078876503
Short name T307
Test name
Test status
Simulation time 5280338568 ps
CPU time 22.32 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:34:18 PM PDT 24
Peak memory 201456 kb
Host smart-2e8e4cfd-4467-4463-90ec-74a345084fa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078876503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1078876503
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1532622986
Short name T160
Test name
Test status
Simulation time 279233476141 ps
CPU time 1087.61 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:51:56 PM PDT 24
Peak memory 217864 kb
Host smart-5d36d4ba-de22-4833-9b94-3bb2a20901e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1532622986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1532622986
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.854202433
Short name T725
Test name
Test status
Simulation time 78503193 ps
CPU time 1.09 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201232 kb
Host smart-f2bae2ed-4e52-4c2e-8fbe-f6b7fdaaf2a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854202433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.854202433
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.1707878824
Short name T360
Test name
Test status
Simulation time 64807896 ps
CPU time 0.91 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201044 kb
Host smart-6b15cd6a-8b6c-4495-b20a-2e7fa7ed2ca8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707878824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.1707878824
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1592750795
Short name T534
Test name
Test status
Simulation time 41072949 ps
CPU time 0.8 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 200980 kb
Host smart-fca6ca87-b3e8-407d-9a89-e9c922ff4f32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592750795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.1592750795
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.3086283514
Short name T76
Test name
Test status
Simulation time 51985796 ps
CPU time 0.81 seconds
Started Jul 29 07:34:03 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 200228 kb
Host smart-9d575433-9eda-4940-a30e-c232ba9ca0bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086283514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.3086283514
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3825342404
Short name T724
Test name
Test status
Simulation time 76472179 ps
CPU time 1.04 seconds
Started Jul 29 07:34:06 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 201112 kb
Host smart-15cbbb69-b841-4b8e-8beb-6281db509339
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825342404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3825342404
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.895496511
Short name T234
Test name
Test status
Simulation time 24946374 ps
CPU time 0.84 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201032 kb
Host smart-ad9b90aa-92c1-4ef4-b92e-cda8f8d1a437
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895496511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.895496511
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1704962253
Short name T276
Test name
Test status
Simulation time 313816636 ps
CPU time 1.61 seconds
Started Jul 29 07:34:00 PM PDT 24
Finished Jul 29 07:34:02 PM PDT 24
Peak memory 201112 kb
Host smart-e3fb3a36-1946-4db8-b604-fdfb6399d396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704962253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1704962253
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.4228601179
Short name T782
Test name
Test status
Simulation time 1236528240 ps
CPU time 4.79 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:06 PM PDT 24
Peak memory 201192 kb
Host smart-4f5096aa-c4a2-44cc-a7ef-3adc75c9194f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228601179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.4228601179
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.738481144
Short name T737
Test name
Test status
Simulation time 97907049 ps
CPU time 0.97 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 201044 kb
Host smart-7cc33231-4111-4db7-a443-5e5e080b8739
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738481144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_idle_intersig_mubi.738481144
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.125589110
Short name T741
Test name
Test status
Simulation time 77533514 ps
CPU time 1.02 seconds
Started Jul 29 07:34:00 PM PDT 24
Finished Jul 29 07:34:01 PM PDT 24
Peak memory 201052 kb
Host smart-420cc366-37d7-4b16-a7bf-489e54eb6ec4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125589110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_clk_byp_req_intersig_mubi.125589110
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3426816840
Short name T437
Test name
Test status
Simulation time 21881987 ps
CPU time 0.8 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 201280 kb
Host smart-0aef3e66-7501-446c-a058-93ca712785ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426816840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.3426816840
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3247586770
Short name T39
Test name
Test status
Simulation time 40957897 ps
CPU time 0.79 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:46 PM PDT 24
Peak memory 201068 kb
Host smart-5073b3cc-1073-4d45-9dd7-ae15c5dc9727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247586770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3247586770
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.2505351060
Short name T9
Test name
Test status
Simulation time 816452874 ps
CPU time 4.77 seconds
Started Jul 29 07:33:45 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 201272 kb
Host smart-53ae30ab-ffc4-4f29-b552-af9e19b53621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505351060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2505351060
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2154711037
Short name T147
Test name
Test status
Simulation time 24973796 ps
CPU time 0.86 seconds
Started Jul 29 07:34:04 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 200952 kb
Host smart-8354e86b-461c-4131-bab3-679908119fe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154711037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2154711037
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.2202664011
Short name T712
Test name
Test status
Simulation time 7656508355 ps
CPU time 40.34 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:34:29 PM PDT 24
Peak memory 201392 kb
Host smart-9c4d3317-e9b5-4fd7-860a-604acbbc57eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202664011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.2202664011
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.2625295748
Short name T458
Test name
Test status
Simulation time 533074136046 ps
CPU time 2024.7 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 08:07:29 PM PDT 24
Peak memory 214328 kb
Host smart-d76c0de4-5130-450d-995d-763b7d2425bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2625295748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.2625295748
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.1983236665
Short name T755
Test name
Test status
Simulation time 34083173 ps
CPU time 1.01 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201100 kb
Host smart-561e134c-92da-4af0-ad3f-dc89ce0ce532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983236665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.1983236665
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.1616777568
Short name T810
Test name
Test status
Simulation time 18622519 ps
CPU time 0.77 seconds
Started Jul 29 07:34:06 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 201104 kb
Host smart-6a503b27-1b8a-4b27-96f1-f45669ac4895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616777568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.1616777568
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.533767275
Short name T53
Test name
Test status
Simulation time 27764549 ps
CPU time 0.79 seconds
Started Jul 29 07:33:49 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 201160 kb
Host smart-5cccc673-49d2-40a1-8adf-fedbbd1ba67c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533767275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.533767275
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.341638295
Short name T415
Test name
Test status
Simulation time 39466035 ps
CPU time 0.72 seconds
Started Jul 29 07:33:49 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 200148 kb
Host smart-2df0c3e7-6b3e-4ae1-b3e6-249be562e091
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341638295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.341638295
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2203889359
Short name T614
Test name
Test status
Simulation time 73874664 ps
CPU time 0.97 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201100 kb
Host smart-317a8194-e0b5-4c18-96fd-b9f2fc2412eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203889359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.2203889359
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.528542977
Short name T313
Test name
Test status
Simulation time 26519550 ps
CPU time 0.93 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:02 PM PDT 24
Peak memory 201072 kb
Host smart-1cc3b437-8a01-4346-af66-ac2764fec3cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528542977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.528542977
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.1263679763
Short name T404
Test name
Test status
Simulation time 202297905 ps
CPU time 2.39 seconds
Started Jul 29 07:34:02 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 201148 kb
Host smart-8ab8ef44-1c16-4c51-837d-7ff1b102f88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263679763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1263679763
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.306558845
Short name T445
Test name
Test status
Simulation time 1455012502 ps
CPU time 11.54 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 201176 kb
Host smart-aff0cc1f-f2bf-4429-9638-e68bd6078f1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306558845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti
meout.306558845
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.957674206
Short name T468
Test name
Test status
Simulation time 316408184 ps
CPU time 1.78 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201020 kb
Host smart-c05ee54e-95e1-4f99-a745-6684a8eab860
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957674206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_idle_intersig_mubi.957674206
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.4276470782
Short name T654
Test name
Test status
Simulation time 68619223 ps
CPU time 1 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 201160 kb
Host smart-2152be76-d24b-4444-a0fd-910271cd7982
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276470782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.4276470782
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3408446625
Short name T241
Test name
Test status
Simulation time 33846278 ps
CPU time 0.95 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201088 kb
Host smart-57065d6b-a89c-419a-a9c8-a4fcd1545860
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408446625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.3408446625
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1055373154
Short name T538
Test name
Test status
Simulation time 52261960 ps
CPU time 0.86 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201088 kb
Host smart-e8dd5cdd-88c6-40d9-9d89-de77b606b1a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055373154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1055373154
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.3341735100
Short name T355
Test name
Test status
Simulation time 592343185 ps
CPU time 3.44 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:57 PM PDT 24
Peak memory 201220 kb
Host smart-cc6fa37b-6ca2-4517-a83f-970632953125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341735100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.3341735100
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.3445652686
Short name T78
Test name
Test status
Simulation time 37089279 ps
CPU time 0.87 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 200988 kb
Host smart-d81bceca-68cd-48cd-8891-8211945a451e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445652686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3445652686
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.3689000307
Short name T146
Test name
Test status
Simulation time 3674079572 ps
CPU time 20.29 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 201620 kb
Host smart-0ae0f092-342f-493d-a1af-e91cb97d0266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689000307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3689000307
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.4007903015
Short name T69
Test name
Test status
Simulation time 223744404802 ps
CPU time 1323.1 seconds
Started Jul 29 07:34:09 PM PDT 24
Finished Jul 29 07:56:13 PM PDT 24
Peak memory 217936 kb
Host smart-cd4b246f-bcef-4094-9e04-8ded866c122a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4007903015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.4007903015
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.2669052523
Short name T543
Test name
Test status
Simulation time 70636166 ps
CPU time 0.98 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201044 kb
Host smart-61245743-da1d-49e2-9b57-6b81b34941dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669052523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.2669052523
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1388398775
Short name T40
Test name
Test status
Simulation time 46416138 ps
CPU time 0.8 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201124 kb
Host smart-0f3abe04-44e2-4ac1-9ec4-501d07c2d1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388398775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1388398775
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1572481604
Short name T299
Test name
Test status
Simulation time 16832907 ps
CPU time 0.79 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 201072 kb
Host smart-1b989bf1-84eb-4d1e-8fd7-3266ca51fc19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572481604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1572481604
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.4077624859
Short name T716
Test name
Test status
Simulation time 56225408 ps
CPU time 0.79 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 200956 kb
Host smart-87f57a26-876f-45d3-8ccd-032c587744a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077624859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.4077624859
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.897497540
Short name T249
Test name
Test status
Simulation time 36506057 ps
CPU time 0.78 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 201108 kb
Host smart-f7f00dec-1030-4ec6-901f-fb43f1a36902
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897497540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.897497540
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3617826108
Short name T809
Test name
Test status
Simulation time 64167063 ps
CPU time 0.94 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201076 kb
Host smart-9a7d6b57-1cff-4ac3-9246-3879d1c16b74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617826108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3617826108
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.2507319752
Short name T575
Test name
Test status
Simulation time 2481598802 ps
CPU time 19.58 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201388 kb
Host smart-6579b473-1ef2-465b-9a37-2873027b9b18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507319752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2507319752
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2144617059
Short name T439
Test name
Test status
Simulation time 744098602 ps
CPU time 4.41 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:35 PM PDT 24
Peak memory 201184 kb
Host smart-53365488-dd56-4dee-b4c8-ab276501e382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144617059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2144617059
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1193618611
Short name T764
Test name
Test status
Simulation time 16468686 ps
CPU time 0.75 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 201040 kb
Host smart-1fc400c2-2cdc-499c-8919-962c7f6c0866
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193618611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1193618611
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3244435866
Short name T287
Test name
Test status
Simulation time 21008563 ps
CPU time 0.86 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201152 kb
Host smart-2f50f5ef-23d6-4e1b-8070-11efb70fefbc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244435866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3244435866
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3837283141
Short name T356
Test name
Test status
Simulation time 22217990 ps
CPU time 0.88 seconds
Started Jul 29 07:32:21 PM PDT 24
Finished Jul 29 07:32:22 PM PDT 24
Peak memory 200996 kb
Host smart-2f28458e-cd04-4277-946d-0f342fae0c24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837283141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.3837283141
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.3725519227
Short name T285
Test name
Test status
Simulation time 12643863 ps
CPU time 0.71 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201072 kb
Host smart-74bd1945-5483-4e36-b098-c0e52e4e72b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725519227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3725519227
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.3344451802
Short name T674
Test name
Test status
Simulation time 460771153 ps
CPU time 3.04 seconds
Started Jul 29 07:32:43 PM PDT 24
Finished Jul 29 07:32:46 PM PDT 24
Peak memory 201048 kb
Host smart-5e0caa2b-4d19-4946-847f-100aced4e5fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344451802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.3344451802
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.2564612811
Short name T483
Test name
Test status
Simulation time 15803689 ps
CPU time 0.8 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 200984 kb
Host smart-02b65e93-94e6-4ac8-8c7e-041de6014ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564612811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2564612811
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all_with_rand_reset.2269075657
Short name T70
Test name
Test status
Simulation time 38402507976 ps
CPU time 420.33 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:39:26 PM PDT 24
Peak memory 209844 kb
Host smart-97cc1273-8d1c-431a-bed8-2206ffce1a9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2269075657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.2269075657
Directory /workspace/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.clkmgr_trans.2775458516
Short name T407
Test name
Test status
Simulation time 81109850 ps
CPU time 1.16 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201092 kb
Host smart-c1f7bad0-f721-4be8-8939-9f70fe366087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775458516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2775458516
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.646494093
Short name T745
Test name
Test status
Simulation time 12309878 ps
CPU time 0.71 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201116 kb
Host smart-77c182c8-09f6-42ad-b99c-9a4ab25a2862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646494093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkm
gr_alert_test.646494093
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.1425243359
Short name T443
Test name
Test status
Simulation time 56797190 ps
CPU time 0.89 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201056 kb
Host smart-ed159404-e8f3-4808-acef-a1b2bdc81eb9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425243359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.1425243359
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.3501187622
Short name T695
Test name
Test status
Simulation time 14123173 ps
CPU time 0.71 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 200180 kb
Host smart-3d9c0f22-68aa-496a-9b7c-8f9a28994315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501187622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3501187622
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.760985539
Short name T577
Test name
Test status
Simulation time 12785294 ps
CPU time 0.7 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 201028 kb
Host smart-83ad146d-43f3-4e9d-87bc-f637497140bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760985539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.760985539
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1643025219
Short name T451
Test name
Test status
Simulation time 25699661 ps
CPU time 0.78 seconds
Started Jul 29 07:33:59 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 201080 kb
Host smart-45d7f9e7-f5f8-4c9f-9069-eae4dff32134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643025219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1643025219
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.3892879353
Short name T130
Test name
Test status
Simulation time 1162054335 ps
CPU time 8.04 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201136 kb
Host smart-7deed6b4-f176-4715-a8db-7993c9478306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892879353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3892879353
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.2944887444
Short name T658
Test name
Test status
Simulation time 1334546431 ps
CPU time 10.01 seconds
Started Jul 29 07:33:49 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 201240 kb
Host smart-3ef11191-fd4d-4390-9ff5-542c7b82e182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944887444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.2944887444
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.3989522972
Short name T272
Test name
Test status
Simulation time 29099495 ps
CPU time 0.97 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 200992 kb
Host smart-edf86167-688b-45e5-979c-91031f7008f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989522972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.3989522972
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1596485978
Short name T203
Test name
Test status
Simulation time 39829838 ps
CPU time 0.81 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201048 kb
Host smart-f788143f-9acd-4e74-9237-d16cce30c6f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596485978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1596485978
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.4062748315
Short name T372
Test name
Test status
Simulation time 23187489 ps
CPU time 0.81 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201048 kb
Host smart-defca411-733d-4aa7-84a6-efdddd851ca3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062748315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.4062748315
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2489829785
Short name T734
Test name
Test status
Simulation time 13753131 ps
CPU time 0.68 seconds
Started Jul 29 07:33:44 PM PDT 24
Finished Jul 29 07:33:45 PM PDT 24
Peak memory 201068 kb
Host smart-4df1113c-31ac-41bb-ae71-13196b02c9b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489829785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2489829785
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.12212661
Short name T271
Test name
Test status
Simulation time 500816513 ps
CPU time 2.37 seconds
Started Jul 29 07:33:59 PM PDT 24
Finished Jul 29 07:34:01 PM PDT 24
Peak memory 201132 kb
Host smart-8a93c86c-6ff7-4a6d-a322-f3ce2a7306db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12212661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.12212661
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.3464960217
Short name T496
Test name
Test status
Simulation time 39046521 ps
CPU time 0.87 seconds
Started Jul 29 07:34:07 PM PDT 24
Finished Jul 29 07:34:08 PM PDT 24
Peak memory 201044 kb
Host smart-b83b643d-656b-47a8-af34-585215142ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464960217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3464960217
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.661624911
Short name T54
Test name
Test status
Simulation time 2330115610 ps
CPU time 17.07 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:34:12 PM PDT 24
Peak memory 201464 kb
Host smart-e937290f-590a-40c1-9bcb-31af5601522f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661624911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.661624911
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.3627540572
Short name T186
Test name
Test status
Simulation time 19667709 ps
CPU time 0.77 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 200896 kb
Host smart-371782e7-f005-44c5-a20c-44c1766c7b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627540572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3627540572
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1279416298
Short name T499
Test name
Test status
Simulation time 38089684 ps
CPU time 0.78 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:01 PM PDT 24
Peak memory 201016 kb
Host smart-795d785a-a6dc-40a6-9952-8f53539fb5d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279416298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1279416298
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1891328464
Short name T33
Test name
Test status
Simulation time 16564442 ps
CPU time 0.76 seconds
Started Jul 29 07:34:05 PM PDT 24
Finished Jul 29 07:34:06 PM PDT 24
Peak memory 201080 kb
Host smart-e103d9e8-f32d-48b9-bf6c-9fc0c5037657
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891328464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1891328464
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.450420104
Short name T99
Test name
Test status
Simulation time 37183730 ps
CPU time 0.75 seconds
Started Jul 29 07:34:10 PM PDT 24
Finished Jul 29 07:34:11 PM PDT 24
Peak memory 201008 kb
Host smart-c5d2b63a-ac50-4704-b9e6-2486afca23a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450420104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.450420104
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.2884194185
Short name T402
Test name
Test status
Simulation time 80050501 ps
CPU time 1 seconds
Started Jul 29 07:34:08 PM PDT 24
Finished Jul 29 07:34:09 PM PDT 24
Peak memory 201064 kb
Host smart-fc13e17e-7e04-4833-9110-a0bd4e13c155
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884194185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.2884194185
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.2191979223
Short name T798
Test name
Test status
Simulation time 26654269 ps
CPU time 0.75 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201072 kb
Host smart-26cdbf5d-1fbd-417f-9174-545bd4f624f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191979223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2191979223
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1630002829
Short name T747
Test name
Test status
Simulation time 458839998 ps
CPU time 2.2 seconds
Started Jul 29 07:33:50 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201220 kb
Host smart-85eac3b2-e0bd-4216-b45c-77f8944a0179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630002829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1630002829
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.107525509
Short name T690
Test name
Test status
Simulation time 1221519972 ps
CPU time 8.83 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:34:01 PM PDT 24
Peak memory 201024 kb
Host smart-db31de4f-35a4-4f1f-851c-70cf2f5e884c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107525509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.107525509
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.987795920
Short name T80
Test name
Test status
Simulation time 110312942 ps
CPU time 1.21 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 200980 kb
Host smart-a0456319-9b28-4dfd-9f8e-5ed80bf44ee5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987795920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_idle_intersig_mubi.987795920
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2639390595
Short name T720
Test name
Test status
Simulation time 22869376 ps
CPU time 0.87 seconds
Started Jul 29 07:34:00 PM PDT 24
Finished Jul 29 07:34:01 PM PDT 24
Peak memory 200996 kb
Host smart-cbcc55a7-c23e-43c8-92e3-922d94978a60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639390595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2639390595
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3540791265
Short name T357
Test name
Test status
Simulation time 14577038 ps
CPU time 0.73 seconds
Started Jul 29 07:33:51 PM PDT 24
Finished Jul 29 07:33:52 PM PDT 24
Peak memory 201000 kb
Host smart-ed1a0fe6-ef26-4b5f-8519-79ef80c08ec4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540791265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.3540791265
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3899767494
Short name T447
Test name
Test status
Simulation time 16939445 ps
CPU time 0.74 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201064 kb
Host smart-9ce9db3a-1144-4950-b056-49e3f07bee96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899767494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3899767494
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.1651509251
Short name T450
Test name
Test status
Simulation time 182111927 ps
CPU time 1.56 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201120 kb
Host smart-5ceda66a-37a2-4ee6-9655-9d24963af57b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651509251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.1651509251
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1934427038
Short name T345
Test name
Test status
Simulation time 45585296 ps
CPU time 0.86 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 200948 kb
Host smart-ab33fe66-6a3c-4662-a96d-4cf773d6a0ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934427038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1934427038
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.1466263841
Short name T430
Test name
Test status
Simulation time 2947622395 ps
CPU time 23.18 seconds
Started Jul 29 07:34:09 PM PDT 24
Finished Jul 29 07:34:32 PM PDT 24
Peak memory 201464 kb
Host smart-b30de3a6-999c-4764-b294-93f7ca051116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466263841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.1466263841
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.1821353273
Short name T153
Test name
Test status
Simulation time 185145458976 ps
CPU time 987.94 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:50:16 PM PDT 24
Peak memory 213708 kb
Host smart-dec053b4-24bb-4d6a-a83f-665f9e9ee92f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1821353273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.1821353273
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.906066678
Short name T692
Test name
Test status
Simulation time 23728169 ps
CPU time 0.85 seconds
Started Jul 29 07:33:47 PM PDT 24
Finished Jul 29 07:33:48 PM PDT 24
Peak memory 201000 kb
Host smart-f580c489-2c87-4c82-8f5a-ba533bf3b5be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906066678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.906066678
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.992657049
Short name T239
Test name
Test status
Simulation time 68878569 ps
CPU time 0.88 seconds
Started Jul 29 07:34:03 PM PDT 24
Finished Jul 29 07:34:04 PM PDT 24
Peak memory 201120 kb
Host smart-67d33f06-c989-4c3f-a496-603a89aa8969
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992657049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkm
gr_alert_test.992657049
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.3326675624
Short name T374
Test name
Test status
Simulation time 31924699 ps
CPU time 0.81 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201036 kb
Host smart-41cefbeb-3fa3-4454-97ad-4f2d37429933
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326675624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.3326675624
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.713567835
Short name T606
Test name
Test status
Simulation time 40724014 ps
CPU time 0.76 seconds
Started Jul 29 07:34:06 PM PDT 24
Finished Jul 29 07:34:07 PM PDT 24
Peak memory 200284 kb
Host smart-eaf0adb5-41c9-4e76-ab26-3d3e34ea6ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713567835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.713567835
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3244766739
Short name T280
Test name
Test status
Simulation time 70546329 ps
CPU time 0.98 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201088 kb
Host smart-2faab277-192e-47e3-acd6-bf84145c8a10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244766739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.3244766739
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.1961652197
Short name T368
Test name
Test status
Simulation time 88082486 ps
CPU time 1.09 seconds
Started Jul 29 07:34:04 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 200992 kb
Host smart-c9cd9dcd-d84b-45a9-8f40-6be21a14b0b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961652197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1961652197
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3974054836
Short name T301
Test name
Test status
Simulation time 2121558315 ps
CPU time 16.28 seconds
Started Jul 29 07:34:07 PM PDT 24
Finished Jul 29 07:34:24 PM PDT 24
Peak memory 201344 kb
Host smart-2bd36d09-84f7-46f0-b283-fc9414f88f89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974054836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3974054836
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.1906652656
Short name T350
Test name
Test status
Simulation time 981443115 ps
CPU time 7.29 seconds
Started Jul 29 07:34:06 PM PDT 24
Finished Jul 29 07:34:13 PM PDT 24
Peak memory 201168 kb
Host smart-39e1003a-62b2-4b23-aebe-9e8212f20231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906652656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.1906652656
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2250812948
Short name T729
Test name
Test status
Simulation time 22902046 ps
CPU time 0.84 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201152 kb
Host smart-f22ee39b-539a-4673-a599-6ca8156dfcd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250812948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.2250812948
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.2714250860
Short name T96
Test name
Test status
Simulation time 20319122 ps
CPU time 0.71 seconds
Started Jul 29 07:33:57 PM PDT 24
Finished Jul 29 07:33:58 PM PDT 24
Peak memory 201072 kb
Host smart-1ea1fe87-42a9-41c9-be20-3274ecab8c92
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714250860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.2714250860
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2236757698
Short name T305
Test name
Test status
Simulation time 21647392 ps
CPU time 0.82 seconds
Started Jul 29 07:33:48 PM PDT 24
Finished Jul 29 07:33:49 PM PDT 24
Peak memory 201144 kb
Host smart-c762dba7-12fb-4be7-b390-fbf3c6dc1971
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236757698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.2236757698
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.4273030515
Short name T622
Test name
Test status
Simulation time 37850863 ps
CPU time 0.8 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201076 kb
Host smart-d723c69d-99a5-4482-a237-55bd7af7ae78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273030515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.4273030515
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.3967604902
Short name T689
Test name
Test status
Simulation time 1304988270 ps
CPU time 5.43 seconds
Started Jul 29 07:33:51 PM PDT 24
Finished Jul 29 07:33:57 PM PDT 24
Peak memory 201292 kb
Host smart-4fcec7df-d16b-497b-b95a-4ee4694425c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967604902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3967604902
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.3554889439
Short name T436
Test name
Test status
Simulation time 65002254 ps
CPU time 0.98 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:03 PM PDT 24
Peak memory 200960 kb
Host smart-5fd4379c-57fc-4106-88fb-9ba42da3b6be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554889439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3554889439
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.3868081265
Short name T471
Test name
Test status
Simulation time 6599382188 ps
CPU time 36.27 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:34:30 PM PDT 24
Peak memory 201520 kb
Host smart-22f5fe64-03c7-4a48-bfe2-6c360a0c39e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868081265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.3868081265
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.3106772841
Short name T124
Test name
Test status
Simulation time 13122412 ps
CPU time 0.71 seconds
Started Jul 29 07:33:49 PM PDT 24
Finished Jul 29 07:33:50 PM PDT 24
Peak memory 201148 kb
Host smart-73d5cdc5-e5c3-4ca6-bf40-3603a1d9454a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106772841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.3106772841
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.2554408589
Short name T6
Test name
Test status
Simulation time 33357143 ps
CPU time 0.77 seconds
Started Jul 29 07:34:08 PM PDT 24
Finished Jul 29 07:34:09 PM PDT 24
Peak memory 201108 kb
Host smart-8e1dfdd2-fb2a-4344-a970-af7790e95511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554408589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.2554408589
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.4141030887
Short name T733
Test name
Test status
Simulation time 17642430 ps
CPU time 0.79 seconds
Started Jul 29 07:33:57 PM PDT 24
Finished Jul 29 07:33:58 PM PDT 24
Peak memory 201044 kb
Host smart-1d6f537f-0736-4d96-8468-e299599dcdae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141030887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.4141030887
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.1969138744
Short name T163
Test name
Test status
Simulation time 17820944 ps
CPU time 0.69 seconds
Started Jul 29 07:33:58 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 200272 kb
Host smart-a9cadae8-af17-4201-ace4-8dd71b24834c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969138744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.1969138744
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.4211690932
Short name T420
Test name
Test status
Simulation time 65986977 ps
CPU time 0.95 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201012 kb
Host smart-72c270cd-47f9-4ed1-b439-812e808f53ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211690932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.4211690932
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.1313702234
Short name T386
Test name
Test status
Simulation time 21638408 ps
CPU time 0.72 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 200936 kb
Host smart-c9181d79-2365-4970-bad9-b06dbbf36850
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313702234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1313702234
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.3523818499
Short name T531
Test name
Test status
Simulation time 2238012916 ps
CPU time 17.79 seconds
Started Jul 29 07:34:08 PM PDT 24
Finished Jul 29 07:34:26 PM PDT 24
Peak memory 201464 kb
Host smart-04fecf4f-42e3-4615-852f-4735c737c2a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523818499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3523818499
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3088842015
Short name T684
Test name
Test status
Simulation time 1221510051 ps
CPU time 6.88 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:08 PM PDT 24
Peak memory 201208 kb
Host smart-7126b897-dc01-49e8-b89d-8ca92b0fbb5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088842015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3088842015
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.2896402722
Short name T216
Test name
Test status
Simulation time 455283831 ps
CPU time 2.25 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:57 PM PDT 24
Peak memory 201088 kb
Host smart-f5d750a2-24e0-4852-99bd-298645f1ebfd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896402722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.2896402722
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.4116119461
Short name T237
Test name
Test status
Simulation time 39976365 ps
CPU time 0.91 seconds
Started Jul 29 07:34:09 PM PDT 24
Finished Jul 29 07:34:11 PM PDT 24
Peak memory 201076 kb
Host smart-12146a82-b17e-4d33-85a3-a767613fe9eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116119461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.4116119461
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3854331068
Short name T219
Test name
Test status
Simulation time 29367549 ps
CPU time 0.8 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201292 kb
Host smart-37be9c7b-2093-4ccd-a879-218d3457be83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854331068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.3854331068
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2373930647
Short name T498
Test name
Test status
Simulation time 20359212 ps
CPU time 0.74 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201020 kb
Host smart-04e7d25c-cc53-4e65-8e98-0346d92fde38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373930647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2373930647
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.1980508048
Short name T10
Test name
Test status
Simulation time 1136260491 ps
CPU time 5.92 seconds
Started Jul 29 07:34:11 PM PDT 24
Finished Jul 29 07:34:17 PM PDT 24
Peak memory 201260 kb
Host smart-694a44af-236f-4c12-b4df-80c004a38430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980508048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1980508048
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2911333995
Short name T247
Test name
Test status
Simulation time 18815623 ps
CPU time 0.82 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201144 kb
Host smart-7a50bc73-9cf5-49b6-928d-84f01379d725
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911333995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2911333995
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1355892130
Short name T700
Test name
Test status
Simulation time 122820064 ps
CPU time 1.45 seconds
Started Jul 29 07:33:55 PM PDT 24
Finished Jul 29 07:33:56 PM PDT 24
Peak memory 201056 kb
Host smart-2749f7a1-617a-4670-8a3f-04eee8c40f73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355892130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1355892130
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.2672996973
Short name T777
Test name
Test status
Simulation time 24081391377 ps
CPU time 380.4 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:40:14 PM PDT 24
Peak memory 209780 kb
Host smart-5be6f058-8574-433b-86e9-c44fbce7d7a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2672996973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.2672996973
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.3988025611
Short name T366
Test name
Test status
Simulation time 27519502 ps
CPU time 0.95 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201080 kb
Host smart-ac9da45c-fbec-494b-823e-880946b98460
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988025611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3988025611
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1247773739
Short name T286
Test name
Test status
Simulation time 103760350 ps
CPU time 1 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201076 kb
Host smart-df95dc59-da2e-4501-a36e-c1350b46f8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247773739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1247773739
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.4073008491
Short name T380
Test name
Test status
Simulation time 24004444 ps
CPU time 0.76 seconds
Started Jul 29 07:33:52 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 201116 kb
Host smart-e4cc4707-cc09-4681-b72b-2c49ae38f117
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073008491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.4073008491
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.3130428015
Short name T425
Test name
Test status
Simulation time 83781833 ps
CPU time 0.92 seconds
Started Jul 29 07:34:09 PM PDT 24
Finished Jul 29 07:34:10 PM PDT 24
Peak memory 200260 kb
Host smart-c0420d32-4021-436b-ab4b-12b4da9dd078
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130428015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.3130428015
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.1147401028
Short name T590
Test name
Test status
Simulation time 82369363 ps
CPU time 1.02 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201088 kb
Host smart-20f62f8a-47aa-413f-bb61-c97d3bb2c207
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147401028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.1147401028
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.3280295076
Short name T648
Test name
Test status
Simulation time 82893099 ps
CPU time 1.07 seconds
Started Jul 29 07:33:51 PM PDT 24
Finished Jul 29 07:33:53 PM PDT 24
Peak memory 200948 kb
Host smart-9cc9a6a8-6cc0-4210-9c84-7b13853831f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280295076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3280295076
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.322105501
Short name T296
Test name
Test status
Simulation time 2100354403 ps
CPU time 9.23 seconds
Started Jul 29 07:33:56 PM PDT 24
Finished Jul 29 07:34:05 PM PDT 24
Peak memory 201332 kb
Host smart-c30e891f-4054-44c2-8c4e-42060d7e01d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322105501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.322105501
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.69093651
Short name T332
Test name
Test status
Simulation time 262727455 ps
CPU time 1.55 seconds
Started Jul 29 07:34:12 PM PDT 24
Finished Jul 29 07:34:14 PM PDT 24
Peak memory 201088 kb
Host smart-60252c71-55ce-464d-9743-52c0fc1150aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69093651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_tim
eout.69093651
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3289993678
Short name T480
Test name
Test status
Simulation time 34451854 ps
CPU time 0.84 seconds
Started Jul 29 07:33:58 PM PDT 24
Finished Jul 29 07:33:59 PM PDT 24
Peak memory 201084 kb
Host smart-fc9c9412-1e93-4542-84aa-dc001e3450c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289993678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.3289993678
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1713664004
Short name T459
Test name
Test status
Simulation time 252736449 ps
CPU time 1.55 seconds
Started Jul 29 07:34:11 PM PDT 24
Finished Jul 29 07:34:12 PM PDT 24
Peak memory 201032 kb
Host smart-bcac9b62-cca0-47be-af21-d2fc76d9dabf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713664004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1713664004
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2898077912
Short name T564
Test name
Test status
Simulation time 31564280 ps
CPU time 0.8 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:33:54 PM PDT 24
Peak memory 201028 kb
Host smart-c6509236-9365-4a91-9b5d-ee868a876eec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898077912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.2898077912
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.3734056319
Short name T212
Test name
Test status
Simulation time 11951038 ps
CPU time 0.67 seconds
Started Jul 29 07:33:51 PM PDT 24
Finished Jul 29 07:33:51 PM PDT 24
Peak memory 201088 kb
Host smart-48216f61-a430-4a23-98cd-9cd33ec9ec94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734056319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3734056319
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.295519743
Short name T795
Test name
Test status
Simulation time 820292380 ps
CPU time 3.21 seconds
Started Jul 29 07:34:08 PM PDT 24
Finished Jul 29 07:34:11 PM PDT 24
Peak memory 201256 kb
Host smart-e5f7f890-7fde-47c8-b718-d177db89f765
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295519743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.295519743
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.4205590943
Short name T202
Test name
Test status
Simulation time 39070752 ps
CPU time 0.87 seconds
Started Jul 29 07:34:17 PM PDT 24
Finished Jul 29 07:34:18 PM PDT 24
Peak memory 201088 kb
Host smart-3cae0abb-ba1d-4348-ac1d-ae66fcfb11c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205590943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.4205590943
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3240223868
Short name T42
Test name
Test status
Simulation time 8990650213 ps
CPU time 64.82 seconds
Started Jul 29 07:33:53 PM PDT 24
Finished Jul 29 07:34:58 PM PDT 24
Peak memory 201532 kb
Host smart-63fa4b8b-a533-4443-a67a-e5c53b9887a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240223868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3240223868
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.642536366
Short name T659
Test name
Test status
Simulation time 35684819 ps
CPU time 0.89 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201072 kb
Host smart-d3235a9b-c54f-4423-953b-c67ea4ffde4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642536366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.642536366
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3797065788
Short name T693
Test name
Test status
Simulation time 58919066 ps
CPU time 0.91 seconds
Started Jul 29 07:34:29 PM PDT 24
Finished Jul 29 07:34:30 PM PDT 24
Peak memory 201112 kb
Host smart-058a0742-8972-4333-9b15-5b37fa54d4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797065788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3797065788
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.285233433
Short name T572
Test name
Test status
Simulation time 75769710 ps
CPU time 1.09 seconds
Started Jul 29 07:34:31 PM PDT 24
Finished Jul 29 07:34:32 PM PDT 24
Peak memory 201024 kb
Host smart-0745772e-240e-4ea2-8cd9-fa92f0609e7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285233433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.285233433
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.2869172917
Short name T769
Test name
Test status
Simulation time 25908989 ps
CPU time 0.72 seconds
Started Jul 29 07:34:23 PM PDT 24
Finished Jul 29 07:34:24 PM PDT 24
Peak memory 200348 kb
Host smart-50ed45d4-ca1d-495b-9799-8c200ebab7b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869172917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.2869172917
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.366493892
Short name T321
Test name
Test status
Simulation time 51459522 ps
CPU time 0.86 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:29 PM PDT 24
Peak memory 201000 kb
Host smart-f7ebeaf7-50cd-4c98-a3ef-e1fbf354ddc6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366493892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_div_intersig_mubi.366493892
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.349271835
Short name T409
Test name
Test status
Simulation time 49830034 ps
CPU time 0.82 seconds
Started Jul 29 07:34:02 PM PDT 24
Finished Jul 29 07:34:03 PM PDT 24
Peak memory 201088 kb
Host smart-a3f2041d-de71-4af5-8d21-0ca3c8e92ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349271835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.349271835
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3986099838
Short name T753
Test name
Test status
Simulation time 685414434 ps
CPU time 4.3 seconds
Started Jul 29 07:33:57 PM PDT 24
Finished Jul 29 07:34:02 PM PDT 24
Peak memory 201092 kb
Host smart-2c5f7b48-df15-47a9-b424-cf8e67526fd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986099838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3986099838
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.1722172151
Short name T723
Test name
Test status
Simulation time 1097034554 ps
CPU time 8.55 seconds
Started Jul 29 07:34:09 PM PDT 24
Finished Jul 29 07:34:18 PM PDT 24
Peak memory 201196 kb
Host smart-af3c8571-9844-4156-99ed-8505ef90ba80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722172151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.1722172151
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2308104378
Short name T609
Test name
Test status
Simulation time 28603828 ps
CPU time 0.81 seconds
Started Jul 29 07:34:24 PM PDT 24
Finished Jul 29 07:34:25 PM PDT 24
Peak memory 201016 kb
Host smart-72bda91f-9230-4557-a81f-e8e46c599eb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308104378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2308104378
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1580443192
Short name T50
Test name
Test status
Simulation time 21663584 ps
CPU time 0.74 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201056 kb
Host smart-ed80b27c-6e1a-45e2-9e2d-584247c5c1de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580443192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1580443192
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2290359283
Short name T327
Test name
Test status
Simulation time 13405465 ps
CPU time 0.77 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:34:28 PM PDT 24
Peak memory 201076 kb
Host smart-b0e9d8e2-eacf-4070-9e84-8784d4e76ec2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290359283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.2290359283
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.247294096
Short name T752
Test name
Test status
Simulation time 16766353 ps
CPU time 0.78 seconds
Started Jul 29 07:33:54 PM PDT 24
Finished Jul 29 07:33:55 PM PDT 24
Peak memory 201020 kb
Host smart-4f9bc4ad-9a78-49c5-b7c2-40e75df222e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247294096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.247294096
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2469911230
Short name T592
Test name
Test status
Simulation time 493429229 ps
CPU time 3.06 seconds
Started Jul 29 07:34:31 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 201184 kb
Host smart-2c66a1ef-702d-4267-a820-aa26123bdeb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469911230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2469911230
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2153363731
Short name T569
Test name
Test status
Simulation time 50599175 ps
CPU time 0.9 seconds
Started Jul 29 07:34:01 PM PDT 24
Finished Jul 29 07:34:02 PM PDT 24
Peak memory 201092 kb
Host smart-5e11c2b7-e2bd-440e-b21c-f41d525a5afb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153363731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2153363731
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3740690230
Short name T744
Test name
Test status
Simulation time 9756925769 ps
CPU time 65.24 seconds
Started Jul 29 07:34:24 PM PDT 24
Finished Jul 29 07:35:30 PM PDT 24
Peak memory 201452 kb
Host smart-e62c9af8-ada8-4e8a-bda5-520aec9c3755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740690230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3740690230
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.2466764514
Short name T353
Test name
Test status
Simulation time 16489471 ps
CPU time 0.74 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:34:28 PM PDT 24
Peak memory 201100 kb
Host smart-0e4ff1c4-7ba8-4293-aa71-7687d10d5ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466764514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2466764514
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.345402300
Short name T637
Test name
Test status
Simulation time 17181346 ps
CPU time 0.77 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:29 PM PDT 24
Peak memory 200980 kb
Host smart-6080cd81-10c2-4844-819a-8b7e640fbee0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345402300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.345402300
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.4153188470
Short name T434
Test name
Test status
Simulation time 32625529 ps
CPU time 0.86 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201056 kb
Host smart-c3441d9a-f644-41eb-8729-4809f0363e75
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153188470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.4153188470
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1548142827
Short name T358
Test name
Test status
Simulation time 13903881 ps
CPU time 0.77 seconds
Started Jul 29 07:34:29 PM PDT 24
Finished Jul 29 07:34:30 PM PDT 24
Peak memory 200248 kb
Host smart-1ab90740-f085-4484-854b-6e8b7d781f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548142827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1548142827
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.3752182710
Short name T378
Test name
Test status
Simulation time 17469975 ps
CPU time 0.78 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201088 kb
Host smart-2157e849-21cb-4ac8-844d-9b0f0c18b754
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752182710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.3752182710
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.2136129445
Short name T311
Test name
Test status
Simulation time 23396197 ps
CPU time 0.93 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201032 kb
Host smart-3d654509-eec1-4d58-8d5d-d1a0b97a8d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136129445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2136129445
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.3747638694
Short name T619
Test name
Test status
Simulation time 1169181847 ps
CPU time 5.62 seconds
Started Jul 29 07:34:29 PM PDT 24
Finished Jul 29 07:34:35 PM PDT 24
Peak memory 201148 kb
Host smart-7c5a37c8-bfdb-4d0b-a0b3-613caf6e32f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747638694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3747638694
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.467124900
Short name T310
Test name
Test status
Simulation time 2422699896 ps
CPU time 12.34 seconds
Started Jul 29 07:34:29 PM PDT 24
Finished Jul 29 07:34:41 PM PDT 24
Peak memory 201392 kb
Host smart-aaf3aa25-77d1-4112-a052-33d67babff78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467124900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_ti
meout.467124900
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1691558488
Short name T200
Test name
Test status
Simulation time 25146941 ps
CPU time 0.93 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:32 PM PDT 24
Peak memory 201076 kb
Host smart-1930d2e2-72cf-4e12-80f0-4fa4d1ccd0af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691558488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1691558488
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.154264480
Short name T593
Test name
Test status
Simulation time 13764060 ps
CPU time 0.81 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201088 kb
Host smart-c321c482-b6ce-4729-b565-27f3f16ac429
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154264480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_clk_byp_req_intersig_mubi.154264480
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3111752775
Short name T185
Test name
Test status
Simulation time 19548733 ps
CPU time 0.8 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 200868 kb
Host smart-a86673a9-8273-451f-a1dc-097071372464
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111752775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3111752775
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.2292507
Short name T396
Test name
Test status
Simulation time 51338162 ps
CPU time 0.79 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201072 kb
Host smart-1d33b6ff-0df3-45c3-a259-86ea8b6065a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2292507
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.3838024853
Short name T182
Test name
Test status
Simulation time 660417668 ps
CPU time 3.77 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:30 PM PDT 24
Peak memory 201296 kb
Host smart-bc342401-f58e-418c-816d-4c4598baa904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838024853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.3838024853
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.2538896870
Short name T47
Test name
Test status
Simulation time 41674051 ps
CPU time 0.87 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:32 PM PDT 24
Peak memory 201016 kb
Host smart-3371a391-25f4-48ab-834e-dac9a5fdc9f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538896870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2538896870
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.2499809018
Short name T391
Test name
Test status
Simulation time 11050234475 ps
CPU time 58.57 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:35:26 PM PDT 24
Peak memory 201468 kb
Host smart-a9f52969-ccb9-4cde-91f4-738208ded6db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499809018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.2499809018
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.4137413197
Short name T51
Test name
Test status
Simulation time 92370200 ps
CPU time 0.99 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:26 PM PDT 24
Peak memory 201092 kb
Host smart-6d55a782-7805-49dd-a5fc-ad706a6d3cc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137413197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.4137413197
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2636429287
Short name T392
Test name
Test status
Simulation time 27315014 ps
CPU time 0.83 seconds
Started Jul 29 07:34:30 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201100 kb
Host smart-fa419fd3-8694-461a-8367-b4a185b7206b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636429287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2636429287
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2524387735
Short name T740
Test name
Test status
Simulation time 84917291 ps
CPU time 1.02 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201096 kb
Host smart-bb17de25-4371-4421-bf47-ba4abfcb5421
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524387735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2524387735
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.4287464978
Short name T37
Test name
Test status
Simulation time 15369801 ps
CPU time 0.71 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 200292 kb
Host smart-6b0054d7-4cdf-48b9-996b-6437ac7ea23a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287464978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.4287464978
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1464280488
Short name T507
Test name
Test status
Simulation time 47452433 ps
CPU time 0.87 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201084 kb
Host smart-537e68ab-d006-4d67-ae9e-f0f723e769eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464280488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.1464280488
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3529166056
Short name T349
Test name
Test status
Simulation time 85073699 ps
CPU time 0.94 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:34:28 PM PDT 24
Peak memory 201080 kb
Host smart-f00207a7-b0d1-4393-8a07-1ad7ab44d489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529166056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3529166056
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.3223153477
Short name T215
Test name
Test status
Simulation time 1292248885 ps
CPU time 7.32 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 201172 kb
Host smart-0a2db1f5-0933-4fcc-b7f1-ef060dbaf8e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223153477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3223153477
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.3266293854
Short name T773
Test name
Test status
Simulation time 1238574117 ps
CPU time 5.41 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201144 kb
Host smart-4a1cb42e-3b0b-4a98-a664-1640ee9398c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266293854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.3266293854
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3476809227
Short name T562
Test name
Test status
Simulation time 42770061 ps
CPU time 0.8 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201056 kb
Host smart-2ad00e06-12b3-4123-befc-f2f1dc820d18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476809227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3476809227
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2673149168
Short name T27
Test name
Test status
Simulation time 26726218 ps
CPU time 1.03 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:35 PM PDT 24
Peak memory 200864 kb
Host smart-09437296-0eeb-49e1-9b4f-d81535917e86
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673149168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2673149168
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.986747002
Short name T585
Test name
Test status
Simulation time 77322667 ps
CPU time 0.98 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:26 PM PDT 24
Peak memory 201032 kb
Host smart-a0a90993-6362-4fb7-9a25-ba33feb30d38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986747002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_ctrl_intersig_mubi.986747002
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.3144401704
Short name T541
Test name
Test status
Simulation time 16066644 ps
CPU time 0.78 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:26 PM PDT 24
Peak memory 201140 kb
Host smart-d864fc0d-8708-4166-81cf-44ad77652af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144401704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.3144401704
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2761392408
Short name T363
Test name
Test status
Simulation time 153477822 ps
CPU time 1.3 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:30 PM PDT 24
Peak memory 201076 kb
Host smart-2fdda356-5e2a-4a8d-9574-b16ed139590d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761392408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2761392408
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.569062527
Short name T488
Test name
Test status
Simulation time 53997259 ps
CPU time 1 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:35 PM PDT 24
Peak memory 200880 kb
Host smart-c533bdc0-b66e-4676-a4c6-aef8c4f72e5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569062527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.569062527
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2153808776
Short name T588
Test name
Test status
Simulation time 5848454972 ps
CPU time 43.29 seconds
Started Jul 29 07:34:29 PM PDT 24
Finished Jul 29 07:35:12 PM PDT 24
Peak memory 201428 kb
Host smart-321d0549-eb13-4262-bb82-a42a3a44526b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153808776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2153808776
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.1012119244
Short name T718
Test name
Test status
Simulation time 107617946654 ps
CPU time 584.89 seconds
Started Jul 29 07:34:27 PM PDT 24
Finished Jul 29 07:44:12 PM PDT 24
Peak memory 217940 kb
Host smart-176d6dae-9490-4d23-a3c2-520a7a82a0bd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1012119244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.1012119244
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2450194439
Short name T211
Test name
Test status
Simulation time 23750668 ps
CPU time 0.87 seconds
Started Jul 29 07:34:24 PM PDT 24
Finished Jul 29 07:34:25 PM PDT 24
Peak memory 201144 kb
Host smart-18bbac91-5485-4a2f-a486-7597bcb7081a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450194439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2450194439
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.1678196706
Short name T193
Test name
Test status
Simulation time 57523561 ps
CPU time 0.9 seconds
Started Jul 29 07:34:34 PM PDT 24
Finished Jul 29 07:34:35 PM PDT 24
Peak memory 201268 kb
Host smart-334d28a4-1c78-4c9e-80a8-898a9fe17171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678196706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.1678196706
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2971685239
Short name T102
Test name
Test status
Simulation time 52236191 ps
CPU time 0.83 seconds
Started Jul 29 07:34:37 PM PDT 24
Finished Jul 29 07:34:38 PM PDT 24
Peak memory 201060 kb
Host smart-8092378f-e5f2-4022-abf6-911c090c1b6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971685239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2971685239
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.2805199491
Short name T730
Test name
Test status
Simulation time 114262507 ps
CPU time 1 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:29 PM PDT 24
Peak memory 200292 kb
Host smart-717cbd98-fa25-4b92-abb1-23f827a0acd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805199491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2805199491
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.918434275
Short name T540
Test name
Test status
Simulation time 33910241 ps
CPU time 0.88 seconds
Started Jul 29 07:34:34 PM PDT 24
Finished Jul 29 07:34:36 PM PDT 24
Peak memory 201112 kb
Host smart-f4cf8052-7233-444a-9716-349d6d715390
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918434275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.918434275
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.2771226313
Short name T532
Test name
Test status
Simulation time 21150206 ps
CPU time 0.84 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201032 kb
Host smart-45678c8d-2216-4945-a5ee-e9918d9171ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771226313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2771226313
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.169665785
Short name T388
Test name
Test status
Simulation time 321727800 ps
CPU time 3.02 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201040 kb
Host smart-3c10f8da-6ecb-4dc8-b220-a4c11e49d704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169665785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.169665785
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.4188639492
Short name T270
Test name
Test status
Simulation time 1220530314 ps
CPU time 6.68 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:31 PM PDT 24
Peak memory 201212 kb
Host smart-5bc7fff9-914a-4049-8a35-f6a83aebb48b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188639492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.4188639492
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1453967844
Short name T269
Test name
Test status
Simulation time 37316951 ps
CPU time 1.03 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 201276 kb
Host smart-71837298-379a-4535-b707-a0f5f7769c1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453967844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.1453967844
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1302170620
Short name T644
Test name
Test status
Simulation time 63101520 ps
CPU time 0.95 seconds
Started Jul 29 07:34:40 PM PDT 24
Finished Jul 29 07:34:41 PM PDT 24
Peak memory 201000 kb
Host smart-03f25906-54c0-4411-a854-3b517e563b9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302170620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1302170620
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1015635214
Short name T774
Test name
Test status
Simulation time 48783626 ps
CPU time 0.94 seconds
Started Jul 29 07:34:39 PM PDT 24
Finished Jul 29 07:34:40 PM PDT 24
Peak memory 201084 kb
Host smart-25bf4b32-54e9-4bdb-829e-97c65612e463
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015635214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.1015635214
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.1777080855
Short name T291
Test name
Test status
Simulation time 39585464 ps
CPU time 0.88 seconds
Started Jul 29 07:34:25 PM PDT 24
Finished Jul 29 07:34:26 PM PDT 24
Peak memory 201100 kb
Host smart-a4917183-aeff-40a3-bda8-b9fa337aa2f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777080855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1777080855
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2431663209
Short name T438
Test name
Test status
Simulation time 861474564 ps
CPU time 3.41 seconds
Started Jul 29 07:34:36 PM PDT 24
Finished Jul 29 07:34:40 PM PDT 24
Peak memory 201264 kb
Host smart-3b306302-ac4f-4eaa-8cc4-bd0ed14b5498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431663209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2431663209
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.4169314527
Short name T475
Test name
Test status
Simulation time 59258273 ps
CPU time 0.98 seconds
Started Jul 29 07:34:26 PM PDT 24
Finished Jul 29 07:34:27 PM PDT 24
Peak memory 201072 kb
Host smart-193a4499-61e5-49ef-b082-ef5951ff644f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169314527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.4169314527
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.2926633208
Short name T77
Test name
Test status
Simulation time 4869859550 ps
CPU time 21.15 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:55 PM PDT 24
Peak memory 201448 kb
Host smart-64fda4fc-0c06-4ff3-a7dc-3cda8492411d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926633208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.2926633208
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3271290759
Short name T265
Test name
Test status
Simulation time 27006195 ps
CPU time 0.99 seconds
Started Jul 29 07:34:28 PM PDT 24
Finished Jul 29 07:34:29 PM PDT 24
Peak memory 201044 kb
Host smart-95ea0f09-7967-4d93-bdca-eab2e3ceac23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271290759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3271290759
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.587192438
Short name T330
Test name
Test status
Simulation time 52728125 ps
CPU time 0.88 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 200800 kb
Host smart-729815df-0b47-4905-a931-fd6dc3460e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587192438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkm
gr_alert_test.587192438
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2576064387
Short name T94
Test name
Test status
Simulation time 80265546 ps
CPU time 1.1 seconds
Started Jul 29 07:34:32 PM PDT 24
Finished Jul 29 07:34:33 PM PDT 24
Peak memory 201076 kb
Host smart-929fb99c-a849-47b0-bc80-494d2c80f532
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576064387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.2576064387
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.2731689081
Short name T479
Test name
Test status
Simulation time 27286062 ps
CPU time 0.76 seconds
Started Jul 29 07:34:35 PM PDT 24
Finished Jul 29 07:34:36 PM PDT 24
Peak memory 200316 kb
Host smart-84a99307-d9e7-4812-94b3-8c873ee04157
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731689081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2731689081
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.672840834
Short name T568
Test name
Test status
Simulation time 52872094 ps
CPU time 0.96 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 201092 kb
Host smart-8c7eb3b2-39f5-426d-ac2b-9951e14bfcb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672840834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_div_intersig_mubi.672840834
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3959275813
Short name T669
Test name
Test status
Simulation time 22901729 ps
CPU time 0.85 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:34 PM PDT 24
Peak memory 201124 kb
Host smart-2ab6368c-7945-4845-a7d7-4753d0dcca94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959275813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3959275813
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.1981624733
Short name T717
Test name
Test status
Simulation time 1485524417 ps
CPU time 6.54 seconds
Started Jul 29 07:34:33 PM PDT 24
Finished Jul 29 07:34:40 PM PDT 24
Peak memory 200920 kb
Host smart-d0533e91-fe02-4f4d-9c93-87caacf77dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981624733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.1981624733
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.3909080958
Short name T199
Test name
Test status
Simulation time 2212811113 ps
CPU time 7.2 seconds
Started Jul 29 07:34:32 PM PDT 24
Finished Jul 29 07:34:39 PM PDT 24
Peak memory 201256 kb
Host smart-b9be3a6d-c1c4-4faf-acb9-a3b6faef8ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909080958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.3909080958
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.316719514
Short name T817
Test name
Test status
Simulation time 20976990 ps
CPU time 0.85 seconds
Started Jul 29 07:34:35 PM PDT 24
Finished Jul 29 07:34:36 PM PDT 24
Peak memory 200996 kb
Host smart-090de81c-167b-4832-b727-ebeed3f48a5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316719514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_idle_intersig_mubi.316719514
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2201166226
Short name T315
Test name
Test status
Simulation time 18976083 ps
CPU time 0.85 seconds
Started Jul 29 07:34:40 PM PDT 24
Finished Jul 29 07:34:41 PM PDT 24
Peak memory 201000 kb
Host smart-ac7f33c0-ce83-4008-8ead-8da633033f29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201166226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2201166226
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.983007262
Short name T715
Test name
Test status
Simulation time 18816738 ps
CPU time 0.82 seconds
Started Jul 29 07:34:39 PM PDT 24
Finished Jul 29 07:34:40 PM PDT 24
Peak memory 201076 kb
Host smart-e27cd03f-8952-45b3-9c8d-0d2309ec1f5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983007262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_ctrl_intersig_mubi.983007262
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1883204518
Short name T170
Test name
Test status
Simulation time 41417098 ps
CPU time 0.8 seconds
Started Jul 29 07:34:34 PM PDT 24
Finished Jul 29 07:34:35 PM PDT 24
Peak memory 200964 kb
Host smart-612ae2e2-b9f3-4c96-8ab0-90270dbf3a68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883204518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1883204518
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.4127589305
Short name T698
Test name
Test status
Simulation time 1360320453 ps
CPU time 4.43 seconds
Started Jul 29 07:34:40 PM PDT 24
Finished Jul 29 07:34:45 PM PDT 24
Peak memory 201192 kb
Host smart-996d9309-872f-4a15-9bd9-9b308fac6d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127589305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4127589305
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.3725510461
Short name T127
Test name
Test status
Simulation time 157120977 ps
CPU time 1.17 seconds
Started Jul 29 07:34:34 PM PDT 24
Finished Jul 29 07:34:36 PM PDT 24
Peak memory 201056 kb
Host smart-3dca8617-b209-4531-aec6-7ec440014656
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725510461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3725510461
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1239740002
Short name T303
Test name
Test status
Simulation time 4680421998 ps
CPU time 36.62 seconds
Started Jul 29 07:34:36 PM PDT 24
Finished Jul 29 07:35:13 PM PDT 24
Peak memory 201404 kb
Host smart-c2060fe8-cbad-47b8-8aea-105aeddc38d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239740002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1239740002
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1181329547
Short name T663
Test name
Test status
Simulation time 41740721 ps
CPU time 0.88 seconds
Started Jul 29 07:34:36 PM PDT 24
Finished Jul 29 07:34:37 PM PDT 24
Peak memory 200992 kb
Host smart-0404ccc5-41c1-49a5-9678-881ad5f2c2d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181329547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1181329547
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2197570041
Short name T790
Test name
Test status
Simulation time 18733328 ps
CPU time 0.8 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 200996 kb
Host smart-6f2cc311-82e2-4364-8fb4-ac273b61a5cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197570041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2197570041
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1557568219
Short name T460
Test name
Test status
Simulation time 66549109 ps
CPU time 0.99 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 201104 kb
Host smart-c9bf7812-2d7d-448d-9e68-0828c8ee26fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557568219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.1557568219
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.4158783647
Short name T611
Test name
Test status
Simulation time 41914219 ps
CPU time 0.77 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 200292 kb
Host smart-ebbe17bf-80eb-41db-bdcd-79d57f75432a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158783647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.4158783647
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2793643390
Short name T666
Test name
Test status
Simulation time 27266493 ps
CPU time 0.89 seconds
Started Jul 29 07:32:27 PM PDT 24
Finished Jul 29 07:32:28 PM PDT 24
Peak memory 201108 kb
Host smart-90f36fd3-7157-4e7f-af53-22f6cf7b3db7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793643390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2793643390
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.1395771891
Short name T256
Test name
Test status
Simulation time 49921124 ps
CPU time 0.91 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201052 kb
Host smart-a38ae672-4cfc-4392-af80-4818154ed1d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395771891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1395771891
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.394596328
Short name T704
Test name
Test status
Simulation time 2135751049 ps
CPU time 9.94 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201324 kb
Host smart-d21cf45b-2274-48a9-9ebb-f98607552f0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394596328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.394596328
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.512481568
Short name T804
Test name
Test status
Simulation time 264412456 ps
CPU time 1.9 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 201148 kb
Host smart-ab5eabbc-e261-43a3-a584-2075c325bd66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512481568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim
eout.512481568
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.1280634394
Short name T302
Test name
Test status
Simulation time 82773872 ps
CPU time 1.09 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 201236 kb
Host smart-8f9758ae-9ae7-4a3c-8bc8-7df2585ab5a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280634394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.1280634394
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2502860940
Short name T188
Test name
Test status
Simulation time 204079788 ps
CPU time 1.36 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201132 kb
Host smart-0f1a5dff-f1ae-4368-becb-6e3ff16c80fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502860940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2502860940
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.345665924
Short name T604
Test name
Test status
Simulation time 51796021 ps
CPU time 1 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201000 kb
Host smart-71632540-8d93-4d1e-8c6f-4124607d0c64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345665924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_ctrl_intersig_mubi.345665924
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.374695942
Short name T598
Test name
Test status
Simulation time 30915005 ps
CPU time 0.83 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201016 kb
Host smart-e854cf53-4cf2-43e1-8979-ebc0422ba8cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374695942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.374695942
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.3811294821
Short name T369
Test name
Test status
Simulation time 1072016903 ps
CPU time 5.21 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:34 PM PDT 24
Peak memory 201220 kb
Host smart-31e24f87-65e1-47c6-a778-4df00a537402
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811294821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3811294821
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2582185312
Short name T245
Test name
Test status
Simulation time 59750937 ps
CPU time 0.92 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201104 kb
Host smart-6e736186-978e-4223-ac65-90688ef6629d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582185312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2582185312
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.2371188722
Short name T713
Test name
Test status
Simulation time 7507117265 ps
CPU time 30.76 seconds
Started Jul 29 07:32:36 PM PDT 24
Finished Jul 29 07:33:07 PM PDT 24
Peak memory 201492 kb
Host smart-2f736667-7e74-4257-b061-6a324cfdc8b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371188722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.2371188722
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3461784865
Short name T71
Test name
Test status
Simulation time 398778840850 ps
CPU time 1670.37 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 08:00:16 PM PDT 24
Peak memory 217936 kb
Host smart-5385b38d-a6c8-4228-9891-9de6ed8d35bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3461784865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3461784865
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.682208091
Short name T517
Test name
Test status
Simulation time 30619932 ps
CPU time 0.77 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:25 PM PDT 24
Peak memory 201072 kb
Host smart-aa1624db-6df6-4d22-80dc-29ce7681df80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682208091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.682208091
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.2450240897
Short name T524
Test name
Test status
Simulation time 27794678 ps
CPU time 0.78 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201040 kb
Host smart-853b895a-7c65-4549-9eb1-ef0968a58acb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450240897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.2450240897
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2204888955
Short name T680
Test name
Test status
Simulation time 275402528 ps
CPU time 1.66 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201048 kb
Host smart-30c43468-4c0f-4344-87c3-05aeaa502fdb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204888955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2204888955
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.239431903
Short name T165
Test name
Test status
Simulation time 20799231 ps
CPU time 0.7 seconds
Started Jul 29 07:32:32 PM PDT 24
Finished Jul 29 07:32:33 PM PDT 24
Peak memory 200312 kb
Host smart-0614bbe5-300a-48df-ae1d-4d0837c4df78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239431903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.239431903
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3594416969
Short name T808
Test name
Test status
Simulation time 20235967 ps
CPU time 0.81 seconds
Started Jul 29 07:32:33 PM PDT 24
Finished Jul 29 07:32:34 PM PDT 24
Peak memory 201228 kb
Host smart-4216b3e7-594a-48aa-94bb-a5cce8585caa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594416969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3594416969
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3781856436
Short name T657
Test name
Test status
Simulation time 25249421 ps
CPU time 0.79 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 200992 kb
Host smart-0a71a57b-e708-435f-9974-d5c1621318f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781856436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3781856436
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.3326070957
Short name T297
Test name
Test status
Simulation time 564666732 ps
CPU time 3.7 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201148 kb
Host smart-0d2781ac-7ff5-48de-8f6a-3c52d8990475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326070957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3326070957
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.3254767795
Short name T250
Test name
Test status
Simulation time 1700524794 ps
CPU time 12.73 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:52 PM PDT 24
Peak memory 201096 kb
Host smart-d9ff45d4-b003-4fc1-b740-18e506c2b9f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254767795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.3254767795
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3717954900
Short name T194
Test name
Test status
Simulation time 20230675 ps
CPU time 0.79 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201124 kb
Host smart-7e9896d8-ae80-40ff-9141-9b44473d7501
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717954900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3717954900
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.262664825
Short name T561
Test name
Test status
Simulation time 72889781 ps
CPU time 0.94 seconds
Started Jul 29 07:32:34 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201092 kb
Host smart-c63d66cc-6411-4fd8-a284-d1062ad4a119
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262664825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_clk_byp_req_intersig_mubi.262664825
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.2036016201
Short name T181
Test name
Test status
Simulation time 226471319 ps
CPU time 1.45 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 201092 kb
Host smart-80b641ca-3151-4028-9319-f4c02f8d7c96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036016201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.2036016201
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.4199047880
Short name T710
Test name
Test status
Simulation time 14738489 ps
CPU time 0.72 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201084 kb
Host smart-dc091df3-f771-4df0-bb5c-9977ab702520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199047880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.4199047880
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.1514753167
Short name T207
Test name
Test status
Simulation time 495650509 ps
CPU time 3.12 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 201000 kb
Host smart-7a28bac5-c26b-440e-8dda-7a6ab858ff98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514753167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1514753167
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.2046082128
Short name T398
Test name
Test status
Simulation time 16225452 ps
CPU time 0.86 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201140 kb
Host smart-59494963-16cf-4c23-b358-f65f4a9627f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046082128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.2046082128
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2864869831
Short name T16
Test name
Test status
Simulation time 7143047971 ps
CPU time 39.19 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:33:18 PM PDT 24
Peak memory 201364 kb
Host smart-33fd5f48-58a4-40e5-92b3-54d503c6ae79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864869831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2864869831
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.794061514
Short name T465
Test name
Test status
Simulation time 601896650 ps
CPU time 2.57 seconds
Started Jul 29 07:32:36 PM PDT 24
Finished Jul 29 07:32:38 PM PDT 24
Peak memory 201140 kb
Host smart-0bc3be38-be46-42c5-9340-3a4821394c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794061514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.794061514
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.1187268788
Short name T394
Test name
Test status
Simulation time 18536728 ps
CPU time 0.78 seconds
Started Jul 29 07:32:44 PM PDT 24
Finished Jul 29 07:32:45 PM PDT 24
Peak memory 201040 kb
Host smart-09563831-3557-4a32-a223-3325fcbe51aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187268788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.1187268788
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3199311200
Short name T103
Test name
Test status
Simulation time 18493972 ps
CPU time 0.78 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 201104 kb
Host smart-84cf33f4-1f39-4ee7-bfe0-ee4674031792
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199311200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.3199311200
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2781375264
Short name T668
Test name
Test status
Simulation time 35222802 ps
CPU time 0.77 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 200288 kb
Host smart-e94a35ff-6253-4173-9a03-1bb1465eb845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781375264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2781375264
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3535772975
Short name T652
Test name
Test status
Simulation time 103235566 ps
CPU time 1.1 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201108 kb
Host smart-f825ee46-1a3a-4396-bf4d-cca73f48be6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535772975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3535772975
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3828349917
Short name T605
Test name
Test status
Simulation time 22626605 ps
CPU time 0.84 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201076 kb
Host smart-df037de9-637b-4054-baf0-ba90a3f50ef1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828349917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3828349917
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3046995458
Short name T91
Test name
Test status
Simulation time 438782179 ps
CPU time 3.9 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:30 PM PDT 24
Peak memory 201084 kb
Host smart-32e1ac35-4229-49bd-81e0-8869b2fd41dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046995458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3046995458
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.3346292435
Short name T678
Test name
Test status
Simulation time 304438168 ps
CPU time 1.69 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:32 PM PDT 24
Peak memory 201240 kb
Host smart-330a71ff-ce24-4fc6-8539-f9140ddf2561
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346292435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.3346292435
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.499698398
Short name T198
Test name
Test status
Simulation time 40355720 ps
CPU time 0.98 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201064 kb
Host smart-25137fea-5cee-42c1-a6a6-e60e93b16ec5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499698398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.499698398
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2376600577
Short name T348
Test name
Test status
Simulation time 17413477 ps
CPU time 0.76 seconds
Started Jul 29 07:32:28 PM PDT 24
Finished Jul 29 07:32:29 PM PDT 24
Peak memory 201068 kb
Host smart-5f7135e3-22ff-4dc3-8dc7-e464883068b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376600577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2376600577
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3154509152
Short name T727
Test name
Test status
Simulation time 35220602 ps
CPU time 0.94 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201000 kb
Host smart-c58d9a58-b4b5-47a2-b52a-79e0617a0b04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154509152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.3154509152
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.604871777
Short name T756
Test name
Test status
Simulation time 50942890 ps
CPU time 0.93 seconds
Started Jul 29 07:32:26 PM PDT 24
Finished Jul 29 07:32:27 PM PDT 24
Peak memory 201000 kb
Host smart-7cb54e51-5baa-4d1f-845b-b45f565d97b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604871777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.604871777
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.1492900898
Short name T599
Test name
Test status
Simulation time 68951501 ps
CPU time 0.99 seconds
Started Jul 29 07:32:45 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201048 kb
Host smart-5a5b9b32-97e0-4216-83f7-aa973ec0c666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492900898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1492900898
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.3222170061
Short name T651
Test name
Test status
Simulation time 19174749 ps
CPU time 0.83 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 200992 kb
Host smart-f696071a-e011-4de7-88a2-b6eee58dcbda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222170061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3222170061
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.3125752726
Short name T336
Test name
Test status
Simulation time 5791189194 ps
CPU time 24.59 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:33:04 PM PDT 24
Peak memory 201348 kb
Host smart-e635c278-4cf6-4ee3-bea4-66fce063152c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125752726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.3125752726
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1080400819
Short name T546
Test name
Test status
Simulation time 81557138 ps
CPU time 1.06 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201040 kb
Host smart-bdc3aa38-1b4e-4ae5-a6fc-d10a14cd4dff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080400819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1080400819
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.3060090543
Short name T770
Test name
Test status
Simulation time 38378377 ps
CPU time 0.76 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201232 kb
Host smart-c121b022-02d7-4589-9bbb-99587a73da52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060090543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.3060090543
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.885145843
Short name T781
Test name
Test status
Simulation time 113803461 ps
CPU time 1.18 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201004 kb
Host smart-72755333-35a0-467b-a4d2-1dc6a8dd2004
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885145843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.885145843
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1641282908
Short name T419
Test name
Test status
Simulation time 39048520 ps
CPU time 0.78 seconds
Started Jul 29 07:32:32 PM PDT 24
Finished Jul 29 07:32:33 PM PDT 24
Peak memory 200220 kb
Host smart-209c057e-c321-4516-bb81-9438ebf57885
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641282908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1641282908
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.3720768248
Short name T697
Test name
Test status
Simulation time 56007048 ps
CPU time 0.88 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201032 kb
Host smart-9d9756d7-e832-4676-b122-bf2029d64ab0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720768248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.3720768248
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3640633856
Short name T405
Test name
Test status
Simulation time 21960518 ps
CPU time 0.89 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 201028 kb
Host smart-8c2cd517-29b9-4ddb-bd5a-29a848d55fec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640633856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3640633856
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2529941351
Short name T807
Test name
Test status
Simulation time 2132008766 ps
CPU time 11.8 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201344 kb
Host smart-55c9127a-05f3-45c2-91c4-4b96910ee463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529941351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2529941351
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1807418242
Short name T228
Test name
Test status
Simulation time 1858491616 ps
CPU time 7.95 seconds
Started Jul 29 07:32:29 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 201208 kb
Host smart-5d1cc284-c159-4338-a7ff-1e46a0929a66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807418242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1807418242
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.3633518875
Short name T281
Test name
Test status
Simulation time 112592832 ps
CPU time 1.15 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 201148 kb
Host smart-1319adb5-e42b-48fb-8476-6ecc36daf52f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633518875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.3633518875
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2676463237
Short name T440
Test name
Test status
Simulation time 59729849 ps
CPU time 0.86 seconds
Started Jul 29 07:32:25 PM PDT 24
Finished Jul 29 07:32:26 PM PDT 24
Peak memory 201092 kb
Host smart-c97602a5-02f6-4cd8-85e6-4dacb2ef39e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676463237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2676463237
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1888766634
Short name T26
Test name
Test status
Simulation time 46148097 ps
CPU time 0.95 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 200992 kb
Host smart-46f271df-e2dc-4fa1-ab1c-f2cf6771309b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888766634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1888766634
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.1498680810
Short name T339
Test name
Test status
Simulation time 45043744 ps
CPU time 0.85 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:36 PM PDT 24
Peak memory 201000 kb
Host smart-af64dd5c-567d-4160-a146-345f1e711900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498680810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1498680810
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1208389581
Short name T456
Test name
Test status
Simulation time 1133999462 ps
CPU time 6.23 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201204 kb
Host smart-b9b30bb1-b977-4c9b-83bd-14a6f13d368a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208389581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1208389581
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.1206652313
Short name T618
Test name
Test status
Simulation time 18436655 ps
CPU time 0.79 seconds
Started Jul 29 07:32:30 PM PDT 24
Finished Jul 29 07:32:31 PM PDT 24
Peak memory 201060 kb
Host smart-113dc30b-ee6e-4369-9a37-96b7c8a35c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206652313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1206652313
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.3597566793
Short name T316
Test name
Test status
Simulation time 2894330417 ps
CPU time 15.33 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201440 kb
Host smart-98aa0bcc-d5ac-4ab1-9bc1-0d3ef339938e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597566793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.3597566793
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.2115495240
Short name T68
Test name
Test status
Simulation time 19790212199 ps
CPU time 349.02 seconds
Started Jul 29 07:32:35 PM PDT 24
Finished Jul 29 07:38:24 PM PDT 24
Peak memory 217448 kb
Host smart-faa36302-0f94-4804-ada2-e1dfcaace566
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2115495240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.2115495240
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.3346694835
Short name T701
Test name
Test status
Simulation time 23095316 ps
CPU time 0.84 seconds
Started Jul 29 07:32:36 PM PDT 24
Finished Jul 29 07:32:37 PM PDT 24
Peak memory 201064 kb
Host smart-a49110cc-b71f-49b0-8e01-cdbd30db5c08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346694835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3346694835
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.3123118930
Short name T390
Test name
Test status
Simulation time 119640724 ps
CPU time 1.08 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201124 kb
Host smart-600f4786-b69a-4940-94c0-71f434f3570d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123118930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.3123118930
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2508236168
Short name T639
Test name
Test status
Simulation time 24321340 ps
CPU time 0.88 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201096 kb
Host smart-ad952fa1-7e23-4309-ab66-3825d704a85f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508236168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.2508236168
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.3769124372
Short name T552
Test name
Test status
Simulation time 43925246 ps
CPU time 0.78 seconds
Started Jul 29 07:32:42 PM PDT 24
Finished Jul 29 07:32:43 PM PDT 24
Peak memory 200292 kb
Host smart-037a6034-f829-45e9-b093-b49a38be7c8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769124372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3769124372
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1609431819
Short name T636
Test name
Test status
Simulation time 222164118 ps
CPU time 1.43 seconds
Started Jul 29 07:32:37 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201080 kb
Host smart-dcd5a397-9f8b-46ef-82ad-1a1d13c829c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609431819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.1609431819
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1300750261
Short name T48
Test name
Test status
Simulation time 46091954 ps
CPU time 0.88 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201012 kb
Host smart-0a7ea7b0-5e53-474f-b3b8-c33a7c1e4ab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300750261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1300750261
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.2524962994
Short name T15
Test name
Test status
Simulation time 1399919703 ps
CPU time 8.29 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:47 PM PDT 24
Peak memory 201224 kb
Host smart-f9508faa-4765-4846-9225-dd74b8751168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524962994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2524962994
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.1025642192
Short name T97
Test name
Test status
Simulation time 501972515 ps
CPU time 4.54 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:45 PM PDT 24
Peak memory 201252 kb
Host smart-1638dabe-ef0f-48e2-8ebd-0c9076b09a7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025642192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.1025642192
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.239971160
Short name T325
Test name
Test status
Simulation time 62216386 ps
CPU time 1.1 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:41 PM PDT 24
Peak memory 201012 kb
Host smart-92da78cc-cd3f-4afe-8a8c-f776b70b1614
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239971160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_idle_intersig_mubi.239971160
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1437052444
Short name T613
Test name
Test status
Simulation time 37359463 ps
CPU time 0.92 seconds
Started Jul 29 07:32:38 PM PDT 24
Finished Jul 29 07:32:39 PM PDT 24
Peak memory 201088 kb
Host smart-75497534-a5a6-4315-b109-5688e07aa3f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437052444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1437052444
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.653154988
Short name T616
Test name
Test status
Simulation time 70454102 ps
CPU time 0.9 seconds
Started Jul 29 07:32:39 PM PDT 24
Finished Jul 29 07:32:40 PM PDT 24
Peak memory 201088 kb
Host smart-bc693841-f8fd-4e58-ad15-71a09f664067
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653154988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_ctrl_intersig_mubi.653154988
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.2605772159
Short name T504
Test name
Test status
Simulation time 16939434 ps
CPU time 0.76 seconds
Started Jul 29 07:32:43 PM PDT 24
Finished Jul 29 07:32:44 PM PDT 24
Peak memory 201048 kb
Host smart-c5c6be2d-cfed-49eb-bcbb-f2f3982fa933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605772159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.2605772159
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1100848753
Short name T751
Test name
Test status
Simulation time 524016338 ps
CPU time 2.52 seconds
Started Jul 29 07:32:46 PM PDT 24
Finished Jul 29 07:32:48 PM PDT 24
Peak memory 201120 kb
Host smart-2b59abf2-5c01-4025-a432-e1071003b294
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100848753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1100848753
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.4223184037
Short name T295
Test name
Test status
Simulation time 15066334 ps
CPU time 0.79 seconds
Started Jul 29 07:32:37 PM PDT 24
Finished Jul 29 07:32:38 PM PDT 24
Peak memory 201000 kb
Host smart-bb3bc392-ab3d-4aa8-b93b-85412dd05932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223184037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.4223184037
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1718361014
Short name T671
Test name
Test status
Simulation time 2100652265 ps
CPU time 13.87 seconds
Started Jul 29 07:32:41 PM PDT 24
Finished Jul 29 07:32:55 PM PDT 24
Peak memory 201404 kb
Host smart-6d451860-32b7-4e87-9e48-e63528dd9659
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718361014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1718361014
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.2688154097
Short name T708
Test name
Test status
Simulation time 135818246661 ps
CPU time 819.78 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:46:20 PM PDT 24
Peak memory 217988 kb
Host smart-7935e245-4185-4e3f-9866-34ef3eff1b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2688154097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2688154097
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.2221929775
Short name T738
Test name
Test status
Simulation time 91299327 ps
CPU time 1.14 seconds
Started Jul 29 07:32:40 PM PDT 24
Finished Jul 29 07:32:42 PM PDT 24
Peak memory 201056 kb
Host smart-2e2f8a16-85be-49de-bd18-48415d997c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221929775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2221929775
Directory /workspace/9.clkmgr_trans/latest
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