Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134497070 1 T5 4708 T6 20202 T4 12124
auto[1] 229336 1 T23 64 T1 2068 T17 776


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134472378 1 T5 4708 T6 20202 T4 12124
auto[1] 254028 1 T23 280 T1 1614 T17 622


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 134421490 1 T5 4708 T6 20202 T4 12124
auto[1] 304916 1 T23 304 T1 1846 T17 700


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 126666064 1 T5 4708 T6 20202 T4 12124
auto[1] 8060342 1 T23 772 T1 201764 T17 190


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 81399130 1 T5 3834 T6 20202 T4 12124
auto[1] 53327276 1 T5 874 T23 138 T1 129840


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 74275400 1 T5 3834 T6 20202 T4 12124
auto[0] auto[0] auto[0] auto[0] auto[1] 52135018 1 T5 874 T23 30 T1 319870
auto[0] auto[0] auto[0] auto[1] auto[0] 17812 1 T23 12 T1 88 T17 220
auto[0] auto[0] auto[0] auto[1] auto[1] 3502 1 T1 2 T17 30 T9 10
auto[0] auto[0] auto[1] auto[0] auto[0] 6735962 1 T23 528 T1 103772 T17 94
auto[0] auto[0] auto[1] auto[0] auto[1] 1130506 1 T23 88 T1 978160 T19 176
auto[0] auto[0] auto[1] auto[1] auto[0] 26724 1 T1 236 T17 30 T19 34
auto[0] auto[0] auto[1] auto[1] auto[1] 6794 1 T1 84 T9 108 T10 52
auto[0] auto[1] auto[0] auto[0] auto[0] 58072 1 T23 32 T1 34 T17 10
auto[0] auto[1] auto[0] auto[0] auto[1] 878 1 T11 16 T153 8 T154 44
auto[0] auto[1] auto[0] auto[1] auto[0] 8330 1 T1 46 T17 46 T100 96
auto[0] auto[1] auto[0] auto[1] auto[1] 1450 1 T11 76 T155 52 T55 100
auto[0] auto[1] auto[1] auto[0] auto[0] 6058 1 T1 58 T17 12 T19 68
auto[0] auto[1] auto[1] auto[0] auto[1] 1258 1 T9 4 T156 18 T153 2
auto[0] auto[1] auto[1] auto[1] auto[0] 11074 1 T1 228 T17 54 T19 70
auto[0] auto[1] auto[1] auto[1] auto[1] 2652 1 T9 116 T153 40 T33 88
auto[1] auto[0] auto[0] auto[0] auto[0] 58602 1 T1 46 T17 58 T19 2
auto[1] auto[0] auto[0] auto[0] auto[1] 2434 1 T9 8 T10 14 T11 64
auto[1] auto[0] auto[0] auto[1] auto[0] 19976 1 T1 96 T17 142 T19 82
auto[1] auto[0] auto[0] auto[1] auto[1] 4388 1 T10 62 T13 44 T60 50
auto[1] auto[0] auto[1] auto[0] auto[0] 14580 1 T23 56 T1 122 T19 54
auto[1] auto[0] auto[1] auto[0] auto[1] 4200 1 T1 10 T22 8 T9 30
auto[1] auto[0] auto[1] auto[1] auto[0] 29374 1 T1 324 T19 74 T22 62
auto[1] auto[0] auto[1] auto[1] auto[1] 7106 1 T11 202 T13 38 T60 46
auto[1] auto[1] auto[0] auto[0] auto[0] 40022 1 T23 96 T1 102 T17 206
auto[1] auto[1] auto[0] auto[0] auto[1] 3874 1 T1 10 T17 40 T9 2
auto[1] auto[1] auto[0] auto[1] auto[0] 28826 1 T23 52 T1 318 T17 190
auto[1] auto[1] auto[0] auto[1] auto[1] 7480 1 T1 114 T17 64 T9 48
auto[1] auto[1] auto[1] auto[0] auto[0] 24704 1 T23 80 T1 112 T22 8
auto[1] auto[1] auto[1] auto[0] auto[1] 5502 1 T23 20 T1 60 T19 98
auto[1] auto[1] auto[1] auto[1] auto[0] 43614 1 T1 434 T100 74 T101 184
auto[1] auto[1] auto[1] auto[1] auto[1] 10234 1 T1 98 T9 64 T10 178

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