Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.51 99.15 95.76 100.00 100.00 98.81 97.02 98.80


Total test records in report: 980
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T809 /workspace/coverage/default/33.clkmgr_peri.3377520733 Jul 30 06:26:05 PM PDT 24 Jul 30 06:26:06 PM PDT 24 36662927 ps
T810 /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.3127855465 Jul 30 06:24:35 PM PDT 24 Jul 30 06:24:36 PM PDT 24 37865185 ps
T811 /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3662723618 Jul 30 06:24:35 PM PDT 24 Jul 30 06:24:36 PM PDT 24 135768163 ps
T41 /workspace/coverage/default/0.clkmgr_sec_cm.1399083247 Jul 30 06:24:39 PM PDT 24 Jul 30 06:24:43 PM PDT 24 297424715 ps
T812 /workspace/coverage/default/12.clkmgr_trans.3793560048 Jul 30 06:25:12 PM PDT 24 Jul 30 06:25:13 PM PDT 24 101162952 ps
T813 /workspace/coverage/default/37.clkmgr_regwen.1414093838 Jul 30 06:26:15 PM PDT 24 Jul 30 06:26:16 PM PDT 24 103206426 ps
T814 /workspace/coverage/default/45.clkmgr_frequency.2550231992 Jul 30 06:26:32 PM PDT 24 Jul 30 06:26:39 PM PDT 24 1283077477 ps
T815 /workspace/coverage/default/45.clkmgr_smoke.1636597649 Jul 30 06:26:20 PM PDT 24 Jul 30 06:26:21 PM PDT 24 45871755 ps
T816 /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.3701412571 Jul 30 06:25:48 PM PDT 24 Jul 30 06:25:49 PM PDT 24 97262636 ps
T817 /workspace/coverage/default/47.clkmgr_clk_status.3280682869 Jul 30 06:26:21 PM PDT 24 Jul 30 06:26:22 PM PDT 24 16391496 ps
T818 /workspace/coverage/default/46.clkmgr_trans.2679509066 Jul 30 06:26:31 PM PDT 24 Jul 30 06:26:32 PM PDT 24 52374666 ps
T819 /workspace/coverage/default/37.clkmgr_peri.3688291600 Jul 30 06:26:14 PM PDT 24 Jul 30 06:26:15 PM PDT 24 27465417 ps
T820 /workspace/coverage/default/32.clkmgr_peri.48476984 Jul 30 06:25:50 PM PDT 24 Jul 30 06:25:51 PM PDT 24 20256040 ps
T821 /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1332997288 Jul 30 06:26:19 PM PDT 24 Jul 30 06:26:20 PM PDT 24 60812630 ps
T822 /workspace/coverage/default/28.clkmgr_extclk.417438958 Jul 30 06:25:41 PM PDT 24 Jul 30 06:25:42 PM PDT 24 88921956 ps
T823 /workspace/coverage/default/25.clkmgr_extclk.78923730 Jul 30 06:25:44 PM PDT 24 Jul 30 06:25:45 PM PDT 24 96002739 ps
T824 /workspace/coverage/default/6.clkmgr_frequency_timeout.1693766315 Jul 30 06:24:53 PM PDT 24 Jul 30 06:24:56 PM PDT 24 525386238 ps
T825 /workspace/coverage/default/9.clkmgr_frequency_timeout.2218048998 Jul 30 06:25:05 PM PDT 24 Jul 30 06:25:07 PM PDT 24 134895803 ps
T826 /workspace/coverage/default/33.clkmgr_stress_all.847242723 Jul 30 06:26:10 PM PDT 24 Jul 30 06:26:37 PM PDT 24 4713671780 ps
T827 /workspace/coverage/default/25.clkmgr_div_intersig_mubi.69588579 Jul 30 06:25:38 PM PDT 24 Jul 30 06:25:39 PM PDT 24 26775411 ps
T828 /workspace/coverage/default/32.clkmgr_clk_status.1627992588 Jul 30 06:25:50 PM PDT 24 Jul 30 06:25:50 PM PDT 24 16525376 ps
T42 /workspace/coverage/default/1.clkmgr_sec_cm.270735014 Jul 30 06:24:38 PM PDT 24 Jul 30 06:24:47 PM PDT 24 2299598272 ps
T829 /workspace/coverage/default/26.clkmgr_clk_status.201191638 Jul 30 06:25:43 PM PDT 24 Jul 30 06:25:44 PM PDT 24 43782956 ps
T830 /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.370868278 Jul 30 06:26:31 PM PDT 24 Jul 30 06:26:32 PM PDT 24 70859741 ps
T831 /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3484510873 Jul 30 06:25:53 PM PDT 24 Jul 30 06:25:54 PM PDT 24 29503891 ps
T43 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3750897145 Jul 30 06:43:35 PM PDT 24 Jul 30 06:43:37 PM PDT 24 87073612 ps
T64 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.558631224 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 20350228 ps
T89 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1613231135 Jul 30 06:43:15 PM PDT 24 Jul 30 06:43:17 PM PDT 24 38754144 ps
T832 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3810776412 Jul 30 06:44:38 PM PDT 24 Jul 30 06:44:38 PM PDT 24 12976866 ps
T44 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1911804635 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 60980961 ps
T83 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3400570008 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:27 PM PDT 24 293034407 ps
T84 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2600090975 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 61875147 ps
T833 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3296143053 Jul 30 06:43:31 PM PDT 24 Jul 30 06:43:32 PM PDT 24 24594481 ps
T834 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2677531897 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:29 PM PDT 24 204480980 ps
T65 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.355211136 Jul 30 06:43:09 PM PDT 24 Jul 30 06:43:11 PM PDT 24 54008971 ps
T835 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.4192998590 Jul 30 06:43:34 PM PDT 24 Jul 30 06:43:34 PM PDT 24 21136224 ps
T836 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1252306432 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:27 PM PDT 24 882875742 ps
T66 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3852591436 Jul 30 06:43:31 PM PDT 24 Jul 30 06:43:32 PM PDT 24 56899125 ps
T85 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1800854773 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 172357546 ps
T837 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2522057961 Jul 30 06:43:42 PM PDT 24 Jul 30 06:43:43 PM PDT 24 34913228 ps
T67 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.494784796 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:23 PM PDT 24 114154442 ps
T45 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3978847107 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 81167946 ps
T47 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1980475141 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 144820810 ps
T68 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3430461534 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 141533772 ps
T838 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.4227849898 Jul 30 06:43:32 PM PDT 24 Jul 30 06:43:32 PM PDT 24 11784505 ps
T69 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2251647588 Jul 30 06:43:18 PM PDT 24 Jul 30 06:43:19 PM PDT 24 48552230 ps
T46 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2343260510 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 158781745 ps
T839 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2631786783 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 36106510 ps
T70 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.4086282458 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 112481320 ps
T71 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.395444028 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 37436422 ps
T840 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1290637239 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 102946497 ps
T841 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3144569224 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:22 PM PDT 24 66287744 ps
T842 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1984942329 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 22658518 ps
T843 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2312615989 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:20 PM PDT 24 41396523 ps
T844 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2104102251 Jul 30 06:43:40 PM PDT 24 Jul 30 06:43:41 PM PDT 24 25937781 ps
T50 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2449767932 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 84961816 ps
T845 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.500137248 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:29 PM PDT 24 13350703 ps
T846 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3060427644 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 45890631 ps
T52 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3362538730 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:22 PM PDT 24 92789728 ps
T847 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.4209118548 Jul 30 06:43:29 PM PDT 24 Jul 30 06:43:39 PM PDT 24 446485117 ps
T848 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1609509516 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:23 PM PDT 24 138568093 ps
T849 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3461897952 Jul 30 06:43:15 PM PDT 24 Jul 30 06:43:18 PM PDT 24 274519061 ps
T51 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3765677377 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:27 PM PDT 24 266953693 ps
T850 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.892651997 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:24 PM PDT 24 100407844 ps
T851 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1802310759 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:32 PM PDT 24 85126611 ps
T852 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1245451323 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 21525213 ps
T853 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3926385680 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:28 PM PDT 24 13491524 ps
T854 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.932097667 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 16552173 ps
T48 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3341550681 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:32 PM PDT 24 56177122 ps
T855 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.650456010 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 15183831 ps
T49 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2465508038 Jul 30 06:43:36 PM PDT 24 Jul 30 06:43:38 PM PDT 24 112956633 ps
T856 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3134738218 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:26 PM PDT 24 28870671 ps
T857 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.165701062 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 43308970 ps
T858 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2746790738 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 17586704 ps
T859 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.932315915 Jul 30 06:43:10 PM PDT 24 Jul 30 06:43:11 PM PDT 24 21234790 ps
T860 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1784955461 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 255044382 ps
T861 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1499218159 Jul 30 06:43:36 PM PDT 24 Jul 30 06:43:36 PM PDT 24 83060918 ps
T862 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1600484627 Jul 30 06:43:29 PM PDT 24 Jul 30 06:43:30 PM PDT 24 14928629 ps
T863 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2550347358 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:33 PM PDT 24 1136766053 ps
T864 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1542276298 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 351449051 ps
T865 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1735753092 Jul 30 06:43:38 PM PDT 24 Jul 30 06:43:40 PM PDT 24 114949810 ps
T866 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.130330856 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:23 PM PDT 24 13099433 ps
T867 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2206894147 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:24 PM PDT 24 122580825 ps
T868 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1604539121 Jul 30 06:43:35 PM PDT 24 Jul 30 06:43:36 PM PDT 24 15752659 ps
T869 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.288396907 Jul 30 06:43:36 PM PDT 24 Jul 30 06:43:36 PM PDT 24 16009858 ps
T870 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.237630543 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 132346135 ps
T871 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1579843979 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:20 PM PDT 24 52178085 ps
T86 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3972810645 Jul 30 06:43:10 PM PDT 24 Jul 30 06:43:12 PM PDT 24 89879858 ps
T872 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.816302920 Jul 30 06:43:37 PM PDT 24 Jul 30 06:43:45 PM PDT 24 43743679 ps
T873 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1405988682 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:20 PM PDT 24 139210772 ps
T152 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1894630367 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 236562096 ps
T105 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2128317717 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 174185752 ps
T874 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1074270508 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:27 PM PDT 24 19647135 ps
T875 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.666554465 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 68392542 ps
T876 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.4147807140 Jul 30 06:43:11 PM PDT 24 Jul 30 06:43:13 PM PDT 24 40265993 ps
T877 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.971756105 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 27998721 ps
T90 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.127222364 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:24 PM PDT 24 646386229 ps
T878 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.541032034 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 82486916 ps
T879 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1334636567 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 30451954 ps
T880 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.225255146 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 61441123 ps
T91 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1626251532 Jul 30 06:43:42 PM PDT 24 Jul 30 06:43:44 PM PDT 24 82578147 ps
T881 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.917557408 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:30 PM PDT 24 126879826 ps
T107 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2574476367 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 292108031 ps
T882 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4289022797 Jul 30 06:43:29 PM PDT 24 Jul 30 06:43:31 PM PDT 24 76727804 ps
T53 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2082013469 Jul 30 06:43:14 PM PDT 24 Jul 30 06:43:19 PM PDT 24 982309524 ps
T883 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2325582357 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 41728728 ps
T884 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3400578827 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 86982090 ps
T885 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.261848754 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 17577937 ps
T886 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3412512477 Jul 30 06:44:19 PM PDT 24 Jul 30 06:44:23 PM PDT 24 26136742 ps
T887 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.618166900 Jul 30 06:43:12 PM PDT 24 Jul 30 06:43:13 PM PDT 24 14099744 ps
T888 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3140705896 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 37285740 ps
T889 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.1438100057 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:25 PM PDT 24 89732213 ps
T108 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3077281012 Jul 30 06:43:18 PM PDT 24 Jul 30 06:43:20 PM PDT 24 87825948 ps
T890 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2572199989 Jul 30 06:43:34 PM PDT 24 Jul 30 06:43:35 PM PDT 24 24230303 ps
T891 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4259664317 Jul 30 06:43:34 PM PDT 24 Jul 30 06:43:35 PM PDT 24 36754334 ps
T106 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.4035125452 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:30 PM PDT 24 152284975 ps
T113 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3929584758 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 87658414 ps
T892 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3268793421 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:20 PM PDT 24 27298108 ps
T109 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3202219632 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 78009481 ps
T117 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2293915414 Jul 30 06:43:29 PM PDT 24 Jul 30 06:43:31 PM PDT 24 101231948 ps
T110 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3534647458 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 68986302 ps
T893 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3632275351 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:31 PM PDT 24 523373215 ps
T894 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2838550762 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 22224989 ps
T895 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.905103551 Jul 30 06:43:18 PM PDT 24 Jul 30 06:43:19 PM PDT 24 12950720 ps
T111 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.220457195 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:23 PM PDT 24 95494693 ps
T896 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.380648874 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 54357688 ps
T897 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2307426961 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 103406000 ps
T898 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.31112866 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 39737286 ps
T899 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.394578884 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 54539676 ps
T900 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3149413623 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:29 PM PDT 24 295397128 ps
T96 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.667604125 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:25 PM PDT 24 56281081 ps
T126 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.352151155 Jul 30 06:43:12 PM PDT 24 Jul 30 06:43:14 PM PDT 24 233721445 ps
T901 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2062092953 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 19052440 ps
T902 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4150633031 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:24 PM PDT 24 30329344 ps
T903 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2043080683 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 170540149 ps
T904 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.390062177 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 39093003 ps
T905 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.268494088 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:23 PM PDT 24 144523524 ps
T906 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.469957645 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:29 PM PDT 24 19405273 ps
T907 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.867700217 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 33836080 ps
T908 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1836909782 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:28 PM PDT 24 26246726 ps
T909 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1780746800 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 46029130 ps
T910 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2418913096 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:27 PM PDT 24 12822312 ps
T92 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.154967009 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:25 PM PDT 24 225873513 ps
T911 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.991223970 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 246681379 ps
T93 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2480491521 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 241765305 ps
T912 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3720764546 Jul 30 06:43:09 PM PDT 24 Jul 30 06:43:10 PM PDT 24 66145078 ps
T913 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2392138267 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 40315988 ps
T114 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3298515571 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 77827809 ps
T914 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.726725869 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:35 PM PDT 24 193623111 ps
T915 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3355258160 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:27 PM PDT 24 18041890 ps
T916 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.440535951 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 36733336 ps
T917 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.572239005 Jul 30 06:43:34 PM PDT 24 Jul 30 06:43:35 PM PDT 24 22971030 ps
T94 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.248714283 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:30 PM PDT 24 353985300 ps
T918 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1285704909 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 34623579 ps
T919 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3434338082 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 108387216 ps
T95 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.223663935 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:23 PM PDT 24 285315473 ps
T920 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.829110557 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:26 PM PDT 24 24916808 ps
T921 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.83316497 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:29 PM PDT 24 53883195 ps
T87 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1811721033 Jul 30 06:43:32 PM PDT 24 Jul 30 06:43:35 PM PDT 24 209059238 ps
T922 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.827398595 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 22174574 ps
T923 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3251100462 Jul 30 06:43:07 PM PDT 24 Jul 30 06:43:07 PM PDT 24 10967713 ps
T924 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.418763631 Jul 30 06:43:38 PM PDT 24 Jul 30 06:43:40 PM PDT 24 139157549 ps
T925 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.980447460 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 14570954 ps
T115 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1343111762 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 231906532 ps
T926 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3861462086 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 46225270 ps
T88 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.4230026443 Jul 30 06:43:37 PM PDT 24 Jul 30 06:43:40 PM PDT 24 109433154 ps
T927 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.293867694 Jul 30 06:43:17 PM PDT 24 Jul 30 06:43:20 PM PDT 24 110550901 ps
T118 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.56176452 Jul 30 06:43:06 PM PDT 24 Jul 30 06:43:09 PM PDT 24 766493420 ps
T928 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3184981648 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 12265049 ps
T119 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4195911337 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:21 PM PDT 24 200526318 ps
T121 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3043994230 Jul 30 06:43:12 PM PDT 24 Jul 30 06:43:15 PM PDT 24 390943531 ps
T929 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.432660391 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:28 PM PDT 24 89493937 ps
T123 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.756239977 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 69730746 ps
T930 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1023257156 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 354835167 ps
T116 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1251503214 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 221521652 ps
T931 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.873228386 Jul 30 06:43:32 PM PDT 24 Jul 30 06:43:33 PM PDT 24 36382653 ps
T932 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1845953318 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:22 PM PDT 24 237594378 ps
T933 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3928015142 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:24 PM PDT 24 29783609 ps
T934 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3340789945 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 14352849 ps
T935 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3945061820 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:21 PM PDT 24 12641213 ps
T936 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4226062718 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 105368599 ps
T937 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.343913954 Jul 30 06:43:18 PM PDT 24 Jul 30 06:43:23 PM PDT 24 551586792 ps
T938 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.997573031 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:28 PM PDT 24 20324072 ps
T939 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4061374398 Jul 30 06:43:18 PM PDT 24 Jul 30 06:43:19 PM PDT 24 29033004 ps
T940 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1030423318 Jul 30 06:43:17 PM PDT 24 Jul 30 06:43:19 PM PDT 24 61300025 ps
T941 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1686154704 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:21 PM PDT 24 153029942 ps
T942 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.791563579 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 42881313 ps
T122 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3467480157 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:23 PM PDT 24 91863045 ps
T943 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.4195290880 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 49339887 ps
T944 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2032323104 Jul 30 06:43:31 PM PDT 24 Jul 30 06:43:34 PM PDT 24 378414373 ps
T945 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1784178653 Jul 30 06:43:15 PM PDT 24 Jul 30 06:43:18 PM PDT 24 133829946 ps
T946 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2559116334 Jul 30 06:43:32 PM PDT 24 Jul 30 06:43:33 PM PDT 24 46070576 ps
T947 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2040856313 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:23 PM PDT 24 38223164 ps
T948 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1996007926 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:27 PM PDT 24 679557234 ps
T949 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2806449721 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:29 PM PDT 24 13509047 ps
T950 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4243468946 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 101420549 ps
T951 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.764092876 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 80119866 ps
T952 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2801881376 Jul 30 06:43:11 PM PDT 24 Jul 30 06:43:13 PM PDT 24 39559409 ps
T953 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2906971046 Jul 30 06:43:33 PM PDT 24 Jul 30 06:43:34 PM PDT 24 12559475 ps
T954 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3849012025 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:23 PM PDT 24 128609944 ps
T955 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3514001875 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 40923255 ps
T956 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1062679040 Jul 30 06:43:23 PM PDT 24 Jul 30 06:43:26 PM PDT 24 177994088 ps
T957 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1977669980 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:30 PM PDT 24 223022632 ps
T958 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2461451290 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:25 PM PDT 24 14670989 ps
T959 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2521491048 Jul 30 06:43:35 PM PDT 24 Jul 30 06:43:36 PM PDT 24 24581393 ps
T124 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.947141315 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:26 PM PDT 24 1463885984 ps
T960 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1272991736 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:28 PM PDT 24 58526152 ps
T961 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4089741848 Jul 30 06:43:10 PM PDT 24 Jul 30 06:43:12 PM PDT 24 137560871 ps
T962 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.849554826 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 439627312 ps
T963 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.65216843 Jul 30 06:43:46 PM PDT 24 Jul 30 06:43:46 PM PDT 24 11215695 ps
T112 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1039791018 Jul 30 06:43:19 PM PDT 24 Jul 30 06:43:21 PM PDT 24 90199047 ps
T964 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.4081179659 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:21 PM PDT 24 38966782 ps
T965 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.519225693 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 95904318 ps
T966 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2271806642 Jul 30 06:43:35 PM PDT 24 Jul 30 06:43:36 PM PDT 24 18430957 ps
T967 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2885613136 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 91121732 ps
T968 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1443325527 Jul 30 06:43:27 PM PDT 24 Jul 30 06:43:28 PM PDT 24 15185459 ps
T120 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2909842261 Jul 30 06:43:28 PM PDT 24 Jul 30 06:43:30 PM PDT 24 159725792 ps
T969 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3790767826 Jul 30 06:43:30 PM PDT 24 Jul 30 06:43:31 PM PDT 24 12984989 ps
T970 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.39060142 Jul 30 06:43:21 PM PDT 24 Jul 30 06:43:22 PM PDT 24 37626026 ps
T971 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3539136178 Jul 30 06:43:29 PM PDT 24 Jul 30 06:43:30 PM PDT 24 32338800 ps
T972 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3559708968 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:27 PM PDT 24 249474965 ps
T973 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2165900868 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:22 PM PDT 24 43840071 ps
T974 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.416756986 Jul 30 06:43:13 PM PDT 24 Jul 30 06:43:22 PM PDT 24 536410073 ps
T975 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3413816137 Jul 30 06:43:22 PM PDT 24 Jul 30 06:43:23 PM PDT 24 24959167 ps
T976 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1617497925 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 145463687 ps
T977 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.297373160 Jul 30 06:43:24 PM PDT 24 Jul 30 06:43:26 PM PDT 24 155801391 ps
T125 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.885780819 Jul 30 06:43:25 PM PDT 24 Jul 30 06:43:28 PM PDT 24 189152632 ps
T978 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1361962958 Jul 30 06:43:26 PM PDT 24 Jul 30 06:43:27 PM PDT 24 23241076 ps
T979 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.212142469 Jul 30 06:43:43 PM PDT 24 Jul 30 06:43:44 PM PDT 24 15530429 ps
T980 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.251604705 Jul 30 06:43:20 PM PDT 24 Jul 30 06:43:22 PM PDT 24 174036881 ps

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.3671615571
Short name T1
Test name
Test status
Simulation time 38654101287 ps
CPU time 379.15 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:32:51 PM PDT 24
Peak memory 217872 kb
Host smart-ac3063b8-110d-43d0-9e83-167d03930cb1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3671615571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.3671615571
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.3932634310
Short name T13
Test name
Test status
Simulation time 7337243140 ps
CPU time 43.02 seconds
Started Jul 30 06:26:06 PM PDT 24
Finished Jul 30 06:26:49 PM PDT 24
Peak memory 201440 kb
Host smart-d48c9ec0-194c-4505-9cc7-8acc177ec955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932634310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.3932634310
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2465508038
Short name T49
Test name
Test status
Simulation time 112956633 ps
CPU time 1.94 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:38 PM PDT 24
Peak memory 217148 kb
Host smart-d459ef05-afc7-449f-b759-a632125d7043
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465508038 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2465508038
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.8660637
Short name T20
Test name
Test status
Simulation time 1062818765 ps
CPU time 4.46 seconds
Started Jul 30 06:26:12 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201316 kb
Host smart-13325a41-f6b2-42eb-83d5-30b0a300bb16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8660637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.8660637
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.4063366910
Short name T6
Test name
Test status
Simulation time 371091103 ps
CPU time 3.11 seconds
Started Jul 30 06:24:43 PM PDT 24
Finished Jul 30 06:24:47 PM PDT 24
Peak memory 222036 kb
Host smart-c86857ee-efe7-4a08-913d-f8ac6502fbff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063366910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.4063366910
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.1059160698
Short name T149
Test name
Test status
Simulation time 13672249 ps
CPU time 0.7 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 200260 kb
Host smart-0f8cd34e-eee8-4ed4-b452-f4f751f7b6da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059160698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.1059160698
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.3750897145
Short name T43
Test name
Test status
Simulation time 87073612 ps
CPU time 2.02 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:37 PM PDT 24
Peak memory 208996 kb
Host smart-28723862-100e-4942-8dbb-bd2bae0c031c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750897145 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3750897145
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.681312899
Short name T18
Test name
Test status
Simulation time 37177779 ps
CPU time 1.03 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201064 kb
Host smart-a63d6e15-a0f2-4b56-bbe5-c31a612c02e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681312899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_idle_intersig_mubi.681312899
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2480491521
Short name T93
Test name
Test status
Simulation time 241765305 ps
CPU time 2.95 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200528 kb
Host smart-da4d1cac-af96-4a05-9172-cd1be4f74440
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480491521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.2480491521
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.2892810059
Short name T55
Test name
Test status
Simulation time 129047110515 ps
CPU time 778.71 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:39:29 PM PDT 24
Peak memory 217980 kb
Host smart-45c9a572-cc2f-4892-a369-1fe7f1b7bd33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2892810059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.2892810059
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.365720883
Short name T9
Test name
Test status
Simulation time 5116135423 ps
CPU time 17.05 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:20 PM PDT 24
Peak memory 201448 kb
Host smart-53563c07-ff6c-4144-9dc3-6a24d1a612eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365720883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.365720883
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2293915414
Short name T117
Test name
Test status
Simulation time 101231948 ps
CPU time 1.74 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 209076 kb
Host smart-e9e03707-5b88-4a84-9064-e053f7ace442
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293915414 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2293915414
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.2273880649
Short name T25
Test name
Test status
Simulation time 17156294 ps
CPU time 0.79 seconds
Started Jul 30 06:24:46 PM PDT 24
Finished Jul 30 06:24:47 PM PDT 24
Peak memory 201120 kb
Host smart-48a5b314-c66e-4f32-9edd-77cf340dff18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273880649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.2273880649
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.1007338414
Short name T144
Test name
Test status
Simulation time 46047161702 ps
CPU time 286.17 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:30:13 PM PDT 24
Peak memory 209812 kb
Host smart-79173207-c8e7-4b3a-b657-f43dd30a90ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1007338414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.1007338414
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.1818178375
Short name T4
Test name
Test status
Simulation time 958256081 ps
CPU time 4.43 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201232 kb
Host smart-a81cece1-d501-46e2-863d-f8ce56a811e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818178375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1818178375
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1343111762
Short name T115
Test name
Test status
Simulation time 231906532 ps
CPU time 2.07 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 216904 kb
Host smart-4c5603ce-6e10-4f12-885d-825646af9049
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343111762 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.1343111762
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.2662167114
Short name T8
Test name
Test status
Simulation time 1098117999 ps
CPU time 6.46 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:23 PM PDT 24
Peak memory 201332 kb
Host smart-f4b4bbad-7954-4e55-9ea7-f58f8d1c89ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662167114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2662167114
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.154967009
Short name T92
Test name
Test status
Simulation time 225873513 ps
CPU time 2.49 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200528 kb
Host smart-6f001de7-0857-4f05-8b02-7f0970a991b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154967009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_tl_intg_err.154967009
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2489721191
Short name T76
Test name
Test status
Simulation time 291936217 ps
CPU time 1.72 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201164 kb
Host smart-1fdde129-4ad7-462d-99af-c951d9c9b023
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489721191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.2489721191
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1251503214
Short name T116
Test name
Test status
Simulation time 221521652 ps
CPU time 1.52 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200568 kb
Host smart-8ec1bdd5-836d-4c9f-a041-25ab8e125e5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251503214 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1251503214
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1039791018
Short name T112
Test name
Test status
Simulation time 90199047 ps
CPU time 1.36 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:21 PM PDT 24
Peak memory 200656 kb
Host smart-6e09e5c6-21b4-4dcc-85c4-26831e5acd6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039791018 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.1039791018
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.3972810645
Short name T86
Test name
Test status
Simulation time 89879858 ps
CPU time 1.55 seconds
Started Jul 30 06:43:10 PM PDT 24
Finished Jul 30 06:43:12 PM PDT 24
Peak memory 200556 kb
Host smart-22e03e4a-a234-44f7-99b4-5ef7f6352e56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972810645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.3972810645
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.667604125
Short name T96
Test name
Test status
Simulation time 56281081 ps
CPU time 1.5 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200588 kb
Host smart-63a13f3c-db3f-43a6-99c4-7399d5f1fcbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667604125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.667604125
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.223663935
Short name T95
Test name
Test status
Simulation time 285315473 ps
CPU time 2.71 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200544 kb
Host smart-6e339fd9-8c98-459f-803f-adcd3bad486d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223663935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_tl_intg_err.223663935
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.558631224
Short name T64
Test name
Test status
Simulation time 20350228 ps
CPU time 1.08 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200372 kb
Host smart-4598c3e1-8d63-4e97-802c-6f74b31b6939
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558631224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_aliasing.558631224
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.1252306432
Short name T836
Test name
Test status
Simulation time 882875742 ps
CPU time 6.01 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200572 kb
Host smart-da4ab08a-0f6a-43c7-8135-0ac30613aee8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252306432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.1252306432
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.261848754
Short name T885
Test name
Test status
Simulation time 17577937 ps
CPU time 0.8 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200388 kb
Host smart-2bb5e858-cd7c-4cdc-96f6-e494b5d64042
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261848754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_hw_reset.261848754
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.932315915
Short name T859
Test name
Test status
Simulation time 21234790 ps
CPU time 0.92 seconds
Started Jul 30 06:43:10 PM PDT 24
Finished Jul 30 06:43:11 PM PDT 24
Peak memory 200456 kb
Host smart-7d1d4b21-40ba-470a-ba03-53c8fa9b06c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932315915 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.932315915
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.4081179659
Short name T964
Test name
Test status
Simulation time 38966782 ps
CPU time 0.78 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:21 PM PDT 24
Peak memory 200268 kb
Host smart-7f102374-a6ee-4d18-a0ce-7d1947b42369
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081179659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.4081179659
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.130330856
Short name T866
Test name
Test status
Simulation time 13099433 ps
CPU time 0.7 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 198960 kb
Host smart-315d5c5f-68ad-49ec-ac0e-11c5235bc51b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130330856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm
gr_intr_test.130330856
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1334636567
Short name T879
Test name
Test status
Simulation time 30451954 ps
CPU time 1.03 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200372 kb
Host smart-f59f548e-8862-4f9f-a37a-5ebfa7272e1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334636567 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1334636567
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3043994230
Short name T121
Test name
Test status
Simulation time 390943531 ps
CPU time 2.55 seconds
Started Jul 30 06:43:12 PM PDT 24
Finished Jul 30 06:43:15 PM PDT 24
Peak memory 209096 kb
Host smart-1e2bb1f9-1fa2-4473-b6de-8b5c11a5b996
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043994230 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.3043994230
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3077281012
Short name T108
Test name
Test status
Simulation time 87825948 ps
CPU time 1.62 seconds
Started Jul 30 06:43:18 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 217080 kb
Host smart-02c3e160-633a-4bd9-a932-40b7e469b156
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077281012 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3077281012
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2801881376
Short name T952
Test name
Test status
Simulation time 39559409 ps
CPU time 2.32 seconds
Started Jul 30 06:43:11 PM PDT 24
Finished Jul 30 06:43:13 PM PDT 24
Peak memory 200500 kb
Host smart-01600395-3d65-4b9b-a67d-ca89ee3f97ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801881376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2801881376
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3461897952
Short name T849
Test name
Test status
Simulation time 274519061 ps
CPU time 2.45 seconds
Started Jul 30 06:43:15 PM PDT 24
Finished Jul 30 06:43:18 PM PDT 24
Peak memory 200512 kb
Host smart-51361454-a5f9-4e7d-823b-37a46f4c03bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461897952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.3461897952
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.416756986
Short name T974
Test name
Test status
Simulation time 536410073 ps
CPU time 8.29 seconds
Started Jul 30 06:43:13 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200504 kb
Host smart-18f4ad24-3ab3-4401-8e35-1c1cbaaa69d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416756986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_bit_bash.416756986
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2307426961
Short name T897
Test name
Test status
Simulation time 103406000 ps
CPU time 0.95 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200364 kb
Host smart-b7c5f94f-20b8-44ce-a26f-dc8b845663a9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307426961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2307426961
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1613231135
Short name T89
Test name
Test status
Simulation time 38754144 ps
CPU time 1.17 seconds
Started Jul 30 06:43:15 PM PDT 24
Finished Jul 30 06:43:17 PM PDT 24
Peak memory 200468 kb
Host smart-df193cef-70b3-4310-aad9-aa40d9f2d009
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613231135 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.1613231135
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1285704909
Short name T918
Test name
Test status
Simulation time 34623579 ps
CPU time 0.87 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200348 kb
Host smart-85a5550a-e555-4303-b889-788c837f0383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285704909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.1285704909
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.3251100462
Short name T923
Test name
Test status
Simulation time 10967713 ps
CPU time 0.66 seconds
Started Jul 30 06:43:07 PM PDT 24
Finished Jul 30 06:43:07 PM PDT 24
Peak memory 198956 kb
Host smart-b3ec9dde-8c41-46d6-939f-19c68eab4fe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251100462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.3251100462
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.394578884
Short name T899
Test name
Test status
Simulation time 54539676 ps
CPU time 1.36 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200480 kb
Host smart-7ae11a53-be38-4f11-bb65-fa51e8dfd17b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394578884 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.clkmgr_same_csr_outstanding.394578884
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.56176452
Short name T118
Test name
Test status
Simulation time 766493420 ps
CPU time 3.15 seconds
Started Jul 30 06:43:06 PM PDT 24
Finished Jul 30 06:43:09 PM PDT 24
Peak memory 200824 kb
Host smart-4623c958-3da8-48ac-8de0-70d1596aa9b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56176452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.clkmgr_shadow_reg_errors.56176452
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.352151155
Short name T126
Test name
Test status
Simulation time 233721445 ps
CPU time 2.08 seconds
Started Jul 30 06:43:12 PM PDT 24
Finished Jul 30 06:43:14 PM PDT 24
Peak memory 209052 kb
Host smart-182e5384-5a44-48cb-8c5f-e9cf04fd3a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352151155 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.352151155
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.31112866
Short name T898
Test name
Test status
Simulation time 39737286 ps
CPU time 2.44 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200524 kb
Host smart-9d89ed29-fff3-4a4c-87aa-7c47b3b6fba1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmg
r_tl_errors.31112866
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.248714283
Short name T94
Test name
Test status
Simulation time 353985300 ps
CPU time 3.12 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200612 kb
Host smart-a1115033-e817-4020-a47c-d7bce5ca0e71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248714283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_tl_intg_err.248714283
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.1784955461
Short name T860
Test name
Test status
Simulation time 255044382 ps
CPU time 1.53 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200432 kb
Host smart-5fd9eae1-0d19-48fd-999a-46bfac3d79bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784955461 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.1784955461
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3355258160
Short name T915
Test name
Test status
Simulation time 18041890 ps
CPU time 0.76 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200300 kb
Host smart-cf30206b-6a16-40b0-838b-2f258e84ea50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355258160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3355258160
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.2631786783
Short name T839
Test name
Test status
Simulation time 36106510 ps
CPU time 0.7 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 198744 kb
Host smart-ff357363-22e8-4575-897f-b45605801b27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631786783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.2631786783
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.494784796
Short name T67
Test name
Test status
Simulation time 114154442 ps
CPU time 1.26 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200368 kb
Host smart-2a2ce328-71ae-493b-bdaf-7a391818a633
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494784796 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.494784796
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3362538730
Short name T52
Test name
Test status
Simulation time 92789728 ps
CPU time 1.97 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 208980 kb
Host smart-ae8bcdcc-0128-435b-a469-0b7124dcd073
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362538730 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3362538730
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.418763631
Short name T924
Test name
Test status
Simulation time 139157549 ps
CPU time 2.48 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:43:40 PM PDT 24
Peak memory 200372 kb
Host smart-d7f2b978-38af-4bec-99ff-ea753109a2fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418763631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_tl_errors.418763631
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.297373160
Short name T977
Test name
Test status
Simulation time 155801391 ps
CPU time 1.61 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200644 kb
Host smart-1d182527-3f9c-4a1b-b460-06a14c5afdcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297373160 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.297373160
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.541032034
Short name T878
Test name
Test status
Simulation time 82486916 ps
CPU time 1.04 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200372 kb
Host smart-6faa4aff-3fd6-4903-a225-e77c6725d5b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541032034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
clkmgr_csr_rw.541032034
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.500137248
Short name T845
Test name
Test status
Simulation time 13350703 ps
CPU time 0.68 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 198932 kb
Host smart-de87d90d-0e0f-4dfe-9427-06ceee3d279c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500137248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk
mgr_intr_test.500137248
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3852591436
Short name T66
Test name
Test status
Simulation time 56899125 ps
CPU time 1.04 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 200376 kb
Host smart-1fb0d87f-f402-4633-8095-17fffec3e90b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852591436 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3852591436
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.3849012025
Short name T954
Test name
Test status
Simulation time 128609944 ps
CPU time 2.13 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200904 kb
Host smart-777e7dd6-395c-4e42-b373-88b7cab9a5d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849012025 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.3849012025
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.2082013469
Short name T53
Test name
Test status
Simulation time 982309524 ps
CPU time 4.74 seconds
Started Jul 30 06:43:14 PM PDT 24
Finished Jul 30 06:43:19 PM PDT 24
Peak memory 208988 kb
Host smart-7a570f69-c01a-4a56-8e51-ccd04355db0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082013469 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.2082013469
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3149413623
Short name T900
Test name
Test status
Simulation time 295397128 ps
CPU time 2.64 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 200380 kb
Host smart-aac96f0d-ad74-4283-9d20-2dec54bcca8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149413623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.3149413623
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1800854773
Short name T85
Test name
Test status
Simulation time 172357546 ps
CPU time 1.82 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200540 kb
Host smart-1719c4c6-7daa-4f36-83f6-82f6b1d0c7e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800854773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1800854773
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.519225693
Short name T965
Test name
Test status
Simulation time 95904318 ps
CPU time 1.16 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200428 kb
Host smart-b428f631-c888-4535-acfa-02b10378eedb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519225693 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.519225693
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1579843979
Short name T871
Test name
Test status
Simulation time 52178085 ps
CPU time 0.88 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 200264 kb
Host smart-37b78ae4-c015-46bc-af03-93da3317dee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579843979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.1579843979
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.873228386
Short name T931
Test name
Test status
Simulation time 36382653 ps
CPU time 0.72 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:33 PM PDT 24
Peak memory 199056 kb
Host smart-6ff74044-78c8-415a-9f08-132aee92fc7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873228386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.873228386
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3430461534
Short name T68
Test name
Test status
Simulation time 141533772 ps
CPU time 1.29 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200376 kb
Host smart-4c5054a9-0ac7-4446-84b8-2c39608c4f93
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430461534 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.3430461534
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3434338082
Short name T919
Test name
Test status
Simulation time 108387216 ps
CPU time 1.91 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200568 kb
Host smart-ecd4f88e-3a20-43ed-9eb8-afee333021db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434338082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3434338082
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1894630367
Short name T152
Test name
Test status
Simulation time 236562096 ps
CPU time 2.09 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200480 kb
Host smart-48cbd8e8-a917-4fcf-99d8-9cccff98a5aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894630367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1894630367
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3144569224
Short name T841
Test name
Test status
Simulation time 66287744 ps
CPU time 1.32 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200504 kb
Host smart-4b53f325-74e0-4a55-aec5-e56c2bc0becb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144569224 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3144569224
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.997573031
Short name T938
Test name
Test status
Simulation time 20324072 ps
CPU time 0.87 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200300 kb
Host smart-1502220f-847b-4b2c-b7c0-a78f9e29c6fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997573031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.997573031
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1600484627
Short name T862
Test name
Test status
Simulation time 14928629 ps
CPU time 0.68 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 199112 kb
Host smart-e6dd1b78-c7cf-48a1-8f56-c964c565b111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600484627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.1600484627
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1542276298
Short name T864
Test name
Test status
Simulation time 351449051 ps
CPU time 1.75 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200288 kb
Host smart-7199f551-ed9d-4aa0-bfce-cc8667f0027d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542276298 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.1542276298
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1062679040
Short name T956
Test name
Test status
Simulation time 177994088 ps
CPU time 3.15 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 209032 kb
Host smart-1290bd3c-9331-45be-8b31-7bcf040725fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062679040 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1062679040
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.816302920
Short name T872
Test name
Test status
Simulation time 43743679 ps
CPU time 2.62 seconds
Started Jul 30 06:43:37 PM PDT 24
Finished Jul 30 06:43:45 PM PDT 24
Peak memory 200560 kb
Host smart-4896896e-03d6-4dcc-85b4-238e30cd64ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816302920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_tl_errors.816302920
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3400570008
Short name T83
Test name
Test status
Simulation time 293034407 ps
CPU time 3.19 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200536 kb
Host smart-c41c08af-606e-431a-b6c4-fea16cf813a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400570008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.3400570008
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.4289022797
Short name T882
Test name
Test status
Simulation time 76727804 ps
CPU time 1.53 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 200684 kb
Host smart-17945645-29d2-4413-b240-0cb522e9e2cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289022797 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.4289022797
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1245451323
Short name T852
Test name
Test status
Simulation time 21525213 ps
CPU time 0.83 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200548 kb
Host smart-58c871e0-ded8-4a26-8187-a2b187b1d201
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245451323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1245451323
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2392138267
Short name T913
Test name
Test status
Simulation time 40315988 ps
CPU time 0.74 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 198952 kb
Host smart-7d0fe028-50a3-4701-9b7a-e465d53af64b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392138267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2392138267
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.432660391
Short name T929
Test name
Test status
Simulation time 89493937 ps
CPU time 1.24 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200420 kb
Host smart-c6b3c2c1-a203-44ae-adfd-1ec3878202a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432660391 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 14.clkmgr_same_csr_outstanding.432660391
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3202219632
Short name T109
Test name
Test status
Simulation time 78009481 ps
CPU time 1.45 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200660 kb
Host smart-76198c15-d2aa-4e6b-8540-786c6d611c48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202219632 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.3202219632
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1980475141
Short name T47
Test name
Test status
Simulation time 144820810 ps
CPU time 3.01 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 201100 kb
Host smart-0f642dc2-4467-4d3e-bd22-d1502290f89a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980475141 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1980475141
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.1609509516
Short name T848
Test name
Test status
Simulation time 138568093 ps
CPU time 2.79 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200544 kb
Host smart-1f26edb7-93aa-4814-a199-c7561f7d4639
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609509516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.1609509516
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1626251532
Short name T91
Test name
Test status
Simulation time 82578147 ps
CPU time 1.89 seconds
Started Jul 30 06:43:42 PM PDT 24
Finished Jul 30 06:43:44 PM PDT 24
Peak memory 200576 kb
Host smart-00337cf4-41c3-408b-99a8-98611c3d1630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626251532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1626251532
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1735753092
Short name T865
Test name
Test status
Simulation time 114949810 ps
CPU time 1.45 seconds
Started Jul 30 06:43:38 PM PDT 24
Finished Jul 30 06:43:40 PM PDT 24
Peak memory 200476 kb
Host smart-ff793e15-564a-4d20-8126-bdc78c750010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735753092 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.1735753092
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1604539121
Short name T868
Test name
Test status
Simulation time 15752659 ps
CPU time 0.76 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 200348 kb
Host smart-99942708-9e42-4327-976b-90bf7fdf8527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604539121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1604539121
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2325582357
Short name T883
Test name
Test status
Simulation time 41728728 ps
CPU time 0.69 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 199052 kb
Host smart-5559d44a-8f47-4237-b8ff-15d0ece24633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325582357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2325582357
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3413816137
Short name T975
Test name
Test status
Simulation time 24959167 ps
CPU time 0.99 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200336 kb
Host smart-304fbb5f-1a98-4078-b9fc-e5c999993ddf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413816137 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.3413816137
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3298515571
Short name T114
Test name
Test status
Simulation time 77827809 ps
CPU time 1.42 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200672 kb
Host smart-82048c99-f775-4af1-93d2-e568bafc0ef7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298515571 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3298515571
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.764092876
Short name T951
Test name
Test status
Simulation time 80119866 ps
CPU time 1.74 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200964 kb
Host smart-139583ef-17d8-41a9-a363-6a684e5835d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764092876 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.764092876
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.917557408
Short name T881
Test name
Test status
Simulation time 126879826 ps
CPU time 3.68 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200508 kb
Host smart-b037d13f-2157-431b-943e-d045d48a196b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917557408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk
mgr_tl_errors.917557408
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1272991736
Short name T960
Test name
Test status
Simulation time 58526152 ps
CPU time 1.41 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200360 kb
Host smart-00e66f78-ebdc-439f-84ad-20c5a850cdce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272991736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1272991736
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3861462086
Short name T926
Test name
Test status
Simulation time 46225270 ps
CPU time 1.34 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200472 kb
Host smart-8e87bb18-3afe-4db6-904a-dd6cccaf29ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861462086 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3861462086
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1780746800
Short name T909
Test name
Test status
Simulation time 46029130 ps
CPU time 0.84 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200180 kb
Host smart-47471bf0-521a-493b-a4ed-64b6b79ad721
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780746800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1780746800
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2312615989
Short name T843
Test name
Test status
Simulation time 41396523 ps
CPU time 0.72 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 199048 kb
Host smart-27b65a9f-d7d3-45cb-87ef-a60a64714dba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312615989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2312615989
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2043080683
Short name T903
Test name
Test status
Simulation time 170540149 ps
CPU time 1.4 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200400 kb
Host smart-c49c9493-2317-4ae9-8ab2-1948020d6fbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043080683 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2043080683
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.3341550681
Short name T48
Test name
Test status
Simulation time 56177122 ps
CPU time 1.26 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 200416 kb
Host smart-5a4ac1c3-ff43-4b6b-aa91-008c2e681f42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341550681 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.3341550681
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3534647458
Short name T110
Test name
Test status
Simulation time 68986302 ps
CPU time 1.79 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 209076 kb
Host smart-9066bbe1-1d4f-40c9-9598-cc3ee7aadb63
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534647458 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3534647458
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2550347358
Short name T863
Test name
Test status
Simulation time 1136766053 ps
CPU time 4.93 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:33 PM PDT 24
Peak memory 200480 kb
Host smart-85a1d65a-2ecd-49ee-b5ad-03d9d8f88e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550347358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2550347358
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2032323104
Short name T944
Test name
Test status
Simulation time 378414373 ps
CPU time 3.17 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 200552 kb
Host smart-6af1562f-9479-402b-bdd8-99af119d6da7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032323104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.2032323104
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1617497925
Short name T976
Test name
Test status
Simulation time 145463687 ps
CPU time 1.62 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200476 kb
Host smart-c2ca6fb8-c391-4f4f-a0d6-eef59d10af32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617497925 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.1617497925
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.650456010
Short name T855
Test name
Test status
Simulation time 15183831 ps
CPU time 0.75 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200388 kb
Host smart-cba98705-5085-464b-81b2-a590399cf934
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650456010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
clkmgr_csr_rw.650456010
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1836909782
Short name T908
Test name
Test status
Simulation time 26246726 ps
CPU time 0.68 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 199024 kb
Host smart-db716bb8-2faa-4e7f-902a-09300b83ef18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836909782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.1836909782
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.390062177
Short name T904
Test name
Test status
Simulation time 39093003 ps
CPU time 1.26 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200572 kb
Host smart-f2ae09ed-6b20-468b-a81d-cf181e4008e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390062177 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 17.clkmgr_same_csr_outstanding.390062177
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2128317717
Short name T105
Test name
Test status
Simulation time 174185752 ps
CPU time 1.49 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200664 kb
Host smart-730dbbcb-cc55-4057-bea6-65a0fdaa3fad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128317717 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.2128317717
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2885613136
Short name T967
Test name
Test status
Simulation time 91121732 ps
CPU time 1.83 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 209012 kb
Host smart-d14fbaeb-6cc8-42b5-ac14-6557f822deee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885613136 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.2885613136
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.1438100057
Short name T889
Test name
Test status
Simulation time 89732213 ps
CPU time 2.86 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200500 kb
Host smart-5f0a4837-a6b4-4266-990f-367b6cd1971f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438100057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.1438100057
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.237630543
Short name T870
Test name
Test status
Simulation time 132346135 ps
CPU time 1.51 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200500 kb
Host smart-9592fbad-8cf5-4abc-9c0c-db226500cd71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237630543 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.237630543
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.932097667
Short name T854
Test name
Test status
Simulation time 16552173 ps
CPU time 0.8 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 200312 kb
Host smart-ee844ad6-b73b-4dc0-935e-e416cf10f98d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932097667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
clkmgr_csr_rw.932097667
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.829110557
Short name T920
Test name
Test status
Simulation time 24916808 ps
CPU time 0.7 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 198972 kb
Host smart-80519aea-1eeb-4e77-bcb0-b6d0fc951233
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829110557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.829110557
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3400578827
Short name T884
Test name
Test status
Simulation time 86982090 ps
CPU time 1.15 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 200380 kb
Host smart-6cc13e94-3811-4476-ac33-d193df4b3fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400578827 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.3400578827
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1911804635
Short name T44
Test name
Test status
Simulation time 60980961 ps
CPU time 1.31 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200508 kb
Host smart-1e9d8f77-aa46-46b6-b24a-f7aa3ffbacf2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911804635 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.1911804635
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3765677377
Short name T51
Test name
Test status
Simulation time 266953693 ps
CPU time 3.38 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 209036 kb
Host smart-cd9b20b1-6815-4f5f-9b6c-540dfc43d285
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765677377 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3765677377
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.2206894147
Short name T867
Test name
Test status
Simulation time 122580825 ps
CPU time 2.19 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200516 kb
Host smart-35889229-4187-49aa-ab77-7be3b4351d76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206894147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.2206894147
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.4230026443
Short name T88
Test name
Test status
Simulation time 109433154 ps
CPU time 2.54 seconds
Started Jul 30 06:43:37 PM PDT 24
Finished Jul 30 06:43:40 PM PDT 24
Peak memory 200604 kb
Host smart-672f3d9b-792b-4137-afbe-435c9c41a74c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230026443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.4230026443
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3412512477
Short name T886
Test name
Test status
Simulation time 26136742 ps
CPU time 1.47 seconds
Started Jul 30 06:44:19 PM PDT 24
Finished Jul 30 06:44:23 PM PDT 24
Peak memory 199456 kb
Host smart-b2ffe57c-ae1d-4288-ae3c-772321687a52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412512477 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3412512477
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.3928015142
Short name T933
Test name
Test status
Simulation time 29783609 ps
CPU time 0.86 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200340 kb
Host smart-a55df34c-0066-4d37-854a-8702457095bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928015142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.3928015142
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.827398595
Short name T922
Test name
Test status
Simulation time 22174574 ps
CPU time 0.78 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 199016 kb
Host smart-66163218-937a-4379-ab6b-a19a4534b3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827398595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_intr_test.827398595
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.892651997
Short name T850
Test name
Test status
Simulation time 100407844 ps
CPU time 1.53 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200544 kb
Host smart-98b83b05-55da-42d5-9749-a7c66129c5b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892651997 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.clkmgr_same_csr_outstanding.892651997
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2574476367
Short name T107
Test name
Test status
Simulation time 292108031 ps
CPU time 2.34 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200764 kb
Host smart-2521c680-7356-4837-9af1-2607b8786eb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574476367 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2574476367
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.3632275351
Short name T893
Test name
Test status
Simulation time 523373215 ps
CPU time 3.77 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 200492 kb
Host smart-faae787f-c8d4-4c4f-a38f-30aea16ae7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632275351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.3632275351
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.726725869
Short name T914
Test name
Test status
Simulation time 193623111 ps
CPU time 1.9 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 200192 kb
Host smart-d3f93302-3c20-4dbc-aca0-8c725b3335fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726725869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.726725869
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3268793421
Short name T892
Test name
Test status
Simulation time 27298108 ps
CPU time 1.38 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 200452 kb
Host smart-0e97793e-8c1b-485e-abda-e9ac1b1932a8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268793421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.3268793421
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1977669980
Short name T957
Test name
Test status
Simulation time 223022632 ps
CPU time 4.29 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200600 kb
Host smart-fd559454-f66c-4dc2-92e1-50b0be671a53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977669980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.1977669980
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.225255146
Short name T880
Test name
Test status
Simulation time 61441123 ps
CPU time 0.88 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200324 kb
Host smart-255f1f1e-220a-478d-96c2-8c5cc91d76d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225255146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_hw_reset.225255146
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.4147807140
Short name T876
Test name
Test status
Simulation time 40265993 ps
CPU time 1.95 seconds
Started Jul 30 06:43:11 PM PDT 24
Finished Jul 30 06:43:13 PM PDT 24
Peak memory 208860 kb
Host smart-6b5ac6d6-cbcd-4742-a824-0fba3a39f8b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147807140 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.4147807140
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.4150633031
Short name T902
Test name
Test status
Simulation time 30329344 ps
CPU time 0.85 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200336 kb
Host smart-90ae2ba8-dcc3-4985-ae24-c3563421f87c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150633031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.4150633031
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.618166900
Short name T887
Test name
Test status
Simulation time 14099744 ps
CPU time 0.67 seconds
Started Jul 30 06:43:12 PM PDT 24
Finished Jul 30 06:43:13 PM PDT 24
Peak memory 199012 kb
Host smart-a2ceffec-dab5-4052-8d1e-7f467b359248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618166900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.618166900
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.1290637239
Short name T840
Test name
Test status
Simulation time 102946497 ps
CPU time 1.21 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200392 kb
Host smart-1fdac8df-f3c6-43b7-95c8-b5d9d4dcbc0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290637239 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.1290637239
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.947141315
Short name T124
Test name
Test status
Simulation time 1463885984 ps
CPU time 5.85 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 209016 kb
Host smart-2ddfaf03-9ab6-4963-9c06-5c6026743909
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947141315 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.947141315
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.4089741848
Short name T961
Test name
Test status
Simulation time 137560871 ps
CPU time 2.01 seconds
Started Jul 30 06:43:10 PM PDT 24
Finished Jul 30 06:43:12 PM PDT 24
Peak memory 200516 kb
Host smart-473b90db-0523-4970-b08e-09ed5fd1d5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089741848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.4089741848
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1784178653
Short name T945
Test name
Test status
Simulation time 133829946 ps
CPU time 2.79 seconds
Started Jul 30 06:43:15 PM PDT 24
Finished Jul 30 06:43:18 PM PDT 24
Peak memory 200624 kb
Host smart-e028ea1d-aab4-4ccf-9bf9-fdebcf0b07c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784178653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1784178653
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.288396907
Short name T869
Test name
Test status
Simulation time 16009858 ps
CPU time 0.69 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 198948 kb
Host smart-86faf289-3d5b-49a8-be91-c50ab59a22b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288396907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clk
mgr_intr_test.288396907
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.2521491048
Short name T959
Test name
Test status
Simulation time 24581393 ps
CPU time 0.75 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 199000 kb
Host smart-a0397ac5-52b0-409a-b62d-bf165874d0ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521491048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.2521491048
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3539136178
Short name T971
Test name
Test status
Simulation time 32338800 ps
CPU time 0.68 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 199024 kb
Host smart-ed2551a2-cca1-4450-b2c3-e47f7fb8d0b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539136178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.3539136178
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.39060142
Short name T970
Test name
Test status
Simulation time 37626026 ps
CPU time 0.73 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 199040 kb
Host smart-98af1ecf-8dd6-493f-90e5-f9fb1e14d130
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39060142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkm
gr_intr_test.39060142
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.572239005
Short name T917
Test name
Test status
Simulation time 22971030 ps
CPU time 0.72 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 198944 kb
Host smart-6cc1de35-c618-4281-9661-663adc2dc7d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572239005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.572239005
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2746790738
Short name T858
Test name
Test status
Simulation time 17586704 ps
CPU time 0.67 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 199088 kb
Host smart-c9165e45-eb63-4679-acb8-73be4e7b9065
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746790738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2746790738
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1361962958
Short name T978
Test name
Test status
Simulation time 23241076 ps
CPU time 0.68 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 199156 kb
Host smart-821e6544-61e4-4bf1-bae3-873dc576ed57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361962958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1361962958
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1499218159
Short name T861
Test name
Test status
Simulation time 83060918 ps
CPU time 0.88 seconds
Started Jul 30 06:43:36 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 198964 kb
Host smart-0de293c0-102a-4275-aeba-4e3053ba5457
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499218159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1499218159
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2838550762
Short name T894
Test name
Test status
Simulation time 22224989 ps
CPU time 0.7 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 199076 kb
Host smart-40e4996a-4307-49b6-8c9f-f8f0ab6081ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838550762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.2838550762
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3810776412
Short name T832
Test name
Test status
Simulation time 12976866 ps
CPU time 0.64 seconds
Started Jul 30 06:44:38 PM PDT 24
Finished Jul 30 06:44:38 PM PDT 24
Peak memory 198720 kb
Host smart-39ad4ad2-28db-4751-ab0d-c49dea00ed2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810776412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3810776412
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.991223970
Short name T911
Test name
Test status
Simulation time 246681379 ps
CPU time 2.27 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200580 kb
Host smart-62057394-94ec-4845-bc39-f45b39bf91e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991223970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_aliasing.991223970
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.268494088
Short name T905
Test name
Test status
Simulation time 144523524 ps
CPU time 3.76 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200600 kb
Host smart-f5ad9cdb-c2a2-4f7f-8818-04295e4c9541
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268494088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.268494088
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2271806642
Short name T966
Test name
Test status
Simulation time 18430957 ps
CPU time 0.81 seconds
Started Jul 30 06:43:35 PM PDT 24
Finished Jul 30 06:43:36 PM PDT 24
Peak memory 200352 kb
Host smart-348882f5-0664-4abb-9df4-6ca7d0cf5613
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271806642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2271806642
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.1845953318
Short name T932
Test name
Test status
Simulation time 237594378 ps
CPU time 2.02 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200624 kb
Host smart-3f20cbc4-9e76-4c59-befb-2aeed57727b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845953318 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.1845953318
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2062092953
Short name T901
Test name
Test status
Simulation time 19052440 ps
CPU time 0.76 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200304 kb
Host smart-213f0920-4fcb-4b33-ac14-775676604645
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062092953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.2062092953
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.905103551
Short name T895
Test name
Test status
Simulation time 12950720 ps
CPU time 0.65 seconds
Started Jul 30 06:43:18 PM PDT 24
Finished Jul 30 06:43:19 PM PDT 24
Peak memory 198940 kb
Host smart-19ede117-124a-4a85-81c5-f3844be8c3db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905103551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_intr_test.905103551
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.4086282458
Short name T70
Test name
Test status
Simulation time 112481320 ps
CPU time 1.23 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200352 kb
Host smart-cc8e6a0c-8d31-47e3-a695-dc9eaef05d4d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086282458 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.4086282458
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3467480157
Short name T122
Test name
Test status
Simulation time 91863045 ps
CPU time 1.33 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200632 kb
Host smart-c84ffafb-8305-41b5-98d2-63ad3952df45
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467480157 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3467480157
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.220457195
Short name T111
Test name
Test status
Simulation time 95494693 ps
CPU time 2.46 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 208964 kb
Host smart-297623bb-0a4e-4aae-bd1e-84f857b53b2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220457195 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.220457195
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.4209118548
Short name T847
Test name
Test status
Simulation time 446485117 ps
CPU time 4.04 seconds
Started Jul 30 06:43:29 PM PDT 24
Finished Jul 30 06:43:39 PM PDT 24
Peak memory 200576 kb
Host smart-aa683fd2-e634-4d3f-acec-fc4ef34a7e0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209118548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.4209118548
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3559708968
Short name T972
Test name
Test status
Simulation time 249474965 ps
CPU time 2.09 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200584 kb
Host smart-7e7fc003-948a-465f-bc86-939327118e70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559708968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.3559708968
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3140705896
Short name T888
Test name
Test status
Simulation time 37285740 ps
CPU time 0.77 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 198984 kb
Host smart-fee75ee8-f878-4ca3-bc2d-28c81a966402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140705896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3140705896
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.3340789945
Short name T934
Test name
Test status
Simulation time 14352849 ps
CPU time 0.72 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 199060 kb
Host smart-a5137275-121d-4e12-a3e6-fca7a1e1d7c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340789945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.3340789945
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3945061820
Short name T935
Test name
Test status
Simulation time 12641213 ps
CPU time 0.67 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:21 PM PDT 24
Peak memory 199072 kb
Host smart-9873fbc3-e48b-47b6-873d-56fda16cfcbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945061820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.3945061820
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3790767826
Short name T969
Test name
Test status
Simulation time 12984989 ps
CPU time 0.66 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 199020 kb
Host smart-cc1382c4-aa59-4a2b-b9af-aad1bf748f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790767826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.3790767826
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.4227849898
Short name T838
Test name
Test status
Simulation time 11784505 ps
CPU time 0.69 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 199004 kb
Host smart-b47a136f-a1a2-4bfc-aca1-cf60e6c8e4e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227849898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.4227849898
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2559116334
Short name T946
Test name
Test status
Simulation time 46070576 ps
CPU time 0.75 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:33 PM PDT 24
Peak memory 198960 kb
Host smart-8f42b035-1a75-44b5-b2f0-897aed68da5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559116334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.2559116334
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4259664317
Short name T891
Test name
Test status
Simulation time 36754334 ps
CPU time 0.74 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 198928 kb
Host smart-c84c2e7b-2755-4a32-ba4d-627570379291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259664317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.4259664317
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.212142469
Short name T979
Test name
Test status
Simulation time 15530429 ps
CPU time 0.65 seconds
Started Jul 30 06:43:43 PM PDT 24
Finished Jul 30 06:43:44 PM PDT 24
Peak memory 198804 kb
Host smart-46837f90-2f05-46f1-95e2-2970d5d4d25d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212142469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.212142469
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2906971046
Short name T953
Test name
Test status
Simulation time 12559475 ps
CPU time 0.68 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 198924 kb
Host smart-e7d30412-e853-4083-a671-6d061d50b2d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906971046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2906971046
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3134738218
Short name T856
Test name
Test status
Simulation time 28870671 ps
CPU time 0.68 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 198944 kb
Host smart-f33ea314-2e51-48e2-ab57-261f9e7e9c1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134738218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.3134738218
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1023257156
Short name T930
Test name
Test status
Simulation time 354835167 ps
CPU time 2.53 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200644 kb
Host smart-db350a9c-b922-4654-b12f-f1907d51dee8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023257156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1023257156
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1996007926
Short name T948
Test name
Test status
Simulation time 679557234 ps
CPU time 5.11 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200456 kb
Host smart-014c7c8e-c79f-4fa9-b207-2170654fc0b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996007926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1996007926
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.380648874
Short name T896
Test name
Test status
Simulation time 54357688 ps
CPU time 0.95 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200352 kb
Host smart-1a873524-7aad-46fb-975b-2738d3cd901c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380648874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.380648874
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1405988682
Short name T873
Test name
Test status
Simulation time 139210772 ps
CPU time 1.38 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 200392 kb
Host smart-c2f96e37-ae0b-450e-a688-36c37d05238a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405988682 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1405988682
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3060427644
Short name T846
Test name
Test status
Simulation time 45890631 ps
CPU time 0.8 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200380 kb
Host smart-6b560738-4a3a-4720-8913-52a2cebff17c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060427644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3060427644
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.4192998590
Short name T835
Test name
Test status
Simulation time 21136224 ps
CPU time 0.69 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 199012 kb
Host smart-143ee0db-de02-428e-863b-5d55c3a9e608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192998590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.4192998590
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.2040856313
Short name T947
Test name
Test status
Simulation time 38223164 ps
CPU time 1.15 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200424 kb
Host smart-768c496e-91e8-4d25-8d56-d5cc1ed4906f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040856313 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.2040856313
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.251604705
Short name T980
Test name
Test status
Simulation time 174036881 ps
CPU time 1.6 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200628 kb
Host smart-f78028ba-0436-4441-ba74-e0e8eb175bd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251604705 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.251604705
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.343913954
Short name T937
Test name
Test status
Simulation time 551586792 ps
CPU time 4.27 seconds
Started Jul 30 06:43:18 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 209032 kb
Host smart-fdc9d866-0197-4284-9379-4ec2a98c476f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343913954 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.343913954
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2165900868
Short name T973
Test name
Test status
Simulation time 43840071 ps
CPU time 1.5 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200532 kb
Host smart-479536ed-548e-4526-9af6-234dd8b4b7a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165900868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.2165900868
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.666554465
Short name T875
Test name
Test status
Simulation time 68392542 ps
CPU time 0.78 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 199036 kb
Host smart-01659416-6560-460a-a84c-c6f07e0babcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666554465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.666554465
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2522057961
Short name T837
Test name
Test status
Simulation time 34913228 ps
CPU time 0.7 seconds
Started Jul 30 06:43:42 PM PDT 24
Finished Jul 30 06:43:43 PM PDT 24
Peak memory 198700 kb
Host smart-1d7a2542-389b-40d1-8379-4a6e028a99bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522057961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2522057961
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3184981648
Short name T928
Test name
Test status
Simulation time 12265049 ps
CPU time 0.64 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 198948 kb
Host smart-2f6fc391-9a8f-4a3a-a277-ab0b91b099f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184981648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.3184981648
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2104102251
Short name T844
Test name
Test status
Simulation time 25937781 ps
CPU time 0.67 seconds
Started Jul 30 06:43:40 PM PDT 24
Finished Jul 30 06:43:41 PM PDT 24
Peak memory 199064 kb
Host smart-9b03d250-b367-4d04-a85b-3972f152cecf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104102251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.2104102251
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1443325527
Short name T968
Test name
Test status
Simulation time 15185459 ps
CPU time 0.63 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 198960 kb
Host smart-d4778f8a-594b-49a7-8976-a873a9ed4210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443325527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.1443325527
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2418913096
Short name T910
Test name
Test status
Simulation time 12822312 ps
CPU time 0.67 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 198612 kb
Host smart-6178aabd-6bc1-4698-9350-dc9c7408c69e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418913096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.2418913096
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.3926385680
Short name T853
Test name
Test status
Simulation time 13491524 ps
CPU time 0.72 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 199008 kb
Host smart-bf384929-dd63-4cac-bb0b-15592c1385d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926385680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.3926385680
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.65216843
Short name T963
Test name
Test status
Simulation time 11215695 ps
CPU time 0.63 seconds
Started Jul 30 06:43:46 PM PDT 24
Finished Jul 30 06:43:46 PM PDT 24
Peak memory 199000 kb
Host smart-c8db649b-ca91-421c-9d4a-397f26051cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65216843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkm
gr_intr_test.65216843
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.980447460
Short name T925
Test name
Test status
Simulation time 14570954 ps
CPU time 0.7 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 199000 kb
Host smart-813352b1-3e2e-4ebd-9788-fcb40715f55f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980447460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clk
mgr_intr_test.980447460
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2806449721
Short name T949
Test name
Test status
Simulation time 13509047 ps
CPU time 0.71 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 199064 kb
Host smart-ac186881-6a92-4193-8dbc-087fe8868dc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806449721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2806449721
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.165701062
Short name T857
Test name
Test status
Simulation time 43308970 ps
CPU time 1.31 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200424 kb
Host smart-d5f0ea23-9939-4cc2-924b-606d993d5a8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165701062 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.165701062
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.2251647588
Short name T69
Test name
Test status
Simulation time 48552230 ps
CPU time 0.87 seconds
Started Jul 30 06:43:18 PM PDT 24
Finished Jul 30 06:43:19 PM PDT 24
Peak memory 200384 kb
Host smart-fe345f5f-0f81-4fb9-b44f-18b8085d9ffc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251647588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.2251647588
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3720764546
Short name T912
Test name
Test status
Simulation time 66145078 ps
CPU time 0.76 seconds
Started Jul 30 06:43:09 PM PDT 24
Finished Jul 30 06:43:10 PM PDT 24
Peak memory 198920 kb
Host smart-80f69788-f85a-4258-9dfc-dfc856777310
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720764546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.3720764546
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.395444028
Short name T71
Test name
Test status
Simulation time 37436422 ps
CPU time 1.12 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200416 kb
Host smart-5056b7ee-4f3d-44ee-a862-8124169da4d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395444028 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.clkmgr_same_csr_outstanding.395444028
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3978847107
Short name T45
Test name
Test status
Simulation time 81167946 ps
CPU time 1.54 seconds
Started Jul 30 06:43:21 PM PDT 24
Finished Jul 30 06:43:22 PM PDT 24
Peak memory 200620 kb
Host smart-2b1643ce-5b7e-4885-ab5a-965c3031c36e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978847107 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.3978847107
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.1686154704
Short name T941
Test name
Test status
Simulation time 153029942 ps
CPU time 2.63 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:21 PM PDT 24
Peak memory 209000 kb
Host smart-d7c0c223-703c-4d48-920f-5daac8d66b96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686154704 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1686154704
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.83316497
Short name T921
Test name
Test status
Simulation time 53883195 ps
CPU time 1.58 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 200592 kb
Host smart-0ca831cd-6a73-4d3a-99bb-4a13741ca5ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83316497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmg
r_tl_errors.83316497
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1030423318
Short name T940
Test name
Test status
Simulation time 61300025 ps
CPU time 1.67 seconds
Started Jul 30 06:43:17 PM PDT 24
Finished Jul 30 06:43:19 PM PDT 24
Peak memory 200628 kb
Host smart-ded2c4b4-6fb1-488c-860c-0e1aaf88d028
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030423318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1030423318
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.469957645
Short name T906
Test name
Test status
Simulation time 19405273 ps
CPU time 0.94 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 200416 kb
Host smart-48f67102-d45d-414c-8b64-63407bd93a36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469957645 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.469957645
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1984942329
Short name T842
Test name
Test status
Simulation time 22658518 ps
CPU time 0.85 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200288 kb
Host smart-dd1eba54-c7fe-4b40-abda-7aa4c2691d66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984942329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.1984942329
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2461451290
Short name T958
Test name
Test status
Simulation time 14670989 ps
CPU time 0.68 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 198968 kb
Host smart-30893b26-edf3-421a-9fa6-9b2b7732749c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461451290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.2461451290
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2572199989
Short name T890
Test name
Test status
Simulation time 24230303 ps
CPU time 1.04 seconds
Started Jul 30 06:43:34 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 200400 kb
Host smart-5fd9dbc3-d35d-4eda-9d5a-a06d24d76d58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572199989 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.2572199989
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.756239977
Short name T123
Test name
Test status
Simulation time 69730746 ps
CPU time 1.35 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200636 kb
Host smart-c9bc7c6a-7029-407a-bd93-5bf441aa8aa6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756239977 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.756239977
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.4035125452
Short name T106
Test name
Test status
Simulation time 152284975 ps
CPU time 2.81 seconds
Started Jul 30 06:43:27 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 208976 kb
Host smart-448a6a49-21a6-4723-82a9-717c7d8d707b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035125452 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.4035125452
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.2677531897
Short name T834
Test name
Test status
Simulation time 204480980 ps
CPU time 2.26 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:29 PM PDT 24
Peak memory 200228 kb
Host smart-5cbb8ab4-a866-42ef-aa2b-73f2ffab665e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677531897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.2677531897
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.971756105
Short name T877
Test name
Test status
Simulation time 27998721 ps
CPU time 0.94 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 200452 kb
Host smart-b6c40f14-46fb-462c-83e9-1720bf198311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971756105 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.971756105
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.4195290880
Short name T943
Test name
Test status
Simulation time 49339887 ps
CPU time 0.9 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:31 PM PDT 24
Peak memory 200328 kb
Host smart-cc4aa498-edbc-4c2e-91df-01c98c4f0900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195290880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.4195290880
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.1074270508
Short name T874
Test name
Test status
Simulation time 19647135 ps
CPU time 0.76 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 199044 kb
Host smart-d75f5645-635f-4b0b-928d-3cb2fcd36519
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074270508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.1074270508
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.355211136
Short name T65
Test name
Test status
Simulation time 54008971 ps
CPU time 1.3 seconds
Started Jul 30 06:43:09 PM PDT 24
Finished Jul 30 06:43:11 PM PDT 24
Peak memory 200572 kb
Host smart-23785c56-5aba-46b6-bc05-bb287fce06d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355211136 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.clkmgr_same_csr_outstanding.355211136
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.4195911337
Short name T119
Test name
Test status
Simulation time 200526318 ps
CPU time 1.63 seconds
Started Jul 30 06:43:19 PM PDT 24
Finished Jul 30 06:43:21 PM PDT 24
Peak memory 200360 kb
Host smart-929711a7-ec46-4bb6-969b-3af496c0325b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195911337 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.4195911337
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3929584758
Short name T113
Test name
Test status
Simulation time 87658414 ps
CPU time 1.85 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 209056 kb
Host smart-019dca36-29ab-4924-a2cb-7d6b3b131f19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929584758 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3929584758
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.867700217
Short name T907
Test name
Test status
Simulation time 33836080 ps
CPU time 1.93 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200540 kb
Host smart-f9848b6f-30b6-46f6-98ad-be19ba0471f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867700217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_tl_errors.867700217
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.1811721033
Short name T87
Test name
Test status
Simulation time 209059238 ps
CPU time 2.55 seconds
Started Jul 30 06:43:32 PM PDT 24
Finished Jul 30 06:43:35 PM PDT 24
Peak memory 200624 kb
Host smart-81fcaea9-c0fd-48c0-8fde-b0854a5a6db9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811721033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.1811721033
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1802310759
Short name T851
Test name
Test status
Simulation time 85126611 ps
CPU time 1.51 seconds
Started Jul 30 06:43:30 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 200568 kb
Host smart-1ca86bf6-ca09-4eba-9c90-c8f636dd82e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802310759 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.1802310759
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.791563579
Short name T942
Test name
Test status
Simulation time 42881313 ps
CPU time 0.82 seconds
Started Jul 30 06:43:33 PM PDT 24
Finished Jul 30 06:43:34 PM PDT 24
Peak memory 200380 kb
Host smart-61b1f9d7-6766-4920-aeec-5c022100eaef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791563579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.c
lkmgr_csr_rw.791563579
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4061374398
Short name T939
Test name
Test status
Simulation time 29033004 ps
CPU time 0.67 seconds
Started Jul 30 06:43:18 PM PDT 24
Finished Jul 30 06:43:19 PM PDT 24
Peak memory 198948 kb
Host smart-5467b1d1-dfb8-4e09-9eb9-294d08c0d245
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061374398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.4061374398
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.849554826
Short name T962
Test name
Test status
Simulation time 439627312 ps
CPU time 2.18 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200480 kb
Host smart-de3fb550-964a-4438-b891-628f908ef519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849554826 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.clkmgr_same_csr_outstanding.849554826
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2343260510
Short name T46
Test name
Test status
Simulation time 158781745 ps
CPU time 2.12 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200892 kb
Host smart-b1816e01-57b1-4ec4-92ff-d0b095d5d9ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343260510 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.2343260510
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2449767932
Short name T50
Test name
Test status
Simulation time 84961816 ps
CPU time 1.81 seconds
Started Jul 30 06:43:23 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200972 kb
Host smart-1bdad058-7c60-4040-bf14-9e0ff7b811ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449767932 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2449767932
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3514001875
Short name T955
Test name
Test status
Simulation time 40923255 ps
CPU time 1.62 seconds
Started Jul 30 06:43:26 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 200552 kb
Host smart-f7597840-a251-4d50-a59c-e454e3455a3c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514001875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.3514001875
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.127222364
Short name T90
Test name
Test status
Simulation time 646386229 ps
CPU time 3.52 seconds
Started Jul 30 06:43:20 PM PDT 24
Finished Jul 30 06:43:24 PM PDT 24
Peak memory 200432 kb
Host smart-05ae478f-52e2-4e68-8977-c652d0224664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127222364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_tl_intg_err.127222364
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4243468946
Short name T950
Test name
Test status
Simulation time 101420549 ps
CPU time 1.26 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:25 PM PDT 24
Peak memory 200472 kb
Host smart-97d26018-8af6-4e7c-8ad7-4822a66d8c49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243468946 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.4243468946
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.440535951
Short name T916
Test name
Test status
Simulation time 36733336 ps
CPU time 0.78 seconds
Started Jul 30 06:43:22 PM PDT 24
Finished Jul 30 06:43:23 PM PDT 24
Peak memory 200080 kb
Host smart-22380799-b23a-4a13-85c9-97c99ca8f8d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440535951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c
lkmgr_csr_rw.440535951
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.3296143053
Short name T833
Test name
Test status
Simulation time 24594481 ps
CPU time 0.74 seconds
Started Jul 30 06:43:31 PM PDT 24
Finished Jul 30 06:43:32 PM PDT 24
Peak memory 198932 kb
Host smart-110cc4e2-8e0f-4e32-9ff1-15b295e0937b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296143053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.3296143053
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4226062718
Short name T936
Test name
Test status
Simulation time 105368599 ps
CPU time 1.13 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:27 PM PDT 24
Peak memory 200276 kb
Host smart-3c24f0af-21b2-4eac-b207-2c3d9c300f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226062718 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.4226062718
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2909842261
Short name T120
Test name
Test status
Simulation time 159725792 ps
CPU time 2.02 seconds
Started Jul 30 06:43:28 PM PDT 24
Finished Jul 30 06:43:30 PM PDT 24
Peak memory 200812 kb
Host smart-34a67943-9d3e-422a-ac8b-7d95d1d17e27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909842261 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.2909842261
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.885780819
Short name T125
Test name
Test status
Simulation time 189152632 ps
CPU time 2.95 seconds
Started Jul 30 06:43:25 PM PDT 24
Finished Jul 30 06:43:28 PM PDT 24
Peak memory 209072 kb
Host smart-f407a3f1-caf3-4e37-b720-8ae676f95866
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885780819 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.885780819
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.293867694
Short name T927
Test name
Test status
Simulation time 110550901 ps
CPU time 2.57 seconds
Started Jul 30 06:43:17 PM PDT 24
Finished Jul 30 06:43:20 PM PDT 24
Peak memory 200504 kb
Host smart-4f0619dd-3443-4086-9da0-d8d809f167f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293867694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_tl_errors.293867694
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2600090975
Short name T84
Test name
Test status
Simulation time 61875147 ps
CPU time 1.6 seconds
Started Jul 30 06:43:24 PM PDT 24
Finished Jul 30 06:43:26 PM PDT 24
Peak memory 200628 kb
Host smart-463a26ef-d860-4354-9545-2475261575fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600090975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2600090975
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.333161355
Short name T333
Test name
Test status
Simulation time 13586347 ps
CPU time 0.78 seconds
Started Jul 30 06:24:38 PM PDT 24
Finished Jul 30 06:24:39 PM PDT 24
Peak memory 201020 kb
Host smart-2b80c3f7-655b-42bb-90c2-74e170fe93c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333161355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.333161355
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1525869145
Short name T368
Test name
Test status
Simulation time 21151629 ps
CPU time 0.91 seconds
Started Jul 30 06:24:34 PM PDT 24
Finished Jul 30 06:24:35 PM PDT 24
Peak memory 201268 kb
Host smart-724319c7-e99f-4404-9ccb-b8a21608aaa5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525869145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1525869145
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2256925214
Short name T679
Test name
Test status
Simulation time 92092405 ps
CPU time 0.92 seconds
Started Jul 30 06:24:34 PM PDT 24
Finished Jul 30 06:24:35 PM PDT 24
Peak memory 201008 kb
Host smart-32d5e8eb-f81c-4ae7-b411-df2dba2bb043
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256925214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2256925214
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.3787210359
Short name T608
Test name
Test status
Simulation time 15244887 ps
CPU time 0.83 seconds
Started Jul 30 06:24:34 PM PDT 24
Finished Jul 30 06:24:35 PM PDT 24
Peak memory 201268 kb
Host smart-898826a1-d1c3-4a60-a423-502e1df80809
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787210359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.3787210359
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.3079684053
Short name T597
Test name
Test status
Simulation time 35973611 ps
CPU time 0.87 seconds
Started Jul 30 06:24:34 PM PDT 24
Finished Jul 30 06:24:34 PM PDT 24
Peak memory 201068 kb
Host smart-4fc763e4-772f-4946-bd2d-31d99fb32ec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079684053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3079684053
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.2222849659
Short name T446
Test name
Test status
Simulation time 1862868550 ps
CPU time 8.6 seconds
Started Jul 30 06:24:36 PM PDT 24
Finished Jul 30 06:24:45 PM PDT 24
Peak memory 201296 kb
Host smart-5b1b2926-defc-4399-9984-defb896ad6c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222849659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2222849659
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.168524968
Short name T646
Test name
Test status
Simulation time 1336112223 ps
CPU time 10.43 seconds
Started Jul 30 06:24:33 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 201196 kb
Host smart-c48ce603-aaeb-44e3-bdf4-35f292935220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168524968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_tim
eout.168524968
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.3127855465
Short name T810
Test name
Test status
Simulation time 37865185 ps
CPU time 0.77 seconds
Started Jul 30 06:24:35 PM PDT 24
Finished Jul 30 06:24:36 PM PDT 24
Peak memory 201092 kb
Host smart-f9526a19-3a63-4bb4-ac56-7ed731e8a6fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127855465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.3127855465
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3415636671
Short name T22
Test name
Test status
Simulation time 45892107 ps
CPU time 0.83 seconds
Started Jul 30 06:24:33 PM PDT 24
Finished Jul 30 06:24:34 PM PDT 24
Peak memory 201032 kb
Host smart-68e05184-8bdc-4e80-a8bc-ff6e9d80fc02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415636671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3415636671
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.963545845
Short name T404
Test name
Test status
Simulation time 67752877 ps
CPU time 0.96 seconds
Started Jul 30 06:24:36 PM PDT 24
Finished Jul 30 06:24:37 PM PDT 24
Peak memory 201044 kb
Host smart-1b3d5afa-4937-42c9-a030-90562fc16a0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963545845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.963545845
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.4007669151
Short name T270
Test name
Test status
Simulation time 22097065 ps
CPU time 0.71 seconds
Started Jul 30 06:24:35 PM PDT 24
Finished Jul 30 06:24:36 PM PDT 24
Peak memory 201108 kb
Host smart-fedd9d5e-b0f5-4e01-aa23-1a561a87e631
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007669151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.4007669151
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.2830812979
Short name T728
Test name
Test status
Simulation time 1500916670 ps
CPU time 5.83 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:43 PM PDT 24
Peak memory 201348 kb
Host smart-e17d04e2-7761-4374-83b4-1e6850063dd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830812979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.2830812979
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.1399083247
Short name T41
Test name
Test status
Simulation time 297424715 ps
CPU time 3.32 seconds
Started Jul 30 06:24:39 PM PDT 24
Finished Jul 30 06:24:43 PM PDT 24
Peak memory 217788 kb
Host smart-99f16835-3170-451b-9f26-3961a6a20340
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399083247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.1399083247
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.28712228
Short name T364
Test name
Test status
Simulation time 177021144 ps
CPU time 1.27 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:38 PM PDT 24
Peak memory 201032 kb
Host smart-5640af23-8896-4802-8838-35c08c05507a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28712228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.28712228
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.4161819750
Short name T775
Test name
Test status
Simulation time 2044770140 ps
CPU time 11.41 seconds
Started Jul 30 06:24:38 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201308 kb
Host smart-2c7fd5ba-55eb-4e16-b3b7-2ba58b99eb02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161819750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.4161819750
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.3440112095
Short name T785
Test name
Test status
Simulation time 26392566 ps
CPU time 0.96 seconds
Started Jul 30 06:24:34 PM PDT 24
Finished Jul 30 06:24:35 PM PDT 24
Peak memory 201044 kb
Host smart-ebbf9880-f5af-44f7-ad59-928ef607587d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440112095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3440112095
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.4024023201
Short name T178
Test name
Test status
Simulation time 55429481 ps
CPU time 0.94 seconds
Started Jul 30 06:24:40 PM PDT 24
Finished Jul 30 06:24:41 PM PDT 24
Peak memory 201104 kb
Host smart-f4ac4522-8503-4ef7-98ad-8dfdbb68b6cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024023201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.4024023201
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.2377311004
Short name T298
Test name
Test status
Simulation time 13424997 ps
CPU time 0.76 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:37 PM PDT 24
Peak memory 200292 kb
Host smart-77453368-1268-4fb7-a879-2defee787c38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377311004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2377311004
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.410720432
Short name T362
Test name
Test status
Simulation time 148009397 ps
CPU time 1.16 seconds
Started Jul 30 06:24:35 PM PDT 24
Finished Jul 30 06:24:37 PM PDT 24
Peak memory 201048 kb
Host smart-67111de8-4715-4299-bf8d-81859eb812bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410720432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_div_intersig_mubi.410720432
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.3862042179
Short name T229
Test name
Test status
Simulation time 23872708 ps
CPU time 0.82 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:38 PM PDT 24
Peak memory 201132 kb
Host smart-e91a3c1b-d6ed-4f1e-bfbe-e1ba70e5a1f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862042179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.3862042179
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.1836521592
Short name T483
Test name
Test status
Simulation time 246255409 ps
CPU time 1.57 seconds
Started Jul 30 06:24:40 PM PDT 24
Finished Jul 30 06:24:41 PM PDT 24
Peak memory 201096 kb
Host smart-cebf5cbc-c411-4bdd-a6b0-a0de04dcf1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836521592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1836521592
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.3084380832
Short name T393
Test name
Test status
Simulation time 1222788884 ps
CPU time 7.35 seconds
Started Jul 30 06:24:36 PM PDT 24
Finished Jul 30 06:24:43 PM PDT 24
Peak memory 201180 kb
Host smart-80c8331e-294b-4dd3-926d-95c23d786c34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084380832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.3084380832
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.367604086
Short name T294
Test name
Test status
Simulation time 53933251 ps
CPU time 1.03 seconds
Started Jul 30 06:24:36 PM PDT 24
Finished Jul 30 06:24:37 PM PDT 24
Peak memory 201064 kb
Host smart-39c9190f-d242-4944-8847-db31b52a95fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367604086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_idle_intersig_mubi.367604086
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3875254154
Short name T517
Test name
Test status
Simulation time 15009778 ps
CPU time 0.8 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:38 PM PDT 24
Peak memory 201068 kb
Host smart-e0bdf229-8e80-4383-94a9-f00daf15efc3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875254154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3875254154
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3662723618
Short name T811
Test name
Test status
Simulation time 135768163 ps
CPU time 1.2 seconds
Started Jul 30 06:24:35 PM PDT 24
Finished Jul 30 06:24:36 PM PDT 24
Peak memory 201064 kb
Host smart-1ac062d3-dd8c-4955-a8bb-8a1b4e925e95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662723618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.3662723618
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.1159950774
Short name T163
Test name
Test status
Simulation time 94024944 ps
CPU time 0.93 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:38 PM PDT 24
Peak memory 201124 kb
Host smart-07198c13-3fe0-4f22-817e-9d0f8a02e99f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159950774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1159950774
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.1261301007
Short name T425
Test name
Test status
Simulation time 1476391530 ps
CPU time 5.66 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:24:43 PM PDT 24
Peak memory 201340 kb
Host smart-7b88dfa4-3612-457b-a269-064f167950af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261301007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1261301007
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.270735014
Short name T42
Test name
Test status
Simulation time 2299598272 ps
CPU time 9.06 seconds
Started Jul 30 06:24:38 PM PDT 24
Finished Jul 30 06:24:47 PM PDT 24
Peak memory 217940 kb
Host smart-a1708f36-7fee-4b56-8741-9d723237e58e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270735014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr
_sec_cm.270735014
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2963171207
Short name T461
Test name
Test status
Simulation time 21894248 ps
CPU time 0.85 seconds
Started Jul 30 06:24:39 PM PDT 24
Finished Jul 30 06:24:40 PM PDT 24
Peak memory 201088 kb
Host smart-b837c98f-8562-42ea-b92f-d0d828d9d70a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963171207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2963171207
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.761356313
Short name T421
Test name
Test status
Simulation time 9992185287 ps
CPU time 36.42 seconds
Started Jul 30 06:24:37 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201496 kb
Host smart-85b4eb75-e6cd-43d7-91e1-fd863be9719d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761356313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.761356313
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.1318358698
Short name T313
Test name
Test status
Simulation time 40287058 ps
CPU time 0.88 seconds
Started Jul 30 06:24:35 PM PDT 24
Finished Jul 30 06:24:36 PM PDT 24
Peak memory 201096 kb
Host smart-a27b65e1-15ad-4064-80bf-2ed1e66d072a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318358698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1318358698
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1079623619
Short name T763
Test name
Test status
Simulation time 18572020 ps
CPU time 0.82 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 201068 kb
Host smart-41016f5b-6c3f-4234-b609-685d3d3717a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079623619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1079623619
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2443315169
Short name T450
Test name
Test status
Simulation time 108400169 ps
CPU time 0.98 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 200284 kb
Host smart-01ab303d-57fe-4ca1-8cf5-6f71817a337d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443315169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2443315169
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.4157396771
Short name T721
Test name
Test status
Simulation time 198560562 ps
CPU time 1.35 seconds
Started Jul 30 06:25:04 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201056 kb
Host smart-a6d37316-f83e-4a7b-a9fb-fbdf4ec344b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157396771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.4157396771
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.1201324572
Short name T736
Test name
Test status
Simulation time 84844817 ps
CPU time 1.02 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201060 kb
Host smart-7cfff273-5f85-4f9b-bf83-31c11bca7dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201324572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.1201324572
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.229776582
Short name T633
Test name
Test status
Simulation time 321955047 ps
CPU time 3.26 seconds
Started Jul 30 06:25:01 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201156 kb
Host smart-67ad64de-b1c4-49c2-9adb-288827d262d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229776582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.229776582
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1398297816
Short name T641
Test name
Test status
Simulation time 620628899 ps
CPU time 3.41 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201140 kb
Host smart-cdcf5a45-e604-4c63-96e9-8ec420dfa040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398297816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1398297816
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.1901056971
Short name T272
Test name
Test status
Simulation time 112351219 ps
CPU time 1.24 seconds
Started Jul 30 06:25:04 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201068 kb
Host smart-240f60e5-ec14-4f9d-a3de-38c22c895cd9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901056971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.1901056971
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.253551206
Short name T99
Test name
Test status
Simulation time 13881101 ps
CPU time 0.74 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:03 PM PDT 24
Peak memory 201068 kb
Host smart-2df20d47-c2e4-49df-83c2-d52e3f663319
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253551206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_clk_byp_req_intersig_mubi.253551206
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.606027203
Short name T184
Test name
Test status
Simulation time 23377707 ps
CPU time 0.82 seconds
Started Jul 30 06:25:01 PM PDT 24
Finished Jul 30 06:25:02 PM PDT 24
Peak memory 201044 kb
Host smart-e9cc0b6c-0204-4720-b1c8-14dbe7f2f5d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606027203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.606027203
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3046404690
Short name T545
Test name
Test status
Simulation time 25999251 ps
CPU time 0.8 seconds
Started Jul 30 06:25:01 PM PDT 24
Finished Jul 30 06:25:02 PM PDT 24
Peak memory 201016 kb
Host smart-252c00cd-cbb6-439f-9dda-ece34affd495
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046404690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3046404690
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.2942951572
Short name T715
Test name
Test status
Simulation time 64910069 ps
CPU time 1.09 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201104 kb
Host smart-6a960c5a-276a-4889-b4fb-37ce10e6fd8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942951572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2942951572
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.3746337993
Short name T284
Test name
Test status
Simulation time 121527225 ps
CPU time 1.36 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201124 kb
Host smart-a6731bd0-4cbd-43ab-8e04-e2b8b55334e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746337993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.3746337993
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.2154846292
Short name T56
Test name
Test status
Simulation time 244900211379 ps
CPU time 1015.91 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:42:02 PM PDT 24
Peak memory 217960 kb
Host smart-ff32ee89-04a7-450b-a59b-db70b96d342f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2154846292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2154846292
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.1139794105
Short name T322
Test name
Test status
Simulation time 35935367 ps
CPU time 1 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:03 PM PDT 24
Peak memory 201080 kb
Host smart-dc8e26bd-b0b4-429c-ad55-01086e89f2b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139794105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1139794105
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.383847410
Short name T214
Test name
Test status
Simulation time 20926380 ps
CPU time 0.87 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201048 kb
Host smart-5e3469be-aea5-4c76-b06d-7d7b9844a72b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383847410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkm
gr_alert_test.383847410
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.709838211
Short name T334
Test name
Test status
Simulation time 38108831 ps
CPU time 0.81 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201004 kb
Host smart-0a048db6-5712-4616-a503-8bbdd8da3b72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709838211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.709838211
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2057409223
Short name T637
Test name
Test status
Simulation time 271804386 ps
CPU time 1.57 seconds
Started Jul 30 06:25:04 PM PDT 24
Finished Jul 30 06:25:06 PM PDT 24
Peak memory 201124 kb
Host smart-d5e3e94a-f551-4aa6-82de-a84eabdc79f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057409223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2057409223
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.422522737
Short name T363
Test name
Test status
Simulation time 73343101 ps
CPU time 0.96 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201016 kb
Host smart-f051cf44-77bc-4524-b308-26ddc0a53db5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422522737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.422522737
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.488782152
Short name T787
Test name
Test status
Simulation time 1806988424 ps
CPU time 8.24 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201352 kb
Host smart-6f96f9bf-a17a-4908-96e8-f05a25c1b542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488782152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.488782152
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.3444259996
Short name T689
Test name
Test status
Simulation time 1106318728 ps
CPU time 4.3 seconds
Started Jul 30 06:25:07 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201164 kb
Host smart-f51ba8a2-b624-4344-8054-8c64d69852c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444259996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.3444259996
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2198962759
Short name T203
Test name
Test status
Simulation time 98142770 ps
CPU time 1.19 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 201136 kb
Host smart-ca9d941b-e89a-4542-9b94-a88143d76833
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198962759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2198962759
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1425188873
Short name T260
Test name
Test status
Simulation time 82611851 ps
CPU time 1.05 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201128 kb
Host smart-ea21d817-5717-4b3c-8f99-595201a20f36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425188873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1425188873
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2581380138
Short name T658
Test name
Test status
Simulation time 19858219 ps
CPU time 0.81 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 201008 kb
Host smart-48b2d7ae-23d8-4e8d-a4f9-c2ae12357c8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581380138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.2581380138
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.2574727291
Short name T639
Test name
Test status
Simulation time 36655834 ps
CPU time 0.78 seconds
Started Jul 30 06:25:07 PM PDT 24
Finished Jul 30 06:25:08 PM PDT 24
Peak memory 201128 kb
Host smart-d2e5f589-94f1-4f97-9811-73ef83b53337
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574727291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2574727291
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.1490758553
Short name T139
Test name
Test status
Simulation time 1473883979 ps
CPU time 8.29 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201268 kb
Host smart-f019c4e5-144c-4dd9-935e-3b018953d0db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490758553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.1490758553
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.312311718
Short name T374
Test name
Test status
Simulation time 38063413 ps
CPU time 0.84 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:06 PM PDT 24
Peak memory 201092 kb
Host smart-d3744875-7e52-48ca-b152-1e6db9c201f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312311718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.312311718
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.3284230222
Short name T193
Test name
Test status
Simulation time 1909205067 ps
CPU time 8.98 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201004 kb
Host smart-d0624ac9-5a56-430f-ae3e-74b3106c972e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284230222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.3284230222
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.3685244788
Short name T158
Test name
Test status
Simulation time 15930670169 ps
CPU time 181.37 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:28:15 PM PDT 24
Peak memory 209676 kb
Host smart-8dc323d3-f683-4592-9c01-3091e11a927d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3685244788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3685244788
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3318498541
Short name T165
Test name
Test status
Simulation time 51994702 ps
CPU time 0.9 seconds
Started Jul 30 06:25:07 PM PDT 24
Finished Jul 30 06:25:08 PM PDT 24
Peak memory 201116 kb
Host smart-cc452831-20f7-4180-bcef-39974345bdfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318498541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3318498541
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2722517870
Short name T753
Test name
Test status
Simulation time 16055383 ps
CPU time 0.74 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201060 kb
Host smart-31d250c2-4d3d-4d64-8396-25be6cc0fca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722517870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2722517870
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.1546719516
Short name T596
Test name
Test status
Simulation time 15917760 ps
CPU time 0.77 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201128 kb
Host smart-e8dd6c3f-bda5-4de5-bbdd-718245ae0485
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546719516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.1546719516
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1082078082
Short name T148
Test name
Test status
Simulation time 15253045 ps
CPU time 0.76 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 200984 kb
Host smart-cfa11a16-218d-45b7-a2c2-bd1d450e6b8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082078082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1082078082
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.3025711575
Short name T568
Test name
Test status
Simulation time 17259245 ps
CPU time 0.77 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 201088 kb
Host smart-a00c02ec-6bbb-4c7a-8368-f3c0049c7173
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025711575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.3025711575
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3523811472
Short name T153
Test name
Test status
Simulation time 60247201 ps
CPU time 0.94 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 201112 kb
Host smart-2d477fde-8529-49d9-8b10-6258435a7866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523811472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3523811472
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.693477600
Short name T12
Test name
Test status
Simulation time 1171599780 ps
CPU time 6.97 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 200880 kb
Host smart-77d32bff-ec14-4e38-903c-8ed2abcb6875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693477600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.693477600
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.1310654447
Short name T220
Test name
Test status
Simulation time 380669543 ps
CPU time 3.34 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:10 PM PDT 24
Peak memory 201212 kb
Host smart-c83cb715-2630-4de6-bbe2-45dccc8a5984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310654447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.1310654447
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3030448979
Short name T686
Test name
Test status
Simulation time 97571218 ps
CPU time 1.18 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 201008 kb
Host smart-2d9e3785-dcff-4e64-afdb-9a693717c8ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030448979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.3030448979
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.89128051
Short name T23
Test name
Test status
Simulation time 22669312 ps
CPU time 0.83 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201064 kb
Host smart-2ff05359-251e-4e2f-b111-b32c6819cc78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89128051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_lc_clk_byp_req_intersig_mubi.89128051
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3696546469
Short name T392
Test name
Test status
Simulation time 166540066 ps
CPU time 1.19 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:06 PM PDT 24
Peak memory 201112 kb
Host smart-42d89814-02e4-47ce-87a0-9178fb813a3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696546469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3696546469
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.3631855935
Short name T296
Test name
Test status
Simulation time 40014871 ps
CPU time 0.85 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 201068 kb
Host smart-d1a0258e-3b76-4e4d-8719-c3c27fee9434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631855935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3631855935
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3487393699
Short name T694
Test name
Test status
Simulation time 350991094 ps
CPU time 1.84 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:16 PM PDT 24
Peak memory 201016 kb
Host smart-994970f9-d2f4-4cb7-8298-b58faa670879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487393699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3487393699
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.1110735186
Short name T447
Test name
Test status
Simulation time 79262448 ps
CPU time 1.01 seconds
Started Jul 30 06:25:06 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201152 kb
Host smart-1b1ddf3c-6c2d-41b1-a93e-cd21021f44d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110735186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1110735186
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.1469153391
Short name T408
Test name
Test status
Simulation time 6236073453 ps
CPU time 36 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:54 PM PDT 24
Peak memory 201432 kb
Host smart-f5a6c053-b01b-44f7-a80d-ee6e97eb9384
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469153391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.1469153391
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3274698224
Short name T11
Test name
Test status
Simulation time 86273007386 ps
CPU time 419.93 seconds
Started Jul 30 06:25:07 PM PDT 24
Finished Jul 30 06:32:07 PM PDT 24
Peak memory 209816 kb
Host smart-4e5fd494-0426-4b28-843e-d9e123fc0368
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3274698224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3274698224
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.3793560048
Short name T812
Test name
Test status
Simulation time 101162952 ps
CPU time 0.98 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201124 kb
Host smart-52b733e4-6947-47ce-8fb1-9b22c46c76c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793560048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.3793560048
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.1189165648
Short name T171
Test name
Test status
Simulation time 16554128 ps
CPU time 0.74 seconds
Started Jul 30 06:25:09 PM PDT 24
Finished Jul 30 06:25:10 PM PDT 24
Peak memory 201084 kb
Host smart-06b3d561-3e6b-4f97-b0b4-064604b72e0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189165648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.1189165648
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.2060078189
Short name T480
Test name
Test status
Simulation time 34362908 ps
CPU time 0.8 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201072 kb
Host smart-45150bc0-b656-4644-a1df-619e6b493d49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060078189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.2060078189
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.2018787864
Short name T712
Test name
Test status
Simulation time 13679281 ps
CPU time 0.73 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:10 PM PDT 24
Peak memory 201008 kb
Host smart-127287e2-72b2-4431-bc14-bf8f4c30641e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018787864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2018787864
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2409759424
Short name T491
Test name
Test status
Simulation time 68986937 ps
CPU time 0.96 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 201072 kb
Host smart-dd53e06a-3d67-467e-a722-d97c8bc546cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409759424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2409759424
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.1767200360
Short name T433
Test name
Test status
Simulation time 28428781 ps
CPU time 0.94 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201120 kb
Host smart-a1f61bd5-e35b-40f0-b6fe-0c1847df7917
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767200360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.1767200360
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.3482760358
Short name T314
Test name
Test status
Simulation time 2497539459 ps
CPU time 14.4 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:32 PM PDT 24
Peak memory 200928 kb
Host smart-2efb80b3-4698-48ff-b947-72f2afdcf48b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482760358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.3482760358
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.1388651936
Short name T661
Test name
Test status
Simulation time 282586824 ps
CPU time 1.8 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:16 PM PDT 24
Peak memory 201140 kb
Host smart-38b93754-0510-40e4-a195-da9fd3153f74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388651936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.1388651936
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.699728431
Short name T254
Test name
Test status
Simulation time 49460920 ps
CPU time 1.04 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201108 kb
Host smart-6a83946e-f79a-4901-ba83-684d0e9955a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699728431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.clkmgr_idle_intersig_mubi.699728431
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.845718783
Short name T600
Test name
Test status
Simulation time 53942606 ps
CPU time 0.87 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201064 kb
Host smart-dc4a87f9-128d-4177-bd6d-55bc9f89b93e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845718783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.845718783
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.374603845
Short name T650
Test name
Test status
Simulation time 18050567 ps
CPU time 0.78 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201048 kb
Host smart-1f73b486-90b2-4ca1-aad3-92217c475247
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374603845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.374603845
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.2440215693
Short name T801
Test name
Test status
Simulation time 17611123 ps
CPU time 0.76 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201040 kb
Host smart-b997a519-c132-4d20-aae6-c396f7cbae4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440215693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2440215693
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3748405106
Short name T138
Test name
Test status
Simulation time 224933316 ps
CPU time 1.94 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201104 kb
Host smart-4c3a77d2-00c6-4bb5-aee0-08b3a38da1b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748405106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3748405106
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1571176597
Short name T219
Test name
Test status
Simulation time 16779837 ps
CPU time 0.82 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 201024 kb
Host smart-70211620-e3d5-45be-bbb6-8d5c8be067d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571176597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1571176597
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.2309336584
Short name T422
Test name
Test status
Simulation time 4891053804 ps
CPU time 21.04 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:31 PM PDT 24
Peak memory 201444 kb
Host smart-54af517a-5de3-4e6f-a6f9-636233baee34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309336584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.2309336584
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2456638381
Short name T354
Test name
Test status
Simulation time 128715777 ps
CPU time 1.27 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 200764 kb
Host smart-77717450-c09b-4f93-ad4a-0169d12a848f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456638381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2456638381
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.1637794233
Short name T249
Test name
Test status
Simulation time 22124210 ps
CPU time 0.72 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 201048 kb
Host smart-d64a356e-ecd7-47f9-a02a-794822bf0f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637794233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.1637794233
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2841449176
Short name T587
Test name
Test status
Simulation time 49055149 ps
CPU time 0.86 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201028 kb
Host smart-154ec7d0-34f5-4835-8c38-cd61a8d968cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841449176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2841449176
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.3015166772
Short name T697
Test name
Test status
Simulation time 20096042 ps
CPU time 0.71 seconds
Started Jul 30 06:25:08 PM PDT 24
Finished Jul 30 06:25:09 PM PDT 24
Peak memory 200324 kb
Host smart-bc9e16c0-9d1d-482b-af68-0c34b7744fc4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015166772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3015166772
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.74296963
Short name T234
Test name
Test status
Simulation time 18181538 ps
CPU time 0.77 seconds
Started Jul 30 06:25:07 PM PDT 24
Finished Jul 30 06:25:08 PM PDT 24
Peak memory 201256 kb
Host smart-1b084011-12bc-40d7-b5dc-e5d7e8ef05d0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74296963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.clkmgr_div_intersig_mubi.74296963
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.31341779
Short name T174
Test name
Test status
Simulation time 16910361 ps
CPU time 0.78 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201100 kb
Host smart-621aaae3-991d-47ff-b669-a1df5e7c0275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.31341779
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.4283235668
Short name T291
Test name
Test status
Simulation time 1170667829 ps
CPU time 6.41 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201144 kb
Host smart-ce45072e-b0a8-475b-8657-01b497845bd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283235668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.4283235668
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.21334183
Short name T581
Test name
Test status
Simulation time 2037405673 ps
CPU time 7.07 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:18 PM PDT 24
Peak memory 200944 kb
Host smart-cbc01448-f550-4b64-a2e1-53b402034675
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21334183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_tim
eout.21334183
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3868525643
Short name T274
Test name
Test status
Simulation time 24250150 ps
CPU time 1.05 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201088 kb
Host smart-aed16e77-3c4b-4192-9876-a56df628a6b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868525643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3868525643
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1841044519
Short name T248
Test name
Test status
Simulation time 24079022 ps
CPU time 0.84 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201104 kb
Host smart-9f0fd8c0-af9f-4763-a37f-9802569ea83d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841044519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1841044519
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.761450012
Short name T490
Test name
Test status
Simulation time 26605411 ps
CPU time 0.93 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201136 kb
Host smart-392147fc-b74d-45a6-b2b6-df1e650369b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761450012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.761450012
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.2087749698
Short name T788
Test name
Test status
Simulation time 33775089 ps
CPU time 0.77 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201096 kb
Host smart-8d50785b-3823-469d-9040-0bae7e9c1c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087749698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2087749698
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3207101410
Short name T263
Test name
Test status
Simulation time 2421144356 ps
CPU time 7.47 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 201328 kb
Host smart-958909f3-e28e-49cb-9586-a9142ee5a596
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207101410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3207101410
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.999413223
Short name T373
Test name
Test status
Simulation time 22916567 ps
CPU time 0.87 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201080 kb
Host smart-bd4e960e-1350-459d-b29b-d23216d1251b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999413223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.999413223
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2892071564
Short name T228
Test name
Test status
Simulation time 2694215222 ps
CPU time 9.04 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 201436 kb
Host smart-7b3aea28-4712-4e9b-918e-06f5c40001fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892071564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2892071564
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.1781818752
Short name T622
Test name
Test status
Simulation time 137915482 ps
CPU time 1.25 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201016 kb
Host smart-daeb6e04-325b-4a60-a51d-103d70e86f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781818752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.1781818752
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1844241420
Short name T673
Test name
Test status
Simulation time 14226861 ps
CPU time 0.73 seconds
Started Jul 30 06:25:15 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 200908 kb
Host smart-5c444daa-6247-444d-ba07-2e712c873cc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844241420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1844241420
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2475946317
Short name T741
Test name
Test status
Simulation time 40294210 ps
CPU time 0.79 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201036 kb
Host smart-b5ddd9da-d4db-418e-84f0-21bf97c8a5c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475946317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2475946317
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.1535253725
Short name T395
Test name
Test status
Simulation time 12236652 ps
CPU time 0.68 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 200212 kb
Host smart-77bfc0db-f58b-4bcb-86df-8422036eafaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535253725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.1535253725
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3240197613
Short name T351
Test name
Test status
Simulation time 84515476 ps
CPU time 1.05 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201052 kb
Host smart-b6b7f9aa-3fca-44bc-9e58-701a98f4b7f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240197613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.3240197613
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.2763414393
Short name T798
Test name
Test status
Simulation time 25692515 ps
CPU time 0.79 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201096 kb
Host smart-e15242cc-7ba8-40a3-89b4-324a9bc9372a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763414393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2763414393
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.3982059159
Short name T250
Test name
Test status
Simulation time 1378123450 ps
CPU time 6.17 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201168 kb
Host smart-9fe34c9f-7caa-41d2-adc9-eed653407b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982059159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3982059159
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3530888603
Short name T398
Test name
Test status
Simulation time 2059505650 ps
CPU time 15.38 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201320 kb
Host smart-b6fa1577-578d-46a6-b63c-2e591687c07a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530888603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3530888603
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.945668598
Short name T692
Test name
Test status
Simulation time 37746678 ps
CPU time 0.91 seconds
Started Jul 30 06:25:10 PM PDT 24
Finished Jul 30 06:25:11 PM PDT 24
Peak memory 201080 kb
Host smart-455498c2-5225-414f-b248-46dba2c2eae8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945668598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.945668598
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1050147887
Short name T215
Test name
Test status
Simulation time 90075774 ps
CPU time 1.05 seconds
Started Jul 30 06:25:15 PM PDT 24
Finished Jul 30 06:25:16 PM PDT 24
Peak memory 201056 kb
Host smart-74adc072-09c7-476d-a3c1-26a634b36ed0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050147887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.1050147887
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1540644673
Short name T684
Test name
Test status
Simulation time 29598624 ps
CPU time 0.93 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 201068 kb
Host smart-2704e4de-0f4d-4311-9bc6-ed5bd820a5f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540644673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1540644673
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.1239609118
Short name T273
Test name
Test status
Simulation time 16642233 ps
CPU time 0.8 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 200992 kb
Host smart-f7bf8c0e-240e-4f9a-b24f-0073db893087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239609118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1239609118
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.4097429
Short name T592
Test name
Test status
Simulation time 77830943 ps
CPU time 1.03 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 201020 kb
Host smart-061464bb-9a56-4c50-a941-6a3d3a2323bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.4097429
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3228453416
Short name T2
Test name
Test status
Simulation time 3443758934 ps
CPU time 18.53 seconds
Started Jul 30 06:25:19 PM PDT 24
Finished Jul 30 06:25:38 PM PDT 24
Peak memory 201380 kb
Host smart-7a74aea5-3194-4d56-b4ce-56cf972677e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228453416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3228453416
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.2225827873
Short name T554
Test name
Test status
Simulation time 57441790 ps
CPU time 0.92 seconds
Started Jul 30 06:25:11 PM PDT 24
Finished Jul 30 06:25:12 PM PDT 24
Peak memory 201020 kb
Host smart-c0c044ec-db7f-4202-8591-17be6c0ea84d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225827873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.2225827873
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.4145817247
Short name T524
Test name
Test status
Simulation time 25515908 ps
CPU time 0.77 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 201128 kb
Host smart-a8b3e148-a161-48d5-882a-83b0639cad69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145817247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.4145817247
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1754536603
Short name T523
Test name
Test status
Simulation time 19926105 ps
CPU time 0.82 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:18 PM PDT 24
Peak memory 201096 kb
Host smart-49774f59-1d47-4414-9059-b46000930f82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754536603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.1754536603
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.1807300436
Short name T735
Test name
Test status
Simulation time 43670638 ps
CPU time 0.79 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 200292 kb
Host smart-fb251bf2-7009-4193-ace1-ecea81bfb069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807300436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1807300436
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1822282326
Short name T612
Test name
Test status
Simulation time 42940152 ps
CPU time 0.8 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201080 kb
Host smart-49444ccf-7280-44d3-a11e-1a5540619a26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822282326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.1822282326
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.151361316
Short name T807
Test name
Test status
Simulation time 50028186 ps
CPU time 0.97 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:15 PM PDT 24
Peak memory 201056 kb
Host smart-91a630ec-4de2-4c9d-a419-9e29b553df44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151361316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.151361316
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1314880176
Short name T103
Test name
Test status
Simulation time 2624707119 ps
CPU time 10.59 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201388 kb
Host smart-1431bfca-dcc2-4538-815b-6000278682f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314880176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1314880176
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2345356950
Short name T530
Test name
Test status
Simulation time 770027937 ps
CPU time 3.58 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201220 kb
Host smart-7548f4c6-2d7f-4565-86a8-c78036baa534
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345356950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2345356950
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.106898157
Short name T369
Test name
Test status
Simulation time 25366445 ps
CPU time 0.89 seconds
Started Jul 30 06:25:15 PM PDT 24
Finished Jul 30 06:25:16 PM PDT 24
Peak memory 201064 kb
Host smart-aa1d263b-2c32-4dbb-8bf5-dfb507202da2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106898157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_idle_intersig_mubi.106898157
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.267341472
Short name T500
Test name
Test status
Simulation time 43726237 ps
CPU time 0.92 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:22 PM PDT 24
Peak memory 201088 kb
Host smart-b062761e-e886-4b81-b428-b4670ab30a83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267341472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_clk_byp_req_intersig_mubi.267341472
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3605262828
Short name T434
Test name
Test status
Simulation time 22693948 ps
CPU time 0.77 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201148 kb
Host smart-4d72618e-93af-4d25-9d63-62888ce2e4f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605262828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3605262828
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.1625695173
Short name T187
Test name
Test status
Simulation time 52952802 ps
CPU time 0.85 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:22 PM PDT 24
Peak memory 201124 kb
Host smart-b919f4b3-2d8d-40a4-a45c-6795b1573208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625695173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1625695173
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.449237591
Short name T410
Test name
Test status
Simulation time 697242113 ps
CPU time 3.39 seconds
Started Jul 30 06:25:14 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201280 kb
Host smart-0baf2288-4dbd-4db6-927d-6f8f6b3e5f6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449237591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.449237591
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2563541965
Short name T130
Test name
Test status
Simulation time 79584621 ps
CPU time 1.01 seconds
Started Jul 30 06:25:13 PM PDT 24
Finished Jul 30 06:25:14 PM PDT 24
Peak memory 201028 kb
Host smart-f7bc9005-6651-48b6-be22-957cee830913
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563541965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2563541965
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3818381346
Short name T607
Test name
Test status
Simulation time 1393997288 ps
CPU time 8.43 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201372 kb
Host smart-5ccea814-a3ae-4ab4-a61b-34be9ebf65cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818381346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3818381346
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.2920676965
Short name T618
Test name
Test status
Simulation time 23577524 ps
CPU time 0.87 seconds
Started Jul 30 06:25:12 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201036 kb
Host smart-88c20d75-5abc-4b94-b060-591965e69311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920676965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.2920676965
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2946812544
Short name T515
Test name
Test status
Simulation time 39074321 ps
CPU time 0.81 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201040 kb
Host smart-91e9b2bc-992c-4927-9114-4b6326003398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946812544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2946812544
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.4028543157
Short name T302
Test name
Test status
Simulation time 54570697 ps
CPU time 0.92 seconds
Started Jul 30 06:25:19 PM PDT 24
Finished Jul 30 06:25:20 PM PDT 24
Peak memory 201088 kb
Host smart-237a9d62-83aa-4e6b-a217-0fa064f6a6cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028543157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.4028543157
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.33030434
Short name T311
Test name
Test status
Simulation time 25584833 ps
CPU time 0.75 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 200304 kb
Host smart-05f5dde4-9f35-427f-ab31-479744d48729
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.33030434
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.3345419311
Short name T420
Test name
Test status
Simulation time 41829715 ps
CPU time 0.96 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201160 kb
Host smart-fa6f5d08-dc0c-4708-a58f-d4108eb96283
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345419311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.3345419311
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.3532193694
Short name T261
Test name
Test status
Simulation time 209371081 ps
CPU time 1.29 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201004 kb
Host smart-645fe24f-ce30-427b-95b2-d198bfc9539a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532193694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3532193694
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3851968345
Short name T556
Test name
Test status
Simulation time 575902852 ps
CPU time 3.01 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:23 PM PDT 24
Peak memory 201108 kb
Host smart-31cf914e-f0a9-40c9-9fb3-9ad0d383fe85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851968345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3851968345
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.3441347698
Short name T232
Test name
Test status
Simulation time 2303677058 ps
CPU time 11.54 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201472 kb
Host smart-e418330e-f51f-44e7-816f-7afbb63f213a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441347698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.3441347698
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2111946528
Short name T565
Test name
Test status
Simulation time 23182316 ps
CPU time 0.87 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201092 kb
Host smart-40c55369-4230-4fdf-a7dd-4a9ec21a2c4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111946528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2111946528
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.469692630
Short name T431
Test name
Test status
Simulation time 26146173 ps
CPU time 0.88 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:23 PM PDT 24
Peak memory 201032 kb
Host smart-3146e1bb-bf4f-4df4-95f9-9e84bc35250b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469692630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.469692630
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.803323825
Short name T654
Test name
Test status
Simulation time 51161207 ps
CPU time 0.89 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 201088 kb
Host smart-3ff54bf8-8494-4eee-bc0b-2101966c3d5a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803323825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_ctrl_intersig_mubi.803323825
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.2544934510
Short name T648
Test name
Test status
Simulation time 34081969 ps
CPU time 0.78 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201096 kb
Host smart-bdf44454-70b5-4733-9f33-b2aa9e2f2f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544934510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2544934510
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2614812176
Short name T598
Test name
Test status
Simulation time 1251116063 ps
CPU time 5.73 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201340 kb
Host smart-f925944c-c117-4c7b-a239-9effae4dcb2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614812176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2614812176
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2816939864
Short name T167
Test name
Test status
Simulation time 29948728 ps
CPU time 0.86 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:18 PM PDT 24
Peak memory 201076 kb
Host smart-a8d76509-970c-46c6-848f-8af035b6a001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816939864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2816939864
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2680990544
Short name T768
Test name
Test status
Simulation time 4065286558 ps
CPU time 18.52 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201476 kb
Host smart-fa8139b7-509e-44be-9182-0cc8c04ed17c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680990544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2680990544
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1094569392
Short name T143
Test name
Test status
Simulation time 21842516971 ps
CPU time 328.5 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:30:48 PM PDT 24
Peak memory 209812 kb
Host smart-b9066d5c-f1f2-4cd8-9f0e-ad060421f9a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1094569392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1094569392
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.903055596
Short name T733
Test name
Test status
Simulation time 205986248 ps
CPU time 1.39 seconds
Started Jul 30 06:25:31 PM PDT 24
Finished Jul 30 06:25:33 PM PDT 24
Peak memory 201068 kb
Host smart-020d8e8b-4ca6-483d-8b7c-4e9e758d1546
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903055596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.903055596
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.3986224299
Short name T180
Test name
Test status
Simulation time 13520358 ps
CPU time 0.76 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:22 PM PDT 24
Peak memory 201124 kb
Host smart-07e5ac9b-02ff-4643-be61-868ec857491d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986224299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.3986224299
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.3231845121
Short name T82
Test name
Test status
Simulation time 83737393 ps
CPU time 1.05 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201044 kb
Host smart-a9ff5946-2889-457e-9f2a-ed85f08d76c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231845121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.3231845121
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.2432584985
Short name T482
Test name
Test status
Simulation time 11636116 ps
CPU time 0.69 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 200260 kb
Host smart-5aaee425-4307-4dd8-ac88-f4c5995cad81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432584985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2432584985
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1116206279
Short name T243
Test name
Test status
Simulation time 39439258 ps
CPU time 0.86 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201084 kb
Host smart-697da666-4910-4f23-9884-44f0b8e0a5c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116206279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1116206279
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.3562373814
Short name T231
Test name
Test status
Simulation time 24521163 ps
CPU time 0.9 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:22 PM PDT 24
Peak memory 201040 kb
Host smart-cb81de24-db10-433f-a920-6e2cb6d3212d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562373814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3562373814
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1741392777
Short name T358
Test name
Test status
Simulation time 1885124933 ps
CPU time 10.71 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201320 kb
Host smart-4d0fd586-65c8-4fde-a2eb-7492f8149888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741392777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1741392777
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.4124676210
Short name T312
Test name
Test status
Simulation time 737897862 ps
CPU time 5.35 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201272 kb
Host smart-ddcbdc4b-d2b4-443b-8c76-f45742d9842e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124676210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.4124676210
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1481025376
Short name T276
Test name
Test status
Simulation time 30829803 ps
CPU time 0.84 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201080 kb
Host smart-f6a45c47-d522-42b0-9b16-cc973a6cb1d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481025376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1481025376
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.626695980
Short name T647
Test name
Test status
Simulation time 86507621 ps
CPU time 1.06 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201148 kb
Host smart-4a98a678-eef9-4cd9-9afd-f84bf925e2c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626695980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.clkmgr_lc_clk_byp_req_intersig_mubi.626695980
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2893749023
Short name T479
Test name
Test status
Simulation time 24726661 ps
CPU time 0.87 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201032 kb
Host smart-ef60285a-7a59-436b-8a9c-9d6bf78966b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893749023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2893749023
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2135322512
Short name T624
Test name
Test status
Simulation time 13507043 ps
CPU time 0.8 seconds
Started Jul 30 06:25:18 PM PDT 24
Finished Jul 30 06:25:19 PM PDT 24
Peak memory 201048 kb
Host smart-8e9b3719-9b19-4c1e-a4cb-0aba2802a9a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135322512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2135322512
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.767996979
Short name T514
Test name
Test status
Simulation time 1018874402 ps
CPU time 4.63 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201248 kb
Host smart-93e7d93a-0572-42fd-98f7-f27de8cd80b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767996979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.767996979
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.4289783723
Short name T162
Test name
Test status
Simulation time 18675268 ps
CPU time 0.85 seconds
Started Jul 30 06:25:20 PM PDT 24
Finished Jul 30 06:25:21 PM PDT 24
Peak memory 201048 kb
Host smart-d6f15235-3055-4143-9070-9619c7513d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289783723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.4289783723
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1406667774
Short name T304
Test name
Test status
Simulation time 7280344870 ps
CPU time 26 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201368 kb
Host smart-f1c02c97-2f84-4441-9be2-836895a371f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406667774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1406667774
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.790945360
Short name T157
Test name
Test status
Simulation time 138297737459 ps
CPU time 888.19 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:40:15 PM PDT 24
Peak memory 217956 kb
Host smart-0ed14afb-80a6-458e-a595-3c5910d54432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=790945360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.790945360
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.1732653439
Short name T403
Test name
Test status
Simulation time 42981284 ps
CPU time 0.95 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201028 kb
Host smart-ce45b78d-e2e4-404a-b17b-ad35c95d8023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732653439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1732653439
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.2437082304
Short name T360
Test name
Test status
Simulation time 14994243 ps
CPU time 0.76 seconds
Started Jul 30 06:25:21 PM PDT 24
Finished Jul 30 06:25:22 PM PDT 24
Peak memory 201120 kb
Host smart-82fc25d4-2a30-41c2-a04e-85b9d8737e97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437082304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.2437082304
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.820992238
Short name T701
Test name
Test status
Simulation time 47017699 ps
CPU time 0.96 seconds
Started Jul 30 06:25:28 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201136 kb
Host smart-7eced5ed-6c1f-46db-9f83-62e1eafe53f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820992238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.820992238
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.871997934
Short name T305
Test name
Test status
Simulation time 15728654 ps
CPU time 0.73 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 200268 kb
Host smart-1b80dc74-4133-463e-b7c8-78ce948e0c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871997934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.871997934
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.2724068021
Short name T510
Test name
Test status
Simulation time 129854304 ps
CPU time 1.18 seconds
Started Jul 30 06:25:29 PM PDT 24
Finished Jul 30 06:25:30 PM PDT 24
Peak memory 201100 kb
Host smart-c89d1c73-20cb-42bc-935d-85ea69a70339
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724068021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.2724068021
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.699614127
Short name T806
Test name
Test status
Simulation time 38195828 ps
CPU time 0.88 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201120 kb
Host smart-df89ff7b-cdcf-49d7-858c-5da7cf6ba313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699614127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.699614127
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3112515481
Short name T445
Test name
Test status
Simulation time 387842188 ps
CPU time 2.11 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201108 kb
Host smart-defa22cb-f355-4271-9117-86186bebc78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112515481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3112515481
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1588936522
Short name T512
Test name
Test status
Simulation time 1916707025 ps
CPU time 8.11 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:31 PM PDT 24
Peak memory 201196 kb
Host smart-3c52c994-9c64-4427-bc11-09bd2c3cc690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588936522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1588936522
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.3920401516
Short name T799
Test name
Test status
Simulation time 37605234 ps
CPU time 0.96 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201056 kb
Host smart-14946a2e-426f-44d1-8896-3d9763c11742
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920401516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.3920401516
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.3371067435
Short name T318
Test name
Test status
Simulation time 13786920 ps
CPU time 0.8 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 200744 kb
Host smart-6fd0e74b-0038-40ac-a806-e9f8774450a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371067435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.3371067435
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.1001808016
Short name T782
Test name
Test status
Simulation time 58854669 ps
CPU time 0.89 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:25:23 PM PDT 24
Peak memory 201108 kb
Host smart-86a7fdad-f983-4acd-9cb1-3af1f41cba39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001808016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.1001808016
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.856590043
Short name T562
Test name
Test status
Simulation time 16582265 ps
CPU time 0.73 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201048 kb
Host smart-11f42ab7-ed32-41e5-988a-01f3b77b4884
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856590043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.856590043
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.3266712892
Short name T326
Test name
Test status
Simulation time 1250974364 ps
CPU time 5.51 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201212 kb
Host smart-27c25cf8-d73d-42a2-91fa-74e8790f82de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266712892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.3266712892
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.666365136
Short name T127
Test name
Test status
Simulation time 26268487 ps
CPU time 0.9 seconds
Started Jul 30 06:25:30 PM PDT 24
Finished Jul 30 06:25:31 PM PDT 24
Peak memory 201088 kb
Host smart-78c104b8-db5e-4862-8587-66677723da61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666365136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.666365136
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.585922303
Short name T703
Test name
Test status
Simulation time 7251973292 ps
CPU time 49.08 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:26:13 PM PDT 24
Peak memory 201520 kb
Host smart-96b58b0b-107a-48bd-a4f1-a723e8e48266
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585922303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.585922303
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.1195091167
Short name T550
Test name
Test status
Simulation time 21452665 ps
CPU time 0.85 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201056 kb
Host smart-994ffb8e-5bcb-487e-9270-420260f38e57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195091167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1195091167
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.2405846044
Short name T522
Test name
Test status
Simulation time 49989674 ps
CPU time 0.89 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 201012 kb
Host smart-1845d87d-e450-4c1c-945e-9368a0d2a6ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405846044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.2405846044
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1362727319
Short name T452
Test name
Test status
Simulation time 71106461 ps
CPU time 1.06 seconds
Started Jul 30 06:24:43 PM PDT 24
Finished Jul 30 06:24:45 PM PDT 24
Peak memory 201068 kb
Host smart-2ec23bb5-0928-4355-8d84-72781e767bd4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362727319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1362727319
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2273449230
Short name T36
Test name
Test status
Simulation time 46929315 ps
CPU time 0.82 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 200284 kb
Host smart-d7b9359a-c9e5-4b42-ba68-5062da8f8c43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273449230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2273449230
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.1230570724
Short name T542
Test name
Test status
Simulation time 78490609 ps
CPU time 1.03 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201132 kb
Host smart-461aeaa8-1d42-47cc-95fa-1b6cc4f23e84
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230570724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.1230570724
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1127805628
Short name T73
Test name
Test status
Simulation time 17436975 ps
CPU time 0.81 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 201044 kb
Host smart-b56ac158-6ca9-4a94-9d44-889c27ee8842
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127805628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1127805628
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.3506304114
Short name T706
Test name
Test status
Simulation time 1400446504 ps
CPU time 11.17 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:52 PM PDT 24
Peak memory 201156 kb
Host smart-a702e5b5-5949-4b5b-a8f2-bdd88ec501a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506304114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3506304114
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.2585035138
Short name T166
Test name
Test status
Simulation time 1814357986 ps
CPU time 12.45 seconds
Started Jul 30 06:24:42 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201160 kb
Host smart-fbb7fb23-3de3-45be-b187-4c5b0d063ea0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585035138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.2585035138
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.372121800
Short name T653
Test name
Test status
Simulation time 30358893 ps
CPU time 0.82 seconds
Started Jul 30 06:24:43 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 201076 kb
Host smart-69d44b17-c4cc-4fd2-8529-d80fa1440dd9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372121800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_idle_intersig_mubi.372121800
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3238298502
Short name T683
Test name
Test status
Simulation time 225940720 ps
CPU time 1.41 seconds
Started Jul 30 06:24:42 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 201148 kb
Host smart-d10e81fd-30fb-4ba7-84bc-4b4671e837df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238298502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.3238298502
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1711226180
Short name T776
Test name
Test status
Simulation time 90725674 ps
CPU time 1.09 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201024 kb
Host smart-bd2410c5-8a27-430a-9090-8b5bb2643e85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711226180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.1711226180
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2508720366
Short name T415
Test name
Test status
Simulation time 45549926 ps
CPU time 0.83 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 201116 kb
Host smart-b6ffd7d9-9725-4f25-8fc1-4df0ca7e5473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508720366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2508720366
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1626833929
Short name T594
Test name
Test status
Simulation time 1158585554 ps
CPU time 4.59 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201252 kb
Host smart-39d85b07-5d51-4763-8ef7-b4ffaace39b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626833929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1626833929
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.2048712781
Short name T589
Test name
Test status
Simulation time 61899283 ps
CPU time 1.02 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201028 kb
Host smart-7da46936-cf67-4241-9cdb-61016878963e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048712781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2048712781
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.4250849626
Short name T667
Test name
Test status
Simulation time 13154079859 ps
CPU time 54.93 seconds
Started Jul 30 06:24:43 PM PDT 24
Finished Jul 30 06:25:38 PM PDT 24
Peak memory 201484 kb
Host smart-6724f7cb-c70c-4345-be41-8330288323b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250849626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.4250849626
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.300325780
Short name T544
Test name
Test status
Simulation time 284615000 ps
CPU time 1.73 seconds
Started Jul 30 06:24:42 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 201092 kb
Host smart-ab673191-77b0-4a6e-85a5-dc37b50cd118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300325780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.300325780
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3526555303
Short name T472
Test name
Test status
Simulation time 16815438 ps
CPU time 0.74 seconds
Started Jul 30 06:25:28 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201104 kb
Host smart-c44e5beb-33b5-46ba-aa14-badd3e769cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526555303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3526555303
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2210208370
Short name T80
Test name
Test status
Simulation time 27342554 ps
CPU time 0.85 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201040 kb
Host smart-c24f90f8-0ed9-4ec9-b187-5b2198d9fe4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210208370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.2210208370
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.2044078410
Short name T378
Test name
Test status
Simulation time 13659809 ps
CPU time 0.73 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 200332 kb
Host smart-e2fe3ce5-e6a6-4959-acef-c13eadc0e079
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044078410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.2044078410
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.4269264739
Short name T593
Test name
Test status
Simulation time 42441911 ps
CPU time 0.94 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 200772 kb
Host smart-6ca35900-2f87-4a10-88b3-99788313270c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269264739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.4269264739
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3790477165
Short name T508
Test name
Test status
Simulation time 30046257 ps
CPU time 0.84 seconds
Started Jul 30 06:25:31 PM PDT 24
Finished Jul 30 06:25:32 PM PDT 24
Peak memory 201132 kb
Host smart-ff07cf77-a475-4cda-a5b9-270b0cc15289
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790477165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3790477165
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.2855462123
Short name T465
Test name
Test status
Simulation time 1637360477 ps
CPU time 12.16 seconds
Started Jul 30 06:25:32 PM PDT 24
Finished Jul 30 06:25:44 PM PDT 24
Peak memory 201108 kb
Host smart-50050c3e-e067-4664-ae96-a392119dafd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855462123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2855462123
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.3859828996
Short name T308
Test name
Test status
Simulation time 2318305510 ps
CPU time 9.94 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201396 kb
Host smart-a301ba33-d032-4424-afb1-42d44bb4e39b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859828996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.3859828996
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.258328064
Short name T159
Test name
Test status
Simulation time 45877245 ps
CPU time 0.9 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201144 kb
Host smart-ba9bca6b-58a0-4164-85cf-a2e4179b6fd9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258328064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.258328064
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.3156532932
Short name T258
Test name
Test status
Simulation time 35899941 ps
CPU time 0.89 seconds
Started Jul 30 06:25:23 PM PDT 24
Finished Jul 30 06:25:24 PM PDT 24
Peak memory 201036 kb
Host smart-5c871387-4594-4267-9d3a-e84d77f4ddf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156532932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.3156532932
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3738629250
Short name T212
Test name
Test status
Simulation time 88787770 ps
CPU time 0.95 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201000 kb
Host smart-58a7c355-5931-4bd0-97fe-aea2eca2af07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738629250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3738629250
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.2752599756
Short name T762
Test name
Test status
Simulation time 22633326 ps
CPU time 0.78 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201064 kb
Host smart-a2c248fc-732e-4a1b-817b-b0c59f4b6dea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752599756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.2752599756
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.4144734451
Short name T346
Test name
Test status
Simulation time 911568002 ps
CPU time 3.96 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:30 PM PDT 24
Peak memory 201016 kb
Host smart-4c5e420b-41e0-4d33-bea5-02f73818c4dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144734451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.4144734451
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.2034971488
Short name T780
Test name
Test status
Simulation time 17788850 ps
CPU time 0.82 seconds
Started Jul 30 06:25:24 PM PDT 24
Finished Jul 30 06:25:25 PM PDT 24
Peak memory 201092 kb
Host smart-cdeace66-0ce8-44a7-8d2b-551de90897f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034971488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.2034971488
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.2772229547
Short name T485
Test name
Test status
Simulation time 13541043488 ps
CPU time 56.44 seconds
Started Jul 30 06:25:22 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201436 kb
Host smart-e550bf24-ebab-4f5e-a4eb-91b6bb236860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772229547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.2772229547
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.4142400185
Short name T676
Test name
Test status
Simulation time 15697744 ps
CPU time 0.74 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201040 kb
Host smart-732294a0-9e7a-4914-bb04-af69d0e25fd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142400185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.4142400185
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.94385992
Short name T773
Test name
Test status
Simulation time 12862151 ps
CPU time 0.72 seconds
Started Jul 30 06:25:28 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201068 kb
Host smart-e16d1c08-93e7-4f78-92b0-a68d0fe474d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94385992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmg
r_alert_test.94385992
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3449191189
Short name T665
Test name
Test status
Simulation time 18861471 ps
CPU time 0.8 seconds
Started Jul 30 06:25:28 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201160 kb
Host smart-28f6416a-e811-431a-8647-edb241710b1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449191189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.3449191189
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.1199552829
Short name T147
Test name
Test status
Simulation time 45136082 ps
CPU time 0.79 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 200976 kb
Host smart-05779d63-c11c-4f08-a7cb-91d5fe8779cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199552829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.1199552829
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1806031491
Short name T414
Test name
Test status
Simulation time 49884642 ps
CPU time 0.83 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201044 kb
Host smart-5eb753e9-1399-4c48-9cb8-c3d8c50ac9d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806031491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1806031491
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2807182820
Short name T179
Test name
Test status
Simulation time 16691847 ps
CPU time 0.77 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201068 kb
Host smart-ea69e78a-d872-4665-b282-dfc9f4c08b9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807182820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2807182820
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.2363759944
Short name T779
Test name
Test status
Simulation time 680464024 ps
CPU time 5.62 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:33 PM PDT 24
Peak memory 201140 kb
Host smart-e7f91c09-5938-40ad-a12c-f7a363fd26d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363759944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.2363759944
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3890099691
Short name T670
Test name
Test status
Simulation time 858312243 ps
CPU time 4.74 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:32 PM PDT 24
Peak memory 201216 kb
Host smart-e07a51ae-4b54-460d-bd02-94bcfef1bc08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890099691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3890099691
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3672403776
Short name T516
Test name
Test status
Simulation time 22001354 ps
CPU time 0.78 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:28 PM PDT 24
Peak memory 201080 kb
Host smart-28696898-e83c-4b25-8243-88eee5ede64e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672403776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.3672403776
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3057935424
Short name T783
Test name
Test status
Simulation time 80751670 ps
CPU time 1.01 seconds
Started Jul 30 06:25:30 PM PDT 24
Finished Jul 30 06:25:31 PM PDT 24
Peak memory 201016 kb
Host smart-6e304109-0c5b-417b-8c9d-7b29bb6fec41
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057935424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.3057935424
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.4167895727
Short name T321
Test name
Test status
Simulation time 18023923 ps
CPU time 0.81 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201096 kb
Host smart-1a216cbb-478e-450d-ae83-ce78b33db167
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167895727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.4167895727
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.646197768
Short name T642
Test name
Test status
Simulation time 34846994 ps
CPU time 0.86 seconds
Started Jul 30 06:25:37 PM PDT 24
Finished Jul 30 06:25:38 PM PDT 24
Peak memory 201080 kb
Host smart-4eab2853-49c8-41ae-ae11-c7abd8e5efec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646197768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.646197768
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.3058442734
Short name T412
Test name
Test status
Simulation time 1132238352 ps
CPU time 5.41 seconds
Started Jul 30 06:25:27 PM PDT 24
Finished Jul 30 06:25:33 PM PDT 24
Peak memory 201264 kb
Host smart-26ad17cd-c6b7-4b1a-9b87-2e343624dea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058442734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.3058442734
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1521149644
Short name T310
Test name
Test status
Simulation time 16579328 ps
CPU time 0.82 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201080 kb
Host smart-06ca1cfc-55ad-4dc3-ad5a-210b45803373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521149644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1521149644
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.20952724
Short name T705
Test name
Test status
Simulation time 3316483526 ps
CPU time 24.18 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201456 kb
Host smart-dbbfdbfa-87a5-4f6b-8308-3e621c68b07e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20952724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_stress_all.20952724
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.1078890727
Short name T590
Test name
Test status
Simulation time 25383296 ps
CPU time 0.76 seconds
Started Jul 30 06:25:28 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201060 kb
Host smart-c0f5ac9e-128b-42c0-960e-f686ebe8bd5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078890727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.1078890727
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.3212491757
Short name T564
Test name
Test status
Simulation time 57167128 ps
CPU time 0.96 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201056 kb
Host smart-07364243-c8fe-4ab0-9d90-b1e51cc0f812
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212491757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.3212491757
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1863853018
Short name T299
Test name
Test status
Simulation time 26300637 ps
CPU time 0.84 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201076 kb
Host smart-a9d257a8-183a-435a-ba09-5d39c2aabf34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863853018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1863853018
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3820107380
Short name T315
Test name
Test status
Simulation time 19460722 ps
CPU time 0.78 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 200952 kb
Host smart-4fb032bc-32f2-4fd5-ac0e-c56cce2ab5f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820107380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3820107380
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.722846036
Short name T307
Test name
Test status
Simulation time 64149934 ps
CPU time 0.95 seconds
Started Jul 30 06:25:33 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201048 kb
Host smart-86d2ab0c-baca-4b37-8b3c-9b18b81c2dc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722846036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_div_intersig_mubi.722846036
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1121388168
Short name T262
Test name
Test status
Simulation time 22888445 ps
CPU time 0.83 seconds
Started Jul 30 06:25:25 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201124 kb
Host smart-f3ec4c0c-bcb6-4fde-a292-3c42f5ba4dfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121388168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1121388168
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.821729328
Short name T102
Test name
Test status
Simulation time 236938974 ps
CPU time 1.54 seconds
Started Jul 30 06:25:31 PM PDT 24
Finished Jul 30 06:25:32 PM PDT 24
Peak memory 201164 kb
Host smart-a14e3b0a-105a-4908-8643-e32f8117cee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821729328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.821729328
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.2917385460
Short name T168
Test name
Test status
Simulation time 638198653 ps
CPU time 3.27 seconds
Started Jul 30 06:25:33 PM PDT 24
Finished Jul 30 06:25:36 PM PDT 24
Peak memory 201220 kb
Host smart-85e6da5f-071d-4a1e-9320-a74be346a9ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917385460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.2917385460
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.1733763141
Short name T789
Test name
Test status
Simulation time 17540128 ps
CPU time 0.87 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201040 kb
Host smart-34b02546-b773-41fb-a2fd-2e96e355d0ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733763141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.1733763141
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.122395106
Short name T437
Test name
Test status
Simulation time 23626328 ps
CPU time 0.88 seconds
Started Jul 30 06:25:29 PM PDT 24
Finished Jul 30 06:25:30 PM PDT 24
Peak memory 201080 kb
Host smart-0e3980a0-57d0-4af9-94f0-09df36824c6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122395106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_clk_byp_req_intersig_mubi.122395106
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.487511855
Short name T295
Test name
Test status
Simulation time 134592422 ps
CPU time 1.22 seconds
Started Jul 30 06:25:32 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201052 kb
Host smart-c18fb2bd-e2a4-4c2c-bf4b-f0d2fd2d061a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487511855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_ctrl_intersig_mubi.487511855
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.2158305142
Short name T137
Test name
Test status
Simulation time 15545143 ps
CPU time 0.74 seconds
Started Jul 30 06:25:32 PM PDT 24
Finished Jul 30 06:25:33 PM PDT 24
Peak memory 201068 kb
Host smart-490c4e45-6589-47b8-a907-a3c962a8c16a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158305142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.2158305142
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.1433012106
Short name T511
Test name
Test status
Simulation time 1125380006 ps
CPU time 4.95 seconds
Started Jul 30 06:25:30 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201248 kb
Host smart-d2ef121b-c146-4ee0-b1ba-3e8d0bfdfc8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433012106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1433012106
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.4286702662
Short name T604
Test name
Test status
Simulation time 20872153 ps
CPU time 0.86 seconds
Started Jul 30 06:25:26 PM PDT 24
Finished Jul 30 06:25:27 PM PDT 24
Peak memory 201076 kb
Host smart-547726b7-5e25-4f23-ad8a-e58760d7c25a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286702662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.4286702662
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.1870689703
Short name T790
Test name
Test status
Simulation time 5040608739 ps
CPU time 34.9 seconds
Started Jul 30 06:25:30 PM PDT 24
Finished Jul 30 06:26:05 PM PDT 24
Peak memory 201452 kb
Host smart-c7ad2e3c-88dc-4d38-b54e-f93df6179bd7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870689703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.1870689703
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1379031188
Short name T35
Test name
Test status
Simulation time 114227349923 ps
CPU time 681.69 seconds
Started Jul 30 06:25:32 PM PDT 24
Finished Jul 30 06:36:54 PM PDT 24
Peak memory 217916 kb
Host smart-0e54e3cb-d5ac-4a71-ab32-b830e7738f09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1379031188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1379031188
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.819470770
Short name T419
Test name
Test status
Simulation time 16075231 ps
CPU time 0.74 seconds
Started Jul 30 06:25:33 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201052 kb
Host smart-b9b876e8-e94f-4021-8134-c6b47f0becf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819470770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.819470770
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.3478124329
Short name T182
Test name
Test status
Simulation time 20298271 ps
CPU time 0.8 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201096 kb
Host smart-4e7fcbfe-f073-404f-ad3f-9b398c7a21dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478124329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.3478124329
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2628912501
Short name T527
Test name
Test status
Simulation time 51364566 ps
CPU time 1.05 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:37 PM PDT 24
Peak memory 201272 kb
Host smart-90570a12-2335-4571-804d-7fde88c77a2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628912501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2628912501
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3451020032
Short name T335
Test name
Test status
Simulation time 18431656 ps
CPU time 0.72 seconds
Started Jul 30 06:25:35 PM PDT 24
Finished Jul 30 06:25:36 PM PDT 24
Peak memory 201032 kb
Host smart-dea68d4b-1633-4606-8061-e83106f418cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451020032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3451020032
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2778697702
Short name T386
Test name
Test status
Simulation time 122937413 ps
CPU time 1.13 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201028 kb
Host smart-8d390f39-dd50-4958-b76a-ff599db1106b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778697702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2778697702
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.3846155426
Short name T323
Test name
Test status
Simulation time 53182206 ps
CPU time 0.82 seconds
Started Jul 30 06:25:33 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201008 kb
Host smart-25176954-2efd-45c0-9e0e-c87bd258d3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846155426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3846155426
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.1433801756
Short name T662
Test name
Test status
Simulation time 439002421 ps
CPU time 3.92 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201104 kb
Host smart-aa75b38c-7343-4741-a3a0-a6e6d9dfabea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433801756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1433801756
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.1308900583
Short name T740
Test name
Test status
Simulation time 379604096 ps
CPU time 3.31 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201160 kb
Host smart-e727fd29-4916-4604-9165-02addb306604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308900583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.1308900583
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2007476497
Short name T488
Test name
Test status
Simulation time 33851303 ps
CPU time 1 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201088 kb
Host smart-170ebc4c-7f5c-47d9-94dc-aecc8e08e4ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007476497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.2007476497
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3679397987
Short name T417
Test name
Test status
Simulation time 89783036 ps
CPU time 1.01 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201056 kb
Host smart-3cfd45f0-cf60-447e-8f31-4dd1be64057d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679397987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3679397987
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2143935624
Short name T744
Test name
Test status
Simulation time 23516871 ps
CPU time 0.78 seconds
Started Jul 30 06:25:33 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201128 kb
Host smart-27796044-51b7-4bb2-9359-f8147c0fd192
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143935624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2143935624
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1477036160
Short name T690
Test name
Test status
Simulation time 25719660 ps
CPU time 0.77 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:34 PM PDT 24
Peak memory 201088 kb
Host smart-99a1204a-726d-4f3d-a2ba-ea45d16b987b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477036160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1477036160
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.759770708
Short name T793
Test name
Test status
Simulation time 837425672 ps
CPU time 4.85 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201332 kb
Host smart-e778039f-e68a-4f68-95a2-4e370de7019a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759770708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.759770708
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.602834799
Short name T755
Test name
Test status
Simulation time 23892208 ps
CPU time 0.89 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201028 kb
Host smart-9c7d435f-c593-4653-9198-fad879dbb182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602834799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.602834799
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.401995582
Short name T34
Test name
Test status
Simulation time 1078960475 ps
CPU time 7.25 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201372 kb
Host smart-2f3ee4fb-1e74-4f5e-9ec9-40c643bbae5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401995582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.401995582
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2869407947
Short name T142
Test name
Test status
Simulation time 22300374764 ps
CPU time 333.07 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:31:09 PM PDT 24
Peak memory 209804 kb
Host smart-c657a328-97c3-47df-bd2a-d0690547f9dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2869407947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2869407947
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2520061725
Short name T341
Test name
Test status
Simulation time 34676355 ps
CPU time 1.03 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201092 kb
Host smart-77d167e9-b9ce-4d38-a9b1-7c8a7fd4a7f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520061725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2520061725
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.1877074499
Short name T584
Test name
Test status
Simulation time 51987226 ps
CPU time 0.88 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201076 kb
Host smart-9be4fcf2-2367-47d8-98cb-e1410b43e8d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877074499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.1877074499
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2223821402
Short name T306
Test name
Test status
Simulation time 41651038 ps
CPU time 0.83 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201096 kb
Host smart-fc4872e6-9b0d-4441-bb1d-553fa6ee3b1e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223821402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.2223821402
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3633881819
Short name T397
Test name
Test status
Simulation time 44470117 ps
CPU time 0.82 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:37 PM PDT 24
Peak memory 200936 kb
Host smart-b54b9a5e-cc46-47c9-9ed6-c9cc7fde0d32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633881819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3633881819
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3917782278
Short name T19
Test name
Test status
Simulation time 100872819 ps
CPU time 1.02 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201088 kb
Host smart-b00d2d51-c665-46d7-9851-9b4d195335ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917782278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3917782278
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2050896276
Short name T349
Test name
Test status
Simulation time 13774091 ps
CPU time 0.81 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 200568 kb
Host smart-25a58db4-0d80-45e3-8224-ae287f502d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050896276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2050896276
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3169682369
Short name T636
Test name
Test status
Simulation time 990113954 ps
CPU time 4.78 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201152 kb
Host smart-a9304862-8cf2-4014-8916-b47da2a9f525
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169682369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3169682369
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1386551590
Short name T357
Test name
Test status
Simulation time 2057070431 ps
CPU time 10.37 seconds
Started Jul 30 06:25:35 PM PDT 24
Finished Jul 30 06:25:46 PM PDT 24
Peak memory 201460 kb
Host smart-9a73b30f-2c86-4565-b092-aac1216cad0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386551590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1386551590
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.1866226267
Short name T401
Test name
Test status
Simulation time 30878537 ps
CPU time 0.86 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201072 kb
Host smart-4c21579c-1f7f-431f-95bd-b2f565e97111
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866226267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.1866226267
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1123695429
Short name T518
Test name
Test status
Simulation time 22876566 ps
CPU time 0.79 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201100 kb
Host smart-b306e269-b5e8-4319-938c-f4cf8442df19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123695429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1123695429
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2025795873
Short name T17
Test name
Test status
Simulation time 25198889 ps
CPU time 0.87 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201096 kb
Host smart-e16c2edb-93da-41be-8fef-7044211ce81e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025795873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.2025795873
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.1016958114
Short name T21
Test name
Test status
Simulation time 41483480 ps
CPU time 0.79 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:37 PM PDT 24
Peak memory 201044 kb
Host smart-825952db-55e5-45f0-8210-d643b575bc14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016958114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1016958114
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.437438658
Short name T537
Test name
Test status
Simulation time 859335988 ps
CPU time 3.52 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201292 kb
Host smart-5ea119f8-720f-483f-a262-3c8f8fdd2f4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437438658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.437438658
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.2631878542
Short name T649
Test name
Test status
Simulation time 26405319 ps
CPU time 0.85 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201020 kb
Host smart-3089ccbe-2bc9-4c50-8666-02c48ed103db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631878542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2631878542
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.3334032801
Short name T440
Test name
Test status
Simulation time 2489074081 ps
CPU time 19 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:26:05 PM PDT 24
Peak memory 201444 kb
Host smart-d80b2cfd-981d-4693-8863-b361325431dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334032801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.3334032801
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2529733763
Short name T492
Test name
Test status
Simulation time 61000369 ps
CPU time 0.86 seconds
Started Jul 30 06:25:35 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201052 kb
Host smart-c65e585d-c23b-4ea8-8bcc-5f3d350f521e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529733763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2529733763
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3717353601
Short name T521
Test name
Test status
Simulation time 26300659 ps
CPU time 0.85 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201072 kb
Host smart-51fff3a6-2a3d-4430-a17e-f29031844fd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717353601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3717353601
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1063967381
Short name T185
Test name
Test status
Simulation time 55300129 ps
CPU time 0.89 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201032 kb
Host smart-7c492430-9d43-41d2-9f04-2c8a4d12a298
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063967381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1063967381
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.4274122171
Short name T629
Test name
Test status
Simulation time 22961216 ps
CPU time 0.74 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 200968 kb
Host smart-8d999ea0-943a-42d3-8e5f-66ed6c09251d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274122171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.4274122171
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.69588579
Short name T827
Test name
Test status
Simulation time 26775411 ps
CPU time 0.83 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201064 kb
Host smart-842d2d63-5d33-4a49-ad6d-63b85acc1f03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69588579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.clkmgr_div_intersig_mubi.69588579
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.78923730
Short name T823
Test name
Test status
Simulation time 96002739 ps
CPU time 1.22 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 200652 kb
Host smart-3c9e8686-bcdf-4cbe-af5a-e2811e19552e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78923730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.78923730
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.895905625
Short name T336
Test name
Test status
Simulation time 1876140768 ps
CPU time 14.61 seconds
Started Jul 30 06:25:35 PM PDT 24
Finished Jul 30 06:25:50 PM PDT 24
Peak memory 201300 kb
Host smart-db1d2e92-9917-42e2-94e9-c311a77e91b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895905625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.895905625
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3382887235
Short name T702
Test name
Test status
Simulation time 1120422965 ps
CPU time 5.16 seconds
Started Jul 30 06:25:34 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201184 kb
Host smart-8464d1b0-46b5-4b24-b646-989d118b8061
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382887235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3382887235
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.724066251
Short name T582
Test name
Test status
Simulation time 80252449 ps
CPU time 1.01 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201128 kb
Host smart-c2a30d5e-6f61-4787-8b7a-6cbce5c306e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724066251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_idle_intersig_mubi.724066251
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1927179606
Short name T235
Test name
Test status
Simulation time 65720782 ps
CPU time 1.03 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201104 kb
Host smart-c02733b6-1d10-4259-a137-ab9a0a740364
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927179606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1927179606
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3783158095
Short name T567
Test name
Test status
Simulation time 18791212 ps
CPU time 0.76 seconds
Started Jul 30 06:25:37 PM PDT 24
Finished Jul 30 06:25:38 PM PDT 24
Peak memory 201112 kb
Host smart-c97d8435-c225-494e-b411-1804f8191cb0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783158095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.3783158095
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.1120919423
Short name T464
Test name
Test status
Simulation time 16226487 ps
CPU time 0.82 seconds
Started Jul 30 06:25:37 PM PDT 24
Finished Jul 30 06:25:38 PM PDT 24
Peak memory 201080 kb
Host smart-ff50dcd3-526c-465e-8dba-8de53d8f6d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120919423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1120919423
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.983480865
Short name T255
Test name
Test status
Simulation time 241456184 ps
CPU time 1.41 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201104 kb
Host smart-074d15bf-45f6-409c-9344-0c7f09de12d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983480865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.983480865
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2071746021
Short name T666
Test name
Test status
Simulation time 47196576 ps
CPU time 0.95 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201036 kb
Host smart-4818b864-b110-4d19-9ca8-8445f1969ec2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071746021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2071746021
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.353721225
Short name T520
Test name
Test status
Simulation time 517356526 ps
CPU time 3.08 seconds
Started Jul 30 06:25:36 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201224 kb
Host smart-462090ea-a807-4fbd-9f7a-fbf213be3d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353721225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.353721225
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.1451299214
Short name T29
Test name
Test status
Simulation time 134952701218 ps
CPU time 869.87 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:40:10 PM PDT 24
Peak memory 218000 kb
Host smart-ca3288a1-7f27-40dd-a21b-8593b27180f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1451299214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.1451299214
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.2002279598
Short name T202
Test name
Test status
Simulation time 23168655 ps
CPU time 0.93 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201084 kb
Host smart-5000c27e-4e2e-4d11-942c-c72aedd381a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002279598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2002279598
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3409615298
Short name T24
Test name
Test status
Simulation time 15400958 ps
CPU time 0.77 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201068 kb
Host smart-ef6d4cef-a455-4486-a1e2-256c094303a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409615298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3409615298
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.2535757110
Short name T331
Test name
Test status
Simulation time 23234413 ps
CPU time 0.78 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201036 kb
Host smart-8974c5a4-718e-4737-88fa-a21461705544
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535757110 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.2535757110
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.201191638
Short name T829
Test name
Test status
Simulation time 43782956 ps
CPU time 0.78 seconds
Started Jul 30 06:25:43 PM PDT 24
Finished Jul 30 06:25:44 PM PDT 24
Peak memory 200300 kb
Host smart-9c898e5e-ab71-441a-a791-8adedf2e0c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201191638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.201191638
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.4007956528
Short name T286
Test name
Test status
Simulation time 19373592 ps
CPU time 0.78 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:39 PM PDT 24
Peak memory 201044 kb
Host smart-0faae721-c31d-4e79-b3a1-32cde61a3c23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007956528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.4007956528
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.1737050029
Short name T340
Test name
Test status
Simulation time 82111863 ps
CPU time 1.05 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201116 kb
Host smart-6c5612f2-28c6-44ce-a376-2bb694ec6454
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737050029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.1737050029
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.880613861
Short name T396
Test name
Test status
Simulation time 591025028 ps
CPU time 3.21 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201108 kb
Host smart-fe18def3-b41a-4b14-b92d-144b6136b372
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880613861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.880613861
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1710413919
Short name T161
Test name
Test status
Simulation time 1096464912 ps
CPU time 7.92 seconds
Started Jul 30 06:25:37 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201200 kb
Host smart-c252dfce-3e0a-44e6-bafa-55f50cca6610
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710413919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1710413919
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3279892473
Short name T451
Test name
Test status
Simulation time 278531657 ps
CPU time 1.76 seconds
Started Jul 30 06:25:38 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201144 kb
Host smart-4b2509b0-2067-421c-8cf2-ed163da3c5c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279892473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.3279892473
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3509759868
Short name T504
Test name
Test status
Simulation time 84625340 ps
CPU time 1.06 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:41 PM PDT 24
Peak memory 201020 kb
Host smart-f1c48898-960c-4bb0-b3b5-2e0c72853d02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509759868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3509759868
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.488593423
Short name T586
Test name
Test status
Simulation time 60113065 ps
CPU time 0.96 seconds
Started Jul 30 06:25:43 PM PDT 24
Finished Jul 30 06:25:44 PM PDT 24
Peak memory 201100 kb
Host smart-39d95e7d-3f27-4948-9798-59fdf20a0e64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488593423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 26.clkmgr_lc_ctrl_intersig_mubi.488593423
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.2376995823
Short name T558
Test name
Test status
Simulation time 22086648 ps
CPU time 0.81 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201048 kb
Host smart-4435101b-c53d-4e6c-b319-34df292e2455
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376995823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2376995823
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.3480289564
Short name T549
Test name
Test status
Simulation time 1393781824 ps
CPU time 4.5 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201328 kb
Host smart-3b9cf74d-8f38-4b51-9812-67f349017622
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480289564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3480289564
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.2851185782
Short name T183
Test name
Test status
Simulation time 162749807 ps
CPU time 1.28 seconds
Started Jul 30 06:25:39 PM PDT 24
Finished Jul 30 06:25:40 PM PDT 24
Peak memory 201004 kb
Host smart-073bc4be-33a9-43c2-8b67-86ffd75db77f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851185782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2851185782
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.1794365539
Short name T129
Test name
Test status
Simulation time 2155224590 ps
CPU time 9.57 seconds
Started Jul 30 06:25:45 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201400 kb
Host smart-e7f9f827-5013-40ea-acfd-a1216028fddc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794365539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.1794365539
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.2780177153
Short name T805
Test name
Test status
Simulation time 86669986 ps
CPU time 1.13 seconds
Started Jul 30 06:25:40 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201096 kb
Host smart-9b067d2e-84e8-4700-a861-86d9ffd23fd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780177153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2780177153
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.403294589
Short name T671
Test name
Test status
Simulation time 45297381 ps
CPU time 0.83 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201080 kb
Host smart-0abe88f0-c9f8-47e1-a107-6644f4966fab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403294589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkm
gr_alert_test.403294589
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.2301061459
Short name T626
Test name
Test status
Simulation time 36113983 ps
CPU time 0.88 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201104 kb
Host smart-84f3bd33-3360-4b9e-906f-77e80073b49e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301061459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.2301061459
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.564232182
Short name T739
Test name
Test status
Simulation time 99550968 ps
CPU time 1.02 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 200276 kb
Host smart-5021b702-a3f6-4971-b224-fe287c13f338
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564232182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.564232182
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3697916851
Short name T577
Test name
Test status
Simulation time 303315547 ps
CPU time 1.71 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 201144 kb
Host smart-bcddb4a4-437d-4b23-b5e6-d6e2b060a19a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697916851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3697916851
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.827666864
Short name T688
Test name
Test status
Simulation time 17441554 ps
CPU time 0.84 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 200996 kb
Host smart-392aa3df-dafc-4e4f-9e6d-ef6af9c7d473
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827666864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.827666864
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.286738128
Short name T345
Test name
Test status
Simulation time 1522505266 ps
CPU time 12.57 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:26:03 PM PDT 24
Peak memory 201160 kb
Host smart-04497126-316c-4fba-b9b6-0a21b565b1ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286738128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.286738128
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.4058109500
Short name T752
Test name
Test status
Simulation time 2413516637 ps
CPU time 17.41 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:26:04 PM PDT 24
Peak memory 201392 kb
Host smart-b3f0bedd-56f6-4a0d-a48d-b8d547a8ed57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058109500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.4058109500
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3075269593
Short name T188
Test name
Test status
Simulation time 92428098 ps
CPU time 1.11 seconds
Started Jul 30 06:26:06 PM PDT 24
Finished Jul 30 06:26:07 PM PDT 24
Peak memory 201124 kb
Host smart-7cb325bf-ece4-46af-a5d4-2b5c24b28e5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075269593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3075269593
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.550775713
Short name T745
Test name
Test status
Simulation time 16055619 ps
CPU time 0.76 seconds
Started Jul 30 06:25:42 PM PDT 24
Finished Jul 30 06:25:43 PM PDT 24
Peak memory 201128 kb
Host smart-557359f4-8591-4255-a5c3-e2792fd693ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550775713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_clk_byp_req_intersig_mubi.550775713
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3280144508
Short name T797
Test name
Test status
Simulation time 133676125 ps
CPU time 1.19 seconds
Started Jul 30 06:25:57 PM PDT 24
Finished Jul 30 06:25:58 PM PDT 24
Peak memory 201120 kb
Host smart-24c855f7-d037-4f32-90be-11f7dfe54596
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280144508 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.3280144508
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.693955767
Short name T634
Test name
Test status
Simulation time 26912071 ps
CPU time 0.82 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201112 kb
Host smart-79132485-78f0-4f9c-9a87-e33cdd2c101f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693955767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.693955767
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1199131707
Short name T309
Test name
Test status
Simulation time 139559059 ps
CPU time 1.42 seconds
Started Jul 30 06:25:45 PM PDT 24
Finished Jul 30 06:25:46 PM PDT 24
Peak memory 201072 kb
Host smart-d117f626-5281-4cab-8df2-cb1e9d1155f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199131707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1199131707
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3493051832
Short name T132
Test name
Test status
Simulation time 21681174 ps
CPU time 0.9 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 201064 kb
Host smart-ad508ee5-1cbb-4448-b598-294782e41cad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493051832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3493051832
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.2755412244
Short name T722
Test name
Test status
Simulation time 2136122885 ps
CPU time 9.54 seconds
Started Jul 30 06:25:45 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201328 kb
Host smart-dcbf20ab-282b-4482-88a2-68fddde268f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755412244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.2755412244
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.721340067
Short name T278
Test name
Test status
Simulation time 42970488 ps
CPU time 0.94 seconds
Started Jul 30 06:25:45 PM PDT 24
Finished Jul 30 06:25:46 PM PDT 24
Peak memory 201132 kb
Host smart-c7fe0ec1-3d28-45c4-bec6-f5d7707b3a43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721340067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.721340067
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.2499990455
Short name T734
Test name
Test status
Simulation time 27447048 ps
CPU time 0.81 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201084 kb
Host smart-a4732cb7-6a7f-4074-b98c-c06599fce698
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499990455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.2499990455
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1201571134
Short name T195
Test name
Test status
Simulation time 27116113 ps
CPU time 0.82 seconds
Started Jul 30 06:25:49 PM PDT 24
Finished Jul 30 06:25:50 PM PDT 24
Peak memory 201032 kb
Host smart-9e88e1f3-e53d-44a4-b02b-cb5c6031018a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201571134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.1201571134
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3238616387
Short name T38
Test name
Test status
Simulation time 27663652 ps
CPU time 0.73 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 200248 kb
Host smart-be188b97-66c1-44eb-8ae3-45f7d306d39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238616387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3238616387
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.938294542
Short name T233
Test name
Test status
Simulation time 13907177 ps
CPU time 0.76 seconds
Started Jul 30 06:25:44 PM PDT 24
Finished Jul 30 06:25:45 PM PDT 24
Peak memory 201104 kb
Host smart-189f4837-cc50-4352-872e-a872e5a07e05
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938294542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_div_intersig_mubi.938294542
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.417438958
Short name T822
Test name
Test status
Simulation time 88921956 ps
CPU time 1.02 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201104 kb
Host smart-8e2fd553-6fdf-4c41-80b7-0f2101cb70e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417438958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.417438958
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2859735452
Short name T525
Test name
Test status
Simulation time 442388673 ps
CPU time 4.24 seconds
Started Jul 30 06:25:43 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 201172 kb
Host smart-3a118ae3-0d17-43f9-8b04-58d690b83114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859735452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2859735452
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.3382776248
Short name T377
Test name
Test status
Simulation time 2295589382 ps
CPU time 9.64 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:57 PM PDT 24
Peak memory 201632 kb
Host smart-85a671d0-733c-4d0b-97cd-b4c1d0d625e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382776248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.3382776248
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.2300637971
Short name T551
Test name
Test status
Simulation time 66762446 ps
CPU time 0.95 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 200792 kb
Host smart-d8a66359-2f5e-497d-b8fc-cd767c9816e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300637971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.2300637971
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3171011267
Short name T468
Test name
Test status
Simulation time 21808395 ps
CPU time 0.9 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201100 kb
Host smart-be9d1e1c-7262-42f7-a0e6-4bfcc6b99648
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171011267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3171011267
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3903835004
Short name T573
Test name
Test status
Simulation time 62091103 ps
CPU time 0.96 seconds
Started Jul 30 06:25:57 PM PDT 24
Finished Jul 30 06:25:58 PM PDT 24
Peak memory 201108 kb
Host smart-10ee2ade-b2f3-467c-aec9-b608c300cc7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903835004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.3903835004
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.3800601710
Short name T778
Test name
Test status
Simulation time 23901102 ps
CPU time 0.76 seconds
Started Jul 30 06:25:41 PM PDT 24
Finished Jul 30 06:25:42 PM PDT 24
Peak memory 201020 kb
Host smart-fc1ca290-6a7e-43d0-a877-e840b2fbbfff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800601710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3800601710
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2542907594
Short name T792
Test name
Test status
Simulation time 274758422 ps
CPU time 1.47 seconds
Started Jul 30 06:26:08 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201128 kb
Host smart-141de263-0a5e-4845-a362-e2d9e02faebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542907594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2542907594
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.1052329680
Short name T685
Test name
Test status
Simulation time 20864347 ps
CPU time 0.85 seconds
Started Jul 30 06:25:56 PM PDT 24
Finished Jul 30 06:25:57 PM PDT 24
Peak memory 201108 kb
Host smart-53bea376-ad4d-405a-8262-72f2d96736a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052329680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1052329680
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.462049678
Short name T439
Test name
Test status
Simulation time 27179089403 ps
CPU time 497.97 seconds
Started Jul 30 06:26:03 PM PDT 24
Finished Jul 30 06:34:22 PM PDT 24
Peak memory 217916 kb
Host smart-0d5b487f-749b-451b-86db-62d081a5d6e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=462049678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.462049678
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3148470389
Short name T595
Test name
Test status
Simulation time 108389145 ps
CPU time 1.17 seconds
Started Jul 30 06:26:07 PM PDT 24
Finished Jul 30 06:26:08 PM PDT 24
Peak memory 201108 kb
Host smart-14d07962-184a-4cab-9aa2-14b0a153f4f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148470389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3148470389
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.1916098822
Short name T603
Test name
Test status
Simulation time 59387723 ps
CPU time 0.86 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201084 kb
Host smart-88cedfcd-8a9f-4cb9-b86f-57bd1cd05429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916098822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.1916098822
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3538981932
Short name T75
Test name
Test status
Simulation time 26154791 ps
CPU time 0.92 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201116 kb
Host smart-b1a8ac67-fd6d-4d1f-adf5-bba2dfef2ee0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538981932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3538981932
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.1239330177
Short name T327
Test name
Test status
Simulation time 14973629 ps
CPU time 0.72 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 200316 kb
Host smart-57a1f911-d96f-409d-842e-332a2e9ec670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239330177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1239330177
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3708827576
Short name T623
Test name
Test status
Simulation time 21363084 ps
CPU time 0.84 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201084 kb
Host smart-b89497db-2a10-4d21-92b0-47250c59e302
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708827576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.3708827576
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.916182979
Short name T700
Test name
Test status
Simulation time 57939145 ps
CPU time 0.96 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201096 kb
Host smart-bde1b787-e6b7-4463-9aa9-510bf9b64398
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916182979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.916182979
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.4232685870
Short name T3
Test name
Test status
Simulation time 556003210 ps
CPU time 4.82 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201156 kb
Host smart-1afbc525-a441-41a4-9b36-c1b49e050037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232685870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.4232685870
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3178992095
Short name T350
Test name
Test status
Simulation time 2062695563 ps
CPU time 10.89 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:58 PM PDT 24
Peak memory 201348 kb
Host smart-3f14f024-be1c-41b0-a923-64ec6d0ec3ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178992095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3178992095
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1143467873
Short name T344
Test name
Test status
Simulation time 44455294 ps
CPU time 0.82 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 201028 kb
Host smart-ea16b584-9075-47e0-ae27-8915be00033b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143467873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.1143467873
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2727869545
Short name T376
Test name
Test status
Simulation time 18914427 ps
CPU time 0.87 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201060 kb
Host smart-849d65b8-60b6-4c8c-87d0-9340b8794ce7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727869545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2727869545
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.1541051564
Short name T338
Test name
Test status
Simulation time 25593641 ps
CPU time 0.88 seconds
Started Jul 30 06:25:49 PM PDT 24
Finished Jul 30 06:25:50 PM PDT 24
Peak memory 201080 kb
Host smart-4a1e924c-0492-4ec0-97af-cbeef959718f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541051564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.1541051564
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2366817784
Short name T751
Test name
Test status
Simulation time 16663133 ps
CPU time 0.74 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:53 PM PDT 24
Peak memory 201128 kb
Host smart-5d79ca8b-592b-4db9-95b0-3588708a6742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366817784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2366817784
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.397720609
Short name T176
Test name
Test status
Simulation time 1121248258 ps
CPU time 4.27 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201252 kb
Host smart-d5beee96-f663-4e7f-899a-f9148c416d53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397720609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.397720609
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.35530577
Short name T473
Test name
Test status
Simulation time 36822747 ps
CPU time 0.88 seconds
Started Jul 30 06:25:45 PM PDT 24
Finished Jul 30 06:25:46 PM PDT 24
Peak memory 201056 kb
Host smart-d15cdc0d-6c0d-449f-85a7-bbf6a53d658a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35530577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.35530577
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.489699818
Short name T189
Test name
Test status
Simulation time 3385422407 ps
CPU time 15.24 seconds
Started Jul 30 06:25:57 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201484 kb
Host smart-2277302e-6422-4843-a19d-8b4a6f9ace88
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489699818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.489699818
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.932891118
Short name T718
Test name
Test status
Simulation time 92150762 ps
CPU time 1.08 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201140 kb
Host smart-51b9210f-32ee-4c97-933b-21515e1e13a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932891118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.932891118
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1445576163
Short name T186
Test name
Test status
Simulation time 26005895 ps
CPU time 0.8 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201096 kb
Host smart-674744de-05bb-44f5-b0a2-df49c3b76b63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445576163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1445576163
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3181681317
Short name T78
Test name
Test status
Simulation time 56577300 ps
CPU time 0.91 seconds
Started Jul 30 06:24:40 PM PDT 24
Finished Jul 30 06:24:40 PM PDT 24
Peak memory 201072 kb
Host smart-1cc2596f-0a9f-4301-ad10-627a92f9fdbf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181681317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3181681317
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.1533366922
Short name T356
Test name
Test status
Simulation time 19320140 ps
CPU time 0.72 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:45 PM PDT 24
Peak memory 200240 kb
Host smart-a571444b-dbee-45cf-84a4-209c7e5a680f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533366922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1533366922
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.619265794
Short name T399
Test name
Test status
Simulation time 89772579 ps
CPU time 1.16 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201092 kb
Host smart-38d3a567-e398-4e96-bb33-ebb2e4bbcc7d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619265794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
.clkmgr_div_intersig_mubi.619265794
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.762079415
Short name T757
Test name
Test status
Simulation time 18430483 ps
CPU time 0.85 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201104 kb
Host smart-00750c1d-6c20-4f53-aa07-0b7e86f62834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762079415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.762079415
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.3561037026
Short name T570
Test name
Test status
Simulation time 1018204071 ps
CPU time 4.38 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201148 kb
Host smart-8d2e37cd-d593-4c0d-b1ba-e37aa13b0804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561037026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3561037026
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.1612110013
Short name T206
Test name
Test status
Simulation time 615407819 ps
CPU time 5.26 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201200 kb
Host smart-a897b13e-d0a4-407d-9de9-837734344141
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612110013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.1612110013
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3017014850
Short name T275
Test name
Test status
Simulation time 82744794 ps
CPU time 1.11 seconds
Started Jul 30 06:24:42 PM PDT 24
Finished Jul 30 06:24:43 PM PDT 24
Peak memory 201064 kb
Host smart-cd98f039-7fd6-4b45-84fd-bdddc036b8b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017014850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3017014850
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3910394227
Short name T244
Test name
Test status
Simulation time 46719219 ps
CPU time 0.87 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201120 kb
Host smart-1e5b47d4-0e3d-4c49-9fad-3d815eea3318
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910394227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.3910394227
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.4182084019
Short name T781
Test name
Test status
Simulation time 53346421 ps
CPU time 0.99 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201128 kb
Host smart-44300401-9ffc-4e08-ae52-9ba12b07e958
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182084019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.4182084019
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.3537350561
Short name T625
Test name
Test status
Simulation time 17754932 ps
CPU time 0.77 seconds
Started Jul 30 06:24:43 PM PDT 24
Finished Jul 30 06:24:44 PM PDT 24
Peak memory 201124 kb
Host smart-3b16bc67-23f9-420c-b56b-fb54a084981a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537350561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.3537350561
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.4081937185
Short name T7
Test name
Test status
Simulation time 1408398754 ps
CPU time 7.22 seconds
Started Jul 30 06:24:46 PM PDT 24
Finished Jul 30 06:24:53 PM PDT 24
Peak memory 201276 kb
Host smart-1cba65f5-9f12-4049-84e6-8958723ee5c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081937185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.4081937185
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.1952369771
Short name T39
Test name
Test status
Simulation time 781143767 ps
CPU time 4.65 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:52 PM PDT 24
Peak memory 217876 kb
Host smart-b2b7e4cb-69ac-444d-883c-6ddbbaac5be1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952369771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.1952369771
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2703383163
Short name T495
Test name
Test status
Simulation time 22524485 ps
CPU time 0.85 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:45 PM PDT 24
Peak memory 201220 kb
Host smart-bfe493bd-8b32-4315-91bb-f683e12c442c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703383163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2703383163
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.2339996523
Short name T267
Test name
Test status
Simulation time 4732847508 ps
CPU time 19.86 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201412 kb
Host smart-d7697e07-0c0c-4d4c-8d0c-cfe5fbe3743d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339996523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.2339996523
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.1832876203
Short name T601
Test name
Test status
Simulation time 19596887 ps
CPU time 0.82 seconds
Started Jul 30 06:24:41 PM PDT 24
Finished Jul 30 06:24:42 PM PDT 24
Peak memory 201060 kb
Host smart-a946f172-2327-4bc8-a450-9e0542309877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832876203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1832876203
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.2584164630
Short name T784
Test name
Test status
Simulation time 23184110 ps
CPU time 0.74 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201092 kb
Host smart-b39cf699-e862-4e72-856e-1c0c84eb3b00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584164630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.2584164630
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.3701412571
Short name T816
Test name
Test status
Simulation time 97262636 ps
CPU time 1.06 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201140 kb
Host smart-4e9d3901-ce6b-49ae-8d8a-9cf7ef09def3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701412571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.3701412571
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.1373873186
Short name T534
Test name
Test status
Simulation time 18138634 ps
CPU time 0.73 seconds
Started Jul 30 06:25:49 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 200332 kb
Host smart-cd2982d2-be51-454e-8ff4-f7bf03ad2849
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373873186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1373873186
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.3107255427
Short name T135
Test name
Test status
Simulation time 61944162 ps
CPU time 0.94 seconds
Started Jul 30 06:25:54 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201092 kb
Host smart-096f903d-8c35-4aec-a689-15dd0fba76e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107255427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.3107255427
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.2133743238
Short name T164
Test name
Test status
Simulation time 26931489 ps
CPU time 0.77 seconds
Started Jul 30 06:25:49 PM PDT 24
Finished Jul 30 06:25:50 PM PDT 24
Peak memory 201084 kb
Host smart-1b9d1c46-6058-4723-a08b-fee88ac867b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133743238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2133743238
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.4262021736
Short name T28
Test name
Test status
Simulation time 1286345530 ps
CPU time 7.77 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:54 PM PDT 24
Peak memory 201148 kb
Host smart-5b27d7a5-ef63-49cb-bb52-c0de18335595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262021736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.4262021736
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2349146999
Short name T631
Test name
Test status
Simulation time 1700755653 ps
CPU time 12.82 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:26:08 PM PDT 24
Peak memory 201388 kb
Host smart-ccdbc0a8-d7be-48ac-a566-8f898ffeab07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349146999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2349146999
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1805634880
Short name T497
Test name
Test status
Simulation time 55749555 ps
CPU time 1.01 seconds
Started Jul 30 06:25:48 PM PDT 24
Finished Jul 30 06:25:49 PM PDT 24
Peak memory 201132 kb
Host smart-71138767-cabc-4266-8ff2-61f94868ff95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805634880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.1805634880
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1572544825
Short name T509
Test name
Test status
Simulation time 42809366 ps
CPU time 0.81 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201160 kb
Host smart-04c04549-5cc4-4c3f-afb7-6471f0dcc334
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572544825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1572544825
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.2043685085
Short name T503
Test name
Test status
Simulation time 56442839 ps
CPU time 0.92 seconds
Started Jul 30 06:25:46 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201064 kb
Host smart-4db3db3d-ff73-48b4-ab62-fc8cc370c6ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043685085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.2043685085
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.3061430289
Short name T361
Test name
Test status
Simulation time 29795349 ps
CPU time 0.72 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:47 PM PDT 24
Peak memory 201052 kb
Host smart-97491080-9cb9-4c69-b877-3add96d9f214
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061430289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3061430289
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.2132194290
Short name T134
Test name
Test status
Simulation time 1052097348 ps
CPU time 4.99 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:56 PM PDT 24
Peak memory 201472 kb
Host smart-4d62f20b-65c5-4e57-bda8-1974176a5950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132194290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2132194290
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3208582533
Short name T546
Test name
Test status
Simulation time 15550575 ps
CPU time 0.79 seconds
Started Jul 30 06:25:47 PM PDT 24
Finished Jul 30 06:25:48 PM PDT 24
Peak memory 200996 kb
Host smart-132ad385-a993-4d46-9937-b7c34365ee73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208582533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3208582533
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.2078611992
Short name T695
Test name
Test status
Simulation time 2326931146 ps
CPU time 18.01 seconds
Started Jul 30 06:25:56 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201032 kb
Host smart-9b92972b-9725-4a65-9827-085d11815418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078611992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.2078611992
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.758654470
Short name T175
Test name
Test status
Simulation time 43367168 ps
CPU time 0.95 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201268 kb
Host smart-7e1ef502-d0a1-4983-8a63-5360302d4ae1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758654470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.758654470
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.2221603834
Short name T436
Test name
Test status
Simulation time 51436721 ps
CPU time 0.82 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201016 kb
Host smart-9d606cbd-a529-4ab9-97e6-ee0aa3621d1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221603834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.2221603834
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.1321785974
Short name T770
Test name
Test status
Simulation time 16138487 ps
CPU time 0.75 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201068 kb
Host smart-ca47519b-47f1-4cf3-b711-0cce13c4f1a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321785974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.1321785974
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1518053570
Short name T758
Test name
Test status
Simulation time 16597386 ps
CPU time 0.73 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:53 PM PDT 24
Peak memory 201056 kb
Host smart-4cacd2bb-6bce-4a0d-9cf4-8393a29ecd5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518053570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1518053570
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.1251743130
Short name T289
Test name
Test status
Simulation time 192178697 ps
CPU time 1.34 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 201100 kb
Host smart-ea2f6fa9-6147-4b13-ba6e-10ea5e55db9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251743130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.1251743130
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.2854863080
Short name T691
Test name
Test status
Simulation time 28255815 ps
CPU time 0.9 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201068 kb
Host smart-2677bf1f-bc83-44f8-8954-51849c2d7c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854863080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2854863080
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.677323414
Short name T455
Test name
Test status
Simulation time 1294777274 ps
CPU time 5.92 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:56 PM PDT 24
Peak memory 201332 kb
Host smart-0ba2f335-33b6-41be-ae2b-30d8eddf10a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677323414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.677323414
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.1290540179
Short name T506
Test name
Test status
Simulation time 1352649198 ps
CPU time 5.78 seconds
Started Jul 30 06:25:56 PM PDT 24
Finished Jul 30 06:26:02 PM PDT 24
Peak memory 200736 kb
Host smart-943cc1ce-b888-45df-9046-4ea755d7a2c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290540179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.1290540179
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3737688894
Short name T402
Test name
Test status
Simulation time 52917241 ps
CPU time 1.04 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201044 kb
Host smart-7582e596-ae90-468d-99f7-3daea1ca093b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737688894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.3737688894
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1150110998
Short name T424
Test name
Test status
Simulation time 90453246 ps
CPU time 1.03 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:53 PM PDT 24
Peak memory 201136 kb
Host smart-b29b75b3-9bc8-401f-a8bf-b0bf10efd309
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150110998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1150110998
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1328836950
Short name T678
Test name
Test status
Simulation time 20809760 ps
CPU time 0.79 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201140 kb
Host smart-ba82b67b-4d9b-4b26-9975-83965d479c3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328836950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1328836950
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.796084756
Short name T198
Test name
Test status
Simulation time 40993516 ps
CPU time 0.85 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:53 PM PDT 24
Peak memory 200992 kb
Host smart-575924c9-e087-4864-bf6f-59fbf782669e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796084756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.796084756
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.232789842
Short name T478
Test name
Test status
Simulation time 93603927 ps
CPU time 0.99 seconds
Started Jul 30 06:26:10 PM PDT 24
Finished Jul 30 06:26:11 PM PDT 24
Peak memory 201052 kb
Host smart-d3a3c954-f41d-4f32-b5ed-9412d28d5c06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232789842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.232789842
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.1092655627
Short name T387
Test name
Test status
Simulation time 45429259 ps
CPU time 0.89 seconds
Started Jul 30 06:25:57 PM PDT 24
Finished Jul 30 06:25:58 PM PDT 24
Peak memory 201104 kb
Host smart-25e3b434-9193-44f1-a698-e42e68c6762f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092655627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.1092655627
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1086823266
Short name T33
Test name
Test status
Simulation time 7733011946 ps
CPU time 55.98 seconds
Started Jul 30 06:25:55 PM PDT 24
Finished Jul 30 06:26:51 PM PDT 24
Peak memory 201524 kb
Host smart-99bc55fb-f9df-4880-a78c-694e899b4fbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086823266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1086823266
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.1234813834
Short name T772
Test name
Test status
Simulation time 28298507 ps
CPU time 0.94 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201044 kb
Host smart-7e8bbc46-4fe0-4296-9a7f-e23a061cd577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234813834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.1234813834
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.253987623
Short name T383
Test name
Test status
Simulation time 22713112 ps
CPU time 0.77 seconds
Started Jul 30 06:26:04 PM PDT 24
Finished Jul 30 06:26:05 PM PDT 24
Peak memory 201052 kb
Host smart-f299190a-3141-444b-9381-22995a336fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253987623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm
gr_alert_test.253987623
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1534642372
Short name T477
Test name
Test status
Simulation time 35950588 ps
CPU time 0.89 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201092 kb
Host smart-e4fee116-a581-4b01-b610-0a140686474b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534642372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.1534642372
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1627992588
Short name T828
Test name
Test status
Simulation time 16525376 ps
CPU time 0.72 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:50 PM PDT 24
Peak memory 201044 kb
Host smart-a2f78b88-9bfc-419b-9c8f-8c56564b1463
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627992588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1627992588
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.3790672683
Short name T435
Test name
Test status
Simulation time 31447747 ps
CPU time 0.85 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201132 kb
Host smart-48ecf58d-a4eb-4c1e-901b-caaf4c2b4b0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790672683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.3790672683
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.2036487233
Short name T613
Test name
Test status
Simulation time 18534093 ps
CPU time 0.78 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201064 kb
Host smart-b36e3cdd-ef6d-4f54-9c32-5439b8be2aa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036487233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2036487233
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.3733542057
Short name T411
Test name
Test status
Simulation time 854165184 ps
CPU time 4.39 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:57 PM PDT 24
Peak memory 201172 kb
Host smart-54ec97a8-0cca-4a03-a6cd-6ea1e5823f99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733542057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.3733542057
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.105588645
Short name T385
Test name
Test status
Simulation time 2061099598 ps
CPU time 14.08 seconds
Started Jul 30 06:25:53 PM PDT 24
Finished Jul 30 06:26:07 PM PDT 24
Peak memory 201376 kb
Host smart-6678bec3-c888-44c0-9622-b37cea4c92c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105588645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.105588645
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.411533783
Short name T609
Test name
Test status
Simulation time 18250570 ps
CPU time 0.82 seconds
Started Jul 30 06:25:53 PM PDT 24
Finished Jul 30 06:25:57 PM PDT 24
Peak memory 201020 kb
Host smart-b7b0c6a1-a1ab-4250-8066-276e04904b83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411533783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_idle_intersig_mubi.411533783
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3390976230
Short name T156
Test name
Test status
Simulation time 18389750 ps
CPU time 0.78 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201120 kb
Host smart-e63ec480-fdc7-4f07-9713-a28847f12d42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390976230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3390976230
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2769878649
Short name T466
Test name
Test status
Simulation time 53076452 ps
CPU time 0.89 seconds
Started Jul 30 06:25:51 PM PDT 24
Finished Jul 30 06:25:52 PM PDT 24
Peak memory 201068 kb
Host smart-ee077e2f-5aaa-4836-90d7-db38f92e4153
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769878649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.2769878649
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.48476984
Short name T820
Test name
Test status
Simulation time 20256040 ps
CPU time 0.75 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201116 kb
Host smart-1ed51300-3847-45c0-95b0-d66b44ef0606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48476984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.48476984
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.1857565205
Short name T409
Test name
Test status
Simulation time 1162677814 ps
CPU time 4.29 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:56 PM PDT 24
Peak memory 201268 kb
Host smart-c97e9fc7-46fa-44f0-a433-577b1c358a02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857565205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1857565205
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.1067675269
Short name T559
Test name
Test status
Simulation time 76648108 ps
CPU time 1.03 seconds
Started Jul 30 06:25:50 PM PDT 24
Finished Jul 30 06:25:51 PM PDT 24
Peak memory 201076 kb
Host smart-384b9d1b-65c1-4250-b107-16ff7ca38d41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067675269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1067675269
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.2862158728
Short name T723
Test name
Test status
Simulation time 7101215023 ps
CPU time 50.01 seconds
Started Jul 30 06:26:10 PM PDT 24
Finished Jul 30 06:27:00 PM PDT 24
Peak memory 201468 kb
Host smart-6a773034-eed7-4f2f-a164-cc3a5dfc9502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862158728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.2862158728
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.3294376010
Short name T487
Test name
Test status
Simulation time 186023512226 ps
CPU time 1309.74 seconds
Started Jul 30 06:25:53 PM PDT 24
Finished Jul 30 06:47:43 PM PDT 24
Peak memory 216972 kb
Host smart-c1097377-8c73-4ed2-8e72-053bfebb7761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3294376010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.3294376010
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2991501375
Short name T347
Test name
Test status
Simulation time 28722911 ps
CPU time 0.99 seconds
Started Jul 30 06:25:52 PM PDT 24
Finished Jul 30 06:25:53 PM PDT 24
Peak memory 201068 kb
Host smart-e115db0b-c61b-4d4f-a32e-63f7cc11843d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991501375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2991501375
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.3993158496
Short name T316
Test name
Test status
Simulation time 18132753 ps
CPU time 0.79 seconds
Started Jul 30 06:26:11 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201080 kb
Host smart-00fe3c76-8034-4625-94aa-395b01a9adb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993158496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.3993158496
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3484510873
Short name T831
Test name
Test status
Simulation time 29503891 ps
CPU time 0.89 seconds
Started Jul 30 06:25:53 PM PDT 24
Finished Jul 30 06:25:54 PM PDT 24
Peak memory 201144 kb
Host smart-15b86191-acba-4a08-a330-edde6289dd66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484510873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3484510873
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2378217241
Short name T297
Test name
Test status
Simulation time 18138334 ps
CPU time 0.74 seconds
Started Jul 30 06:25:56 PM PDT 24
Finished Jul 30 06:25:57 PM PDT 24
Peak memory 201044 kb
Host smart-993fd641-1714-4432-b0f9-1ba6415adfdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378217241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2378217241
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.68454858
Short name T704
Test name
Test status
Simulation time 29595205 ps
CPU time 0.87 seconds
Started Jul 30 06:26:00 PM PDT 24
Finished Jul 30 06:26:01 PM PDT 24
Peak memory 201088 kb
Host smart-a6e09ff7-993e-4c69-8754-06d39466ac40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68454858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.clkmgr_div_intersig_mubi.68454858
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.552256544
Short name T448
Test name
Test status
Simulation time 52296143 ps
CPU time 0.99 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201068 kb
Host smart-55d7b07e-5e8b-40dc-b70c-e0c250f6b715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552256544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.552256544
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.643547863
Short name T576
Test name
Test status
Simulation time 1160641830 ps
CPU time 6.66 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201168 kb
Host smart-82fd9d12-0395-47d0-89e9-45018905bf04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643547863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.643547863
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.317247866
Short name T754
Test name
Test status
Simulation time 1581629878 ps
CPU time 12.3 seconds
Started Jul 30 06:26:11 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201180 kb
Host smart-e5e3ef83-5180-4df6-9601-7df35f106d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317247866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti
meout.317247866
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2400596410
Short name T644
Test name
Test status
Simulation time 76927371 ps
CPU time 0.97 seconds
Started Jul 30 06:26:11 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201072 kb
Host smart-4d2a9542-9fba-4f1f-8d83-8b92d91ef59b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400596410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.2400596410
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1411316840
Short name T285
Test name
Test status
Simulation time 118510192 ps
CPU time 1.21 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201044 kb
Host smart-333ed194-bc2b-41fd-a43f-2b3f1e5704ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411316840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.1411316840
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1268239641
Short name T265
Test name
Test status
Simulation time 30833833 ps
CPU time 0.93 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201100 kb
Host smart-1ba80dfb-b407-4862-89a7-c4ff806eff1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268239641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1268239641
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.3377520733
Short name T809
Test name
Test status
Simulation time 36662927 ps
CPU time 0.79 seconds
Started Jul 30 06:26:05 PM PDT 24
Finished Jul 30 06:26:06 PM PDT 24
Peak memory 201044 kb
Host smart-003f5b9a-4c37-498f-bbaf-70e7c7cbee87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377520733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.3377520733
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.297949781
Short name T140
Test name
Test status
Simulation time 1008780895 ps
CPU time 6.32 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201300 kb
Host smart-8212b328-640b-4f76-adc4-c34cb68311f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297949781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.297949781
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.1936457373
Short name T602
Test name
Test status
Simulation time 23743292 ps
CPU time 0.87 seconds
Started Jul 30 06:25:54 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201080 kb
Host smart-d4ee0692-0383-474f-8652-4dd4d6a014df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936457373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1936457373
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.847242723
Short name T826
Test name
Test status
Simulation time 4713671780 ps
CPU time 27.14 seconds
Started Jul 30 06:26:10 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 201476 kb
Host smart-50f796cf-374c-46a2-886c-7819217c3cab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847242723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.847242723
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.640920195
Short name T802
Test name
Test status
Simulation time 177639303 ps
CPU time 1.32 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201076 kb
Host smart-ba6ae9ed-bc53-4cd3-a614-339519f9a6a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640920195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.640920195
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.3493486148
Short name T698
Test name
Test status
Simulation time 58195109 ps
CPU time 1 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201036 kb
Host smart-84bcf155-7e16-4e3e-bdc4-b4c2bfc36ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493486148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.3493486148
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.1541443883
Short name T98
Test name
Test status
Simulation time 12892074 ps
CPU time 0.74 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:14 PM PDT 24
Peak memory 201164 kb
Host smart-67b383f8-2a65-4f3d-998c-4a37e30752a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541443883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.1541443883
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.1394089599
Short name T713
Test name
Test status
Simulation time 24861842 ps
CPU time 0.76 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:13 PM PDT 24
Peak memory 200268 kb
Host smart-9a37c7cb-399a-422a-bb67-0fdc708c01f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394089599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1394089599
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.4200102512
Short name T230
Test name
Test status
Simulation time 26870965 ps
CPU time 0.9 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201088 kb
Host smart-c921d2af-dfba-445a-983b-b52d8b8f1e7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200102512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.4200102512
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.4096396447
Short name T719
Test name
Test status
Simulation time 187006118 ps
CPU time 1.35 seconds
Started Jul 30 06:26:05 PM PDT 24
Finished Jul 30 06:26:06 PM PDT 24
Peak memory 201028 kb
Host smart-dfe58467-7fd7-44b1-ba06-6ec7820537b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096396447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.4096396447
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.2435769170
Short name T663
Test name
Test status
Simulation time 1162192478 ps
CPU time 7.63 seconds
Started Jul 30 06:25:59 PM PDT 24
Finished Jul 30 06:26:07 PM PDT 24
Peak memory 201200 kb
Host smart-d7232234-b259-465d-bddf-8af1845a6744
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435769170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2435769170
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.2805876850
Short name T630
Test name
Test status
Simulation time 2407279691 ps
CPU time 10.07 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201428 kb
Host smart-0e3eadd8-93a7-4f5c-a8b9-7a9df9b6fe40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805876850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.2805876850
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.923189273
Short name T169
Test name
Test status
Simulation time 20099118 ps
CPU time 0.9 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201072 kb
Host smart-b2623fdd-d675-42c3-ac75-a1f55be18d6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923189273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.923189273
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2568443241
Short name T660
Test name
Test status
Simulation time 27060187 ps
CPU time 0.81 seconds
Started Jul 30 06:25:54 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201076 kb
Host smart-fbe8ffa9-e4f0-4f21-aa1a-9e950135f380
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568443241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2568443241
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.2938432034
Short name T560
Test name
Test status
Simulation time 16343825 ps
CPU time 0.78 seconds
Started Jul 30 06:26:05 PM PDT 24
Finished Jul 30 06:26:06 PM PDT 24
Peak memory 201072 kb
Host smart-26c7f920-65a6-4abf-82a9-e92a90d35d33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938432034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.2938432034
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.346907693
Short name T62
Test name
Test status
Simulation time 880722617 ps
CPU time 4.25 seconds
Started Jul 30 06:26:02 PM PDT 24
Finished Jul 30 06:26:07 PM PDT 24
Peak memory 201268 kb
Host smart-e051f9ea-383b-4929-b144-33440a583696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346907693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.346907693
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.3326799823
Short name T738
Test name
Test status
Simulation time 65897529 ps
CPU time 1.02 seconds
Started Jul 30 06:26:06 PM PDT 24
Finished Jul 30 06:26:07 PM PDT 24
Peak memory 201152 kb
Host smart-f217cd26-fefb-43cd-89c1-e0e5acdb745a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326799823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.3326799823
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.140574318
Short name T303
Test name
Test status
Simulation time 3699575534 ps
CPU time 14.08 seconds
Started Jul 30 06:26:12 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201364 kb
Host smart-045f575b-9ebd-42e3-bf3d-3ddade0ade52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140574318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.140574318
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3437815522
Short name T10
Test name
Test status
Simulation time 21857931036 ps
CPU time 333.54 seconds
Started Jul 30 06:26:00 PM PDT 24
Finished Jul 30 06:31:34 PM PDT 24
Peak memory 217972 kb
Host smart-153752d4-e51b-4ea8-9767-004158fc2228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3437815522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3437815522
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.2463677912
Short name T192
Test name
Test status
Simulation time 121795623 ps
CPU time 1.3 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201084 kb
Host smart-10ade466-c8a6-4c9e-8262-82cf13b07a9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463677912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2463677912
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.2886170670
Short name T300
Test name
Test status
Simulation time 129739072 ps
CPU time 1.11 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201064 kb
Host smart-c20f174a-2a42-4530-8fd8-7e54ad67f8b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886170670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.2886170670
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.631799319
Short name T585
Test name
Test status
Simulation time 49955645 ps
CPU time 0.85 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201036 kb
Host smart-1139c347-d142-44ec-bd90-7ac418a4cde5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631799319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.631799319
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.352908205
Short name T443
Test name
Test status
Simulation time 24882434 ps
CPU time 0.74 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:14 PM PDT 24
Peak memory 200344 kb
Host smart-ae8bf20d-9fec-4611-9e8c-0154dc3b3c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352908205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.352908205
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.4086791951
Short name T764
Test name
Test status
Simulation time 50574536 ps
CPU time 0.99 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:24 PM PDT 24
Peak memory 201144 kb
Host smart-2fe25858-83eb-4908-bb94-f295231e6075
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086791951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.4086791951
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.573179974
Short name T674
Test name
Test status
Simulation time 63081074 ps
CPU time 0.9 seconds
Started Jul 30 06:26:05 PM PDT 24
Finished Jul 30 06:26:06 PM PDT 24
Peak memory 201080 kb
Host smart-435f634f-95d2-4b0e-a809-04aae772c0f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573179974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.573179974
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.200952513
Short name T283
Test name
Test status
Simulation time 2355775075 ps
CPU time 18.35 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201388 kb
Host smart-293a5dc9-ddcf-4463-b845-4c07cccf9904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200952513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.200952513
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.2751453516
Short name T196
Test name
Test status
Simulation time 1938670348 ps
CPU time 9.86 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201228 kb
Host smart-f5efcec8-0f78-4fba-b4b6-577a77fec426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751453516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.2751453516
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3264566442
Short name T210
Test name
Test status
Simulation time 56910528 ps
CPU time 1.08 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201020 kb
Host smart-22d007af-3ec6-4abc-871a-8983e6d6a1b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264566442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3264566442
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.140789437
Short name T257
Test name
Test status
Simulation time 49511184 ps
CPU time 0.93 seconds
Started Jul 30 06:26:04 PM PDT 24
Finished Jul 30 06:26:05 PM PDT 24
Peak memory 201120 kb
Host smart-b82ab499-c83a-4e9a-892e-8841e44a6f6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140789437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 35.clkmgr_lc_clk_byp_req_intersig_mubi.140789437
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.3841007451
Short name T245
Test name
Test status
Simulation time 20930251 ps
CPU time 0.79 seconds
Started Jul 30 06:26:12 PM PDT 24
Finished Jul 30 06:26:13 PM PDT 24
Peak memory 201048 kb
Host smart-0670d4aa-cec8-4d71-8704-c6811c6f21cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841007451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.3841007451
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.567795428
Short name T796
Test name
Test status
Simulation time 139243227 ps
CPU time 1.11 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201076 kb
Host smart-5d886600-608f-48a3-b042-16b57ec75878
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567795428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.567795428
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.3041439253
Short name T225
Test name
Test status
Simulation time 20794747 ps
CPU time 0.93 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201100 kb
Host smart-c007db01-7356-4590-baeb-c88d07f722d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041439253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3041439253
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.2670494518
Short name T566
Test name
Test status
Simulation time 12571363600 ps
CPU time 92.1 seconds
Started Jul 30 06:26:00 PM PDT 24
Finished Jul 30 06:27:32 PM PDT 24
Peak memory 201448 kb
Host smart-f2057f04-ae55-40c5-a111-ab87697f9480
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670494518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.2670494518
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.3720855254
Short name T651
Test name
Test status
Simulation time 534908787 ps
CPU time 2.48 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201136 kb
Host smart-5daf069b-ba35-4f0b-bb22-40c3d6ea4599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720855254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3720855254
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.4109244397
Short name T453
Test name
Test status
Simulation time 19260693 ps
CPU time 0.76 seconds
Started Jul 30 06:26:11 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201148 kb
Host smart-9d59b698-b498-4199-a54d-86359f83466d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109244397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.4109244397
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1585492697
Short name T535
Test name
Test status
Simulation time 18317299 ps
CPU time 0.88 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201096 kb
Host smart-5909cd3e-6539-469d-9457-05d8462362a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585492697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1585492697
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.1814448062
Short name T150
Test name
Test status
Simulation time 23465045 ps
CPU time 0.73 seconds
Started Jul 30 06:26:24 PM PDT 24
Finished Jul 30 06:26:25 PM PDT 24
Peak memory 200344 kb
Host smart-ff258739-504e-41b3-bc17-bd4c5d4c23f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814448062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.1814448062
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.303848899
Short name T557
Test name
Test status
Simulation time 18842218 ps
CPU time 0.81 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201132 kb
Host smart-4866ad26-aaaa-4738-951f-c0aadf0d46c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303848899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_div_intersig_mubi.303848899
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2261453249
Short name T761
Test name
Test status
Simulation time 18601941 ps
CPU time 0.74 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201060 kb
Host smart-50c6742f-410d-4da1-9827-f57d60aa7bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261453249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2261453249
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1249441946
Short name T543
Test name
Test status
Simulation time 1156441172 ps
CPU time 8.84 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:25 PM PDT 24
Peak memory 201140 kb
Host smart-dc09bf14-f177-4e2a-af4a-8a0e620f3af2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249441946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1249441946
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.3618662703
Short name T777
Test name
Test status
Simulation time 162259929 ps
CPU time 1.34 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201152 kb
Host smart-ac51d3ed-d8a3-4c63-9675-6ed4a5981893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618662703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.3618662703
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.695599556
Short name T578
Test name
Test status
Simulation time 57534613 ps
CPU time 1 seconds
Started Jul 30 06:26:01 PM PDT 24
Finished Jul 30 06:26:02 PM PDT 24
Peak memory 201100 kb
Host smart-c13a0b4d-070b-4b7f-897e-24453048b5a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695599556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_idle_intersig_mubi.695599556
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3412717442
Short name T687
Test name
Test status
Simulation time 61964444 ps
CPU time 0.94 seconds
Started Jul 30 06:26:00 PM PDT 24
Finished Jul 30 06:26:01 PM PDT 24
Peak memory 201140 kb
Host smart-2bac2aae-0b75-42db-ab3b-7ca01d6e4a6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412717442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3412717442
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.558834139
Short name T632
Test name
Test status
Simulation time 234638502 ps
CPU time 1.5 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201048 kb
Host smart-12223a67-23ea-42b4-8a6d-93e4f5b81804
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558834139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_ctrl_intersig_mubi.558834139
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1003597926
Short name T16
Test name
Test status
Simulation time 15139917 ps
CPU time 0.75 seconds
Started Jul 30 06:26:07 PM PDT 24
Finished Jul 30 06:26:08 PM PDT 24
Peak memory 201076 kb
Host smart-d2eb7dd8-dbe8-4724-a5a5-5cc441c2c4e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003597926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1003597926
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.1790787126
Short name T529
Test name
Test status
Simulation time 248997470 ps
CPU time 1.42 seconds
Started Jul 30 06:26:24 PM PDT 24
Finished Jul 30 06:26:25 PM PDT 24
Peak memory 201092 kb
Host smart-0bff91fd-cfb9-47ae-a7f1-dff9ed24b824
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790787126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1790787126
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.2536812293
Short name T277
Test name
Test status
Simulation time 25983238 ps
CPU time 0.84 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201000 kb
Host smart-9c4c46d0-b5b2-49e5-95ee-4391e1d65c00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536812293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.2536812293
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2162882247
Short name T26
Test name
Test status
Simulation time 7473360142 ps
CPU time 26.89 seconds
Started Jul 30 06:26:07 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201432 kb
Host smart-b01919db-b808-44de-bf63-61b4642aca44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162882247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2162882247
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.2223175656
Short name T547
Test name
Test status
Simulation time 18591953 ps
CPU time 0.82 seconds
Started Jul 30 06:26:01 PM PDT 24
Finished Jul 30 06:26:02 PM PDT 24
Peak memory 201016 kb
Host smart-d7ef82f5-03df-4f64-be96-a1ee547bdeb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223175656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2223175656
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3823740186
Short name T498
Test name
Test status
Simulation time 16728966 ps
CPU time 0.8 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201120 kb
Host smart-eb8881da-656b-4097-8beb-890f146b10f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823740186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3823740186
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.4206822661
Short name T329
Test name
Test status
Simulation time 18912807 ps
CPU time 0.84 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201104 kb
Host smart-7104e85d-50ca-48d5-9feb-e0a6f906afe0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206822661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.4206822661
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2045181361
Short name T271
Test name
Test status
Simulation time 16086145 ps
CPU time 0.72 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201052 kb
Host smart-8b8645d3-13ed-4fb6-894a-cd21a9017613
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045181361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2045181361
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2370391784
Short name T101
Test name
Test status
Simulation time 45670725 ps
CPU time 0.86 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201016 kb
Host smart-6ffe2e4a-a503-4c69-b2d2-acefa825715d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370391784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2370391784
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3863079423
Short name T242
Test name
Test status
Simulation time 13974834 ps
CPU time 0.74 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201080 kb
Host smart-95f72037-ac7e-4025-bec6-2195dd6a5635
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863079423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3863079423
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2700574601
Short name T774
Test name
Test status
Simulation time 2120633280 ps
CPU time 16.88 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201400 kb
Host smart-7715f2c8-4fef-412d-b28f-4df42f138acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700574601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2700574601
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.1533472296
Short name T555
Test name
Test status
Simulation time 379992555 ps
CPU time 3.27 seconds
Started Jul 30 06:26:10 PM PDT 24
Finished Jul 30 06:26:13 PM PDT 24
Peak memory 201156 kb
Host smart-d6253a66-0c76-47fc-a6e7-4eae91378ca4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533472296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.1533472296
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2856805711
Short name T238
Test name
Test status
Simulation time 73096570 ps
CPU time 1.01 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201052 kb
Host smart-8a10a9d5-7691-4ba9-896f-19f3353b22b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856805711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2856805711
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3712680680
Short name T252
Test name
Test status
Simulation time 53507295 ps
CPU time 0.84 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:14 PM PDT 24
Peak memory 201136 kb
Host smart-0ee49086-d844-42d6-9bb6-4de653debd67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712680680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3712680680
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2182533279
Short name T493
Test name
Test status
Simulation time 22587460 ps
CPU time 0.84 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201092 kb
Host smart-af7c4313-0641-48b8-9728-71385b8536b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182533279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.2182533279
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.3688291600
Short name T819
Test name
Test status
Simulation time 27465417 ps
CPU time 0.71 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201024 kb
Host smart-d76c7f92-d909-4f2a-82d1-822219c10607
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688291600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3688291600
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1414093838
Short name T813
Test name
Test status
Simulation time 103206426 ps
CPU time 1.02 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 200980 kb
Host smart-d55bfd97-a297-469f-a7f0-9816f54102a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414093838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1414093838
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.1705851952
Short name T489
Test name
Test status
Simulation time 35112429 ps
CPU time 0.9 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201032 kb
Host smart-1e802f22-b6d1-482f-b23f-8e2ce96523b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705851952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1705851952
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.535290949
Short name T791
Test name
Test status
Simulation time 2505121415 ps
CPU time 10.61 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201460 kb
Host smart-b85029fc-c337-471d-a1e3-8512958da0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535290949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.535290949
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.3950546033
Short name T54
Test name
Test status
Simulation time 109241056179 ps
CPU time 680.39 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:37:38 PM PDT 24
Peak memory 209896 kb
Host smart-f021210c-be36-40c9-842c-bd9b7fcdaee8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3950546033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.3950546033
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.3639889012
Short name T693
Test name
Test status
Simulation time 191328096 ps
CPU time 1.68 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201136 kb
Host smart-769e0570-971e-46ec-98f6-b6124a3b384d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639889012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.3639889012
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.2140546969
Short name T32
Test name
Test status
Simulation time 59986728 ps
CPU time 0.83 seconds
Started Jul 30 06:26:20 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201128 kb
Host smart-c1199515-fd78-470f-b33c-52eee5e98252
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140546969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.2140546969
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.502799710
Short name T748
Test name
Test status
Simulation time 75243799 ps
CPU time 1.05 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201052 kb
Host smart-f5b07f0d-6fc3-4cc0-bdf3-924d800dfd46
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502799710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.502799710
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1839522532
Short name T561
Test name
Test status
Simulation time 18352790 ps
CPU time 0.78 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 200296 kb
Host smart-4dfc1961-13f3-4b52-a9b9-fb246a9c1a07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839522532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1839522532
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.1514791824
Short name T204
Test name
Test status
Simulation time 63907516 ps
CPU time 1.01 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201060 kb
Host smart-4f4e8116-1d54-4b53-9773-1f5712e61ea4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514791824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.1514791824
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.1115360357
Short name T416
Test name
Test status
Simulation time 48744310 ps
CPU time 0.88 seconds
Started Jul 30 06:26:09 PM PDT 24
Finished Jul 30 06:26:10 PM PDT 24
Peak memory 201024 kb
Host smart-dd9083b4-d19f-4704-851e-4b9538012c89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115360357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1115360357
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1304446239
Short name T31
Test name
Test status
Simulation time 1635557068 ps
CPU time 12.89 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201148 kb
Host smart-83212a51-dc62-42a0-8019-3a08ed579ab8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304446239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1304446239
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1443416735
Short name T680
Test name
Test status
Simulation time 278524514 ps
CPU time 1.72 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201112 kb
Host smart-d2d7846c-40a8-44d7-b1fd-4f44dfdd729c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443416735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1443416735
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.3906746771
Short name T160
Test name
Test status
Simulation time 30355943 ps
CPU time 1.02 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201032 kb
Host smart-fd4f3a74-b180-473b-bf14-dc88c471c542
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906746771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.3906746771
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3159869864
Short name T617
Test name
Test status
Simulation time 13379352 ps
CPU time 0.77 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201092 kb
Host smart-9d96f2df-64d8-4b15-a644-8532d6390f11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159869864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.3159869864
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3269075542
Short name T619
Test name
Test status
Simulation time 41170868 ps
CPU time 0.83 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201072 kb
Host smart-d2112df4-e9c3-4ed0-a0f7-858fff8b617c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269075542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.3269075542
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.1006059770
Short name T355
Test name
Test status
Simulation time 36062158 ps
CPU time 0.78 seconds
Started Jul 30 06:26:12 PM PDT 24
Finished Jul 30 06:26:12 PM PDT 24
Peak memory 201048 kb
Host smart-fa7cd65a-6ea6-4dc1-96f4-c8ee5ba11fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006059770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1006059770
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3634838843
Short name T61
Test name
Test status
Simulation time 824944416 ps
CPU time 3.94 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201252 kb
Host smart-c3143ee9-16f9-423d-b8c8-3644628c5c4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634838843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3634838843
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.4028229643
Short name T657
Test name
Test status
Simulation time 17304460 ps
CPU time 0.81 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:14 PM PDT 24
Peak memory 201104 kb
Host smart-bc5a6a11-97e1-4eb6-bc03-470bd36a182e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028229643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.4028229643
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1577977728
Short name T548
Test name
Test status
Simulation time 1265181684 ps
CPU time 5.88 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 201192 kb
Host smart-d03350a2-a440-43c2-b055-ae7c341a241b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577977728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1577977728
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.113487247
Short name T58
Test name
Test status
Simulation time 133265654003 ps
CPU time 515.52 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:34:54 PM PDT 24
Peak memory 209800 kb
Host smart-dcf986e5-3deb-4744-9408-f87f97433ba1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=113487247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.113487247
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.472211532
Short name T742
Test name
Test status
Simulation time 42446970 ps
CPU time 0.81 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201068 kb
Host smart-6c538ba0-6610-4e84-9645-d9dd922f833b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472211532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.472211532
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.219225774
Short name T795
Test name
Test status
Simulation time 46672478 ps
CPU time 0.9 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201072 kb
Host smart-c77bb2a7-5b3b-471d-a92e-052c42d9ace0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219225774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.219225774
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1698621551
Short name T494
Test name
Test status
Simulation time 26645762 ps
CPU time 0.93 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201080 kb
Host smart-e3898572-a057-4ebd-88ae-ed7b07ff7583
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698621551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.1698621551
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.2863829578
Short name T724
Test name
Test status
Simulation time 13721255 ps
CPU time 0.72 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 200264 kb
Host smart-71d73dc1-583a-4249-b393-ba4d715754e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863829578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.2863829578
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.3627633620
Short name T574
Test name
Test status
Simulation time 25141074 ps
CPU time 0.8 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201132 kb
Host smart-b66b7e46-c2aa-45d4-9fe4-10e6a8753f84
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627633620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.3627633620
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.3711609309
Short name T430
Test name
Test status
Simulation time 30847517 ps
CPU time 0.77 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201020 kb
Host smart-5c63a943-ccdf-4d43-b209-a875a10109b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711609309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.3711609309
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.4175850569
Short name T536
Test name
Test status
Simulation time 1045223679 ps
CPU time 6.35 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201172 kb
Host smart-8edf5c34-5beb-4224-b8e4-5c862f39c563
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175850569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.4175850569
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.1599729448
Short name T635
Test name
Test status
Simulation time 502835480 ps
CPU time 3.26 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201204 kb
Host smart-b3a7ecce-13be-4551-b8be-c6946ebb412e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599729448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.1599729448
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.2994284789
Short name T264
Test name
Test status
Simulation time 76394707 ps
CPU time 1.02 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201088 kb
Host smart-c4f7d144-9183-4013-bc25-3a676f32c96e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994284789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.2994284789
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.717228642
Short name T154
Test name
Test status
Simulation time 37584226 ps
CPU time 0.78 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201100 kb
Host smart-19689154-850d-4236-8560-e63f7283a51b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717228642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.717228642
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3373099924
Short name T400
Test name
Test status
Simulation time 38113384 ps
CPU time 0.96 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201032 kb
Host smart-83947afd-7c8c-4c8e-87e8-bb0a02aafc59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373099924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.3373099924
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1103392898
Short name T236
Test name
Test status
Simulation time 25862268 ps
CPU time 0.74 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201100 kb
Host smart-f5cf2fad-1d6d-4985-8679-261d36e5e2ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103392898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1103392898
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.82266510
Short name T337
Test name
Test status
Simulation time 1352209580 ps
CPU time 4.67 seconds
Started Jul 30 06:26:13 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201228 kb
Host smart-3e3c3122-8555-420c-8142-688295d4cc79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82266510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.82266510
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.4118492795
Short name T246
Test name
Test status
Simulation time 30597070 ps
CPU time 0.89 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201016 kb
Host smart-56b07e13-210b-4057-8dc9-8c9e063deb77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118492795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.4118492795
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.618765220
Short name T652
Test name
Test status
Simulation time 3012629985 ps
CPU time 13.77 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201468 kb
Host smart-67515bcc-0e1f-479b-af68-28f84f115119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618765220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.618765220
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.262223106
Short name T177
Test name
Test status
Simulation time 47456849 ps
CPU time 0.87 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201088 kb
Host smart-5e64114b-a69e-4da8-ba60-2bc6650e0943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262223106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.262223106
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.1838703401
Short name T367
Test name
Test status
Simulation time 14899220 ps
CPU time 0.81 seconds
Started Jul 30 06:24:45 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201044 kb
Host smart-36af8c4b-973e-4666-895f-3f371bdde67b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838703401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.1838703401
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1459504948
Short name T74
Test name
Test status
Simulation time 18335197 ps
CPU time 0.8 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:45 PM PDT 24
Peak memory 201120 kb
Host smart-e4a6a449-d637-453c-a0f4-f26984c1fcc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459504948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1459504948
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.1401607979
Short name T324
Test name
Test status
Simulation time 33711471 ps
CPU time 0.77 seconds
Started Jul 30 06:24:48 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201052 kb
Host smart-61f8145c-73ac-4b83-800e-98bf79ecb364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401607979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1401607979
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.511810143
Short name T391
Test name
Test status
Simulation time 14430671 ps
CPU time 0.74 seconds
Started Jul 30 06:24:45 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201128 kb
Host smart-c186a56f-c388-462c-a7cf-856f86b4d52c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511810143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.511810143
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1381140496
Short name T418
Test name
Test status
Simulation time 22077886 ps
CPU time 0.88 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:24:51 PM PDT 24
Peak memory 201064 kb
Host smart-3016ab2b-272a-45c8-98d6-3251c0017c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381140496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1381140496
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1782608348
Short name T682
Test name
Test status
Simulation time 1758589050 ps
CPU time 14.05 seconds
Started Jul 30 06:24:46 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201380 kb
Host smart-b1128546-79a3-4e42-be7c-a6ca2d8d6daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782608348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1782608348
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.3219382489
Short name T456
Test name
Test status
Simulation time 500496030 ps
CPU time 3.35 seconds
Started Jul 30 06:24:45 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201240 kb
Host smart-3294fd0f-b2d0-41cf-b87b-636276f7c5b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219382489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.3219382489
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.960468149
Short name T710
Test name
Test status
Simulation time 18559201 ps
CPU time 0.8 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201064 kb
Host smart-53dacbad-b756-4943-a71d-12882aa67098
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960468149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_idle_intersig_mubi.960468149
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1043461881
Short name T591
Test name
Test status
Simulation time 44244445 ps
CPU time 0.84 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201104 kb
Host smart-0781879f-ae91-4ce2-aac7-3f46284bce78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043461881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1043461881
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2224642121
Short name T190
Test name
Test status
Simulation time 20403421 ps
CPU time 0.83 seconds
Started Jul 30 06:24:46 PM PDT 24
Finished Jul 30 06:24:47 PM PDT 24
Peak memory 201056 kb
Host smart-3db3a9a6-7abe-44fa-8c7d-93954b46db14
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224642121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2224642121
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.62236489
Short name T579
Test name
Test status
Simulation time 227200050 ps
CPU time 1.4 seconds
Started Jul 30 06:24:49 PM PDT 24
Finished Jul 30 06:24:51 PM PDT 24
Peak memory 201024 kb
Host smart-3d3fae11-a2b8-466c-b131-859aaaccfb52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62236489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.62236489
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1105291336
Short name T750
Test name
Test status
Simulation time 728350808 ps
CPU time 4.07 seconds
Started Jul 30 06:24:45 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201272 kb
Host smart-1cad3e98-cac3-4220-b1ef-7cf87300a91c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105291336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1105291336
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.279810558
Short name T40
Test name
Test status
Simulation time 475298560 ps
CPU time 3.71 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:51 PM PDT 24
Peak memory 217876 kb
Host smart-08166a1c-4251-4efb-9406-bda903f74f0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279810558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_sec_cm.279810558
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.3716108284
Short name T128
Test name
Test status
Simulation time 70109781 ps
CPU time 1.05 seconds
Started Jul 30 06:24:44 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201088 kb
Host smart-1962b046-634d-41db-82dd-167ef1cfd105
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716108284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3716108284
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.3353503946
Short name T444
Test name
Test status
Simulation time 9934570525 ps
CPU time 43.75 seconds
Started Jul 30 06:24:46 PM PDT 24
Finished Jul 30 06:25:29 PM PDT 24
Peak memory 201404 kb
Host smart-fcf55330-d710-4ddd-81a9-ae2b34a29041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353503946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.3353503946
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.3361653218
Short name T727
Test name
Test status
Simulation time 22534920 ps
CPU time 0.87 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:24:51 PM PDT 24
Peak memory 201080 kb
Host smart-46857d2e-f130-45ba-9fb8-a986ca4dd255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361653218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.3361653218
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.2252584531
Short name T449
Test name
Test status
Simulation time 31226231 ps
CPU time 0.76 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201100 kb
Host smart-7e2ec4b6-566c-4e29-b534-8540c49efae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252584531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.2252584531
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.700522713
Short name T79
Test name
Test status
Simulation time 32180789 ps
CPU time 0.95 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201092 kb
Host smart-01cd0b5b-73dd-4046-a07c-37679700ad28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700522713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.700522713
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.58358423
Short name T146
Test name
Test status
Simulation time 15738006 ps
CPU time 0.75 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 200264 kb
Host smart-ec0f0045-1054-4e65-9943-64ef95c7f07b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58358423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.58358423
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.1214105916
Short name T227
Test name
Test status
Simulation time 33235043 ps
CPU time 0.87 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201032 kb
Host smart-c0ad8b42-573d-466a-ae51-6f0ddd62b805
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214105916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.1214105916
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.2046592011
Short name T136
Test name
Test status
Simulation time 46014701 ps
CPU time 0.99 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201052 kb
Host smart-b8622915-de1a-4200-9502-b895fcff6c59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046592011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.2046592011
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.2340141737
Short name T353
Test name
Test status
Simulation time 2038030837 ps
CPU time 9.23 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:41 PM PDT 24
Peak memory 201360 kb
Host smart-fb3ec29f-2b0b-4348-871f-6e13483eb697
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340141737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.2340141737
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.3657874172
Short name T63
Test name
Test status
Simulation time 980675132 ps
CPU time 7.49 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 201192 kb
Host smart-e5af6092-75d5-4983-859b-69a0b16efebf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657874172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.3657874172
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2768432806
Short name T406
Test name
Test status
Simulation time 56604936 ps
CPU time 0.97 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201064 kb
Host smart-643b1acf-7c9e-4904-98b4-bcce40ccc704
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768432806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.2768432806
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.4142833014
Short name T379
Test name
Test status
Simulation time 18159960 ps
CPU time 0.78 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201136 kb
Host smart-5881a8ed-09fb-4888-b8ba-679012e19ebb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142833014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.4142833014
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.537382566
Short name T426
Test name
Test status
Simulation time 377203143 ps
CPU time 2.01 seconds
Started Jul 30 06:26:20 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201064 kb
Host smart-87ff050d-821b-4539-9d5d-f9fd16f2284c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537382566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_ctrl_intersig_mubi.537382566
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2704398477
Short name T259
Test name
Test status
Simulation time 21030723 ps
CPU time 0.76 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201040 kb
Host smart-a3b62577-a4a8-4853-842b-87e79f6b4203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704398477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2704398477
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3921977936
Short name T30
Test name
Test status
Simulation time 1309841122 ps
CPU time 6.98 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201296 kb
Host smart-423efef8-5581-4450-8f95-088a285a7077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921977936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3921977936
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.764851760
Short name T467
Test name
Test status
Simulation time 51785638 ps
CPU time 0.99 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:17 PM PDT 24
Peak memory 201080 kb
Host smart-b6a8b02f-c0e1-41f0-82b3-b97945572f29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764851760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.764851760
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.579151251
Short name T375
Test name
Test status
Simulation time 69177949 ps
CPU time 0.95 seconds
Started Jul 30 06:26:15 PM PDT 24
Finished Jul 30 06:26:16 PM PDT 24
Peak memory 201076 kb
Host smart-d5b45397-5549-48f9-9666-fa69be3c74dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579151251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.579151251
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.448196212
Short name T223
Test name
Test status
Simulation time 28740435 ps
CPU time 0.79 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201056 kb
Host smart-5623a993-0c72-4e95-87ce-d76a6f2dd37f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448196212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.448196212
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.3369887065
Short name T394
Test name
Test status
Simulation time 27034180 ps
CPU time 0.85 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201152 kb
Host smart-058c93a4-394a-4262-ae85-9df4d33b0afb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369887065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.3369887065
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1145425148
Short name T615
Test name
Test status
Simulation time 22818118 ps
CPU time 0.9 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201088 kb
Host smart-6135fc3c-3ac4-4f10-8d33-bc39254981bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145425148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1145425148
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3647492126
Short name T151
Test name
Test status
Simulation time 45900039 ps
CPU time 0.79 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 200272 kb
Host smart-4d633f2e-3c58-45a2-bb0a-daa2064583c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647492126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3647492126
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.1232156540
Short name T708
Test name
Test status
Simulation time 30976062 ps
CPU time 0.83 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201056 kb
Host smart-36b479b4-dcce-474c-9116-1f2b855a0b5a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232156540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.1232156540
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.1446294748
Short name T222
Test name
Test status
Simulation time 25707631 ps
CPU time 0.89 seconds
Started Jul 30 06:26:14 PM PDT 24
Finished Jul 30 06:26:15 PM PDT 24
Peak memory 201080 kb
Host smart-15bd9a1c-d466-447b-8a90-314da32d107c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446294748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.1446294748
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1974037268
Short name T533
Test name
Test status
Simulation time 1042799127 ps
CPU time 8.24 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201176 kb
Host smart-e1b94e3a-7759-4bed-bbb2-83de378fc834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974037268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1974037268
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.436722148
Short name T605
Test name
Test status
Simulation time 760926879 ps
CPU time 3.52 seconds
Started Jul 30 06:26:16 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201204 kb
Host smart-e4a94c11-cfd1-47c8-9661-9110e3d23784
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436722148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.436722148
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1474168647
Short name T800
Test name
Test status
Simulation time 145085837 ps
CPU time 1.12 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201084 kb
Host smart-5651e22a-01cf-466e-b5d9-40a31af22ed5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474168647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1474168647
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.2573920995
Short name T711
Test name
Test status
Simulation time 25998968 ps
CPU time 0.78 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 201052 kb
Host smart-d9cf2921-d5df-469a-9d51-1634f829314d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573920995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.2573920995
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1072859563
Short name T405
Test name
Test status
Simulation time 72827908 ps
CPU time 0.97 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201132 kb
Host smart-1a2b5087-2592-4b24-a41e-b3b274e730f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072859563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.1072859563
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.1765213853
Short name T502
Test name
Test status
Simulation time 39311752 ps
CPU time 0.76 seconds
Started Jul 30 06:26:17 PM PDT 24
Finished Jul 30 06:26:18 PM PDT 24
Peak memory 201036 kb
Host smart-f158f6b3-ccdd-4568-a3fc-cd2f01b8d2e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765213853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1765213853
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.2833179720
Short name T717
Test name
Test status
Simulation time 314625173 ps
CPU time 1.77 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201056 kb
Host smart-458f96d2-61d3-4a7f-b5cf-795115adeeb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833179720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.2833179720
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1705400233
Short name T476
Test name
Test status
Simulation time 32042869 ps
CPU time 0.89 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201104 kb
Host smart-a298f6bb-d2d0-4136-bc62-8dfe2b2c3988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705400233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1705400233
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.2652865190
Short name T281
Test name
Test status
Simulation time 8449568616 ps
CPU time 60.76 seconds
Started Jul 30 06:26:23 PM PDT 24
Finished Jul 30 06:27:24 PM PDT 24
Peak memory 201404 kb
Host smart-58df2040-9a73-45ff-aac7-43bda89bbb1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652865190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.2652865190
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1691598802
Short name T681
Test name
Test status
Simulation time 31874679 ps
CPU time 0.97 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 201032 kb
Host smart-ea942cbc-bb80-4d8b-b17b-80bfeb24a58a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691598802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1691598802
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.4088679389
Short name T696
Test name
Test status
Simulation time 51113461 ps
CPU time 0.9 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201080 kb
Host smart-0cf3db57-363b-41a9-a498-4eb4779929c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088679389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.4088679389
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.3946670867
Short name T720
Test name
Test status
Simulation time 49856822 ps
CPU time 1.03 seconds
Started Jul 30 06:26:25 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201044 kb
Host smart-3c3b1deb-518b-4170-bf7d-c6df87d0477d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946670867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.3946670867
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.1586757897
Short name T240
Test name
Test status
Simulation time 11838426 ps
CPU time 0.67 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 200264 kb
Host smart-28cd5cf5-ed29-41d0-8b1e-e3f0da827358
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586757897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1586757897
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.368246698
Short name T266
Test name
Test status
Simulation time 128725771 ps
CPU time 1.19 seconds
Started Jul 30 06:26:24 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201084 kb
Host smart-8e515d0d-83f0-4a9d-9445-626aad02b9c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368246698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_div_intersig_mubi.368246698
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.1898829001
Short name T732
Test name
Test status
Simulation time 27980061 ps
CPU time 0.95 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201008 kb
Host smart-7ee7ea88-55e8-4caf-b906-9629b65248bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898829001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1898829001
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.718949833
Short name T237
Test name
Test status
Simulation time 1756019365 ps
CPU time 12.67 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 201344 kb
Host smart-1a4cb9f2-1b65-495d-90f0-111d46724dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718949833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.718949833
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.4214514823
Short name T221
Test name
Test status
Simulation time 617200027 ps
CPU time 4.83 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201252 kb
Host smart-d1fdcbc7-cbe1-4015-a3d1-3e57b0602870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214514823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.4214514823
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.1571275543
Short name T501
Test name
Test status
Simulation time 47745681 ps
CPU time 0.84 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201068 kb
Host smart-9373622d-9400-4896-b165-0f48489f30d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571275543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.1571275543
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.627102768
Short name T194
Test name
Test status
Simulation time 16091376 ps
CPU time 0.8 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201092 kb
Host smart-5892562b-a420-4163-9c78-89a963643fd0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627102768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_clk_byp_req_intersig_mubi.627102768
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2278126856
Short name T432
Test name
Test status
Simulation time 38794658 ps
CPU time 0.83 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201088 kb
Host smart-4063c1e9-4171-426a-b857-6af58a5c3efa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278126856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.2278126856
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2755055177
Short name T746
Test name
Test status
Simulation time 17841800 ps
CPU time 0.77 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201016 kb
Host smart-46d7f04d-1061-4e5a-8935-5749dbb0a96a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755055177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2755055177
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2701132290
Short name T569
Test name
Test status
Simulation time 594700758 ps
CPU time 3.86 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201248 kb
Host smart-8ae4849e-acfb-4f98-a935-558c98e59023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701132290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2701132290
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.2593009903
Short name T571
Test name
Test status
Simulation time 23776906 ps
CPU time 0.9 seconds
Started Jul 30 06:26:25 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201020 kb
Host smart-e68e8a3a-9279-4c37-b5a3-ffaf0e526a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593009903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2593009903
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.3016498858
Short name T659
Test name
Test status
Simulation time 11447682936 ps
CPU time 42.78 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:27:01 PM PDT 24
Peak memory 201508 kb
Host smart-16d0e5be-369d-4d90-b23f-83a0e10221ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016498858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.3016498858
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1935755094
Short name T716
Test name
Test status
Simulation time 259846136 ps
CPU time 1.65 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201148 kb
Host smart-c1399569-3950-43db-8bc9-402802589d94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935755094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1935755094
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3011206900
Short name T643
Test name
Test status
Simulation time 17013270 ps
CPU time 0.84 seconds
Started Jul 30 06:26:20 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201016 kb
Host smart-c95de790-cc56-4214-b0c0-395cf6be255e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011206900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3011206900
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.1961552997
Short name T572
Test name
Test status
Simulation time 28166513 ps
CPU time 0.81 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201076 kb
Host smart-ba06135c-97ef-46ab-a20d-cfc336a56a47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961552997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.1961552997
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.3517625888
Short name T599
Test name
Test status
Simulation time 12901803 ps
CPU time 0.7 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 200256 kb
Host smart-a0791b71-3fd4-41d8-b3bc-4f0a104d5d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517625888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3517625888
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.740869400
Short name T786
Test name
Test status
Simulation time 25655505 ps
CPU time 0.86 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201148 kb
Host smart-1df81b0c-77b3-409b-b3c9-dee420381c30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740869400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.clkmgr_div_intersig_mubi.740869400
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.3606823773
Short name T293
Test name
Test status
Simulation time 34875075 ps
CPU time 0.86 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201024 kb
Host smart-acb60d68-89b9-4885-9893-8aca8bb2fc64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606823773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.3606823773
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.3315128569
Short name T27
Test name
Test status
Simulation time 1411321378 ps
CPU time 8.1 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201184 kb
Host smart-e12e7d1e-67c6-45ef-b1da-a87ea8f6f738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315128569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3315128569
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.2256182159
Short name T427
Test name
Test status
Simulation time 2568421147 ps
CPU time 8.59 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 201384 kb
Host smart-c3f35d63-a955-4766-9864-34dc98691468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256182159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.2256182159
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1332997288
Short name T821
Test name
Test status
Simulation time 60812630 ps
CPU time 0.89 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201060 kb
Host smart-d05f0cf5-b2ba-406b-ba21-e9a8720574fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332997288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1332997288
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3659286958
Short name T370
Test name
Test status
Simulation time 44602569 ps
CPU time 0.89 seconds
Started Jul 30 06:26:23 PM PDT 24
Finished Jul 30 06:26:24 PM PDT 24
Peak memory 201052 kb
Host smart-2f449591-5174-4da8-a684-c259d5e64714
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659286958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3659286958
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2194114927
Short name T575
Test name
Test status
Simulation time 61579423 ps
CPU time 0.93 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201008 kb
Host smart-b032ba45-c61d-42b3-9d4f-c171121f13d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194114927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.2194114927
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.239011285
Short name T580
Test name
Test status
Simulation time 45151378 ps
CPU time 0.82 seconds
Started Jul 30 06:26:18 PM PDT 24
Finished Jul 30 06:26:19 PM PDT 24
Peak memory 201264 kb
Host smart-bf2e836a-312a-45b6-a4ca-f0770c50971d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239011285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.239011285
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.4019027883
Short name T766
Test name
Test status
Simulation time 947293606 ps
CPU time 5.44 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201264 kb
Host smart-4e4c0e02-a3e1-4f8f-927f-d22f37b5da12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019027883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.4019027883
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.603707498
Short name T441
Test name
Test status
Simulation time 76024763 ps
CPU time 1.04 seconds
Started Jul 30 06:26:19 PM PDT 24
Finished Jul 30 06:26:20 PM PDT 24
Peak memory 201064 kb
Host smart-ede61048-0cd6-4386-8308-4a6a06a2a974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603707498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.603707498
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1706829296
Short name T365
Test name
Test status
Simulation time 10220869250 ps
CPU time 55.45 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:27:21 PM PDT 24
Peak memory 201464 kb
Host smart-551400ca-0320-442e-af5a-a2e1d1fb6c64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706829296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1706829296
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.694150721
Short name T57
Test name
Test status
Simulation time 58744890863 ps
CPU time 356.29 seconds
Started Jul 30 06:26:20 PM PDT 24
Finished Jul 30 06:32:17 PM PDT 24
Peak memory 209792 kb
Host smart-5fbad061-89b7-438e-b367-ec0d6f29e510
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=694150721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.694150721
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.581506752
Short name T359
Test name
Test status
Simulation time 378339535 ps
CPU time 1.99 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201120 kb
Host smart-9c463551-9615-4e91-b037-a51d79840cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581506752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.581506752
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1685633225
Short name T325
Test name
Test status
Simulation time 17310684 ps
CPU time 0.74 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201040 kb
Host smart-d6e8b60c-5201-48df-9197-885750b1ac71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685633225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1685633225
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2698351815
Short name T614
Test name
Test status
Simulation time 87066297 ps
CPU time 1.12 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201108 kb
Host smart-c3e8186f-9579-471a-8ac7-360260454db7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698351815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2698351815
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.1981545475
Short name T771
Test name
Test status
Simulation time 159947598 ps
CPU time 1.07 seconds
Started Jul 30 06:26:35 PM PDT 24
Finished Jul 30 06:26:36 PM PDT 24
Peak memory 200260 kb
Host smart-d9abada5-727e-40fc-ae02-f7c17faa297f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981545475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.1981545475
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.3761142060
Short name T72
Test name
Test status
Simulation time 37282121 ps
CPU time 0.83 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201032 kb
Host smart-61202269-ecbd-41e5-938f-31cd8378b76d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761142060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.3761142060
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.2904177765
Short name T540
Test name
Test status
Simulation time 25768058 ps
CPU time 0.9 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201080 kb
Host smart-aec7240a-f30d-437c-9ab4-228c26b662a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904177765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.2904177765
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2975817740
Short name T388
Test name
Test status
Simulation time 324088595 ps
CPU time 2.37 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201184 kb
Host smart-2f3cb018-0541-4075-9874-5dd55cbc72ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975817740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2975817740
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.3803551580
Short name T380
Test name
Test status
Simulation time 1122091791 ps
CPU time 5.25 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:36 PM PDT 24
Peak memory 201208 kb
Host smart-9a4b0dfc-472f-4a01-bad3-ea604a268194
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803551580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.3803551580
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.1660873382
Short name T726
Test name
Test status
Simulation time 29920101 ps
CPU time 0.77 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 201048 kb
Host smart-dcbdfa89-3918-4e80-9fcd-d3f4f3361b66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660873382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.1660873382
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1216731376
Short name T342
Test name
Test status
Simulation time 38493163 ps
CPU time 0.85 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201116 kb
Host smart-8707fcf7-bd59-40ed-97a7-9b0fd8e082a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216731376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1216731376
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.444940723
Short name T372
Test name
Test status
Simulation time 51202469 ps
CPU time 0.87 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201124 kb
Host smart-a69ed822-22da-4078-bee3-f58ac733bf77
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444940723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.444940723
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.3692845212
Short name T328
Test name
Test status
Simulation time 26604078 ps
CPU time 0.77 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201052 kb
Host smart-7b169651-c0dd-431c-adcf-7e1988cbe96e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692845212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3692845212
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.3095648596
Short name T610
Test name
Test status
Simulation time 1254097199 ps
CPU time 4.89 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201244 kb
Host smart-541c5a19-0156-4d9a-b11a-6b2540e327c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095648596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3095648596
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1987272450
Short name T794
Test name
Test status
Simulation time 25324750 ps
CPU time 0.9 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 201068 kb
Host smart-39d44d88-0dee-471e-a6b8-b3e1c0053d1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987272450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1987272450
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1311677534
Short name T460
Test name
Test status
Simulation time 2118696692 ps
CPU time 17.29 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:48 PM PDT 24
Peak memory 201448 kb
Host smart-ed686c00-067b-4c00-9949-0f7686212a0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311677534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1311677534
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.493933632
Short name T470
Test name
Test status
Simulation time 19781928 ps
CPU time 0.81 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201072 kb
Host smart-b5982ff4-d915-4e42-85bb-91f021553990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493933632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.493933632
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.1983752231
Short name T413
Test name
Test status
Simulation time 35000784 ps
CPU time 0.78 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201096 kb
Host smart-8446223a-fb6f-44e4-b4be-1b20f655e45a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983752231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.1983752231
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.25121673
Short name T731
Test name
Test status
Simulation time 25366321 ps
CPU time 0.93 seconds
Started Jul 30 06:26:25 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201060 kb
Host smart-492b0443-b235-494e-8efa-70f98e977180
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_clk_handshake_intersig_mubi.25121673
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.205111273
Short name T37
Test name
Test status
Simulation time 15791979 ps
CPU time 0.74 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 200232 kb
Host smart-4065ce65-f418-47cb-a88d-5fa106954f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205111273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.205111273
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2424190655
Short name T407
Test name
Test status
Simulation time 22090868 ps
CPU time 0.76 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201136 kb
Host smart-12f6f2c7-40d4-45c8-9fcc-d9b32de2268b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424190655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2424190655
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.2086162538
Short name T672
Test name
Test status
Simulation time 44155977 ps
CPU time 0.94 seconds
Started Jul 30 06:26:22 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201088 kb
Host smart-e02e7fb7-a308-4fde-b3ea-f67dc6044b3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086162538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2086162538
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.2550231992
Short name T814
Test name
Test status
Simulation time 1283077477 ps
CPU time 6.92 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 201144 kb
Host smart-d7dfe395-d7a0-431d-ba3d-b4177c75dac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550231992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2550231992
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3238244022
Short name T767
Test name
Test status
Simulation time 2430301396 ps
CPU time 11.57 seconds
Started Jul 30 06:26:25 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 201472 kb
Host smart-7a52933f-64e7-4d78-a667-aa95cfa7ed61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238244022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3238244022
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.74166836
Short name T454
Test name
Test status
Simulation time 17464538 ps
CPU time 0.78 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201076 kb
Host smart-709b99d8-c760-4e90-86d6-d7f82da6473d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74166836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.clkmgr_idle_intersig_mubi.74166836
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.370868278
Short name T830
Test name
Test status
Simulation time 70859741 ps
CPU time 1.02 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201084 kb
Host smart-c61d25b5-a1e3-4cc4-82cd-0f9fa5a9ab23
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370868278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_clk_byp_req_intersig_mubi.370868278
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2100572767
Short name T348
Test name
Test status
Simulation time 13689124 ps
CPU time 0.72 seconds
Started Jul 30 06:26:23 PM PDT 24
Finished Jul 30 06:26:23 PM PDT 24
Peak memory 201116 kb
Host smart-70b2d8c3-0439-45da-aa15-3a4dc075c281
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100572767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.2100572767
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.1125395934
Short name T371
Test name
Test status
Simulation time 27236096 ps
CPU time 0.78 seconds
Started Jul 30 06:26:34 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201056 kb
Host smart-b405fceb-a00e-4f0e-b7a9-ff03bc64a203
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125395934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1125395934
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.1470439055
Short name T714
Test name
Test status
Simulation time 662549655 ps
CPU time 2.75 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201292 kb
Host smart-84b1abb6-af1e-43e2-a087-5698e32b7412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470439055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1470439055
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.1636597649
Short name T815
Test name
Test status
Simulation time 45871755 ps
CPU time 0.9 seconds
Started Jul 30 06:26:20 PM PDT 24
Finished Jul 30 06:26:21 PM PDT 24
Peak memory 201148 kb
Host smart-bdc5d678-eeb2-4b8a-a205-481f585b994c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636597649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.1636597649
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.2907081786
Short name T458
Test name
Test status
Simulation time 25191473 ps
CPU time 0.86 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 200976 kb
Host smart-822c0a30-b5aa-4f82-92b2-9217ebd44907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907081786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.2907081786
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.587474118
Short name T224
Test name
Test status
Simulation time 27663751 ps
CPU time 0.77 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201036 kb
Host smart-a2dd758c-7ad4-4d82-954b-49792a166373
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587474118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.587474118
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.1907115171
Short name T655
Test name
Test status
Simulation time 64785019 ps
CPU time 0.96 seconds
Started Jul 30 06:26:25 PM PDT 24
Finished Jul 30 06:26:26 PM PDT 24
Peak memory 201056 kb
Host smart-1f1f5c6a-2908-407b-814e-d3072e46f9a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907115171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.1907115171
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2648353816
Short name T319
Test name
Test status
Simulation time 60095783 ps
CPU time 1 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 200820 kb
Host smart-0e866ab7-6c5a-4e63-8e48-b495861dd290
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648353816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.2648353816
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.2899871843
Short name T462
Test name
Test status
Simulation time 129210673 ps
CPU time 1 seconds
Started Jul 30 06:26:34 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 200988 kb
Host smart-ff6eacaf-ca01-447c-8f90-b4f434d079d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899871843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.2899871843
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.4108960000
Short name T205
Test name
Test status
Simulation time 175304442 ps
CPU time 1.24 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 200620 kb
Host smart-09d7365a-f2c6-497b-9ed2-44f987d860c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108960000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.4108960000
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.89692198
Short name T552
Test name
Test status
Simulation time 76667185 ps
CPU time 1.06 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201116 kb
Host smart-4e4aeafa-7ce4-47f9-9ff4-3219d0cb8303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89692198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.89692198
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.915556331
Short name T216
Test name
Test status
Simulation time 1881207294 ps
CPU time 14.8 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:42 PM PDT 24
Peak memory 201340 kb
Host smart-5f0c2acb-d581-4426-a2f9-ce2e8655ca09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915556331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.915556331
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.3440771236
Short name T288
Test name
Test status
Simulation time 1338635509 ps
CPU time 10.13 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:41 PM PDT 24
Peak memory 200832 kb
Host smart-72bb1f1e-c89d-4b51-980c-57bdad3f6ec7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440771236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.3440771236
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.516395723
Short name T268
Test name
Test status
Simulation time 23872428 ps
CPU time 0.88 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201092 kb
Host smart-6e5d8e7b-b10b-4e46-9b4b-ed1a7a993c56
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516395723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_idle_intersig_mubi.516395723
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.1903322534
Short name T469
Test name
Test status
Simulation time 36322514 ps
CPU time 0.79 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201016 kb
Host smart-d95ae82a-a021-4e7e-9b24-e968dacb8555
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903322534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.1903322534
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.3012147989
Short name T155
Test name
Test status
Simulation time 69416548 ps
CPU time 0.98 seconds
Started Jul 30 06:26:24 PM PDT 24
Finished Jul 30 06:26:25 PM PDT 24
Peak memory 201096 kb
Host smart-793f7ce1-6844-48ad-ba9f-61a24e8e8199
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012147989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.3012147989
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.3943572787
Short name T239
Test name
Test status
Simulation time 20870638 ps
CPU time 0.73 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201052 kb
Host smart-6ea3c282-8d1e-415f-b277-9b744b1f6b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943572787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3943572787
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2652899855
Short name T747
Test name
Test status
Simulation time 305983213 ps
CPU time 1.83 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201136 kb
Host smart-10abed30-a88f-44bc-9609-b3b57aa0c816
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652899855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2652899855
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.118489592
Short name T627
Test name
Test status
Simulation time 21951055 ps
CPU time 0.89 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201012 kb
Host smart-6aff8243-8b68-4e35-8c5f-a51befbfc90d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118489592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.118489592
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.4169662768
Short name T528
Test name
Test status
Simulation time 8340147894 ps
CPU time 58.34 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:27:35 PM PDT 24
Peak memory 201380 kb
Host smart-94d9a469-c46f-4762-887e-055aa1c61ed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169662768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.4169662768
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2679509066
Short name T818
Test name
Test status
Simulation time 52374666 ps
CPU time 0.99 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201028 kb
Host smart-a75155cd-3f63-4501-b4ab-6d8e4bef929a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679509066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2679509066
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2858788562
Short name T423
Test name
Test status
Simulation time 47395326 ps
CPU time 0.84 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201088 kb
Host smart-e3890ae4-92a6-4d29-a86f-f06d5a91083f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858788562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2858788562
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2004009766
Short name T77
Test name
Test status
Simulation time 30798432 ps
CPU time 0.89 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 200696 kb
Host smart-d7c8afd5-d0f1-4775-89a4-a7690b7c849d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004009766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2004009766
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.3280682869
Short name T817
Test name
Test status
Simulation time 16391496 ps
CPU time 0.79 seconds
Started Jul 30 06:26:21 PM PDT 24
Finished Jul 30 06:26:22 PM PDT 24
Peak memory 200324 kb
Host smart-02d6e574-ae6f-46d9-a096-f7663178f37b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280682869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.3280682869
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.3083432720
Short name T209
Test name
Test status
Simulation time 14871447 ps
CPU time 0.76 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201008 kb
Host smart-efb3a19e-6fa6-4736-8001-b0a40182f6f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083432720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.3083432720
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.3698776981
Short name T170
Test name
Test status
Simulation time 16947128 ps
CPU time 0.78 seconds
Started Jul 30 06:26:26 PM PDT 24
Finished Jul 30 06:26:27 PM PDT 24
Peak memory 201008 kb
Host smart-0b85216a-8433-40e5-b62e-e7e42ce6cd80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698776981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3698776981
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.2818005432
Short name T804
Test name
Test status
Simulation time 2479284230 ps
CPU time 13.82 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:44 PM PDT 24
Peak memory 201356 kb
Host smart-d5d773b1-da35-407b-a6a0-24d39c4f2f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818005432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.2818005432
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.1123345407
Short name T269
Test name
Test status
Simulation time 1702204839 ps
CPU time 12.19 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:42 PM PDT 24
Peak memory 201220 kb
Host smart-7950b12b-2696-4ce7-a737-39e247d0191d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123345407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.1123345407
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3603544557
Short name T725
Test name
Test status
Simulation time 61962902 ps
CPU time 0.97 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 201016 kb
Host smart-fcdb1b4d-273b-4474-85ab-9291c8944234
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603544557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3603544557
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3877421522
Short name T197
Test name
Test status
Simulation time 21181328 ps
CPU time 0.84 seconds
Started Jul 30 06:26:23 PM PDT 24
Finished Jul 30 06:26:24 PM PDT 24
Peak memory 201060 kb
Host smart-337544ad-714e-4eba-9671-07b00841723a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877421522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3877421522
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.2877876446
Short name T531
Test name
Test status
Simulation time 61815645 ps
CPU time 0.93 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201076 kb
Host smart-83ffe158-a0a8-4ff9-a48f-fbc15bffa99b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877876446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.2877876446
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.380318592
Short name T656
Test name
Test status
Simulation time 13159073 ps
CPU time 0.76 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 201024 kb
Host smart-61c3d845-ccdc-49f3-9118-36fcb39b4bf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380318592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.380318592
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2818581287
Short name T201
Test name
Test status
Simulation time 198594801 ps
CPU time 1.46 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201080 kb
Host smart-055eb90b-dc32-4258-877a-8ca8fd8d3342
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818581287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2818581287
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.3572431339
Short name T519
Test name
Test status
Simulation time 104941349 ps
CPU time 1.08 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 200764 kb
Host smart-91242f16-c8bf-4674-bccd-e35e88a1b47f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572431339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.3572431339
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2200911400
Short name T475
Test name
Test status
Simulation time 90363973 ps
CPU time 1.06 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201124 kb
Host smart-af34d577-5f49-449b-a0ad-0e9b2c5096a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200911400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2200911400
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.4026598674
Short name T429
Test name
Test status
Simulation time 56421916946 ps
CPU time 245.53 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:30:43 PM PDT 24
Peak memory 209492 kb
Host smart-d504d1cf-5fa7-490d-b203-8d72ef3502c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4026598674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.4026598674
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2802364804
Short name T280
Test name
Test status
Simulation time 20658568 ps
CPU time 0.85 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201128 kb
Host smart-893f2146-ea97-48fc-8484-3aa0fec17e13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802364804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2802364804
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.2573803870
Short name T756
Test name
Test status
Simulation time 50429307 ps
CPU time 0.92 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 201116 kb
Host smart-6b0d60bb-b77a-4b6f-bce2-a2afda04bcb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573803870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.2573803870
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2039896994
Short name T640
Test name
Test status
Simulation time 112333940 ps
CPU time 1.31 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201156 kb
Host smart-dec1e13e-3514-4ee1-b0d5-79974faff48c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039896994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2039896994
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.897602127
Short name T382
Test name
Test status
Simulation time 24902650 ps
CPU time 0.79 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 200228 kb
Host smart-25183007-0dc7-4224-b9d6-8c6c875fe4c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897602127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.897602127
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.317153910
Short name T173
Test name
Test status
Simulation time 83868718 ps
CPU time 1.04 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 201096 kb
Host smart-758ad6a1-78f8-4e4b-8169-4ba3ca1dde52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317153910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.317153910
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.1240253870
Short name T541
Test name
Test status
Simulation time 53909615 ps
CPU time 0.92 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 200708 kb
Host smart-7957bca1-6bd6-475b-8677-a6b1de7a5bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240253870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.1240253870
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.3607836443
Short name T330
Test name
Test status
Simulation time 1932235177 ps
CPU time 8.94 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:38 PM PDT 24
Peak memory 201296 kb
Host smart-96f0c373-971c-4ffa-932d-cfa4720aed91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607836443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3607836443
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.1770449690
Short name T389
Test name
Test status
Simulation time 265472628 ps
CPU time 1.8 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:30 PM PDT 24
Peak memory 201156 kb
Host smart-e6f6071c-6511-47ad-a92d-ee206fb78251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770449690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.1770449690
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2585417097
Short name T5
Test name
Test status
Simulation time 25548342 ps
CPU time 0.92 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201136 kb
Host smart-e82a3fa7-de02-445a-a755-f730ec7eb098
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585417097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2585417097
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.2788041997
Short name T668
Test name
Test status
Simulation time 59780032 ps
CPU time 0.97 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201160 kb
Host smart-a77c04b7-a718-426a-b8ea-08b06c990d8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788041997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.2788041997
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2990397435
Short name T339
Test name
Test status
Simulation time 140176207 ps
CPU time 1.11 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201100 kb
Host smart-a7add2d0-06dc-4403-91c1-ec898cd1818f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990397435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2990397435
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.4039663157
Short name T213
Test name
Test status
Simulation time 31390098 ps
CPU time 0.77 seconds
Started Jul 30 06:26:36 PM PDT 24
Finished Jul 30 06:26:37 PM PDT 24
Peak memory 200988 kb
Host smart-9c8e5468-d60b-4deb-aab5-3a59c4162c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039663157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.4039663157
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.3654667977
Short name T352
Test name
Test status
Simulation time 117675604 ps
CPU time 0.99 seconds
Started Jul 30 06:26:24 PM PDT 24
Finished Jul 30 06:26:25 PM PDT 24
Peak memory 201016 kb
Host smart-2041352c-5710-422f-95fe-2f87438dd9e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654667977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.3654667977
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.3376600465
Short name T743
Test name
Test status
Simulation time 27024980 ps
CPU time 0.85 seconds
Started Jul 30 06:26:27 PM PDT 24
Finished Jul 30 06:26:28 PM PDT 24
Peak memory 200992 kb
Host smart-d5afddbf-8a83-4e97-8a89-a046dfbf4f0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376600465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3376600465
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.2711298974
Short name T15
Test name
Test status
Simulation time 4012704242 ps
CPU time 17.74 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:46 PM PDT 24
Peak memory 201460 kb
Host smart-d3dc5e43-56a8-4b6f-b578-ca8085ea059c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711298974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.2711298974
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.123716344
Short name T282
Test name
Test status
Simulation time 112918669 ps
CPU time 1.22 seconds
Started Jul 30 06:26:28 PM PDT 24
Finished Jul 30 06:26:29 PM PDT 24
Peak memory 201092 kb
Host smart-8b51b1de-394e-4acf-91cf-8990dc8db7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123716344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.123716344
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.2109932759
Short name T256
Test name
Test status
Simulation time 15917711 ps
CPU time 0.81 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:38 PM PDT 24
Peak memory 201116 kb
Host smart-1b02c991-b4c6-4ea3-bb3d-cb9807f4d253
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109932759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.2109932759
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1779093469
Short name T60
Test name
Test status
Simulation time 23354098 ps
CPU time 0.89 seconds
Started Jul 30 06:26:35 PM PDT 24
Finished Jul 30 06:26:36 PM PDT 24
Peak memory 201104 kb
Host smart-795cca37-5a6c-45be-a07c-e1b869555a51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779093469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1779093469
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.3334060098
Short name T553
Test name
Test status
Simulation time 16455943 ps
CPU time 0.78 seconds
Started Jul 30 06:26:32 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 200316 kb
Host smart-a0d8c779-c68c-451c-abe4-b500c554b033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334060098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.3334060098
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.1140437081
Short name T611
Test name
Test status
Simulation time 79846615 ps
CPU time 1.01 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201128 kb
Host smart-4b661ff8-3892-4099-8db5-200ee88c2f8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140437081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.1140437081
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2688790832
Short name T669
Test name
Test status
Simulation time 114362977 ps
CPU time 1.06 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201032 kb
Host smart-8f8fefc9-5a44-44e5-9abc-16eb4d49f487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688790832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2688790832
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.3423953266
Short name T532
Test name
Test status
Simulation time 2028232571 ps
CPU time 8.85 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:39 PM PDT 24
Peak memory 201376 kb
Host smart-6b1b1517-0a12-4ae1-a134-c81a7c883685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423953266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3423953266
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.1871857882
Short name T563
Test name
Test status
Simulation time 982643807 ps
CPU time 5.33 seconds
Started Jul 30 06:26:30 PM PDT 24
Finished Jul 30 06:26:35 PM PDT 24
Peak memory 201240 kb
Host smart-429ae1ec-56e9-43dd-a9c8-c891ae86c6b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871857882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.1871857882
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.427205565
Short name T292
Test name
Test status
Simulation time 74504260 ps
CPU time 1.14 seconds
Started Jul 30 06:26:29 PM PDT 24
Finished Jul 30 06:26:31 PM PDT 24
Peak memory 201084 kb
Host smart-698ebfac-bd03-4cda-9999-0684ad38344c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427205565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_idle_intersig_mubi.427205565
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3109342541
Short name T287
Test name
Test status
Simulation time 88452788 ps
CPU time 0.94 seconds
Started Jul 30 06:26:33 PM PDT 24
Finished Jul 30 06:26:34 PM PDT 24
Peak memory 201076 kb
Host smart-3b19d1bb-5e13-4608-9aad-2cb2f47467f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109342541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3109342541
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3151963830
Short name T486
Test name
Test status
Simulation time 79097027 ps
CPU time 1.01 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201004 kb
Host smart-ff823e10-a2d1-41d8-ac4b-a89b78633e76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151963830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3151963830
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.4090718278
Short name T384
Test name
Test status
Simulation time 15033432 ps
CPU time 0.72 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201108 kb
Host smart-22d1cf30-cd74-4eb5-96a2-cbed770dd0be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090718278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.4090718278
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.2564650915
Short name T538
Test name
Test status
Simulation time 135349567 ps
CPU time 1.07 seconds
Started Jul 30 06:26:39 PM PDT 24
Finished Jul 30 06:26:40 PM PDT 24
Peak memory 201056 kb
Host smart-6273db2c-bd07-4c84-8138-af00d7c3cb60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564650915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2564650915
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.298752341
Short name T217
Test name
Test status
Simulation time 17503713 ps
CPU time 0.83 seconds
Started Jul 30 06:26:37 PM PDT 24
Finished Jul 30 06:26:38 PM PDT 24
Peak memory 200764 kb
Host smart-beb4d507-5c62-470b-aac9-34c50fee4396
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298752341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.298752341
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.762284692
Short name T200
Test name
Test status
Simulation time 111916007 ps
CPU time 1.07 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:33 PM PDT 24
Peak memory 201076 kb
Host smart-4ad18a7b-ef7d-4a5a-b813-f43a283aebf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762284692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.762284692
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1411072008
Short name T459
Test name
Test status
Simulation time 63717838 ps
CPU time 0.93 seconds
Started Jul 30 06:26:31 PM PDT 24
Finished Jul 30 06:26:32 PM PDT 24
Peak memory 201116 kb
Host smart-c59acca8-b19e-4242-8b1f-773a25e656f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411072008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1411072008
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.1962518483
Short name T588
Test name
Test status
Simulation time 65341161 ps
CPU time 0.89 seconds
Started Jul 30 06:24:55 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 201048 kb
Host smart-854c310f-1568-4f2b-b12c-341109d1f6d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962518483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.1962518483
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.514928188
Short name T104
Test name
Test status
Simulation time 29623788 ps
CPU time 0.83 seconds
Started Jul 30 06:24:51 PM PDT 24
Finished Jul 30 06:24:52 PM PDT 24
Peak memory 201048 kb
Host smart-558253f6-c93e-4687-8d17-361fd0bceda6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514928188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.514928188
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1661597834
Short name T279
Test name
Test status
Simulation time 43335863 ps
CPU time 0.79 seconds
Started Jul 30 06:24:48 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 200976 kb
Host smart-d92daf52-fd74-4dad-aa6a-283a5565dbb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661597834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1661597834
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1086466192
Short name T343
Test name
Test status
Simulation time 36759057 ps
CPU time 0.82 seconds
Started Jul 30 06:24:56 PM PDT 24
Finished Jul 30 06:24:57 PM PDT 24
Peak memory 201076 kb
Host smart-f61d8ae9-57c7-4814-881c-c08b5860d22d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086466192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1086466192
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.86441729
Short name T317
Test name
Test status
Simulation time 19781344 ps
CPU time 0.85 seconds
Started Jul 30 06:24:47 PM PDT 24
Finished Jul 30 06:24:48 PM PDT 24
Peak memory 201048 kb
Host smart-9a4265b1-da95-4725-a1ad-e5cd1fd9e648
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86441729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.86441729
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.62848070
Short name T677
Test name
Test status
Simulation time 1041508463 ps
CPU time 8.62 seconds
Started Jul 30 06:24:52 PM PDT 24
Finished Jul 30 06:25:01 PM PDT 24
Peak memory 201140 kb
Host smart-71a60f13-8c8a-4fe3-b4da-00a271f12ee8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62848070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.62848070
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1973177864
Short name T675
Test name
Test status
Simulation time 2055960173 ps
CPU time 15.37 seconds
Started Jul 30 06:24:49 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201332 kb
Host smart-9d8facdf-55c2-4298-9ac1-45e19b4a1436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973177864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1973177864
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3442991690
Short name T366
Test name
Test status
Simulation time 54990951 ps
CPU time 1.13 seconds
Started Jul 30 06:24:51 PM PDT 24
Finished Jul 30 06:24:52 PM PDT 24
Peak memory 200988 kb
Host smart-9f399222-83f2-476a-adff-6e14fc10674c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442991690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3442991690
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3908653579
Short name T759
Test name
Test status
Simulation time 76436494 ps
CPU time 1.03 seconds
Started Jul 30 06:24:52 PM PDT 24
Finished Jul 30 06:24:53 PM PDT 24
Peak memory 201080 kb
Host smart-8277df92-006f-4ef0-bd5b-b256ad968299
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908653579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.3908653579
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.863817287
Short name T749
Test name
Test status
Simulation time 74522369 ps
CPU time 0.99 seconds
Started Jul 30 06:24:49 PM PDT 24
Finished Jul 30 06:24:50 PM PDT 24
Peak memory 201088 kb
Host smart-9a93b421-7bbb-4e7a-a128-5713010c94bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863817287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_ctrl_intersig_mubi.863817287
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3759592875
Short name T638
Test name
Test status
Simulation time 23132230 ps
CPU time 0.71 seconds
Started Jul 30 06:24:48 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201120 kb
Host smart-1482c7cd-4998-40ff-95ce-93feb5ea7331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759592875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3759592875
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1494422910
Short name T191
Test name
Test status
Simulation time 145503351 ps
CPU time 1.1 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:24:51 PM PDT 24
Peak memory 201060 kb
Host smart-1e62a209-e639-4033-be07-f714adbb8983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494422910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1494422910
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.1519663083
Short name T181
Test name
Test status
Simulation time 43777454 ps
CPU time 0.9 seconds
Started Jul 30 06:24:45 PM PDT 24
Finished Jul 30 06:24:46 PM PDT 24
Peak memory 201080 kb
Host smart-9cf2e0ce-79e1-4297-a928-daf051e4019f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519663083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.1519663083
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.3973763795
Short name T760
Test name
Test status
Simulation time 5234727129 ps
CPU time 22.93 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:25:13 PM PDT 24
Peak memory 201528 kb
Host smart-67079ffd-ec4f-4e04-9b8b-6aa5f62d3bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973763795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.3973763795
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.3681577559
Short name T620
Test name
Test status
Simulation time 25254609 ps
CPU time 0.92 seconds
Started Jul 30 06:24:48 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201112 kb
Host smart-ad49481f-651d-4645-a5c2-31522d2ae976
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681577559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3681577559
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.2180070142
Short name T606
Test name
Test status
Simulation time 14838768 ps
CPU time 0.76 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201064 kb
Host smart-6d50b7c7-fd97-4ac6-a930-65d88a2a953a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180070142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.2180070142
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2996446081
Short name T539
Test name
Test status
Simulation time 56262543 ps
CPU time 0.92 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201088 kb
Host smart-1bb4c49f-09ea-4d19-babf-03b8a01061d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996446081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2996446081
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2012794600
Short name T484
Test name
Test status
Simulation time 31556046 ps
CPU time 0.74 seconds
Started Jul 30 06:24:55 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 200984 kb
Host smart-61befee6-d997-40c2-83be-cb6e732fca04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012794600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2012794600
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.4168847132
Short name T100
Test name
Test status
Simulation time 77742564 ps
CPU time 1.06 seconds
Started Jul 30 06:24:53 PM PDT 24
Finished Jul 30 06:24:54 PM PDT 24
Peak memory 201084 kb
Host smart-d7b6fd07-82ed-44da-8ae0-6f6186113106
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168847132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.4168847132
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.820786063
Short name T765
Test name
Test status
Simulation time 13745342 ps
CPU time 0.8 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:24:50 PM PDT 24
Peak memory 201096 kb
Host smart-8f5212c2-b7bd-411a-91ec-8dfe47a447df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820786063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.820786063
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.571936759
Short name T621
Test name
Test status
Simulation time 1639155275 ps
CPU time 12.25 seconds
Started Jul 30 06:24:50 PM PDT 24
Finished Jul 30 06:25:02 PM PDT 24
Peak memory 201184 kb
Host smart-4496b83e-c639-42c2-924f-f3743cb1a44c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571936759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.571936759
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1693766315
Short name T824
Test name
Test status
Simulation time 525386238 ps
CPU time 2.73 seconds
Started Jul 30 06:24:53 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 201204 kb
Host smart-6dad026c-506d-4843-a9e4-e59476c499b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693766315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1693766315
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1232768031
Short name T253
Test name
Test status
Simulation time 116799732 ps
CPU time 1.11 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201112 kb
Host smart-b3f50bc3-4af9-425b-8070-b42334446dd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232768031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.1232768031
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.148012843
Short name T729
Test name
Test status
Simulation time 88577675 ps
CPU time 1.04 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 201068 kb
Host smart-ac6f82a1-ed3b-4f87-bc80-a1ae4022cf2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148012843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_clk_byp_req_intersig_mubi.148012843
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1031443859
Short name T664
Test name
Test status
Simulation time 26739623 ps
CPU time 0.84 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201080 kb
Host smart-c070bc50-2069-4648-88f7-9f2d933fe6b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031443859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1031443859
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.3099609061
Short name T803
Test name
Test status
Simulation time 82715129 ps
CPU time 0.94 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201060 kb
Host smart-3678fd1a-f6b3-43ab-810e-6aaf1872dd1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099609061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3099609061
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3347090719
Short name T97
Test name
Test status
Simulation time 816061736 ps
CPU time 5.13 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201320 kb
Host smart-800aa043-0175-4f2c-944c-50f693330981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347090719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3347090719
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1420808788
Short name T769
Test name
Test status
Simulation time 92653440 ps
CPU time 1.06 seconds
Started Jul 30 06:24:48 PM PDT 24
Finished Jul 30 06:24:49 PM PDT 24
Peak memory 201036 kb
Host smart-7e4f4ce9-3781-4bec-8cd2-ea58fd481143
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420808788 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1420808788
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.4082784840
Short name T320
Test name
Test status
Simulation time 4971777896 ps
CPU time 37.65 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:35 PM PDT 24
Peak memory 201460 kb
Host smart-e6ce45aa-d307-4c2c-b505-c6a04d774c70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082784840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.4082784840
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1391423027
Short name T301
Test name
Test status
Simulation time 31352074 ps
CPU time 0.93 seconds
Started Jul 30 06:24:53 PM PDT 24
Finished Jul 30 06:24:54 PM PDT 24
Peak memory 201084 kb
Host smart-ce22c6a4-f4b3-442d-b800-04b813da16cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391423027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1391423027
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3583613979
Short name T247
Test name
Test status
Simulation time 19067251 ps
CPU time 0.81 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201120 kb
Host smart-332c522f-18f0-4300-8230-01ccfe5cc532
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583613979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3583613979
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.3316103305
Short name T428
Test name
Test status
Simulation time 23610049 ps
CPU time 0.92 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201132 kb
Host smart-f3b61dc2-1f56-4e88-bb29-c92576d4ca98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316103305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.3316103305
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.1491963644
Short name T616
Test name
Test status
Simulation time 24325959 ps
CPU time 0.72 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 200260 kb
Host smart-6fe2bea1-3058-4d27-8eee-005a67028740
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491963644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1491963644
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1866329775
Short name T207
Test name
Test status
Simulation time 59659939 ps
CPU time 0.96 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201108 kb
Host smart-49702ea2-7067-4342-9200-fc18f5fd327e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866329775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1866329775
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.1443400101
Short name T381
Test name
Test status
Simulation time 64988708 ps
CPU time 0.97 seconds
Started Jul 30 06:24:52 PM PDT 24
Finished Jul 30 06:24:53 PM PDT 24
Peak memory 201008 kb
Host smart-578c65ce-11ea-4112-aff3-2ca76022d364
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443400101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.1443400101
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.1458849591
Short name T390
Test name
Test status
Simulation time 1043956418 ps
CPU time 8.84 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:06 PM PDT 24
Peak memory 201164 kb
Host smart-b561d526-e839-473f-a99d-32c2b4ae55ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458849591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1458849591
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.32419340
Short name T707
Test name
Test status
Simulation time 1826108198 ps
CPU time 10.38 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201172 kb
Host smart-8443bc61-3927-4e29-8b87-b0f737d929fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32419340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_time
out.32419340
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.81337493
Short name T496
Test name
Test status
Simulation time 22274816 ps
CPU time 0.78 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201048 kb
Host smart-ba01a50e-0d26-4a65-8242-9a3450c43831
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81337493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
clkmgr_idle_intersig_mubi.81337493
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.241713765
Short name T241
Test name
Test status
Simulation time 127253135 ps
CPU time 1.2 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201056 kb
Host smart-f6621f3a-7510-472e-b75c-464293370914
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241713765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.clkmgr_lc_clk_byp_req_intersig_mubi.241713765
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.2422839794
Short name T211
Test name
Test status
Simulation time 101689648 ps
CPU time 1.17 seconds
Started Jul 30 06:24:55 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 201040 kb
Host smart-8531279b-812e-417f-8e8a-abe021c9bfbe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422839794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.2422839794
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.4121582784
Short name T438
Test name
Test status
Simulation time 40047321 ps
CPU time 0.81 seconds
Started Jul 30 06:24:54 PM PDT 24
Finished Jul 30 06:24:55 PM PDT 24
Peak memory 201116 kb
Host smart-9a5216ab-f432-4db2-8ced-6c52cd2a3b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121582784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.4121582784
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.2510901045
Short name T133
Test name
Test status
Simulation time 1020047512 ps
CPU time 6.41 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201300 kb
Host smart-52637c43-50a1-4e0e-9b44-baba20ae735e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510901045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2510901045
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.2152197979
Short name T141
Test name
Test status
Simulation time 21832405 ps
CPU time 0.88 seconds
Started Jul 30 06:24:55 PM PDT 24
Finished Jul 30 06:24:56 PM PDT 24
Peak memory 201068 kb
Host smart-c08719fa-49bb-4615-9575-b79226877e17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152197979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2152197979
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.4004988272
Short name T808
Test name
Test status
Simulation time 18949004041 ps
CPU time 57.48 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:55 PM PDT 24
Peak memory 201468 kb
Host smart-1b15a038-606e-43e1-b964-909ba2b158e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004988272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.4004988272
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.291775336
Short name T730
Test name
Test status
Simulation time 37471196 ps
CPU time 1.04 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201100 kb
Host smart-320b6333-59d0-48ac-9a6c-148e5d1c5d95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291775336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.291775336
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.1575372957
Short name T737
Test name
Test status
Simulation time 26349652 ps
CPU time 0.79 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201096 kb
Host smart-b72e6b44-69c1-48c4-be1b-691fa201321d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575372957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.1575372957
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2985062815
Short name T628
Test name
Test status
Simulation time 80582270 ps
CPU time 1.08 seconds
Started Jul 30 06:24:56 PM PDT 24
Finished Jul 30 06:24:57 PM PDT 24
Peak memory 201092 kb
Host smart-d601634e-c8a7-49ba-8420-8525dd87c9a1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985062815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.2985062815
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1958332554
Short name T145
Test name
Test status
Simulation time 34243470 ps
CPU time 0.72 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:57 PM PDT 24
Peak memory 200276 kb
Host smart-caebc97d-472f-49fe-a42f-20ccb8d8834b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958332554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1958332554
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.3767375513
Short name T505
Test name
Test status
Simulation time 15277601 ps
CPU time 0.77 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201040 kb
Host smart-f4834d59-b64e-412b-b3c0-c961389b0a3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767375513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.3767375513
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3127563389
Short name T442
Test name
Test status
Simulation time 59774270 ps
CPU time 0.97 seconds
Started Jul 30 06:24:59 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201036 kb
Host smart-a59848ad-60e8-472d-90cc-5f9fcb2efefd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127563389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3127563389
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.4202014408
Short name T251
Test name
Test status
Simulation time 1663605958 ps
CPU time 7.75 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:10 PM PDT 24
Peak memory 201144 kb
Host smart-e2b01772-1b52-45a8-80a0-add23c44125b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202014408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.4202014408
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.2731162428
Short name T526
Test name
Test status
Simulation time 2196094671 ps
CPU time 8.28 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201404 kb
Host smart-f22aa8b9-f66e-4496-a787-c112d1ed9731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731162428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.2731162428
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2642335879
Short name T513
Test name
Test status
Simulation time 22888226 ps
CPU time 0.77 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:24:59 PM PDT 24
Peak memory 201092 kb
Host smart-336616de-284b-4c2d-a447-611229a87968
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642335879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.2642335879
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2810948043
Short name T226
Test name
Test status
Simulation time 81278643 ps
CPU time 1.08 seconds
Started Jul 30 06:24:59 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201084 kb
Host smart-724a960b-a24d-4922-9843-23488a17daea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810948043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2810948043
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.116438222
Short name T471
Test name
Test status
Simulation time 24261139 ps
CPU time 0.82 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201072 kb
Host smart-d060b59e-c30c-4aac-8e3a-92470418ad71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116438222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_ctrl_intersig_mubi.116438222
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.912792268
Short name T208
Test name
Test status
Simulation time 26047958 ps
CPU time 0.76 seconds
Started Jul 30 06:24:56 PM PDT 24
Finished Jul 30 06:24:57 PM PDT 24
Peak memory 201048 kb
Host smart-6a94daa6-e7cf-4f87-86bc-b326f320d068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912792268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.912792268
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1461385819
Short name T507
Test name
Test status
Simulation time 1034006920 ps
CPU time 6.1 seconds
Started Jul 30 06:24:56 PM PDT 24
Finished Jul 30 06:25:02 PM PDT 24
Peak memory 201328 kb
Host smart-b99bde62-5a6b-4fc2-87cc-08077f34ea37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461385819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1461385819
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.2675643176
Short name T457
Test name
Test status
Simulation time 73514603 ps
CPU time 0.99 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201148 kb
Host smart-297f110e-94a7-4da7-933a-c1d2e1edd7cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675643176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.2675643176
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.1407927315
Short name T474
Test name
Test status
Simulation time 4738482221 ps
CPU time 30.27 seconds
Started Jul 30 06:24:56 PM PDT 24
Finished Jul 30 06:25:26 PM PDT 24
Peak memory 201452 kb
Host smart-341e8429-0c41-4593-9329-1779f9ebebb2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407927315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.1407927315
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.2513613883
Short name T709
Test name
Test status
Simulation time 34077996516 ps
CPU time 549.82 seconds
Started Jul 30 06:25:00 PM PDT 24
Finished Jul 30 06:34:10 PM PDT 24
Peak memory 217924 kb
Host smart-ee3db1c9-d7b6-42bc-a478-56a36d586636
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2513613883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.2513613883
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.3948451125
Short name T199
Test name
Test status
Simulation time 64335119 ps
CPU time 0.96 seconds
Started Jul 30 06:24:58 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201068 kb
Host smart-374c9694-be49-4bd3-a100-98cbcea84f22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948451125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3948451125
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.1761665417
Short name T481
Test name
Test status
Simulation time 21350879 ps
CPU time 0.85 seconds
Started Jul 30 06:25:03 PM PDT 24
Finished Jul 30 06:25:04 PM PDT 24
Peak memory 201088 kb
Host smart-9c12728f-2e9f-42d3-9bc8-4beeb5cb7446
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761665417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.1761665417
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.818152380
Short name T81
Test name
Test status
Simulation time 49857817 ps
CPU time 1 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:03 PM PDT 24
Peak memory 201072 kb
Host smart-84551fdd-17d6-4979-a936-a53d3e2a2ed3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818152380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.818152380
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.2670786124
Short name T499
Test name
Test status
Simulation time 15939634 ps
CPU time 0.74 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:03 PM PDT 24
Peak memory 200304 kb
Host smart-6cfd53e3-df64-468b-81cd-f80ef5f52e29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670786124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.2670786124
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1413413709
Short name T699
Test name
Test status
Simulation time 84344772 ps
CPU time 1.06 seconds
Started Jul 30 06:25:04 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201028 kb
Host smart-5de32d84-3700-4ff5-bfd9-1b842e2ef8de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413413709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.1413413709
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.310779552
Short name T583
Test name
Test status
Simulation time 17932270 ps
CPU time 0.75 seconds
Started Jul 30 06:24:57 PM PDT 24
Finished Jul 30 06:24:58 PM PDT 24
Peak memory 201020 kb
Host smart-a02101b4-247a-40ac-8ff5-3940e233b5a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310779552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.310779552
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.939549973
Short name T14
Test name
Test status
Simulation time 1403024533 ps
CPU time 8.24 seconds
Started Jul 30 06:24:59 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201156 kb
Host smart-a28ee48f-2f44-4169-941a-cb882ba8b3d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939549973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.939549973
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.2218048998
Short name T825
Test name
Test status
Simulation time 134895803 ps
CPU time 1.56 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:07 PM PDT 24
Peak memory 201216 kb
Host smart-a2d64a09-728b-401e-9717-369056f06604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218048998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.2218048998
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3797001190
Short name T218
Test name
Test status
Simulation time 16716416 ps
CPU time 0.79 seconds
Started Jul 30 06:25:04 PM PDT 24
Finished Jul 30 06:25:05 PM PDT 24
Peak memory 201132 kb
Host smart-b5d19702-4d4b-470d-8b92-bad518157ca3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797001190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.3797001190
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.3465320132
Short name T290
Test name
Test status
Simulation time 15946257 ps
CPU time 0.79 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:25:03 PM PDT 24
Peak memory 201060 kb
Host smart-53ed09fb-fe03-41b7-9709-e764ff015838
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465320132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.3465320132
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1626089738
Short name T463
Test name
Test status
Simulation time 33727377 ps
CPU time 0.87 seconds
Started Jul 30 06:25:16 PM PDT 24
Finished Jul 30 06:25:17 PM PDT 24
Peak memory 201008 kb
Host smart-945474a2-13b9-40d8-8e56-6c920b404e71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626089738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1626089738
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1449199883
Short name T332
Test name
Test status
Simulation time 35889820 ps
CPU time 0.87 seconds
Started Jul 30 06:24:59 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201040 kb
Host smart-2639b19f-4868-4d95-98c6-19b6027920fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449199883 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1449199883
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.4205124051
Short name T645
Test name
Test status
Simulation time 789752248 ps
CPU time 4.78 seconds
Started Jul 30 06:25:05 PM PDT 24
Finished Jul 30 06:25:10 PM PDT 24
Peak memory 201300 kb
Host smart-02f9f799-e345-43cf-985b-7fe1d1603d92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205124051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.4205124051
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.3727834116
Short name T131
Test name
Test status
Simulation time 28712034 ps
CPU time 0.96 seconds
Started Jul 30 06:24:59 PM PDT 24
Finished Jul 30 06:25:00 PM PDT 24
Peak memory 201016 kb
Host smart-879bf15c-4cbf-4a4a-9420-245102c3a649
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727834116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3727834116
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1770925567
Short name T59
Test name
Test status
Simulation time 37265824148 ps
CPU time 672.67 seconds
Started Jul 30 06:25:02 PM PDT 24
Finished Jul 30 06:36:14 PM PDT 24
Peak memory 217920 kb
Host smart-40e0f1d3-6f2f-48fe-b3cc-23b845b9a287
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1770925567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1770925567
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3384484011
Short name T172
Test name
Test status
Simulation time 17142789 ps
CPU time 0.81 seconds
Started Jul 30 06:25:00 PM PDT 24
Finished Jul 30 06:25:01 PM PDT 24
Peak memory 201036 kb
Host smart-59d326c0-c42d-4196-b112-a2c67c8dcec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384484011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3384484011
Directory /workspace/9.clkmgr_trans/latest
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