Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138110018

1

T5

2888

T6

4860

T1

28538

auto[1]

256636

1

T17

98

T20

212

T22

144

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138099804

1

T5

2888

T6

4860

T1

28538

auto[1]

266850

1

T20

222

T21

128

T22

112

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138031492

1

T5

2888

T6

4860

T1

28538

auto[1]

335162

1

T17

68

T20

126

T21

152

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

130496190

1

T5

2888

T6

4860

T1

28538

auto[1]

7870464

1

T17

1654

T20

146

T21

2468

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87969294

1

T5

2384

T6

3826

T1

28494

auto[1]

50397360

1

T5

504

T6

1034

T1

44

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

80053958

1

T5

2384

T6

3826

T1

28494

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

50188582

1

T5

504

T6

1034

T1

44

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20110

1

T20

6

T2

110

T25

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4974

1

T2

32

T123

166

T183

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

7510404

1

T17

1546

T20

80

T21

2358

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

137470

1

T2

1822

T27

184

T31

2206

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29962

1

T17

40

T20

2

T22

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7214

1

T2

58

T27

60

T183

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

43660

1

T20

2

T27

30

T123

60

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

888

1

T123

20

T44

22

T184

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7476

1

T20

46

T27

176

T185

106

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1572

1

T123

88

T44

80

T184

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

6702

1

T20

2

T2

44

T123

10

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1566

1

T2

48

T157

24

T186

22

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

13078

1

T20

62

T2

232

T123

72

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3876

1

T2

172

T157

82

T186

40

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50780

1

T20

16

T22

24

T2

44

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3376

1

T2

22

T27

20

T31

32

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21940

1

T2

164

T27

94

T123

58

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5218

1

T2

158

T27

72

T123

66

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18892

1

T17

10

T21

24

T22

8

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4018

1

T9

18

T183

2

T186

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35064

1

T17

58

T22

74

T2

226

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7842

1

T9

86

T183

46

T13

36

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53106

1

T20

12

T21

42

T2

30

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4080

1

T20

2

T35

8

T123

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

30094

1

T20

44

T2

156

T25

56

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6376

1

T20

52

T35

52

T123

142

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

24626

1

T21

86

T22

46

T2

254

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7910

1

T2

52

T27

12

T31

46

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

49442

1

T22

66

T2

270

T25

52

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

12398

1

T2

242

T27

52

T82

56