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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 975
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T802 /workspace/coverage/default/0.clkmgr_alert_test.3236943337 Jul 31 05:54:53 PM PDT 24 Jul 31 05:54:54 PM PDT 24 16843367 ps
T803 /workspace/coverage/default/34.clkmgr_frequency.567423754 Jul 31 06:05:44 PM PDT 24 Jul 31 06:05:53 PM PDT 24 2051147359 ps
T804 /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1114629485 Jul 31 05:55:59 PM PDT 24 Jul 31 05:56:00 PM PDT 24 68887100 ps
T805 /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2749161010 Jul 31 06:05:56 PM PDT 24 Jul 31 06:05:57 PM PDT 24 20308853 ps
T806 /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.4072948592 Jul 31 06:02:47 PM PDT 24 Jul 31 06:02:48 PM PDT 24 20684081 ps
T807 /workspace/coverage/default/16.clkmgr_extclk.1504847362 Jul 31 06:00:52 PM PDT 24 Jul 31 06:00:53 PM PDT 24 23306731 ps
T808 /workspace/coverage/default/6.clkmgr_frequency.316309473 Jul 31 05:57:02 PM PDT 24 Jul 31 05:57:10 PM PDT 24 2204655939 ps
T809 /workspace/coverage/default/45.clkmgr_alert_test.4130765002 Jul 31 06:07:14 PM PDT 24 Jul 31 06:07:15 PM PDT 24 17170721 ps
T810 /workspace/coverage/default/28.clkmgr_clk_status.3410515011 Jul 31 06:04:42 PM PDT 24 Jul 31 06:04:43 PM PDT 24 81389598 ps
T811 /workspace/coverage/default/11.clkmgr_frequency_timeout.1016770478 Jul 31 05:58:44 PM PDT 24 Jul 31 05:58:47 PM PDT 24 269364676 ps
T812 /workspace/coverage/default/20.clkmgr_div_intersig_mubi.504726985 Jul 31 06:02:12 PM PDT 24 Jul 31 06:02:13 PM PDT 24 44354284 ps
T813 /workspace/coverage/default/8.clkmgr_frequency.3094141912 Jul 31 05:57:42 PM PDT 24 Jul 31 05:57:58 PM PDT 24 2001516733 ps
T814 /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4174169289 Jul 31 06:01:14 PM PDT 24 Jul 31 06:01:16 PM PDT 24 74367769 ps
T815 /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3559282460 Jul 31 06:01:44 PM PDT 24 Jul 31 06:01:45 PM PDT 24 34908064 ps
T816 /workspace/coverage/default/32.clkmgr_div_intersig_mubi.285562245 Jul 31 06:05:28 PM PDT 24 Jul 31 06:05:29 PM PDT 24 15543775 ps
T817 /workspace/coverage/default/33.clkmgr_div_intersig_mubi.1157175995 Jul 31 06:05:39 PM PDT 24 Jul 31 06:05:40 PM PDT 24 16525339 ps
T818 /workspace/coverage/default/20.clkmgr_trans.4266625897 Jul 31 06:02:04 PM PDT 24 Jul 31 06:02:05 PM PDT 24 220362091 ps
T819 /workspace/coverage/default/26.clkmgr_stress_all.1365593561 Jul 31 06:04:24 PM PDT 24 Jul 31 06:04:52 PM PDT 24 7778527261 ps
T820 /workspace/coverage/default/38.clkmgr_stress_all.886861406 Jul 31 06:06:20 PM PDT 24 Jul 31 06:06:31 PM PDT 24 1306381576 ps
T821 /workspace/coverage/default/17.clkmgr_regwen.2724023488 Jul 31 06:01:23 PM PDT 24 Jul 31 06:01:26 PM PDT 24 620809642 ps
T83 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1358269101 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:05 PM PDT 24 13392942 ps
T110 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3563617340 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:51 PM PDT 24 63464700 ps
T84 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3243414892 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 66478711 ps
T58 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3651643119 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:54 PM PDT 24 99284074 ps
T85 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3766891159 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:51 PM PDT 24 121136118 ps
T822 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3058085843 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 123021539 ps
T59 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1513232611 Jul 31 07:30:16 PM PDT 24 Jul 31 07:30:18 PM PDT 24 137139876 ps
T823 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1764411943 Jul 31 07:29:35 PM PDT 24 Jul 31 07:29:36 PM PDT 24 48550655 ps
T60 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3385509492 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:15 PM PDT 24 62012704 ps
T171 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2668270888 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 58184974 ps
T62 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1906499373 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:06 PM PDT 24 62383362 ps
T65 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2480828597 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:16 PM PDT 24 115800098 ps
T86 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2983622058 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:15 PM PDT 24 27275292 ps
T87 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.392087925 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 99115312 ps
T111 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3808899706 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 147073620 ps
T88 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1224176886 Jul 31 07:29:52 PM PDT 24 Jul 31 07:29:53 PM PDT 24 16979969 ps
T824 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1989481296 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 24328300 ps
T89 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3391048051 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 38902890 ps
T825 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.793227982 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:24 PM PDT 24 37963554 ps
T61 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.256675152 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:49 PM PDT 24 70349738 ps
T826 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3242935297 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:59 PM PDT 24 219366957 ps
T827 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3058718679 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:05 PM PDT 24 55159565 ps
T828 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.824665014 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 13287374 ps
T829 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.952508967 Jul 31 07:30:03 PM PDT 24 Jul 31 07:30:03 PM PDT 24 37225169 ps
T830 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2145323226 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:23 PM PDT 24 17101473 ps
T90 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3687744259 Jul 31 07:29:59 PM PDT 24 Jul 31 07:30:00 PM PDT 24 43206079 ps
T112 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.502910603 Jul 31 07:30:18 PM PDT 24 Jul 31 07:30:20 PM PDT 24 240891254 ps
T831 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.358606018 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 30075287 ps
T116 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1979868107 Jul 31 07:29:57 PM PDT 24 Jul 31 07:30:02 PM PDT 24 932579962 ps
T63 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.333890003 Jul 31 07:29:59 PM PDT 24 Jul 31 07:30:02 PM PDT 24 158082446 ps
T832 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.4214154798 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:05 PM PDT 24 15148306 ps
T833 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3502168429 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:25 PM PDT 24 30261908 ps
T66 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3572188510 Jul 31 07:29:55 PM PDT 24 Jul 31 07:29:57 PM PDT 24 51865921 ps
T64 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1271558662 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:45 PM PDT 24 184625889 ps
T834 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3444213180 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:52 PM PDT 24 50859249 ps
T67 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.359357343 Jul 31 07:29:43 PM PDT 24 Jul 31 07:29:44 PM PDT 24 178207301 ps
T835 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3362477864 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:24 PM PDT 24 19148214 ps
T836 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2841094851 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 28501484 ps
T837 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2714179185 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:42 PM PDT 24 137828460 ps
T838 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3421741690 Jul 31 07:29:36 PM PDT 24 Jul 31 07:29:43 PM PDT 24 789809000 ps
T181 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3810464636 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:44 PM PDT 24 66582456 ps
T839 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1236885168 Jul 31 07:29:34 PM PDT 24 Jul 31 07:29:35 PM PDT 24 37488728 ps
T840 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1335435878 Jul 31 07:30:09 PM PDT 24 Jul 31 07:30:11 PM PDT 24 147998016 ps
T841 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3818969117 Jul 31 07:30:20 PM PDT 24 Jul 31 07:30:21 PM PDT 24 71767529 ps
T842 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3686861949 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:54 PM PDT 24 1773835049 ps
T182 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2588313846 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:44 PM PDT 24 194458447 ps
T843 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1449684587 Jul 31 07:30:20 PM PDT 24 Jul 31 07:30:21 PM PDT 24 11671236 ps
T844 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3599384859 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:15 PM PDT 24 12135885 ps
T132 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2083534176 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:17 PM PDT 24 109396390 ps
T845 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.4110835217 Jul 31 07:29:40 PM PDT 24 Jul 31 07:29:41 PM PDT 24 11816791 ps
T846 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2866546946 Jul 31 07:29:57 PM PDT 24 Jul 31 07:30:01 PM PDT 24 384738794 ps
T847 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1908443718 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:52 PM PDT 24 11827330 ps
T848 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1868390175 Jul 31 07:30:10 PM PDT 24 Jul 31 07:30:11 PM PDT 24 37256793 ps
T849 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1327565856 Jul 31 07:30:20 PM PDT 24 Jul 31 07:30:21 PM PDT 24 16755817 ps
T850 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.844743972 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:51 PM PDT 24 17508177 ps
T851 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.245443405 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:50 PM PDT 24 33234855 ps
T852 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.4294696827 Jul 31 07:29:44 PM PDT 24 Jul 31 07:29:44 PM PDT 24 21604266 ps
T853 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3993319372 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 66561303 ps
T854 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1788591879 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:23 PM PDT 24 101057378 ps
T855 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1911087488 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 14896663 ps
T856 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3815812855 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:58 PM PDT 24 31266617 ps
T139 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3443122878 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:54 PM PDT 24 130086580 ps
T117 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.3963861193 Jul 31 07:30:09 PM PDT 24 Jul 31 07:30:12 PM PDT 24 146244771 ps
T857 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4236653443 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:57 PM PDT 24 24271551 ps
T858 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2299455307 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:16 PM PDT 24 55137296 ps
T859 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4119929013 Jul 31 07:29:58 PM PDT 24 Jul 31 07:29:59 PM PDT 24 95813895 ps
T860 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1118449463 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:25 PM PDT 24 12387867 ps
T861 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3457866802 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 17653863 ps
T862 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1405384871 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:17 PM PDT 24 100277354 ps
T863 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3766995897 Jul 31 07:29:54 PM PDT 24 Jul 31 07:29:55 PM PDT 24 25273528 ps
T864 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4089442055 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 32586331 ps
T865 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3716951597 Jul 31 07:29:45 PM PDT 24 Jul 31 07:29:47 PM PDT 24 160716071 ps
T866 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.678435174 Jul 31 07:29:43 PM PDT 24 Jul 31 07:29:44 PM PDT 24 24495533 ps
T140 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1183709974 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:18 PM PDT 24 601211827 ps
T141 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4059589122 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:16 PM PDT 24 81621492 ps
T867 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3820843812 Jul 31 07:29:43 PM PDT 24 Jul 31 07:29:44 PM PDT 24 83261766 ps
T133 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3683075748 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:54 PM PDT 24 239411932 ps
T868 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3335161118 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:45 PM PDT 24 144814698 ps
T869 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1702130433 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:06 PM PDT 24 92371733 ps
T870 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1090803833 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:23 PM PDT 24 19849479 ps
T871 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.538418325 Jul 31 07:29:35 PM PDT 24 Jul 31 07:29:36 PM PDT 24 22603093 ps
T134 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2149696828 Jul 31 07:29:58 PM PDT 24 Jul 31 07:30:00 PM PDT 24 227871166 ps
T872 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.85826926 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:49 PM PDT 24 22255491 ps
T873 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2981172277 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 36646333 ps
T135 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.717000379 Jul 31 07:29:57 PM PDT 24 Jul 31 07:30:00 PM PDT 24 102189270 ps
T115 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.4176890422 Jul 31 07:29:34 PM PDT 24 Jul 31 07:29:37 PM PDT 24 99361601 ps
T874 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1823175533 Jul 31 07:29:43 PM PDT 24 Jul 31 07:29:45 PM PDT 24 46724784 ps
T875 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3812357616 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 90472811 ps
T876 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1838918113 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:51 PM PDT 24 409329760 ps
T877 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3868888019 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:43 PM PDT 24 38943268 ps
T878 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2487879009 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:50 PM PDT 24 27148639 ps
T879 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.267460190 Jul 31 07:29:53 PM PDT 24 Jul 31 07:29:54 PM PDT 24 34101920 ps
T880 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1086785603 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:14 PM PDT 24 14406771 ps
T136 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4160173797 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:43 PM PDT 24 76347416 ps
T881 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3663393312 Jul 31 07:30:26 PM PDT 24 Jul 31 07:30:27 PM PDT 24 12167892 ps
T882 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1744357580 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 11734161 ps
T883 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1836864014 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 85594453 ps
T884 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.844108754 Jul 31 07:30:10 PM PDT 24 Jul 31 07:30:12 PM PDT 24 72992766 ps
T885 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3282687819 Jul 31 07:29:43 PM PDT 24 Jul 31 07:29:44 PM PDT 24 123397771 ps
T886 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.547951241 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:06 PM PDT 24 104858777 ps
T887 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3809937188 Jul 31 07:30:00 PM PDT 24 Jul 31 07:30:01 PM PDT 24 19204580 ps
T888 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.773343198 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 12359299 ps
T889 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.494298699 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 15675313 ps
T137 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.463714868 Jul 31 07:29:33 PM PDT 24 Jul 31 07:29:35 PM PDT 24 254870836 ps
T890 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2685289632 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:45 PM PDT 24 118002283 ps
T891 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3320095824 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:52 PM PDT 24 13327327 ps
T892 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.4204589569 Jul 31 07:29:39 PM PDT 24 Jul 31 07:29:41 PM PDT 24 63867298 ps
T893 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2332105487 Jul 31 07:30:16 PM PDT 24 Jul 31 07:30:19 PM PDT 24 76289827 ps
T138 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.688126869 Jul 31 07:30:06 PM PDT 24 Jul 31 07:30:09 PM PDT 24 207254512 ps
T894 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1004911999 Jul 31 07:30:10 PM PDT 24 Jul 31 07:30:11 PM PDT 24 50894898 ps
T895 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4224986789 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:58 PM PDT 24 24008043 ps
T896 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4022252674 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:15 PM PDT 24 66177924 ps
T897 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3057529197 Jul 31 07:29:40 PM PDT 24 Jul 31 07:29:44 PM PDT 24 410295492 ps
T142 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.983662686 Jul 31 07:29:47 PM PDT 24 Jul 31 07:29:50 PM PDT 24 278205655 ps
T898 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1768484548 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:52 PM PDT 24 143321422 ps
T120 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1952652658 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:45 PM PDT 24 251765596 ps
T899 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.752673620 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:25 PM PDT 24 14609472 ps
T900 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3085257010 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 32514142 ps
T901 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1138807717 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:06 PM PDT 24 12865135 ps
T902 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2045378045 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:16 PM PDT 24 35658944 ps
T903 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2774102060 Jul 31 07:30:06 PM PDT 24 Jul 31 07:30:06 PM PDT 24 12298740 ps
T904 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3684378804 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:17 PM PDT 24 145593113 ps
T905 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3950308401 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:52 PM PDT 24 128126559 ps
T147 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3515431025 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 111971805 ps
T145 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.4127310405 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:26 PM PDT 24 779990745 ps
T906 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2963324804 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:24 PM PDT 24 28682794 ps
T148 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1236745416 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:42 PM PDT 24 152804713 ps
T907 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3904092087 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:58 PM PDT 24 132908480 ps
T908 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.129370303 Jul 31 07:30:20 PM PDT 24 Jul 31 07:30:21 PM PDT 24 32525338 ps
T909 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.4024925018 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:25 PM PDT 24 12625196 ps
T149 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2145220400 Jul 31 07:30:03 PM PDT 24 Jul 31 07:30:05 PM PDT 24 121314381 ps
T910 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.624238614 Jul 31 07:29:35 PM PDT 24 Jul 31 07:29:37 PM PDT 24 139868761 ps
T911 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2923763490 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:14 PM PDT 24 49822852 ps
T912 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2199267400 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:52 PM PDT 24 474641515 ps
T913 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.806448700 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:15 PM PDT 24 71424104 ps
T119 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2797169214 Jul 31 07:30:09 PM PDT 24 Jul 31 07:30:12 PM PDT 24 408061105 ps
T914 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1391344430 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:43 PM PDT 24 45826385 ps
T915 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1174801454 Jul 31 07:29:58 PM PDT 24 Jul 31 07:29:59 PM PDT 24 24830838 ps
T916 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1036424385 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:17 PM PDT 24 791169209 ps
T917 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2351997312 Jul 31 07:29:44 PM PDT 24 Jul 31 07:29:46 PM PDT 24 57578604 ps
T918 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.816561126 Jul 31 07:30:23 PM PDT 24 Jul 31 07:30:24 PM PDT 24 39838890 ps
T919 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.208078392 Jul 31 07:29:58 PM PDT 24 Jul 31 07:29:59 PM PDT 24 28241209 ps
T920 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.4148867324 Jul 31 07:30:06 PM PDT 24 Jul 31 07:30:08 PM PDT 24 108704382 ps
T921 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2214654152 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:52 PM PDT 24 96586552 ps
T922 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.284858908 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:58 PM PDT 24 31523952 ps
T923 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1750443497 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 34389478 ps
T924 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2086385078 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:49 PM PDT 24 28950930 ps
T925 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.274747817 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:44 PM PDT 24 105859882 ps
T926 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1663386183 Jul 31 07:29:58 PM PDT 24 Jul 31 07:30:00 PM PDT 24 130141452 ps
T927 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3307960120 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:15 PM PDT 24 16290141 ps
T928 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1666246310 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:14 PM PDT 24 13863303 ps
T929 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3191428812 Jul 31 07:29:45 PM PDT 24 Jul 31 07:29:46 PM PDT 24 47439556 ps
T930 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2521562506 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:59 PM PDT 24 91447856 ps
T931 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.325025261 Jul 31 07:30:16 PM PDT 24 Jul 31 07:30:17 PM PDT 24 21897461 ps
T932 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.987972036 Jul 31 07:30:08 PM PDT 24 Jul 31 07:30:09 PM PDT 24 62144380 ps
T933 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1090239119 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:20 PM PDT 24 1359427238 ps
T934 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.108698811 Jul 31 07:29:42 PM PDT 24 Jul 31 07:29:43 PM PDT 24 67771780 ps
T935 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3992193189 Jul 31 07:29:45 PM PDT 24 Jul 31 07:29:46 PM PDT 24 130461802 ps
T936 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3909926522 Jul 31 07:30:25 PM PDT 24 Jul 31 07:30:26 PM PDT 24 32925566 ps
T146 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.520710527 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:58 PM PDT 24 106837399 ps
T937 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.4192871686 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:06 PM PDT 24 23966187 ps
T938 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1039428411 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 13746168 ps
T939 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2454763365 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:58 PM PDT 24 51183005 ps
T143 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1455879947 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:15 PM PDT 24 127194395 ps
T940 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3485606678 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:43 PM PDT 24 169157983 ps
T941 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3919800336 Jul 31 07:29:41 PM PDT 24 Jul 31 07:29:42 PM PDT 24 54936117 ps
T180 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2213292451 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:58 PM PDT 24 227593248 ps
T942 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3620948699 Jul 31 07:30:21 PM PDT 24 Jul 31 07:30:22 PM PDT 24 14679838 ps
T943 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.166044986 Jul 31 07:30:08 PM PDT 24 Jul 31 07:30:11 PM PDT 24 380706177 ps
T118 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.111954453 Jul 31 07:30:17 PM PDT 24 Jul 31 07:30:20 PM PDT 24 140817298 ps
T944 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2281532052 Jul 31 07:30:06 PM PDT 24 Jul 31 07:30:09 PM PDT 24 120531633 ps
T945 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3175475467 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 75859629 ps
T121 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3227848321 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:24 PM PDT 24 59154969 ps
T946 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.23993974 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:06 PM PDT 24 247267474 ps
T947 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1431871530 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:54 PM PDT 24 200982251 ps
T948 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3405222922 Jul 31 07:30:13 PM PDT 24 Jul 31 07:30:15 PM PDT 24 253860451 ps
T949 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.445671000 Jul 31 07:29:55 PM PDT 24 Jul 31 07:29:56 PM PDT 24 28268676 ps
T144 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.375727568 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:07 PM PDT 24 131718193 ps
T950 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2435474170 Jul 31 07:29:57 PM PDT 24 Jul 31 07:29:58 PM PDT 24 57392387 ps
T951 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2912810698 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:53 PM PDT 24 113824138 ps
T952 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.19295726 Jul 31 07:30:20 PM PDT 24 Jul 31 07:30:21 PM PDT 24 15485459 ps
T953 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2645248262 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:08 PM PDT 24 270909132 ps
T954 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.790777490 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:06 PM PDT 24 91502778 ps
T955 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.323523497 Jul 31 07:29:50 PM PDT 24 Jul 31 07:29:50 PM PDT 24 20859628 ps
T956 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1979326485 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:53 PM PDT 24 162276087 ps
T957 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.330928904 Jul 31 07:30:22 PM PDT 24 Jul 31 07:30:23 PM PDT 24 11229243 ps
T958 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.947555623 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:51 PM PDT 24 215924365 ps
T959 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3763482250 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:50 PM PDT 24 98765164 ps
T960 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1368295031 Jul 31 07:29:35 PM PDT 24 Jul 31 07:29:36 PM PDT 24 16067986 ps
T113 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.115308399 Jul 31 07:30:05 PM PDT 24 Jul 31 07:30:07 PM PDT 24 146335898 ps
T961 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.83471812 Jul 31 07:30:04 PM PDT 24 Jul 31 07:30:07 PM PDT 24 272377711 ps
T962 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1312403945 Jul 31 07:29:54 PM PDT 24 Jul 31 07:29:56 PM PDT 24 120390422 ps
T963 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2988003032 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:19 PM PDT 24 178500265 ps
T964 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.4274286551 Jul 31 07:30:09 PM PDT 24 Jul 31 07:30:11 PM PDT 24 124544690 ps
T965 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.979627466 Jul 31 07:30:24 PM PDT 24 Jul 31 07:30:25 PM PDT 24 23459224 ps
T966 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2616420382 Jul 31 07:29:49 PM PDT 24 Jul 31 07:29:54 PM PDT 24 274508996 ps
T967 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.2412077639 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:59 PM PDT 24 39193699 ps
T968 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.684512474 Jul 31 07:29:56 PM PDT 24 Jul 31 07:29:57 PM PDT 24 16742022 ps
T969 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1553364944 Jul 31 07:30:06 PM PDT 24 Jul 31 07:30:10 PM PDT 24 331244497 ps
T970 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2215610456 Jul 31 07:30:14 PM PDT 24 Jul 31 07:30:17 PM PDT 24 63759743 ps
T971 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1592909838 Jul 31 07:29:51 PM PDT 24 Jul 31 07:29:52 PM PDT 24 52991272 ps
T972 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3900924284 Jul 31 07:30:09 PM PDT 24 Jul 31 07:30:10 PM PDT 24 17491814 ps
T973 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3336878060 Jul 31 07:29:48 PM PDT 24 Jul 31 07:29:56 PM PDT 24 428299372 ps
T974 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.883119274 Jul 31 07:30:15 PM PDT 24 Jul 31 07:30:18 PM PDT 24 358187264 ps
T975 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1097839076 Jul 31 07:29:55 PM PDT 24 Jul 31 07:29:56 PM PDT 24 62085658 ps

Test location /workspace/coverage/default/23.clkmgr_frequency.2412318500
Short name T1
Test name
Test status
Simulation time 1428988200 ps
CPU time 5.6 seconds
Started Jul 31 06:02:56 PM PDT 24
Finished Jul 31 06:03:02 PM PDT 24
Peak memory 201136 kb
Host smart-bcc7f040-7242-4392-bc48-c16a5ea6c288
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412318500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2412318500
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1644807723
Short name T2
Test name
Test status
Simulation time 8281171630 ps
CPU time 46.11 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:08:04 PM PDT 24
Peak memory 201472 kb
Host smart-a2bc712e-9c3f-4e6f-accd-28193bb604b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644807723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1644807723
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.3225823074
Short name T8
Test name
Test status
Simulation time 3189597858 ps
CPU time 24.55 seconds
Started Jul 31 05:59:26 PM PDT 24
Finished Jul 31 05:59:51 PM PDT 24
Peak memory 201400 kb
Host smart-c50720cf-6b70-4f17-98b1-04047c855e2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225823074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.3225823074
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.2522262076
Short name T12
Test name
Test status
Simulation time 24940612067 ps
CPU time 437.7 seconds
Started Jul 31 06:03:41 PM PDT 24
Finished Jul 31 06:10:59 PM PDT 24
Peak memory 209724 kb
Host smart-4c239e22-a212-43e4-97d7-a23cbf58ae19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2522262076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2522262076
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3651643119
Short name T58
Test name
Test status
Simulation time 99284074 ps
CPU time 2.03 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 200848 kb
Host smart-6fe64f8c-61a7-4cb0-8e65-67b2e9965767
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651643119 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3651643119
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3425770507
Short name T19
Test name
Test status
Simulation time 35149671 ps
CPU time 0.76 seconds
Started Jul 31 05:58:42 PM PDT 24
Finished Jul 31 05:58:43 PM PDT 24
Peak memory 201064 kb
Host smart-a59ef250-89db-46fc-8152-63282ac5f2cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425770507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3425770507
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.2912530725
Short name T36
Test name
Test status
Simulation time 1104177721 ps
CPU time 6.53 seconds
Started Jul 31 06:00:46 PM PDT 24
Finished Jul 31 06:00:52 PM PDT 24
Peak memory 201244 kb
Host smart-495c1835-bb27-45ea-a934-773d5bd45550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912530725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2912530725
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.865995478
Short name T45
Test name
Test status
Simulation time 748013615 ps
CPU time 4.5 seconds
Started Jul 31 05:56:29 PM PDT 24
Finished Jul 31 05:56:33 PM PDT 24
Peak memory 217764 kb
Host smart-905eb448-f7b9-4bb2-b218-609c5cb9dbb7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865995478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_sec_cm.865995478
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.4287161399
Short name T126
Test name
Test status
Simulation time 40620173 ps
CPU time 1.14 seconds
Started Jul 31 05:59:46 PM PDT 24
Finished Jul 31 05:59:47 PM PDT 24
Peak memory 201036 kb
Host smart-578c1203-576b-477f-85f6-377c0962db2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287161399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.4287161399
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.463714868
Short name T137
Test name
Test status
Simulation time 254870836 ps
CPU time 2.12 seconds
Started Jul 31 07:29:33 PM PDT 24
Finished Jul 31 07:29:35 PM PDT 24
Peak memory 200864 kb
Host smart-fb9cade7-8053-41a8-aeae-d99a5aad2d9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463714868 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.463714868
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1979868107
Short name T116
Test name
Test status
Simulation time 932579962 ps
CPU time 4.7 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:30:02 PM PDT 24
Peak memory 200604 kb
Host smart-d391c363-c359-4c3f-9a40-6c993bdb7d70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979868107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.1979868107
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2187863085
Short name T123
Test name
Test status
Simulation time 31006422 ps
CPU time 0.98 seconds
Started Jul 31 06:05:29 PM PDT 24
Finished Jul 31 06:05:30 PM PDT 24
Peak memory 201112 kb
Host smart-98a303fb-7062-4def-ba8c-77c249ed8030
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187863085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.2187863085
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.532485898
Short name T98
Test name
Test status
Simulation time 35941065 ps
CPU time 0.74 seconds
Started Jul 31 05:55:09 PM PDT 24
Finished Jul 31 05:55:09 PM PDT 24
Peak memory 200964 kb
Host smart-3affbcff-76c4-4986-9a50-9cb502284aa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532485898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.532485898
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1906499373
Short name T62
Test name
Test status
Simulation time 62383362 ps
CPU time 1.7 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 217132 kb
Host smart-141ab630-457e-46b3-a4ee-0d8eebdd9141
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906499373 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.1906499373
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.398920909
Short name T189
Test name
Test status
Simulation time 12553009 ps
CPU time 0.73 seconds
Started Jul 31 05:58:42 PM PDT 24
Finished Jul 31 05:58:43 PM PDT 24
Peak memory 201048 kb
Host smart-d8f2ca6e-6d7c-49dd-94bf-1b85e036037d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398920909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkm
gr_alert_test.398920909
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.286863016
Short name T130
Test name
Test status
Simulation time 5284777580 ps
CPU time 28.24 seconds
Started Jul 31 06:03:23 PM PDT 24
Finished Jul 31 06:03:51 PM PDT 24
Peak memory 201392 kb
Host smart-249a6772-88ff-40b0-9fae-c9f628d66ffe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286863016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.286863016
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3250075947
Short name T73
Test name
Test status
Simulation time 108052291501 ps
CPU time 1032.13 seconds
Started Jul 31 05:56:49 PM PDT 24
Finished Jul 31 06:14:02 PM PDT 24
Peak memory 209700 kb
Host smart-4d12f795-8f02-4339-bbad-b1d41816a938
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3250075947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3250075947
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.1383058112
Short name T7
Test name
Test status
Simulation time 559833273 ps
CPU time 3.65 seconds
Started Jul 31 06:07:14 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201272 kb
Host smart-e0efde73-f5d9-44c9-8f1e-34a4374f1baa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383058112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1383058112
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3249991994
Short name T41
Test name
Test status
Simulation time 144110912035 ps
CPU time 976.64 seconds
Started Jul 31 06:06:51 PM PDT 24
Finished Jul 31 06:23:08 PM PDT 24
Peak memory 209740 kb
Host smart-1089b20a-315e-46a0-908f-bbb7d4003bb0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3249991994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3249991994
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.520710527
Short name T146
Test name
Test status
Simulation time 106837399 ps
CPU time 1.98 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200828 kb
Host smart-01b7d55e-919b-48e8-9d08-4867855e98b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520710527 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.clkmgr_shadow_reg_errors.520710527
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.355045257
Short name T107
Test name
Test status
Simulation time 64480565 ps
CPU time 1.09 seconds
Started Jul 31 05:59:17 PM PDT 24
Finished Jul 31 05:59:18 PM PDT 24
Peak memory 200980 kb
Host smart-68c21a7a-1dfc-4018-87c2-6c6e107330f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355045257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.355045257
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.502910603
Short name T112
Test name
Test status
Simulation time 240891254 ps
CPU time 2.53 seconds
Started Jul 31 07:30:18 PM PDT 24
Finished Jul 31 07:30:20 PM PDT 24
Peak memory 200508 kb
Host smart-2c63519d-ef09-4df2-a33b-92a0ffdfaa0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502910603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.502910603
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3227848321
Short name T121
Test name
Test status
Simulation time 59154969 ps
CPU time 1.56 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 200552 kb
Host smart-ee1c32c6-a01d-4cc0-a2c3-6da0dc9d372b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227848321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.3227848321
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.3191428812
Short name T929
Test name
Test status
Simulation time 47439556 ps
CPU time 1.26 seconds
Started Jul 31 07:29:45 PM PDT 24
Finished Jul 31 07:29:46 PM PDT 24
Peak memory 200380 kb
Host smart-cccdee49-e36a-45c0-9e7a-a8a853f382b9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191428812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.3191428812
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3421741690
Short name T838
Test name
Test status
Simulation time 789809000 ps
CPU time 7.22 seconds
Started Jul 31 07:29:36 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 200528 kb
Host smart-5e0cb5e4-c9e8-4850-b902-d4fdbeeecbe9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421741690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.3421741690
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1764411943
Short name T823
Test name
Test status
Simulation time 48550655 ps
CPU time 0.91 seconds
Started Jul 31 07:29:35 PM PDT 24
Finished Jul 31 07:29:36 PM PDT 24
Peak memory 200364 kb
Host smart-db9479b0-89e8-4315-b14d-d96081a48163
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764411943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1764411943
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2351997312
Short name T917
Test name
Test status
Simulation time 57578604 ps
CPU time 1.8 seconds
Started Jul 31 07:29:44 PM PDT 24
Finished Jul 31 07:29:46 PM PDT 24
Peak memory 200600 kb
Host smart-8a8b290e-cdb4-4e32-ba3b-436b3d411fd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351997312 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2351997312
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1368295031
Short name T960
Test name
Test status
Simulation time 16067986 ps
CPU time 0.8 seconds
Started Jul 31 07:29:35 PM PDT 24
Finished Jul 31 07:29:36 PM PDT 24
Peak memory 200356 kb
Host smart-950bd1b1-a320-4294-85b5-779c3e76f1c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368295031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.1368295031
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.538418325
Short name T871
Test name
Test status
Simulation time 22603093 ps
CPU time 0.67 seconds
Started Jul 31 07:29:35 PM PDT 24
Finished Jul 31 07:29:36 PM PDT 24
Peak memory 198924 kb
Host smart-4b6932e6-1fad-4b7b-ad4c-7ae49c0c3b16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538418325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm
gr_intr_test.538418325
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3716951597
Short name T865
Test name
Test status
Simulation time 160716071 ps
CPU time 1.67 seconds
Started Jul 31 07:29:45 PM PDT 24
Finished Jul 31 07:29:47 PM PDT 24
Peak memory 200536 kb
Host smart-cadf8b3c-b910-4614-8a1c-fd9412de83e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716951597 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.3716951597
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.624238614
Short name T910
Test name
Test status
Simulation time 139868761 ps
CPU time 1.99 seconds
Started Jul 31 07:29:35 PM PDT 24
Finished Jul 31 07:29:37 PM PDT 24
Peak memory 209016 kb
Host smart-5af35d58-1c22-4373-ae70-58c6c438d080
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624238614 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.624238614
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1236885168
Short name T839
Test name
Test status
Simulation time 37488728 ps
CPU time 1.59 seconds
Started Jul 31 07:29:34 PM PDT 24
Finished Jul 31 07:29:35 PM PDT 24
Peak memory 200576 kb
Host smart-139fe514-1627-4989-a204-ebb66dcd234e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236885168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1236885168
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.4176890422
Short name T115
Test name
Test status
Simulation time 99361601 ps
CPU time 2.39 seconds
Started Jul 31 07:29:34 PM PDT 24
Finished Jul 31 07:29:37 PM PDT 24
Peak memory 200592 kb
Host smart-67456e84-7ed8-46ba-9ff2-8e91481cb594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176890422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.4176890422
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3868888019
Short name T877
Test name
Test status
Simulation time 38943268 ps
CPU time 1.28 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 200428 kb
Host smart-a57419df-8d1e-4a98-953e-bda1e153a1d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868888019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.3868888019
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3335161118
Short name T868
Test name
Test status
Simulation time 144814698 ps
CPU time 3.48 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:45 PM PDT 24
Peak memory 200520 kb
Host smart-7e5aa2ea-c3a1-4f62-81e8-f9eb4a9d2e74
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335161118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3335161118
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.678435174
Short name T866
Test name
Test status
Simulation time 24495533 ps
CPU time 0.77 seconds
Started Jul 31 07:29:43 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200344 kb
Host smart-80f593a1-4d24-4094-97c8-f1d74a06b3c0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678435174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_hw_reset.678435174
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3919800336
Short name T941
Test name
Test status
Simulation time 54936117 ps
CPU time 1.16 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:42 PM PDT 24
Peak memory 200460 kb
Host smart-74fbd91d-8d42-49a1-9a13-1c43eda1fae7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919800336 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3919800336
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2714179185
Short name T837
Test name
Test status
Simulation time 137828460 ps
CPU time 1.14 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:42 PM PDT 24
Peak memory 200476 kb
Host smart-97caa457-bbe8-4b3e-9437-cedf9c6b2f4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714179185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2714179185
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.4110835217
Short name T845
Test name
Test status
Simulation time 11816791 ps
CPU time 0.64 seconds
Started Jul 31 07:29:40 PM PDT 24
Finished Jul 31 07:29:41 PM PDT 24
Peak memory 198932 kb
Host smart-2e8e87a9-52be-485d-91e8-d6ef9cf63176
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110835217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.4110835217
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3820843812
Short name T867
Test name
Test status
Simulation time 83261766 ps
CPU time 1.07 seconds
Started Jul 31 07:29:43 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200276 kb
Host smart-3a250fec-96ee-432b-bb2c-0946083af49d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820843812 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.3820843812
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1236745416
Short name T148
Test name
Test status
Simulation time 152804713 ps
CPU time 1.44 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:42 PM PDT 24
Peak memory 200648 kb
Host smart-dfa0348a-4359-49db-9a31-910c5497667a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236745416 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.1236745416
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3485606678
Short name T940
Test name
Test status
Simulation time 169157983 ps
CPU time 2.13 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 200820 kb
Host smart-dfcac9a7-5586-4f4e-a58e-a43b995ebb37
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485606678 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.3485606678
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1823175533
Short name T874
Test name
Test status
Simulation time 46724784 ps
CPU time 2.74 seconds
Started Jul 31 07:29:43 PM PDT 24
Finished Jul 31 07:29:45 PM PDT 24
Peak memory 200548 kb
Host smart-763f025c-87df-4c0d-9cb4-0e7a1b4dc9db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823175533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.1823175533
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.2588313846
Short name T182
Test name
Test status
Simulation time 194458447 ps
CPU time 1.75 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200552 kb
Host smart-b7025519-6507-4f81-95f9-b94072958e85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588313846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.2588313846
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.987972036
Short name T932
Test name
Test status
Simulation time 62144380 ps
CPU time 1 seconds
Started Jul 31 07:30:08 PM PDT 24
Finished Jul 31 07:30:09 PM PDT 24
Peak memory 200360 kb
Host smart-75256685-e4c2-4927-a2fc-76b8554c0ade
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987972036 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.987972036
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.284858908
Short name T922
Test name
Test status
Simulation time 31523952 ps
CPU time 0.89 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200448 kb
Host smart-b675cd8e-7f07-41c6-a31a-94612530c631
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284858908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
clkmgr_csr_rw.284858908
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.684512474
Short name T968
Test name
Test status
Simulation time 16742022 ps
CPU time 0.7 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:57 PM PDT 24
Peak memory 198980 kb
Host smart-8f6690d9-260d-4bac-9fcb-3347edf915dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684512474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_intr_test.684512474
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2454763365
Short name T939
Test name
Test status
Simulation time 51183005 ps
CPU time 1.34 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200520 kb
Host smart-eda25b92-f300-4175-8e06-7b20cd418291
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454763365 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.2454763365
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3572188510
Short name T66
Test name
Test status
Simulation time 51865921 ps
CPU time 1.5 seconds
Started Jul 31 07:29:55 PM PDT 24
Finished Jul 31 07:29:57 PM PDT 24
Peak memory 200836 kb
Host smart-3cf4c5d3-1b28-4cf9-92f8-a090920c95dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572188510 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3572188510
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.2521562506
Short name T930
Test name
Test status
Simulation time 91447856 ps
CPU time 2.42 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200556 kb
Host smart-318e411e-e9a3-4437-a28a-57e2ba558383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521562506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.2521562506
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2866546946
Short name T846
Test name
Test status
Simulation time 384738794 ps
CPU time 3.2 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:30:01 PM PDT 24
Peak memory 200656 kb
Host smart-855b46aa-b83f-4e26-bcb6-bf0f3e168f2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866546946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.2866546946
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.4192871686
Short name T937
Test name
Test status
Simulation time 23966187 ps
CPU time 0.94 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 200436 kb
Host smart-1d08ef8c-1453-413f-a49c-13062be6e733
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192871686 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.4192871686
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1358269101
Short name T83
Test name
Test status
Simulation time 13392942 ps
CPU time 0.79 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:05 PM PDT 24
Peak memory 200284 kb
Host smart-34e9def2-8f24-4679-bf85-17f8e303dd3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358269101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.1358269101
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1138807717
Short name T901
Test name
Test status
Simulation time 12865135 ps
CPU time 0.7 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 198996 kb
Host smart-b0370f2a-6650-4cb3-a1a0-33e7bfe7e157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138807717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1138807717
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.1335435878
Short name T840
Test name
Test status
Simulation time 147998016 ps
CPU time 1.61 seconds
Started Jul 31 07:30:09 PM PDT 24
Finished Jul 31 07:30:11 PM PDT 24
Peak memory 200476 kb
Host smart-269e0797-b894-49ca-92cb-0eef22c0c9a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335435878 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.1335435878
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2281532052
Short name T944
Test name
Test status
Simulation time 120531633 ps
CPU time 2.14 seconds
Started Jul 31 07:30:06 PM PDT 24
Finished Jul 31 07:30:09 PM PDT 24
Peak memory 200812 kb
Host smart-ed6e6b67-ba76-48e9-9213-dc654c19f834
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281532052 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2281532052
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.2645248262
Short name T953
Test name
Test status
Simulation time 270909132 ps
CPU time 2.9 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:08 PM PDT 24
Peak memory 200600 kb
Host smart-280382b1-b865-4db3-a873-7c0bce264d2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645248262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.2645248262
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.2797169214
Short name T119
Test name
Test status
Simulation time 408061105 ps
CPU time 3.27 seconds
Started Jul 31 07:30:09 PM PDT 24
Finished Jul 31 07:30:12 PM PDT 24
Peak memory 199920 kb
Host smart-d4b152a5-f545-4b98-9728-73fff2c03fd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797169214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.2797169214
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.166044986
Short name T943
Test name
Test status
Simulation time 380706177 ps
CPU time 2.52 seconds
Started Jul 31 07:30:08 PM PDT 24
Finished Jul 31 07:30:11 PM PDT 24
Peak memory 200608 kb
Host smart-b9a7677b-9540-4ebb-a7b1-88730ad9a2d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166044986 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.166044986
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1004911999
Short name T894
Test name
Test status
Simulation time 50894898 ps
CPU time 0.85 seconds
Started Jul 31 07:30:10 PM PDT 24
Finished Jul 31 07:30:11 PM PDT 24
Peak memory 200332 kb
Host smart-c429b7c9-18ff-4f1c-8428-41ebe3a13560
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004911999 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.1004911999
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.952508967
Short name T829
Test name
Test status
Simulation time 37225169 ps
CPU time 0.72 seconds
Started Jul 31 07:30:03 PM PDT 24
Finished Jul 31 07:30:03 PM PDT 24
Peak memory 198992 kb
Host smart-c9164325-286e-47cd-8e12-a30ba3f7df94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952508967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.952508967
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1868390175
Short name T848
Test name
Test status
Simulation time 37256793 ps
CPU time 1.1 seconds
Started Jul 31 07:30:10 PM PDT 24
Finished Jul 31 07:30:11 PM PDT 24
Peak memory 200388 kb
Host smart-44e370be-231d-48ff-ba0a-2f6a292277c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868390175 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1868390175
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2145220400
Short name T149
Test name
Test status
Simulation time 121314381 ps
CPU time 1.58 seconds
Started Jul 31 07:30:03 PM PDT 24
Finished Jul 31 07:30:05 PM PDT 24
Peak memory 200572 kb
Host smart-9884ed24-1957-43d4-b7a9-094790613095
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145220400 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2145220400
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.1455879947
Short name T143
Test name
Test status
Simulation time 127194395 ps
CPU time 2.03 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200888 kb
Host smart-51a3aa9c-c5cc-4af4-8947-7a9b8e816c1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455879947 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.1455879947
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.4274286551
Short name T964
Test name
Test status
Simulation time 124544690 ps
CPU time 2.05 seconds
Started Jul 31 07:30:09 PM PDT 24
Finished Jul 31 07:30:11 PM PDT 24
Peak memory 200548 kb
Host smart-2bb23a78-ea9f-400a-83c8-73741fe614bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274286551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.4274286551
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.3963861193
Short name T117
Test name
Test status
Simulation time 146244771 ps
CPU time 2.43 seconds
Started Jul 31 07:30:09 PM PDT 24
Finished Jul 31 07:30:12 PM PDT 24
Peak memory 200504 kb
Host smart-137bf634-dd2a-4129-8cf3-ff0770da2f4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963861193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.3963861193
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.4148867324
Short name T920
Test name
Test status
Simulation time 108704382 ps
CPU time 1.37 seconds
Started Jul 31 07:30:06 PM PDT 24
Finished Jul 31 07:30:08 PM PDT 24
Peak memory 200400 kb
Host smart-fae541f7-6939-4554-bb78-04d1554ce4f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148867324 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.4148867324
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.4214154798
Short name T832
Test name
Test status
Simulation time 15148306 ps
CPU time 0.77 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:05 PM PDT 24
Peak memory 200344 kb
Host smart-b6dac68a-7acf-411a-83d7-aae25c5fad20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214154798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.4214154798
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3058718679
Short name T827
Test name
Test status
Simulation time 55159565 ps
CPU time 0.76 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:05 PM PDT 24
Peak memory 199020 kb
Host smart-ece76f43-dad4-426e-93c8-07265ce1d61a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058718679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.3058718679
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.547951241
Short name T886
Test name
Test status
Simulation time 104858777 ps
CPU time 1.6 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 200636 kb
Host smart-34cc4065-24ad-4d17-8476-e63256b9b0d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547951241 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 13.clkmgr_same_csr_outstanding.547951241
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.375727568
Short name T144
Test name
Test status
Simulation time 131718193 ps
CPU time 1.37 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:07 PM PDT 24
Peak memory 200628 kb
Host smart-2fe2b324-f4b7-4869-86d9-357bb53b6b62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375727568 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.clkmgr_shadow_reg_errors.375727568
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.23993974
Short name T946
Test name
Test status
Simulation time 247267474 ps
CPU time 2.15 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 200908 kb
Host smart-585caf58-d6b2-4b14-9c8f-75811ffbd20f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23993974 -assert nopostproc +UVM_TESTNAME=
clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.23993974
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.83471812
Short name T961
Test name
Test status
Simulation time 272377711 ps
CPU time 2.91 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:07 PM PDT 24
Peak memory 200612 kb
Host smart-66e7797c-9a75-47b5-88e9-12ec2e4f0c35
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83471812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkm
gr_tl_errors.83471812
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.115308399
Short name T113
Test name
Test status
Simulation time 146335898 ps
CPU time 1.79 seconds
Started Jul 31 07:30:05 PM PDT 24
Finished Jul 31 07:30:07 PM PDT 24
Peak memory 200656 kb
Host smart-dc3d26d0-f7b6-4edf-a51c-698dc58c32ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115308399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.115308399
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2215610456
Short name T970
Test name
Test status
Simulation time 63759743 ps
CPU time 2.05 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200776 kb
Host smart-55660268-1402-4c05-8757-ed21f7cad5c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215610456 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.2215610456
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3900924284
Short name T972
Test name
Test status
Simulation time 17491814 ps
CPU time 0.85 seconds
Started Jul 31 07:30:09 PM PDT 24
Finished Jul 31 07:30:10 PM PDT 24
Peak memory 199504 kb
Host smart-f0969c8d-902b-42c5-8d5a-12c3899d3e37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900924284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.3900924284
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2774102060
Short name T903
Test name
Test status
Simulation time 12298740 ps
CPU time 0.68 seconds
Started Jul 31 07:30:06 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 198944 kb
Host smart-7064fc3b-dbf4-4401-b247-4c58a18e0438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774102060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2774102060
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1702130433
Short name T869
Test name
Test status
Simulation time 92371733 ps
CPU time 1.39 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 200544 kb
Host smart-f095a50c-45a3-4298-82b1-18e2550d8c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702130433 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1702130433
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.688126869
Short name T138
Test name
Test status
Simulation time 207254512 ps
CPU time 2.32 seconds
Started Jul 31 07:30:06 PM PDT 24
Finished Jul 31 07:30:09 PM PDT 24
Peak memory 200824 kb
Host smart-6a3ebb5f-4ec9-4ffb-8e54-2f95a34454cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688126869 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.clkmgr_shadow_reg_errors.688126869
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.790777490
Short name T954
Test name
Test status
Simulation time 91502778 ps
CPU time 1.73 seconds
Started Jul 31 07:30:04 PM PDT 24
Finished Jul 31 07:30:06 PM PDT 24
Peak memory 208996 kb
Host smart-b4b8b28e-3287-41aa-acb4-81984d73a4bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790777490 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.790777490
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.844108754
Short name T884
Test name
Test status
Simulation time 72992766 ps
CPU time 2.41 seconds
Started Jul 31 07:30:10 PM PDT 24
Finished Jul 31 07:30:12 PM PDT 24
Peak memory 200560 kb
Host smart-890c363c-8462-4b9d-8b67-af442f30993e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844108754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_tl_errors.844108754
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1553364944
Short name T969
Test name
Test status
Simulation time 331244497 ps
CPU time 3.43 seconds
Started Jul 31 07:30:06 PM PDT 24
Finished Jul 31 07:30:10 PM PDT 24
Peak memory 200556 kb
Host smart-8a4a2ff0-9adc-41d5-8109-188fabb997f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553364944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1553364944
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4022252674
Short name T896
Test name
Test status
Simulation time 66177924 ps
CPU time 1.3 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200496 kb
Host smart-9125fa8b-60e3-4d93-953b-57d06ca5b5cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022252674 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.4022252674
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2983622058
Short name T86
Test name
Test status
Simulation time 27275292 ps
CPU time 0.87 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200340 kb
Host smart-f28cc551-f385-4b7a-a811-cf6b2f0a9b46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983622058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.2983622058
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1086785603
Short name T880
Test name
Test status
Simulation time 14406771 ps
CPU time 0.68 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:14 PM PDT 24
Peak memory 199040 kb
Host smart-17921f2a-2c03-4065-aca9-9db9dd8dec20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086785603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.1086785603
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2045378045
Short name T902
Test name
Test status
Simulation time 35658944 ps
CPU time 1.07 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:16 PM PDT 24
Peak memory 200340 kb
Host smart-46578e78-2e6c-4204-8c5a-b9c2f97b04ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045378045 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.2045378045
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.1036424385
Short name T916
Test name
Test status
Simulation time 791169209 ps
CPU time 3.29 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200832 kb
Host smart-fdb4d8b3-331d-45e0-8e23-2f98ccae2654
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036424385 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.1036424385
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.1513232611
Short name T59
Test name
Test status
Simulation time 137139876 ps
CPU time 1.87 seconds
Started Jul 31 07:30:16 PM PDT 24
Finished Jul 31 07:30:18 PM PDT 24
Peak memory 208980 kb
Host smart-d1b89bbd-8de4-4998-8de8-32e5e3628d5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513232611 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.1513232611
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.806448700
Short name T913
Test name
Test status
Simulation time 71424104 ps
CPU time 1.52 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200544 kb
Host smart-28a5aa94-a77a-4c89-abc1-76e08792c031
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806448700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clk
mgr_tl_errors.806448700
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1090239119
Short name T933
Test name
Test status
Simulation time 1359427238 ps
CPU time 5.68 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:20 PM PDT 24
Peak memory 200608 kb
Host smart-9a7d2703-8597-4e31-bc83-3dcd8c33857e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090239119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1090239119
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.325025261
Short name T931
Test name
Test status
Simulation time 21897461 ps
CPU time 0.84 seconds
Started Jul 31 07:30:16 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200360 kb
Host smart-2be6dd65-870b-494c-8d0a-5d62e960abe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325025261 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.325025261
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3307960120
Short name T927
Test name
Test status
Simulation time 16290141 ps
CPU time 0.77 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200248 kb
Host smart-34058770-8c5f-4e5b-b073-43319832b334
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307960120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3307960120
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.1666246310
Short name T928
Test name
Test status
Simulation time 13863303 ps
CPU time 0.68 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:14 PM PDT 24
Peak memory 198952 kb
Host smart-925ba68c-34b3-4cdb-a444-2b4c74bab389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666246310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.1666246310
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2299455307
Short name T858
Test name
Test status
Simulation time 55137296 ps
CPU time 1.44 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:16 PM PDT 24
Peak memory 200652 kb
Host smart-34b5dce6-e7d5-4e29-8520-a2f4b6b3c81c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299455307 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2299455307
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2480828597
Short name T65
Test name
Test status
Simulation time 115800098 ps
CPU time 1.55 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:16 PM PDT 24
Peak memory 200652 kb
Host smart-109a9b30-179d-41ae-9195-7787b9b22fcb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480828597 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.2480828597
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2988003032
Short name T963
Test name
Test status
Simulation time 178500265 ps
CPU time 3.26 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:19 PM PDT 24
Peak memory 217160 kb
Host smart-12fe01c7-4bc5-43f1-b841-6b61d69ef5c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988003032 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2988003032
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2332105487
Short name T893
Test name
Test status
Simulation time 76289827 ps
CPU time 2.35 seconds
Started Jul 31 07:30:16 PM PDT 24
Finished Jul 31 07:30:19 PM PDT 24
Peak memory 200488 kb
Host smart-9c055c36-29e2-403f-991b-3eedf7a85515
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332105487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2332105487
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.111954453
Short name T118
Test name
Test status
Simulation time 140817298 ps
CPU time 2.77 seconds
Started Jul 31 07:30:17 PM PDT 24
Finished Jul 31 07:30:20 PM PDT 24
Peak memory 200560 kb
Host smart-88d1c66f-613a-49e2-a4af-955232ee9751
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111954453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_tl_intg_err.111954453
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3684378804
Short name T904
Test name
Test status
Simulation time 145593113 ps
CPU time 1.54 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200448 kb
Host smart-86163084-eb2c-4539-bc36-f17f071a8055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684378804 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3684378804
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.2923763490
Short name T911
Test name
Test status
Simulation time 49822852 ps
CPU time 0.89 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:14 PM PDT 24
Peak memory 200252 kb
Host smart-22514e09-07af-4159-8890-03e62095dfc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923763490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.2923763490
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3599384859
Short name T844
Test name
Test status
Simulation time 12135885 ps
CPU time 0.67 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 198920 kb
Host smart-67be4c05-ebca-49d7-908e-427d17073ccb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599384859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3599384859
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3405222922
Short name T948
Test name
Test status
Simulation time 253860451 ps
CPU time 1.79 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200592 kb
Host smart-8db6450a-6924-4a66-a4d5-ed0f043d2a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405222922 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.3405222922
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2083534176
Short name T132
Test name
Test status
Simulation time 109396390 ps
CPU time 1.55 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200664 kb
Host smart-225e3636-8c99-44be-b33c-70f2d622df10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083534176 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.2083534176
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4059589122
Short name T141
Test name
Test status
Simulation time 81621492 ps
CPU time 1.91 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:16 PM PDT 24
Peak memory 201104 kb
Host smart-ec2078b1-8909-4319-b589-0f6f51bb9bc7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059589122 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.4059589122
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.883119274
Short name T974
Test name
Test status
Simulation time 358187264 ps
CPU time 2.27 seconds
Started Jul 31 07:30:15 PM PDT 24
Finished Jul 31 07:30:18 PM PDT 24
Peak memory 200652 kb
Host smart-4a514da6-21af-44b2-89b9-74161fcca3a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883119274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clk
mgr_tl_errors.883119274
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1836864014
Short name T883
Test name
Test status
Simulation time 85594453 ps
CPU time 1.08 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 200468 kb
Host smart-841501ad-d18f-42ce-ba12-baa1575ae3a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836864014 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1836864014
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1911087488
Short name T855
Test name
Test status
Simulation time 14896663 ps
CPU time 0.86 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 200460 kb
Host smart-657066e7-cfdf-4773-ba5a-a828d3e4ad9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911087488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.1911087488
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.773343198
Short name T888
Test name
Test status
Simulation time 12359299 ps
CPU time 0.65 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 198984 kb
Host smart-4c8345f8-f869-4a63-b84d-a9fac179135e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773343198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_intr_test.773343198
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3085257010
Short name T900
Test name
Test status
Simulation time 32514142 ps
CPU time 0.93 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 200392 kb
Host smart-595d8637-6ec3-43a3-b2ac-a3f158c81af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085257010 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.3085257010
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3385509492
Short name T60
Test name
Test status
Simulation time 62012704 ps
CPU time 1.21 seconds
Started Jul 31 07:30:13 PM PDT 24
Finished Jul 31 07:30:15 PM PDT 24
Peak memory 200672 kb
Host smart-88fc2b0a-8c93-45e2-947f-567617334668
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385509492 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3385509492
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1183709974
Short name T140
Test name
Test status
Simulation time 601211827 ps
CPU time 3.19 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:18 PM PDT 24
Peak memory 200836 kb
Host smart-55926644-88c9-428f-bad3-4794a73b1c1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183709974 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1183709974
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.1405384871
Short name T862
Test name
Test status
Simulation time 100277354 ps
CPU time 2.71 seconds
Started Jul 31 07:30:14 PM PDT 24
Finished Jul 31 07:30:17 PM PDT 24
Peak memory 200548 kb
Host smart-32aac13a-5ff3-44b4-b1cb-14f7ff84d6c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405384871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.1405384871
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3993319372
Short name T853
Test name
Test status
Simulation time 66561303 ps
CPU time 1.22 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 200340 kb
Host smart-60f748f1-dea4-470b-929c-98587434999c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993319372 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3993319372
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.1327565856
Short name T849
Test name
Test status
Simulation time 16755817 ps
CPU time 0.75 seconds
Started Jul 31 07:30:20 PM PDT 24
Finished Jul 31 07:30:21 PM PDT 24
Peak memory 200352 kb
Host smart-aceec4d1-ecc7-489b-b5a8-56178175b3e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327565856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.1327565856
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2841094851
Short name T836
Test name
Test status
Simulation time 28501484 ps
CPU time 0.68 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 198540 kb
Host smart-2335d0b7-103e-4053-8d16-95ee2f4198db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841094851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2841094851
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.392087925
Short name T87
Test name
Test status
Simulation time 99115312 ps
CPU time 1.47 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 200552 kb
Host smart-37a42342-c0c2-446d-9dc5-919c604d3d36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392087925 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.clkmgr_same_csr_outstanding.392087925
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3515431025
Short name T147
Test name
Test status
Simulation time 111971805 ps
CPU time 1.3 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 200688 kb
Host smart-545f429c-1eae-4813-996b-08f10c71e8eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515431025 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3515431025
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.4127310405
Short name T145
Test name
Test status
Simulation time 779990745 ps
CPU time 4.54 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:26 PM PDT 24
Peak memory 210172 kb
Host smart-29170ee8-4baa-4b19-bdaa-28d98dba94d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127310405 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.4127310405
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.793227982
Short name T825
Test name
Test status
Simulation time 37963554 ps
CPU time 2.1 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 200564 kb
Host smart-4cd5c1ab-2c5d-4da1-a2a3-7895f3a90b38
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793227982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_tl_errors.793227982
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1788591879
Short name T854
Test name
Test status
Simulation time 101057378 ps
CPU time 1.87 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 200628 kb
Host smart-57faefa7-44a3-47c7-ae86-fcc088b8db81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788591879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.1788591879
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.4204589569
Short name T892
Test name
Test status
Simulation time 63867298 ps
CPU time 1.29 seconds
Started Jul 31 07:29:39 PM PDT 24
Finished Jul 31 07:29:41 PM PDT 24
Peak memory 200240 kb
Host smart-00a2cd46-3e23-4ec2-adba-6b74336ae9d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204589569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.4204589569
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3686861949
Short name T842
Test name
Test status
Simulation time 1773835049 ps
CPU time 11.77 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 200624 kb
Host smart-fe0a035d-ec62-4f29-af63-aef9888f7b2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686861949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.3686861949
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3282687819
Short name T885
Test name
Test status
Simulation time 123397771 ps
CPU time 0.97 seconds
Started Jul 31 07:29:43 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200364 kb
Host smart-21c5e9c9-5763-4f86-9a69-826f4cc7394e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282687819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.3282687819
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1391344430
Short name T914
Test name
Test status
Simulation time 45826385 ps
CPU time 1.4 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 200576 kb
Host smart-35d4f348-d7da-40bc-993d-312d2e710fd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391344430 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1391344430
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.3992193189
Short name T935
Test name
Test status
Simulation time 130461802 ps
CPU time 1.02 seconds
Started Jul 31 07:29:45 PM PDT 24
Finished Jul 31 07:29:46 PM PDT 24
Peak memory 200332 kb
Host smart-b383317d-882d-49a4-bdf2-33cfd227741f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992193189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.3992193189
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.4294696827
Short name T852
Test name
Test status
Simulation time 21604266 ps
CPU time 0.67 seconds
Started Jul 31 07:29:44 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 198968 kb
Host smart-8f7bbc53-ca83-429a-9312-f0c7e4e7799a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294696827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.4294696827
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.274747817
Short name T925
Test name
Test status
Simulation time 105859882 ps
CPU time 1.45 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200508 kb
Host smart-ee9e8d7a-73dc-4aef-ae49-ee2c4d97ea9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274747817 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.clkmgr_same_csr_outstanding.274747817
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.359357343
Short name T67
Test name
Test status
Simulation time 178207301 ps
CPU time 1.58 seconds
Started Jul 31 07:29:43 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200636 kb
Host smart-6aa5ceb1-253d-4caf-82a3-7d3b1399e7e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359357343 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.clkmgr_shadow_reg_errors.359357343
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4160173797
Short name T136
Test name
Test status
Simulation time 76347416 ps
CPU time 1.74 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 210016 kb
Host smart-9aaa3c7e-870c-4d0b-b008-19b7b4ed74d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160173797 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.4160173797
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3057529197
Short name T897
Test name
Test status
Simulation time 410295492 ps
CPU time 3.89 seconds
Started Jul 31 07:29:40 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200520 kb
Host smart-6e024fbf-0a97-42c5-a11e-94709d9fb44f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057529197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.3057529197
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1952652658
Short name T120
Test name
Test status
Simulation time 251765596 ps
CPU time 3.02 seconds
Started Jul 31 07:29:41 PM PDT 24
Finished Jul 31 07:29:45 PM PDT 24
Peak memory 200616 kb
Host smart-7c2e4b4a-88ac-4503-8f88-4772db911aa5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952652658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1952652658
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.1449684587
Short name T843
Test name
Test status
Simulation time 11671236 ps
CPU time 0.66 seconds
Started Jul 31 07:30:20 PM PDT 24
Finished Jul 31 07:30:21 PM PDT 24
Peak memory 198980 kb
Host smart-8457c1e6-4902-4470-864a-0e9978f2a788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449684587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.1449684587
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3909926522
Short name T936
Test name
Test status
Simulation time 32925566 ps
CPU time 0.69 seconds
Started Jul 31 07:30:25 PM PDT 24
Finished Jul 31 07:30:26 PM PDT 24
Peak memory 198904 kb
Host smart-0888b981-a124-40e9-a20a-afe8ea59d13b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909926522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3909926522
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.3663393312
Short name T881
Test name
Test status
Simulation time 12167892 ps
CPU time 0.67 seconds
Started Jul 31 07:30:26 PM PDT 24
Finished Jul 31 07:30:27 PM PDT 24
Peak memory 199032 kb
Host smart-8bfff8a1-299f-4b64-982f-ce9ad32dcbb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663393312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.3663393312
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.1039428411
Short name T938
Test name
Test status
Simulation time 13746168 ps
CPU time 0.67 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 199056 kb
Host smart-7ab8359d-cda6-4567-8864-7c8fc0e875b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039428411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.1039428411
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.494298699
Short name T889
Test name
Test status
Simulation time 15675313 ps
CPU time 0.67 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 198972 kb
Host smart-faaa44ee-b024-43aa-a12e-171a6fe93f6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494298699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.494298699
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.129370303
Short name T908
Test name
Test status
Simulation time 32525338 ps
CPU time 0.68 seconds
Started Jul 31 07:30:20 PM PDT 24
Finished Jul 31 07:30:21 PM PDT 24
Peak memory 198932 kb
Host smart-b36a2bd6-e487-4f21-b619-e76f3e6dd360
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129370303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.129370303
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3812357616
Short name T875
Test name
Test status
Simulation time 90472811 ps
CPU time 0.84 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 199020 kb
Host smart-4acc4106-b6c2-49c8-8489-e6184b94b2a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812357616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3812357616
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.2981172277
Short name T873
Test name
Test status
Simulation time 36646333 ps
CPU time 0.71 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 199020 kb
Host smart-a7445efe-7aaf-4f6e-9cdd-7ed2bc46c123
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981172277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.2981172277
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.330928904
Short name T957
Test name
Test status
Simulation time 11229243 ps
CPU time 0.75 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 199016 kb
Host smart-1acbf7e1-fbbf-4b8f-8ab5-d92811e3ceb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330928904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.330928904
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.979627466
Short name T965
Test name
Test status
Simulation time 23459224 ps
CPU time 0.66 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:25 PM PDT 24
Peak memory 198948 kb
Host smart-9d3539ac-6287-4df2-826b-b6527c1322dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979627466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.979627466
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.3444213180
Short name T834
Test name
Test status
Simulation time 50859249 ps
CPU time 1.57 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200580 kb
Host smart-1fce6973-414e-4f63-8378-24f4853220d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444213180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.3444213180
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.3336878060
Short name T973
Test name
Test status
Simulation time 428299372 ps
CPU time 7.49 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:56 PM PDT 24
Peak memory 200564 kb
Host smart-719edbf8-ad19-4245-a79a-9303965f47af
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336878060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.3336878060
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.2214654152
Short name T921
Test name
Test status
Simulation time 96586552 ps
CPU time 0.93 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200388 kb
Host smart-679681c7-5e00-4a99-b31d-49daf7f7ddcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214654152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.2214654152
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3058085843
Short name T822
Test name
Test status
Simulation time 123021539 ps
CPU time 1.54 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200476 kb
Host smart-8b32ae2a-0146-4908-8658-45a9cc10225e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058085843 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3058085843
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.2086385078
Short name T924
Test name
Test status
Simulation time 28950930 ps
CPU time 0.81 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:49 PM PDT 24
Peak memory 200324 kb
Host smart-8fb9edc8-8f10-4c0a-8355-151a60bc52cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086385078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.2086385078
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1908443718
Short name T847
Test name
Test status
Simulation time 11827330 ps
CPU time 0.67 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 198928 kb
Host smart-ad99f373-d874-4e9a-9214-1f963b181cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908443718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.1908443718
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.3391048051
Short name T89
Test name
Test status
Simulation time 38902890 ps
CPU time 1.1 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200336 kb
Host smart-d56f00bf-7100-43eb-b9ae-043435d32e25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391048051 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.3391048051
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.108698811
Short name T934
Test name
Test status
Simulation time 67771780 ps
CPU time 1.31 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:43 PM PDT 24
Peak memory 200712 kb
Host smart-7549bb2e-7ccb-4ddf-b1ee-45302f75ec25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108698811 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.clkmgr_shadow_reg_errors.108698811
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1271558662
Short name T64
Test name
Test status
Simulation time 184625889 ps
CPU time 3.05 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:45 PM PDT 24
Peak memory 201116 kb
Host smart-8fd32d84-c7ed-495c-8735-5c2e26e8fb4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271558662 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1271558662
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2685289632
Short name T890
Test name
Test status
Simulation time 118002283 ps
CPU time 2.96 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:45 PM PDT 24
Peak memory 200476 kb
Host smart-0d55551f-4cce-4f5c-bdbd-1f09862c7e82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685289632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2685289632
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3810464636
Short name T181
Test name
Test status
Simulation time 66582456 ps
CPU time 1.62 seconds
Started Jul 31 07:29:42 PM PDT 24
Finished Jul 31 07:29:44 PM PDT 24
Peak memory 200552 kb
Host smart-16828164-f60e-4c07-a669-5bac7684f6b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810464636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.3810464636
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.4024925018
Short name T909
Test name
Test status
Simulation time 12625196 ps
CPU time 0.65 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:25 PM PDT 24
Peak memory 199080 kb
Host smart-1e35de7f-360b-4ddd-8e82-2e68f1f191e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024925018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.4024925018
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4089442055
Short name T864
Test name
Test status
Simulation time 32586331 ps
CPU time 0.7 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 198992 kb
Host smart-302f4e57-4358-4573-97ab-a14b21dc92fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089442055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.4089442055
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.752673620
Short name T899
Test name
Test status
Simulation time 14609472 ps
CPU time 0.69 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:25 PM PDT 24
Peak memory 199040 kb
Host smart-d73505a3-f41e-4be2-8705-ad6a026ae566
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752673620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clk
mgr_intr_test.752673620
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.19295726
Short name T952
Test name
Test status
Simulation time 15485459 ps
CPU time 0.65 seconds
Started Jul 31 07:30:20 PM PDT 24
Finished Jul 31 07:30:21 PM PDT 24
Peak memory 198956 kb
Host smart-560c2438-23bf-41b6-a794-85212621142f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19295726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkm
gr_intr_test.19295726
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.3362477864
Short name T835
Test name
Test status
Simulation time 19148214 ps
CPU time 0.7 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 199040 kb
Host smart-63afa642-03f3-4735-8034-23b4389f7b43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362477864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.3362477864
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1989481296
Short name T824
Test name
Test status
Simulation time 24328300 ps
CPU time 0.67 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 198948 kb
Host smart-4ad88a13-7e96-4464-9e87-9804ae8e78b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989481296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.1989481296
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.816561126
Short name T918
Test name
Test status
Simulation time 39838890 ps
CPU time 0.74 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 198988 kb
Host smart-d787eb41-e7a2-4475-939a-f791d53c4ca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816561126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk
mgr_intr_test.816561126
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.3620948699
Short name T942
Test name
Test status
Simulation time 14679838 ps
CPU time 0.67 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 198912 kb
Host smart-23b8d947-5afe-464f-b835-69d9aa4befe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620948699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.3620948699
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2145323226
Short name T830
Test name
Test status
Simulation time 17101473 ps
CPU time 0.68 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 199064 kb
Host smart-a241fc33-a386-4f92-a023-85cbfe2e2009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145323226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2145323226
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2963324804
Short name T906
Test name
Test status
Simulation time 28682794 ps
CPU time 0.69 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 199024 kb
Host smart-3ccd118c-1b82-4439-926c-62195fe11748
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963324804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.2963324804
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.1838918113
Short name T876
Test name
Test status
Simulation time 409329760 ps
CPU time 2.09 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:51 PM PDT 24
Peak memory 200500 kb
Host smart-b492e80c-f072-4a71-b4da-a3a9afd93ba0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838918113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.1838918113
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2616420382
Short name T966
Test name
Test status
Simulation time 274508996 ps
CPU time 4.94 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 200600 kb
Host smart-bd67d78a-c6ba-4328-8912-a781d4d8913a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616420382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.2616420382
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.844743972
Short name T850
Test name
Test status
Simulation time 17508177 ps
CPU time 0.76 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:51 PM PDT 24
Peak memory 200344 kb
Host smart-4d844ee6-0cd2-4b95-bf44-6a5c8f400462
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844743972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_csr_hw_reset.844743972
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.267460190
Short name T879
Test name
Test status
Simulation time 34101920 ps
CPU time 1.77 seconds
Started Jul 31 07:29:53 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 200568 kb
Host smart-334f34e4-a6ee-4608-b054-3d86a6bb2155
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267460190 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.267460190
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3766995897
Short name T863
Test name
Test status
Simulation time 25273528 ps
CPU time 0.93 seconds
Started Jul 31 07:29:54 PM PDT 24
Finished Jul 31 07:29:55 PM PDT 24
Peak memory 200344 kb
Host smart-8d671e00-2dbb-459d-96cf-c956c0031b8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766995897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3766995897
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.245443405
Short name T851
Test name
Test status
Simulation time 33234855 ps
CPU time 0.7 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 198992 kb
Host smart-fc726b3d-28e1-48af-ae5a-1d1d0c275a66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245443405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_intr_test.245443405
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3766891159
Short name T85
Test name
Test status
Simulation time 121136118 ps
CPU time 1.12 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:51 PM PDT 24
Peak memory 200392 kb
Host smart-01242db2-a287-4f1f-8da7-de2f764ec904
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766891159 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3766891159
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.256675152
Short name T61
Test name
Test status
Simulation time 70349738 ps
CPU time 1.26 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:49 PM PDT 24
Peak memory 200656 kb
Host smart-44d059f3-9c41-4080-9fe8-9ae4c4b2ae77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256675152 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.256675152
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3763482250
Short name T959
Test name
Test status
Simulation time 98765164 ps
CPU time 2.03 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 216992 kb
Host smart-1fc77dd7-14bb-4239-b347-0652164fce5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763482250 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3763482250
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1979326485
Short name T956
Test name
Test status
Simulation time 162276087 ps
CPU time 1.9 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:53 PM PDT 24
Peak memory 200532 kb
Host smart-7f2396e9-4bfb-4365-a54d-44f71db6a66c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979326485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1979326485
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1312403945
Short name T962
Test name
Test status
Simulation time 120390422 ps
CPU time 2.68 seconds
Started Jul 31 07:29:54 PM PDT 24
Finished Jul 31 07:29:56 PM PDT 24
Peak memory 200548 kb
Host smart-fd4c97c2-8c9c-4a91-93fb-9c7226d648c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312403945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1312403945
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3818969117
Short name T841
Test name
Test status
Simulation time 71767529 ps
CPU time 0.77 seconds
Started Jul 31 07:30:20 PM PDT 24
Finished Jul 31 07:30:21 PM PDT 24
Peak memory 198968 kb
Host smart-42ff7212-ab27-4eb0-82a0-85aec8cfad49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818969117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3818969117
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.1744357580
Short name T882
Test name
Test status
Simulation time 11734161 ps
CPU time 0.67 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 198992 kb
Host smart-42495b3d-6117-4541-8153-6357aa489885
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744357580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.1744357580
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1750443497
Short name T923
Test name
Test status
Simulation time 34389478 ps
CPU time 0.7 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 198956 kb
Host smart-54fd6a69-9123-473f-829b-2ce6e8e30949
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750443497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1750443497
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3457866802
Short name T861
Test name
Test status
Simulation time 17653863 ps
CPU time 0.67 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 198984 kb
Host smart-50e5d9da-6c46-4a7f-a064-8fa60002fc01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457866802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3457866802
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.358606018
Short name T831
Test name
Test status
Simulation time 30075287 ps
CPU time 0.67 seconds
Started Jul 31 07:30:21 PM PDT 24
Finished Jul 31 07:30:22 PM PDT 24
Peak memory 199004 kb
Host smart-60a10505-4b45-487e-8c1d-67f4df37276b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358606018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clk
mgr_intr_test.358606018
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.3502168429
Short name T833
Test name
Test status
Simulation time 30261908 ps
CPU time 0.69 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:25 PM PDT 24
Peak memory 198968 kb
Host smart-a04e63da-1167-4fa8-84e0-cc9faf92c5a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502168429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.3502168429
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.824665014
Short name T828
Test name
Test status
Simulation time 13287374 ps
CPU time 0.71 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:24 PM PDT 24
Peak memory 198972 kb
Host smart-48aecf11-3494-4ad9-956b-06cecbb9a7d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824665014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk
mgr_intr_test.824665014
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3175475467
Short name T945
Test name
Test status
Simulation time 75859629 ps
CPU time 0.79 seconds
Started Jul 31 07:30:22 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 199136 kb
Host smart-cf4eeee7-4630-4246-adf7-2deb43dc4eb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175475467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.3175475467
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1118449463
Short name T860
Test name
Test status
Simulation time 12387867 ps
CPU time 0.68 seconds
Started Jul 31 07:30:24 PM PDT 24
Finished Jul 31 07:30:25 PM PDT 24
Peak memory 198928 kb
Host smart-af20eddd-ac81-4061-af5b-9bcf025bc257
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118449463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1118449463
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1090803833
Short name T870
Test name
Test status
Simulation time 19849479 ps
CPU time 0.7 seconds
Started Jul 31 07:30:23 PM PDT 24
Finished Jul 31 07:30:23 PM PDT 24
Peak memory 198980 kb
Host smart-07fb4110-246b-4b21-9b57-8cd7d3f9ad59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090803833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1090803833
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2487879009
Short name T878
Test name
Test status
Simulation time 27148639 ps
CPU time 0.92 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200360 kb
Host smart-f7930ed9-e7d7-42dd-a32e-b84d7b8a7da1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487879009 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2487879009
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.85826926
Short name T872
Test name
Test status
Simulation time 22255491 ps
CPU time 0.78 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:49 PM PDT 24
Peak memory 200296 kb
Host smart-650d5d03-ab09-4c2c-b7b4-6fe7c7a9decf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85826926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.cl
kmgr_csr_rw.85826926
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.323523497
Short name T955
Test name
Test status
Simulation time 20859628 ps
CPU time 0.68 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 199040 kb
Host smart-7ca5b4be-c743-4cc6-b478-ecc85186636a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323523497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkm
gr_intr_test.323523497
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3243414892
Short name T84
Test name
Test status
Simulation time 66478711 ps
CPU time 1.52 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200580 kb
Host smart-3092d17e-21e5-4f45-b82f-7894278f2a88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243414892 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.3243414892
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.983662686
Short name T142
Test name
Test status
Simulation time 278205655 ps
CPU time 2.3 seconds
Started Jul 31 07:29:47 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200804 kb
Host smart-017fbf87-7bd5-4a7a-90ef-9bbaa0fdd382
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983662686 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.clkmgr_shadow_reg_errors.983662686
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3683075748
Short name T133
Test name
Test status
Simulation time 239411932 ps
CPU time 2.32 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 217084 kb
Host smart-66dd928d-985e-431b-ac63-e2dc4c121094
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683075748 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3683075748
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2912810698
Short name T951
Test name
Test status
Simulation time 113824138 ps
CPU time 2.8 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:53 PM PDT 24
Peak memory 200556 kb
Host smart-8a8b4708-02ca-4e1c-861e-46e952df58cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912810698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.2912810698
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1431871530
Short name T947
Test name
Test status
Simulation time 200982251 ps
CPU time 2.82 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 200536 kb
Host smart-5162d9f7-efda-4df1-ae15-45f8ecbb9563
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431871530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1431871530
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2668270888
Short name T171
Test name
Test status
Simulation time 58184974 ps
CPU time 1 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200452 kb
Host smart-2af7eea1-d7bb-41ac-8158-c1c5a0ce2469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668270888 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2668270888
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.1224176886
Short name T88
Test name
Test status
Simulation time 16979969 ps
CPU time 0.81 seconds
Started Jul 31 07:29:52 PM PDT 24
Finished Jul 31 07:29:53 PM PDT 24
Peak memory 200380 kb
Host smart-a376196d-ec46-4fc6-a0cb-24730188a892
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224176886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.1224176886
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3320095824
Short name T891
Test name
Test status
Simulation time 13327327 ps
CPU time 0.75 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 198956 kb
Host smart-d63fd331-50bc-44a0-aa69-fb6bb0f4c6a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320095824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3320095824
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.2199267400
Short name T912
Test name
Test status
Simulation time 474641515 ps
CPU time 2.44 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200600 kb
Host smart-c242c468-d934-4ccb-bd76-399b49a27338
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199267400 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.2199267400
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.947555623
Short name T958
Test name
Test status
Simulation time 215924365 ps
CPU time 2.04 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:51 PM PDT 24
Peak memory 200840 kb
Host smart-53f4b436-b8fa-43d8-8e22-b1b6a617bf42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947555623 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.947555623
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3950308401
Short name T905
Test name
Test status
Simulation time 128126559 ps
CPU time 1.79 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200828 kb
Host smart-6196cede-f45f-4aae-8403-c54ea5c923e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950308401 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3950308401
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1768484548
Short name T898
Test name
Test status
Simulation time 143321422 ps
CPU time 2.75 seconds
Started Jul 31 07:29:49 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200460 kb
Host smart-0f08cc14-4f6f-4229-a675-88d8d9c906e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768484548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.1768484548
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3808899706
Short name T111
Test name
Test status
Simulation time 147073620 ps
CPU time 2.44 seconds
Started Jul 31 07:29:48 PM PDT 24
Finished Jul 31 07:29:50 PM PDT 24
Peak memory 200528 kb
Host smart-b4eefbda-9558-47e4-b62b-b7383c7fa124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808899706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3808899706
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.208078392
Short name T919
Test name
Test status
Simulation time 28241209 ps
CPU time 1.13 seconds
Started Jul 31 07:29:58 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200476 kb
Host smart-bd31569d-68fa-46c8-a002-299a504a0812
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208078392 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.208078392
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1097839076
Short name T975
Test name
Test status
Simulation time 62085658 ps
CPU time 0.89 seconds
Started Jul 31 07:29:55 PM PDT 24
Finished Jul 31 07:29:56 PM PDT 24
Peak memory 200276 kb
Host smart-bbdef8fb-26d7-4ec7-ad46-33db1efaef6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097839076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.1097839076
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3809937188
Short name T887
Test name
Test status
Simulation time 19204580 ps
CPU time 0.73 seconds
Started Jul 31 07:30:00 PM PDT 24
Finished Jul 31 07:30:01 PM PDT 24
Peak memory 198928 kb
Host smart-52625009-5ff4-4c73-b3ee-748474c6444a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809937188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3809937188
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3815812855
Short name T856
Test name
Test status
Simulation time 31266617 ps
CPU time 1.05 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200344 kb
Host smart-86bfe344-cc71-4e29-ade2-291813275855
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815812855 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.3815812855
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3443122878
Short name T139
Test name
Test status
Simulation time 130086580 ps
CPU time 2.9 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:54 PM PDT 24
Peak memory 209056 kb
Host smart-6db434cd-5ef7-48fb-9093-876953c0a30c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443122878 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3443122878
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1592909838
Short name T971
Test name
Test status
Simulation time 52991272 ps
CPU time 1.53 seconds
Started Jul 31 07:29:51 PM PDT 24
Finished Jul 31 07:29:52 PM PDT 24
Peak memory 200364 kb
Host smart-07e0b743-4631-4c15-a507-5cf3b27b07e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592909838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1592909838
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3563617340
Short name T110
Test name
Test status
Simulation time 63464700 ps
CPU time 1.61 seconds
Started Jul 31 07:29:50 PM PDT 24
Finished Jul 31 07:29:51 PM PDT 24
Peak memory 200504 kb
Host smart-58c0d14d-711b-493c-a045-d789e702fb75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563617340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3563617340
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4224986789
Short name T895
Test name
Test status
Simulation time 24008043 ps
CPU time 1.02 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200384 kb
Host smart-09e01af7-db1f-4495-86a7-ca2363aa2868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224986789 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.4224986789
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1174801454
Short name T915
Test name
Test status
Simulation time 24830838 ps
CPU time 0.8 seconds
Started Jul 31 07:29:58 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200384 kb
Host smart-2bc1d3ac-d657-4dc0-9b0e-aca05db4bcfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174801454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.1174801454
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4236653443
Short name T857
Test name
Test status
Simulation time 24271551 ps
CPU time 0.69 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:57 PM PDT 24
Peak memory 198968 kb
Host smart-19bff43f-e417-481e-912d-c8cda8c94a9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236653443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.4236653443
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2435474170
Short name T950
Test name
Test status
Simulation time 57392387 ps
CPU time 1.51 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200664 kb
Host smart-f62f5610-1c36-4d00-a0fa-5a0ac5dc63fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435474170 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.2435474170
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.1663386183
Short name T926
Test name
Test status
Simulation time 130141452 ps
CPU time 2.09 seconds
Started Jul 31 07:29:58 PM PDT 24
Finished Jul 31 07:30:00 PM PDT 24
Peak memory 200892 kb
Host smart-d2682dce-cbbd-4b8a-9997-9d64510c32cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663386183 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.1663386183
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.717000379
Short name T135
Test name
Test status
Simulation time 102189270 ps
CPU time 2.46 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:30:00 PM PDT 24
Peak memory 209028 kb
Host smart-db4e4688-5a4d-4f81-8aaa-436b40c5ba50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717000379 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.717000379
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.2412077639
Short name T967
Test name
Test status
Simulation time 39193699 ps
CPU time 2.28 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200544 kb
Host smart-3ad8fed1-f288-4abc-aabb-3c2ac4afb8da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412077639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.2412077639
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2213292451
Short name T180
Test name
Test status
Simulation time 227593248 ps
CPU time 2.14 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200532 kb
Host smart-74572a11-d392-4e8a-9dc6-92aaa0c2f7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213292451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.2213292451
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.4119929013
Short name T859
Test name
Test status
Simulation time 95813895 ps
CPU time 1.19 seconds
Started Jul 31 07:29:58 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200412 kb
Host smart-67c0b886-f805-4073-b441-fe19f99956a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119929013 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.4119929013
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3687744259
Short name T90
Test name
Test status
Simulation time 43206079 ps
CPU time 0.95 seconds
Started Jul 31 07:29:59 PM PDT 24
Finished Jul 31 07:30:00 PM PDT 24
Peak memory 200400 kb
Host smart-404bf6a0-088c-40f5-b459-d06f49c8fc14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687744259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3687744259
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.445671000
Short name T949
Test name
Test status
Simulation time 28268676 ps
CPU time 0.66 seconds
Started Jul 31 07:29:55 PM PDT 24
Finished Jul 31 07:29:56 PM PDT 24
Peak memory 199052 kb
Host smart-35906c4d-0473-4fb2-b5a9-089600f3cb12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445671000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_intr_test.445671000
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3904092087
Short name T907
Test name
Test status
Simulation time 132908480 ps
CPU time 1.71 seconds
Started Jul 31 07:29:56 PM PDT 24
Finished Jul 31 07:29:58 PM PDT 24
Peak memory 200600 kb
Host smart-db1ccad0-f9e9-4269-8c23-2da79ca1e350
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904092087 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.3904092087
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2149696828
Short name T134
Test name
Test status
Simulation time 227871166 ps
CPU time 2.09 seconds
Started Jul 31 07:29:58 PM PDT 24
Finished Jul 31 07:30:00 PM PDT 24
Peak memory 200868 kb
Host smart-28d28e99-0a59-4483-8a79-0c8a30ff52cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149696828 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.2149696828
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.333890003
Short name T63
Test name
Test status
Simulation time 158082446 ps
CPU time 2.77 seconds
Started Jul 31 07:29:59 PM PDT 24
Finished Jul 31 07:30:02 PM PDT 24
Peak memory 208988 kb
Host smart-b3ca9134-8fdf-4f91-a0c8-9092dc86b954
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333890003 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.333890003
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3242935297
Short name T826
Test name
Test status
Simulation time 219366957 ps
CPU time 2.65 seconds
Started Jul 31 07:29:57 PM PDT 24
Finished Jul 31 07:29:59 PM PDT 24
Peak memory 200572 kb
Host smart-bc480eef-9967-444b-8ddf-e97d1c4a2354
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242935297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.3242935297
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3236943337
Short name T802
Test name
Test status
Simulation time 16843367 ps
CPU time 0.79 seconds
Started Jul 31 05:54:53 PM PDT 24
Finished Jul 31 05:54:54 PM PDT 24
Peak memory 201032 kb
Host smart-f2277cff-0fc7-45b0-aef4-a955c8c819d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236943337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3236943337
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.4142681108
Short name T254
Test name
Test status
Simulation time 38835228 ps
CPU time 0.86 seconds
Started Jul 31 05:54:43 PM PDT 24
Finished Jul 31 05:54:44 PM PDT 24
Peak memory 201080 kb
Host smart-fe6036e5-2c23-4e2b-a996-26b1f1ad2ebb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142681108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.4142681108
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2891844331
Short name T248
Test name
Test status
Simulation time 51641278 ps
CPU time 0.8 seconds
Started Jul 31 05:54:36 PM PDT 24
Finished Jul 31 05:54:37 PM PDT 24
Peak memory 200216 kb
Host smart-9bab409e-d992-41ee-95ca-0ff3e4719924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891844331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2891844331
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.4174295018
Short name T410
Test name
Test status
Simulation time 439544637 ps
CPU time 2.11 seconds
Started Jul 31 05:54:40 PM PDT 24
Finished Jul 31 05:54:42 PM PDT 24
Peak memory 201136 kb
Host smart-0a92f44a-b27e-46a9-97c2-abd1053bc40d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174295018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.4174295018
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.3761232395
Short name T560
Test name
Test status
Simulation time 27885409 ps
CPU time 0.92 seconds
Started Jul 31 05:54:31 PM PDT 24
Finished Jul 31 05:54:33 PM PDT 24
Peak memory 201088 kb
Host smart-a5ec01c5-8a9b-47e5-8ced-d27bb3478e52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761232395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.3761232395
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.2477702189
Short name T665
Test name
Test status
Simulation time 439617504 ps
CPU time 4.07 seconds
Started Jul 31 05:54:33 PM PDT 24
Finished Jul 31 05:54:37 PM PDT 24
Peak memory 201100 kb
Host smart-a4d01cb0-1aa8-405f-a53a-a776101c3001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477702189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2477702189
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.2965318581
Short name T484
Test name
Test status
Simulation time 378606182 ps
CPU time 2.84 seconds
Started Jul 31 05:54:34 PM PDT 24
Finished Jul 31 05:54:37 PM PDT 24
Peak memory 201220 kb
Host smart-301ebe2c-5fb1-480d-ad34-8365030559ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965318581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.2965318581
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.429242320
Short name T766
Test name
Test status
Simulation time 126194841 ps
CPU time 1.28 seconds
Started Jul 31 05:54:40 PM PDT 24
Finished Jul 31 05:54:41 PM PDT 24
Peak memory 201044 kb
Host smart-f90cad3c-8b94-4de3-a36e-cbd95df138d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429242320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.429242320
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1697534469
Short name T796
Test name
Test status
Simulation time 12802141 ps
CPU time 0.74 seconds
Started Jul 31 05:54:42 PM PDT 24
Finished Jul 31 05:54:42 PM PDT 24
Peak memory 201004 kb
Host smart-909f8859-4576-4acd-ab70-43256ef22c07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697534469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.1697534469
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.351176061
Short name T379
Test name
Test status
Simulation time 86238488 ps
CPU time 1.09 seconds
Started Jul 31 05:54:40 PM PDT 24
Finished Jul 31 05:54:42 PM PDT 24
Peak memory 201112 kb
Host smart-748012b8-739b-4758-b00f-97c9bf0f2b62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351176061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.351176061
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.3688290704
Short name T360
Test name
Test status
Simulation time 104441226 ps
CPU time 0.97 seconds
Started Jul 31 05:54:37 PM PDT 24
Finished Jul 31 05:54:38 PM PDT 24
Peak memory 201076 kb
Host smart-af2aaee4-a6ce-4c53-9b9f-08d1ae284199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688290704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3688290704
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.894030372
Short name T522
Test name
Test status
Simulation time 518064903 ps
CPU time 2.71 seconds
Started Jul 31 05:54:47 PM PDT 24
Finished Jul 31 05:54:50 PM PDT 24
Peak memory 201064 kb
Host smart-c021d1fe-cb45-44fa-a223-bf83b86182f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894030372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.894030372
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.2236961192
Short name T47
Test name
Test status
Simulation time 287878005 ps
CPU time 3.15 seconds
Started Jul 31 05:54:49 PM PDT 24
Finished Jul 31 05:54:53 PM PDT 24
Peak memory 217880 kb
Host smart-278c5fd5-a4bb-4f8f-a943-fe7020eeef19
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236961192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.2236961192
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.1254496242
Short name T792
Test name
Test status
Simulation time 22286716 ps
CPU time 0.84 seconds
Started Jul 31 05:54:31 PM PDT 24
Finished Jul 31 05:54:32 PM PDT 24
Peak memory 200980 kb
Host smart-968dc07d-6b27-49fe-843d-55561352906c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254496242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1254496242
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.1224191080
Short name T621
Test name
Test status
Simulation time 8415217828 ps
CPU time 62.31 seconds
Started Jul 31 05:54:48 PM PDT 24
Finished Jul 31 05:55:50 PM PDT 24
Peak memory 201432 kb
Host smart-2fe348c2-86fb-46f1-9143-77bba16ac0aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224191080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.1224191080
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.233917862
Short name T540
Test name
Test status
Simulation time 26095189 ps
CPU time 0.74 seconds
Started Jul 31 05:54:39 PM PDT 24
Finished Jul 31 05:54:40 PM PDT 24
Peak memory 201032 kb
Host smart-6578c354-b1ac-4436-b516-0e092f89f6d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233917862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.233917862
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1394988824
Short name T288
Test name
Test status
Simulation time 74324297 ps
CPU time 1.05 seconds
Started Jul 31 05:55:22 PM PDT 24
Finished Jul 31 05:55:23 PM PDT 24
Peak memory 201072 kb
Host smart-020b16b2-de29-4410-ae13-347298bd3c02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394988824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1394988824
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.2476638657
Short name T527
Test name
Test status
Simulation time 31658512 ps
CPU time 1 seconds
Started Jul 31 05:55:13 PM PDT 24
Finished Jul 31 05:55:14 PM PDT 24
Peak memory 201108 kb
Host smart-935355ed-c605-4a82-8a5c-7383bd6ccd4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476638657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.2476638657
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.1968396130
Short name T285
Test name
Test status
Simulation time 52412033 ps
CPU time 0.93 seconds
Started Jul 31 05:55:13 PM PDT 24
Finished Jul 31 05:55:14 PM PDT 24
Peak memory 201060 kb
Host smart-b31e5565-d37f-4f27-8478-dc95bf8a5239
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968396130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.1968396130
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.1636372796
Short name T625
Test name
Test status
Simulation time 22528257 ps
CPU time 0.77 seconds
Started Jul 31 05:54:52 PM PDT 24
Finished Jul 31 05:54:53 PM PDT 24
Peak memory 201056 kb
Host smart-0572a81f-5b87-4e58-8c13-bd924a3e413c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636372796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1636372796
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.327223293
Short name T648
Test name
Test status
Simulation time 1398496556 ps
CPU time 10.79 seconds
Started Jul 31 05:54:57 PM PDT 24
Finished Jul 31 05:55:08 PM PDT 24
Peak memory 201148 kb
Host smart-86115f20-689b-4d64-9c14-fd4fce0f6504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327223293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.327223293
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.2071562198
Short name T301
Test name
Test status
Simulation time 909389953 ps
CPU time 4 seconds
Started Jul 31 05:54:58 PM PDT 24
Finished Jul 31 05:55:02 PM PDT 24
Peak memory 201160 kb
Host smart-48ddc7f1-bf71-4340-b19a-51adaee0e655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071562198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.2071562198
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3342780205
Short name T785
Test name
Test status
Simulation time 22404533 ps
CPU time 0.79 seconds
Started Jul 31 05:55:08 PM PDT 24
Finished Jul 31 05:55:09 PM PDT 24
Peak memory 201080 kb
Host smart-4053192b-11d9-4325-8c3f-b8e33d52dd3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342780205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.3342780205
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.911713494
Short name T791
Test name
Test status
Simulation time 81578191 ps
CPU time 1 seconds
Started Jul 31 05:55:08 PM PDT 24
Finished Jul 31 05:55:09 PM PDT 24
Peak memory 201108 kb
Host smart-eff58362-8e31-4919-919e-26f3cd2c9df0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911713494 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_clk_byp_req_intersig_mubi.911713494
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1828165416
Short name T17
Test name
Test status
Simulation time 20182977 ps
CPU time 0.75 seconds
Started Jul 31 05:55:03 PM PDT 24
Finished Jul 31 05:55:04 PM PDT 24
Peak memory 201036 kb
Host smart-b8ce73a1-6f8f-4d90-bbad-3aae9732dacb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828165416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.1828165416
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2796593750
Short name T633
Test name
Test status
Simulation time 28325926 ps
CPU time 0.76 seconds
Started Jul 31 05:54:59 PM PDT 24
Finished Jul 31 05:54:59 PM PDT 24
Peak memory 201020 kb
Host smart-41a509ad-e8e5-4527-a973-352fef6711d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796593750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2796593750
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.885946551
Short name T493
Test name
Test status
Simulation time 477155250 ps
CPU time 2.26 seconds
Started Jul 31 05:55:13 PM PDT 24
Finished Jul 31 05:55:15 PM PDT 24
Peak memory 201036 kb
Host smart-610d055b-a11d-4894-8dad-3c451a94a858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885946551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.885946551
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.4247150006
Short name T46
Test name
Test status
Simulation time 600944569 ps
CPU time 3.9 seconds
Started Jul 31 05:55:12 PM PDT 24
Finished Jul 31 05:55:16 PM PDT 24
Peak memory 217972 kb
Host smart-227004f8-a734-43c2-b991-000df22eaf7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247150006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.4247150006
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.400218079
Short name T346
Test name
Test status
Simulation time 75411288 ps
CPU time 1.01 seconds
Started Jul 31 05:54:54 PM PDT 24
Finished Jul 31 05:54:55 PM PDT 24
Peak memory 201096 kb
Host smart-233aae66-9120-4493-84eb-18f4116c8be6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400218079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.400218079
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3629912351
Short name T729
Test name
Test status
Simulation time 5211956848 ps
CPU time 39.83 seconds
Started Jul 31 05:55:13 PM PDT 24
Finished Jul 31 05:55:53 PM PDT 24
Peak memory 201456 kb
Host smart-ac9e6f03-d1b4-4ab9-981a-66a518579acc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629912351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3629912351
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.1102568384
Short name T16
Test name
Test status
Simulation time 25180122 ps
CPU time 0.91 seconds
Started Jul 31 05:55:00 PM PDT 24
Finished Jul 31 05:55:01 PM PDT 24
Peak memory 201088 kb
Host smart-15896fec-4ecf-4da5-96cb-f780d829851d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102568384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1102568384
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2636965986
Short name T761
Test name
Test status
Simulation time 37482031 ps
CPU time 0.96 seconds
Started Jul 31 05:58:32 PM PDT 24
Finished Jul 31 05:58:33 PM PDT 24
Peak memory 201032 kb
Host smart-ba1598cf-66d3-455f-8a1e-44af089eb6cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636965986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.2636965986
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2374460230
Short name T460
Test name
Test status
Simulation time 29522107 ps
CPU time 0.77 seconds
Started Jul 31 05:58:27 PM PDT 24
Finished Jul 31 05:58:28 PM PDT 24
Peak memory 200224 kb
Host smart-a7dd9140-a3c7-4de7-9062-a2d0912b358e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374460230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2374460230
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.2332357235
Short name T499
Test name
Test status
Simulation time 24289157 ps
CPU time 0.84 seconds
Started Jul 31 05:58:37 PM PDT 24
Finished Jul 31 05:58:38 PM PDT 24
Peak memory 201092 kb
Host smart-2499d7e1-dc7c-42db-81c8-715733dcc598
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332357235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.2332357235
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.519822805
Short name T259
Test name
Test status
Simulation time 23009078 ps
CPU time 0.89 seconds
Started Jul 31 05:58:23 PM PDT 24
Finished Jul 31 05:58:24 PM PDT 24
Peak memory 201104 kb
Host smart-34b9ec2c-5cbb-4ed6-8ba4-561ae6256846
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519822805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.519822805
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3105991077
Short name T694
Test name
Test status
Simulation time 2248753795 ps
CPU time 13.37 seconds
Started Jul 31 05:58:29 PM PDT 24
Finished Jul 31 05:58:42 PM PDT 24
Peak memory 201408 kb
Host smart-53ef04fb-64fc-448d-9f9f-c8439bca619e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105991077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3105991077
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3868332942
Short name T673
Test name
Test status
Simulation time 1103786378 ps
CPU time 6.09 seconds
Started Jul 31 05:58:26 PM PDT 24
Finished Jul 31 05:58:33 PM PDT 24
Peak memory 201164 kb
Host smart-68350255-6686-45ca-89f8-d6612da06856
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868332942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3868332942
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3346400881
Short name T568
Test name
Test status
Simulation time 492220780 ps
CPU time 2.34 seconds
Started Jul 31 05:58:31 PM PDT 24
Finished Jul 31 05:58:34 PM PDT 24
Peak memory 200980 kb
Host smart-f1fe3595-abdd-4d17-8a03-8997a3587a00
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346400881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.3346400881
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.3359140714
Short name T401
Test name
Test status
Simulation time 31171097 ps
CPU time 0.82 seconds
Started Jul 31 05:58:31 PM PDT 24
Finished Jul 31 05:58:32 PM PDT 24
Peak memory 201016 kb
Host smart-35669688-accd-492d-b95d-5fa546c38ce4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359140714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.3359140714
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.3334309233
Short name T509
Test name
Test status
Simulation time 62071346 ps
CPU time 0.97 seconds
Started Jul 31 05:58:32 PM PDT 24
Finished Jul 31 05:58:34 PM PDT 24
Peak memory 201084 kb
Host smart-081952aa-0cea-4781-82f6-096ce3d3569b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334309233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.3334309233
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.137755163
Short name T213
Test name
Test status
Simulation time 17505217 ps
CPU time 0.8 seconds
Started Jul 31 05:58:27 PM PDT 24
Finished Jul 31 05:58:28 PM PDT 24
Peak memory 201000 kb
Host smart-e81710fd-19fe-4105-97d9-5e4a780b2567
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137755163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.137755163
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.4007426117
Short name T588
Test name
Test status
Simulation time 1217521254 ps
CPU time 4.09 seconds
Started Jul 31 05:58:32 PM PDT 24
Finished Jul 31 05:58:37 PM PDT 24
Peak memory 201232 kb
Host smart-bfc269bf-e79e-467e-b7f1-87ea916695c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007426117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.4007426117
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.1724006737
Short name T455
Test name
Test status
Simulation time 73821553 ps
CPU time 1.06 seconds
Started Jul 31 05:58:21 PM PDT 24
Finished Jul 31 05:58:22 PM PDT 24
Peak memory 201004 kb
Host smart-15accc33-9519-4db8-a8f2-b01bd53eb88d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724006737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1724006737
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.558297499
Short name T652
Test name
Test status
Simulation time 7730995186 ps
CPU time 36.2 seconds
Started Jul 31 05:58:43 PM PDT 24
Finished Jul 31 05:59:19 PM PDT 24
Peak memory 201376 kb
Host smart-b13c9fff-bdf4-4591-a9d0-fe1866a41787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558297499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.558297499
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.1762352801
Short name T786
Test name
Test status
Simulation time 67852109 ps
CPU time 1.1 seconds
Started Jul 31 05:58:27 PM PDT 24
Finished Jul 31 05:58:28 PM PDT 24
Peak memory 201072 kb
Host smart-7f89c592-9c96-4182-b1be-40ba94e19178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762352801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1762352801
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3608903721
Short name T292
Test name
Test status
Simulation time 14036025 ps
CPU time 0.76 seconds
Started Jul 31 05:59:04 PM PDT 24
Finished Jul 31 05:59:04 PM PDT 24
Peak memory 201056 kb
Host smart-45934cf3-445d-428b-bbd6-a4ae5e314876
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608903721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3608903721
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1438190422
Short name T479
Test name
Test status
Simulation time 24933945 ps
CPU time 0.93 seconds
Started Jul 31 05:58:58 PM PDT 24
Finished Jul 31 05:58:59 PM PDT 24
Peak memory 200972 kb
Host smart-3825e9b6-b119-4ee1-9d68-5321aa31b208
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438190422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1438190422
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.3770607364
Short name T54
Test name
Test status
Simulation time 27549240 ps
CPU time 0.88 seconds
Started Jul 31 05:58:57 PM PDT 24
Finished Jul 31 05:58:58 PM PDT 24
Peak memory 201096 kb
Host smart-9c064bc0-dc10-46c2-adee-434882643849
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770607364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.3770607364
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2170556171
Short name T701
Test name
Test status
Simulation time 28375742 ps
CPU time 0.8 seconds
Started Jul 31 05:58:42 PM PDT 24
Finished Jul 31 05:58:42 PM PDT 24
Peak memory 201060 kb
Host smart-3df507c9-7250-478d-b1ab-96c9596e4755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170556171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2170556171
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.958892849
Short name T627
Test name
Test status
Simulation time 1410719100 ps
CPU time 7.94 seconds
Started Jul 31 05:58:44 PM PDT 24
Finished Jul 31 05:58:52 PM PDT 24
Peak memory 201132 kb
Host smart-39d8ba6b-56bb-4568-980c-8beb77a15198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958892849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.958892849
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.1016770478
Short name T811
Test name
Test status
Simulation time 269364676 ps
CPU time 1.99 seconds
Started Jul 31 05:58:44 PM PDT 24
Finished Jul 31 05:58:47 PM PDT 24
Peak memory 201168 kb
Host smart-206cdd4b-b15d-4f40-8adb-c58d93f7dc1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016770478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.1016770478
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2593319213
Short name T175
Test name
Test status
Simulation time 32188739 ps
CPU time 0.82 seconds
Started Jul 31 05:58:51 PM PDT 24
Finished Jul 31 05:58:52 PM PDT 24
Peak memory 201000 kb
Host smart-87fe1073-e3b2-437d-ae31-7d4fa5651277
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593319213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2593319213
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.786660621
Short name T396
Test name
Test status
Simulation time 22192663 ps
CPU time 0.88 seconds
Started Jul 31 05:58:56 PM PDT 24
Finished Jul 31 05:58:57 PM PDT 24
Peak memory 201064 kb
Host smart-a429bd03-031b-4b0f-924d-97789e92b2b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786660621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.clkmgr_lc_clk_byp_req_intersig_mubi.786660621
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.559345207
Short name T403
Test name
Test status
Simulation time 15053800 ps
CPU time 0.76 seconds
Started Jul 31 05:58:56 PM PDT 24
Finished Jul 31 05:58:56 PM PDT 24
Peak memory 201020 kb
Host smart-83579586-ff9d-41cb-b7d7-6e46b2eb93e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559345207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 11.clkmgr_lc_ctrl_intersig_mubi.559345207
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.1858570817
Short name T719
Test name
Test status
Simulation time 13843384 ps
CPU time 0.7 seconds
Started Jul 31 05:58:47 PM PDT 24
Finished Jul 31 05:58:47 PM PDT 24
Peak memory 201056 kb
Host smart-db397ddb-b2fa-4067-bfce-011f282dc056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858570817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1858570817
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.3369235753
Short name T684
Test name
Test status
Simulation time 688186872 ps
CPU time 3.93 seconds
Started Jul 31 05:59:03 PM PDT 24
Finished Jul 31 05:59:07 PM PDT 24
Peak memory 201248 kb
Host smart-a25bb875-2862-44d7-99d7-adf3d59acdb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369235753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3369235753
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.641183937
Short name T294
Test name
Test status
Simulation time 29779517 ps
CPU time 0.88 seconds
Started Jul 31 05:58:43 PM PDT 24
Finished Jul 31 05:58:44 PM PDT 24
Peak memory 200984 kb
Host smart-bdac470c-d7b9-427d-b92e-fed780406caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641183937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.641183937
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.1227301407
Short name T724
Test name
Test status
Simulation time 6533803384 ps
CPU time 34.49 seconds
Started Jul 31 05:59:01 PM PDT 24
Finished Jul 31 05:59:36 PM PDT 24
Peak memory 201368 kb
Host smart-f0224b02-c16e-44aa-bfe3-2be0ac9246c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227301407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.1227301407
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3773312029
Short name T500
Test name
Test status
Simulation time 38117317 ps
CPU time 0.85 seconds
Started Jul 31 05:58:46 PM PDT 24
Finished Jul 31 05:58:47 PM PDT 24
Peak memory 201048 kb
Host smart-22571934-a150-40a3-ba09-d167a6a80b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773312029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3773312029
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.1286570659
Short name T574
Test name
Test status
Simulation time 15643102 ps
CPU time 0.75 seconds
Started Jul 31 05:59:25 PM PDT 24
Finished Jul 31 05:59:26 PM PDT 24
Peak memory 201112 kb
Host smart-75f51d88-0746-4038-a661-8ff3da250912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286570659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.1286570659
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.3145671190
Short name T475
Test name
Test status
Simulation time 16579642 ps
CPU time 0.75 seconds
Started Jul 31 05:59:10 PM PDT 24
Finished Jul 31 05:59:11 PM PDT 24
Peak memory 200292 kb
Host smart-64d3cc5a-98b2-4025-8e3f-31b3ef77b199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145671190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3145671190
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.5552744
Short name T682
Test name
Test status
Simulation time 88111892 ps
CPU time 1.13 seconds
Started Jul 31 05:59:16 PM PDT 24
Finished Jul 31 05:59:17 PM PDT 24
Peak memory 201092 kb
Host smart-d505defa-ef0e-4840-9619-3373fc0c6d15
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5552744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
clkmgr_div_intersig_mubi.5552744
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.2603531493
Short name T184
Test name
Test status
Simulation time 26356329 ps
CPU time 0.93 seconds
Started Jul 31 05:59:08 PM PDT 24
Finished Jul 31 05:59:09 PM PDT 24
Peak memory 200952 kb
Host smart-dd24f609-dca0-40ed-b72b-8afd2440f762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603531493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2603531493
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.886409882
Short name T537
Test name
Test status
Simulation time 199250424 ps
CPU time 2.26 seconds
Started Jul 31 05:59:10 PM PDT 24
Finished Jul 31 05:59:13 PM PDT 24
Peak memory 201112 kb
Host smart-6aac3668-bfff-4d7a-ad83-4800d5ff1159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886409882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.886409882
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2177815158
Short name T252
Test name
Test status
Simulation time 634981010 ps
CPU time 2.98 seconds
Started Jul 31 05:59:08 PM PDT 24
Finished Jul 31 05:59:11 PM PDT 24
Peak memory 201168 kb
Host smart-d0298713-cf27-4bf5-bdcc-97b9b019823d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177815158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2177815158
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.2816893462
Short name T573
Test name
Test status
Simulation time 99403734 ps
CPU time 1.21 seconds
Started Jul 31 05:59:14 PM PDT 24
Finished Jul 31 05:59:15 PM PDT 24
Peak memory 201064 kb
Host smart-8f424384-e70a-4228-aaa3-4f90783bb72a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816893462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.2816893462
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.348502529
Short name T260
Test name
Test status
Simulation time 97999816 ps
CPU time 1.14 seconds
Started Jul 31 05:59:17 PM PDT 24
Finished Jul 31 05:59:18 PM PDT 24
Peak memory 201048 kb
Host smart-1528d19a-38e5-4ff1-9060-8d5b8722a930
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348502529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.348502529
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.948824821
Short name T297
Test name
Test status
Simulation time 41113505 ps
CPU time 0.88 seconds
Started Jul 31 05:59:14 PM PDT 24
Finished Jul 31 05:59:15 PM PDT 24
Peak memory 201108 kb
Host smart-0d58b853-d9a4-4203-873a-e505f5b92143
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948824821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_ctrl_intersig_mubi.948824821
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.2095981593
Short name T623
Test name
Test status
Simulation time 15937765 ps
CPU time 0.78 seconds
Started Jul 31 05:59:10 PM PDT 24
Finished Jul 31 05:59:11 PM PDT 24
Peak memory 201036 kb
Host smart-31d7c029-b8f3-4d04-96f0-8f0e3abd3a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095981593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.2095981593
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.2333461320
Short name T752
Test name
Test status
Simulation time 669460448 ps
CPU time 2.62 seconds
Started Jul 31 05:59:26 PM PDT 24
Finished Jul 31 05:59:29 PM PDT 24
Peak memory 201256 kb
Host smart-136068ec-cebd-4340-9cbf-28b636b4544f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333461320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2333461320
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.3469168275
Short name T740
Test name
Test status
Simulation time 54955400 ps
CPU time 0.98 seconds
Started Jul 31 05:59:09 PM PDT 24
Finished Jul 31 05:59:10 PM PDT 24
Peak memory 201028 kb
Host smart-a9663f44-86c2-4319-98b3-627fd77999f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469168275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.3469168275
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_trans.3300912167
Short name T718
Test name
Test status
Simulation time 34420292 ps
CPU time 1.09 seconds
Started Jul 31 05:59:08 PM PDT 24
Finished Jul 31 05:59:09 PM PDT 24
Peak memory 201028 kb
Host smart-048663df-ae4e-4ee6-bac6-d973bd92b615
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300912167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.3300912167
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.61808454
Short name T778
Test name
Test status
Simulation time 322041483 ps
CPU time 1.72 seconds
Started Jul 31 05:59:53 PM PDT 24
Finished Jul 31 05:59:55 PM PDT 24
Peak memory 201028 kb
Host smart-f6231c7c-b04c-4627-92ed-f1354280a4ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61808454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmg
r_alert_test.61808454
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1695888394
Short name T481
Test name
Test status
Simulation time 75538280 ps
CPU time 1.01 seconds
Started Jul 31 05:59:53 PM PDT 24
Finished Jul 31 05:59:55 PM PDT 24
Peak memory 201096 kb
Host smart-b2b353d4-3ccc-422f-9833-ed796ddba350
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695888394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1695888394
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.1431327305
Short name T392
Test name
Test status
Simulation time 41792581 ps
CPU time 0.78 seconds
Started Jul 31 05:59:41 PM PDT 24
Finished Jul 31 05:59:42 PM PDT 24
Peak memory 200164 kb
Host smart-74e31bf4-783b-429d-b72c-4a4c3d677ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431327305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1431327305
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2938030354
Short name T358
Test name
Test status
Simulation time 48692246 ps
CPU time 0.88 seconds
Started Jul 31 05:59:55 PM PDT 24
Finished Jul 31 05:59:56 PM PDT 24
Peak memory 201040 kb
Host smart-ed1f55fa-ff6f-42db-9e77-0cc756d973b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938030354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2938030354
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.548714712
Short name T549
Test name
Test status
Simulation time 31316124 ps
CPU time 0.79 seconds
Started Jul 31 05:59:30 PM PDT 24
Finished Jul 31 05:59:30 PM PDT 24
Peak memory 201052 kb
Host smart-69e61897-184e-410d-976d-7c3da55ba95a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548714712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.548714712
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.4284445090
Short name T788
Test name
Test status
Simulation time 1300948524 ps
CPU time 6.2 seconds
Started Jul 31 05:59:32 PM PDT 24
Finished Jul 31 05:59:38 PM PDT 24
Peak memory 201136 kb
Host smart-b4c5f2e6-3e7d-4530-ade0-b813d73ddef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284445090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4284445090
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.433328663
Short name T4
Test name
Test status
Simulation time 1454469105 ps
CPU time 9.95 seconds
Started Jul 31 05:59:31 PM PDT 24
Finished Jul 31 05:59:41 PM PDT 24
Peak memory 201216 kb
Host smart-1ad46892-87ef-4588-9c00-0d36e54611d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433328663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_ti
meout.433328663
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1289123981
Short name T382
Test name
Test status
Simulation time 12569111 ps
CPU time 0.72 seconds
Started Jul 31 05:59:54 PM PDT 24
Finished Jul 31 05:59:55 PM PDT 24
Peak memory 201060 kb
Host smart-d7eaea18-56e0-44cb-82a9-f68fa2af89ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289123981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1289123981
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.2827617011
Short name T314
Test name
Test status
Simulation time 20777126 ps
CPU time 0.81 seconds
Started Jul 31 05:59:46 PM PDT 24
Finished Jul 31 05:59:47 PM PDT 24
Peak memory 201056 kb
Host smart-27c6a733-813a-4679-9b3f-ecb0f5014d4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827617011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.2827617011
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.557717159
Short name T233
Test name
Test status
Simulation time 24338656 ps
CPU time 0.81 seconds
Started Jul 31 05:59:35 PM PDT 24
Finished Jul 31 05:59:36 PM PDT 24
Peak memory 201100 kb
Host smart-050dbb31-a90d-45c5-bdc7-ab56e3160691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557717159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.557717159
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3588700548
Short name T203
Test name
Test status
Simulation time 1487740130 ps
CPU time 5.62 seconds
Started Jul 31 05:59:52 PM PDT 24
Finished Jul 31 05:59:58 PM PDT 24
Peak memory 201280 kb
Host smart-09a7cd05-60ab-4412-a90c-0d6800b1670b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588700548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3588700548
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2177755018
Short name T582
Test name
Test status
Simulation time 227652414 ps
CPU time 1.43 seconds
Started Jul 31 05:59:30 PM PDT 24
Finished Jul 31 05:59:31 PM PDT 24
Peak memory 201004 kb
Host smart-1a72a8b0-b063-438e-afdf-3ba08dc7d1fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177755018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2177755018
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.3984869557
Short name T429
Test name
Test status
Simulation time 8956937522 ps
CPU time 68.68 seconds
Started Jul 31 05:59:52 PM PDT 24
Finished Jul 31 06:01:01 PM PDT 24
Peak memory 201412 kb
Host smart-21c85b1a-5597-417d-b4bb-9814d7822bde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984869557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.3984869557
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.1094154056
Short name T656
Test name
Test status
Simulation time 67956492 ps
CPU time 0.96 seconds
Started Jul 31 05:59:35 PM PDT 24
Finished Jul 31 05:59:36 PM PDT 24
Peak memory 201000 kb
Host smart-2f9eea94-f9bf-407a-bced-d1ed53b05a45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094154056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1094154056
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.3324830600
Short name T92
Test name
Test status
Simulation time 79476631 ps
CPU time 0.93 seconds
Started Jul 31 06:00:19 PM PDT 24
Finished Jul 31 06:00:20 PM PDT 24
Peak memory 201048 kb
Host smart-cd5fb5b6-fbe7-4035-9719-ab03e33b39bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324830600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.3324830600
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.4233560149
Short name T653
Test name
Test status
Simulation time 38964115 ps
CPU time 0.79 seconds
Started Jul 31 06:00:08 PM PDT 24
Finished Jul 31 06:00:08 PM PDT 24
Peak memory 201084 kb
Host smart-1ed0027f-a959-432a-9243-af968440013b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233560149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.4233560149
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.2058205150
Short name T731
Test name
Test status
Simulation time 16781626 ps
CPU time 0.74 seconds
Started Jul 31 06:00:00 PM PDT 24
Finished Jul 31 06:00:01 PM PDT 24
Peak memory 200240 kb
Host smart-7a0d8782-a492-4390-9b37-cfef14ae6c27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058205150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2058205150
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.1781980452
Short name T698
Test name
Test status
Simulation time 20731215 ps
CPU time 0.83 seconds
Started Jul 31 06:00:08 PM PDT 24
Finished Jul 31 06:00:09 PM PDT 24
Peak memory 201028 kb
Host smart-f66a0404-9fa2-4fb2-894f-1a699710c4b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781980452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.1781980452
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.2076627553
Short name T359
Test name
Test status
Simulation time 33353355 ps
CPU time 0.85 seconds
Started Jul 31 05:59:53 PM PDT 24
Finished Jul 31 05:59:54 PM PDT 24
Peak memory 201008 kb
Host smart-6fcfcf7f-e5d5-4e8a-81f6-86b391972474
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076627553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.2076627553
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.3578954298
Short name T632
Test name
Test status
Simulation time 1056255834 ps
CPU time 5.35 seconds
Started Jul 31 05:59:54 PM PDT 24
Finished Jul 31 05:59:59 PM PDT 24
Peak memory 201156 kb
Host smart-7b8e45ee-b4bd-4e85-b1bb-1ccac2d53918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578954298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.3578954298
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.3044890288
Short name T599
Test name
Test status
Simulation time 860280702 ps
CPU time 5.13 seconds
Started Jul 31 06:00:01 PM PDT 24
Finished Jul 31 06:00:06 PM PDT 24
Peak memory 201076 kb
Host smart-84091cac-0bbf-4dff-8dc8-60aef79ffaa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044890288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.3044890288
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.645942934
Short name T212
Test name
Test status
Simulation time 61018375 ps
CPU time 1.14 seconds
Started Jul 31 06:00:00 PM PDT 24
Finished Jul 31 06:00:01 PM PDT 24
Peak memory 201020 kb
Host smart-421ca3aa-095e-4569-ba28-8b79a8b1eb94
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645942934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_idle_intersig_mubi.645942934
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.4028126908
Short name T75
Test name
Test status
Simulation time 11617115 ps
CPU time 0.71 seconds
Started Jul 31 06:00:06 PM PDT 24
Finished Jul 31 06:00:07 PM PDT 24
Peak memory 201096 kb
Host smart-ed8bdeff-dad0-4318-8d51-35f48a83f344
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028126908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.4028126908
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.137940956
Short name T290
Test name
Test status
Simulation time 64828496 ps
CPU time 0.94 seconds
Started Jul 31 06:00:08 PM PDT 24
Finished Jul 31 06:00:09 PM PDT 24
Peak memory 201064 kb
Host smart-74807397-578a-47c7-90a9-6005f30afd7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137940956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.137940956
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.2389448812
Short name T269
Test name
Test status
Simulation time 16395141 ps
CPU time 0.77 seconds
Started Jul 31 06:00:03 PM PDT 24
Finished Jul 31 06:00:07 PM PDT 24
Peak memory 201020 kb
Host smart-a5303f4e-a498-4d47-ba71-f3151ff5466f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389448812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2389448812
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3764252619
Short name T162
Test name
Test status
Simulation time 1415161213 ps
CPU time 5.42 seconds
Started Jul 31 06:00:12 PM PDT 24
Finished Jul 31 06:00:18 PM PDT 24
Peak memory 201312 kb
Host smart-e7e1d95d-3e87-41b9-bed7-0dab55507feb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764252619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3764252619
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1957148526
Short name T709
Test name
Test status
Simulation time 132674930 ps
CPU time 1.16 seconds
Started Jul 31 05:59:54 PM PDT 24
Finished Jul 31 05:59:55 PM PDT 24
Peak memory 201012 kb
Host smart-ac6f2b2a-9407-4037-b055-c4c422485f8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957148526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1957148526
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.767036406
Short name T596
Test name
Test status
Simulation time 8370008936 ps
CPU time 63.51 seconds
Started Jul 31 06:00:16 PM PDT 24
Finished Jul 31 06:01:19 PM PDT 24
Peak memory 201424 kb
Host smart-cb957eb0-2a68-433d-8322-e6a51d9f6314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767036406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.767036406
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.1850472118
Short name T68
Test name
Test status
Simulation time 46363236897 ps
CPU time 680.16 seconds
Started Jul 31 06:00:16 PM PDT 24
Finished Jul 31 06:11:36 PM PDT 24
Peak memory 217840 kb
Host smart-b6a6f514-a467-4877-bb11-93028e358218
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1850472118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1850472118
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.66133046
Short name T242
Test name
Test status
Simulation time 36656744 ps
CPU time 0.91 seconds
Started Jul 31 06:00:00 PM PDT 24
Finished Jul 31 06:00:01 PM PDT 24
Peak memory 201044 kb
Host smart-86464061-b865-4cbb-849f-2d06441e3221
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66133046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.66133046
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.3176966292
Short name T776
Test name
Test status
Simulation time 20539376 ps
CPU time 0.78 seconds
Started Jul 31 06:00:47 PM PDT 24
Finished Jul 31 06:00:48 PM PDT 24
Peak memory 201068 kb
Host smart-16a80a68-edcc-494b-a79a-7e3d5a6daab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176966292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.3176966292
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3452787994
Short name T630
Test name
Test status
Simulation time 18124079 ps
CPU time 0.77 seconds
Started Jul 31 06:00:39 PM PDT 24
Finished Jul 31 06:00:40 PM PDT 24
Peak memory 201076 kb
Host smart-cf7e921a-f1d1-43c9-a567-524a100000f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452787994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.3452787994
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.2109082727
Short name T232
Test name
Test status
Simulation time 14134895 ps
CPU time 0.73 seconds
Started Jul 31 06:00:32 PM PDT 24
Finished Jul 31 06:00:33 PM PDT 24
Peak memory 200272 kb
Host smart-f6f07e87-7b9d-4b0d-a284-928336a03c50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109082727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2109082727
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3462169325
Short name T705
Test name
Test status
Simulation time 63488910 ps
CPU time 0.97 seconds
Started Jul 31 06:00:43 PM PDT 24
Finished Jul 31 06:00:44 PM PDT 24
Peak memory 201020 kb
Host smart-263992e2-93de-433f-8456-947086e0dcfd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462169325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.3462169325
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.3374402395
Short name T404
Test name
Test status
Simulation time 27051381 ps
CPU time 0.94 seconds
Started Jul 31 06:00:21 PM PDT 24
Finished Jul 31 06:00:22 PM PDT 24
Peak memory 201024 kb
Host smart-c8f72960-466d-42f5-866c-3e6c16571d8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374402395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3374402395
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.4115995484
Short name T11
Test name
Test status
Simulation time 563396734 ps
CPU time 5.05 seconds
Started Jul 31 06:00:25 PM PDT 24
Finished Jul 31 06:00:30 PM PDT 24
Peak memory 201136 kb
Host smart-54805acc-0b14-4504-81a5-9a6e5e49b3b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115995484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.4115995484
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.2696687996
Short name T33
Test name
Test status
Simulation time 2289967470 ps
CPU time 10.13 seconds
Started Jul 31 06:00:33 PM PDT 24
Finished Jul 31 06:00:43 PM PDT 24
Peak memory 201388 kb
Host smart-f1196ad5-cf93-4b91-bec7-750948946d25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696687996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.2696687996
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1864368188
Short name T215
Test name
Test status
Simulation time 35183282 ps
CPU time 0.79 seconds
Started Jul 31 06:00:36 PM PDT 24
Finished Jul 31 06:00:37 PM PDT 24
Peak memory 201076 kb
Host smart-cf61fbd5-dab0-4bad-ad2e-c730af161d5a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864368188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1864368188
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3947202173
Short name T763
Test name
Test status
Simulation time 20561669 ps
CPU time 0.8 seconds
Started Jul 31 06:00:38 PM PDT 24
Finished Jul 31 06:00:38 PM PDT 24
Peak memory 201084 kb
Host smart-4c98db6b-0617-4fe9-b01a-8495d83cf05b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947202173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3947202173
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1463861975
Short name T655
Test name
Test status
Simulation time 13963747 ps
CPU time 0.75 seconds
Started Jul 31 06:00:36 PM PDT 24
Finished Jul 31 06:00:37 PM PDT 24
Peak memory 201048 kb
Host smart-e5d83fad-128e-4638-932b-a093c9382582
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463861975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1463861975
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.1800459941
Short name T606
Test name
Test status
Simulation time 36961193 ps
CPU time 0.81 seconds
Started Jul 31 06:00:31 PM PDT 24
Finished Jul 31 06:00:32 PM PDT 24
Peak memory 201036 kb
Host smart-72f3b535-79ed-4c86-811d-b78e6ef4a752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800459941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1800459941
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.4005228957
Short name T216
Test name
Test status
Simulation time 99594370 ps
CPU time 1.07 seconds
Started Jul 31 06:00:24 PM PDT 24
Finished Jul 31 06:00:25 PM PDT 24
Peak memory 200956 kb
Host smart-8d928eff-e5d2-4fea-9c03-bf6a432a7c17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005228957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.4005228957
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.929960915
Short name T580
Test name
Test status
Simulation time 8336517617 ps
CPU time 36.25 seconds
Started Jul 31 06:00:48 PM PDT 24
Finished Jul 31 06:01:24 PM PDT 24
Peak memory 201424 kb
Host smart-b9327a93-759d-422b-9ab1-ed214f7ccb83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929960915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.929960915
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.233666243
Short name T70
Test name
Test status
Simulation time 14239941310 ps
CPU time 202.19 seconds
Started Jul 31 06:00:48 PM PDT 24
Finished Jul 31 06:04:10 PM PDT 24
Peak memory 209736 kb
Host smart-3ca33755-553d-43c4-8256-9da22b362bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=233666243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.233666243
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.1895685919
Short name T78
Test name
Test status
Simulation time 16388822 ps
CPU time 0.76 seconds
Started Jul 31 06:00:27 PM PDT 24
Finished Jul 31 06:00:27 PM PDT 24
Peak memory 201044 kb
Host smart-332c6aad-267b-40ab-84d2-d0e81e1b9351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895685919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1895685919
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.1914351287
Short name T39
Test name
Test status
Simulation time 89609401 ps
CPU time 1.04 seconds
Started Jul 31 06:01:04 PM PDT 24
Finished Jul 31 06:01:05 PM PDT 24
Peak memory 201084 kb
Host smart-aa309ef3-46f9-4f30-9453-211459a7dde9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914351287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.1914351287
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3270382275
Short name T416
Test name
Test status
Simulation time 24579170 ps
CPU time 0.89 seconds
Started Jul 31 06:00:56 PM PDT 24
Finished Jul 31 06:00:57 PM PDT 24
Peak memory 201104 kb
Host smart-a3732625-fa18-48e1-b0a9-3657dcdc6efc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270382275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3270382275
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.1233375738
Short name T176
Test name
Test status
Simulation time 51343467 ps
CPU time 0.83 seconds
Started Jul 31 06:00:52 PM PDT 24
Finished Jul 31 06:00:53 PM PDT 24
Peak memory 200348 kb
Host smart-b7354f93-98c3-4747-a11c-92fa47a89ee7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233375738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.1233375738
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.165449142
Short name T266
Test name
Test status
Simulation time 59686051 ps
CPU time 0.96 seconds
Started Jul 31 06:00:58 PM PDT 24
Finished Jul 31 06:00:59 PM PDT 24
Peak memory 201108 kb
Host smart-32dc16db-3594-4137-8b5c-06ba344a5e75
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165449142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.clkmgr_div_intersig_mubi.165449142
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.1504847362
Short name T807
Test name
Test status
Simulation time 23306731 ps
CPU time 0.88 seconds
Started Jul 31 06:00:52 PM PDT 24
Finished Jul 31 06:00:53 PM PDT 24
Peak memory 201024 kb
Host smart-f0cc3a83-7961-4912-b7ac-5e372659409e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504847362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.1504847362
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.1044742360
Short name T375
Test name
Test status
Simulation time 1277988603 ps
CPU time 10.41 seconds
Started Jul 31 06:00:58 PM PDT 24
Finished Jul 31 06:01:09 PM PDT 24
Peak memory 201156 kb
Host smart-abb9538d-a220-43db-971e-3fd42a79dd43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044742360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1044742360
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2594984775
Short name T194
Test name
Test status
Simulation time 621131825 ps
CPU time 4.86 seconds
Started Jul 31 06:00:53 PM PDT 24
Finished Jul 31 06:00:58 PM PDT 24
Peak memory 201152 kb
Host smart-fd0ad7fa-9168-4c22-9916-1cbfd74952b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594984775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2594984775
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.1681455417
Short name T746
Test name
Test status
Simulation time 24573203 ps
CPU time 0.79 seconds
Started Jul 31 06:00:54 PM PDT 24
Finished Jul 31 06:00:55 PM PDT 24
Peak memory 201052 kb
Host smart-ba9a6b3e-fad7-4bed-bfbd-ce1a637d1afc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681455417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.1681455417
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.3008824843
Short name T450
Test name
Test status
Simulation time 22058837 ps
CPU time 0.88 seconds
Started Jul 31 06:00:57 PM PDT 24
Finished Jul 31 06:00:58 PM PDT 24
Peak memory 201100 kb
Host smart-39b89627-1b0f-43f8-92cd-41b5d490fee8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008824843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.3008824843
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3901431902
Short name T794
Test name
Test status
Simulation time 14789889 ps
CPU time 0.75 seconds
Started Jul 31 06:00:59 PM PDT 24
Finished Jul 31 06:00:59 PM PDT 24
Peak memory 201080 kb
Host smart-90294b07-878f-4e40-b6a4-55292f38fd54
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901431902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3901431902
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.2435096428
Short name T330
Test name
Test status
Simulation time 177185528 ps
CPU time 1.24 seconds
Started Jul 31 06:00:54 PM PDT 24
Finished Jul 31 06:00:55 PM PDT 24
Peak memory 201056 kb
Host smart-252907fe-051c-4fe3-b20b-2df7c0a47838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435096428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2435096428
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.1977775727
Short name T160
Test name
Test status
Simulation time 1815781280 ps
CPU time 6.22 seconds
Started Jul 31 06:00:56 PM PDT 24
Finished Jul 31 06:01:02 PM PDT 24
Peak memory 201252 kb
Host smart-72d7f903-51b0-4015-ae20-85c2683b5ee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977775727 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.1977775727
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.423642657
Short name T368
Test name
Test status
Simulation time 44648446 ps
CPU time 0.89 seconds
Started Jul 31 06:00:52 PM PDT 24
Finished Jul 31 06:00:53 PM PDT 24
Peak memory 200964 kb
Host smart-63e375f0-d5c9-41ad-a9c0-c4a35becdfcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423642657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.423642657
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.2974277703
Short name T283
Test name
Test status
Simulation time 3765419435 ps
CPU time 16.41 seconds
Started Jul 31 06:01:03 PM PDT 24
Finished Jul 31 06:01:19 PM PDT 24
Peak memory 201452 kb
Host smart-542214b8-512f-4e5b-8ef7-01ba73f48f72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974277703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.2974277703
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.1267696633
Short name T71
Test name
Test status
Simulation time 858035447868 ps
CPU time 3087.35 seconds
Started Jul 31 06:01:02 PM PDT 24
Finished Jul 31 06:52:30 PM PDT 24
Peak memory 217960 kb
Host smart-98da9144-74ac-4e37-88ec-68c580bc3ffe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1267696633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.1267696633
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.4114182709
Short name T639
Test name
Test status
Simulation time 38357530 ps
CPU time 0.8 seconds
Started Jul 31 06:00:52 PM PDT 24
Finished Jul 31 06:00:53 PM PDT 24
Peak memory 201056 kb
Host smart-b041e7d0-5f19-4b7c-a342-fa098f7d3d40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114182709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.4114182709
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.3411658270
Short name T15
Test name
Test status
Simulation time 16751890 ps
CPU time 0.77 seconds
Started Jul 31 06:01:24 PM PDT 24
Finished Jul 31 06:01:25 PM PDT 24
Peak memory 201080 kb
Host smart-a2872fa2-3581-45aa-856f-580dcabcac3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411658270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.3411658270
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2712029083
Short name T102
Test name
Test status
Simulation time 209936948 ps
CPU time 1.49 seconds
Started Jul 31 06:01:26 PM PDT 24
Finished Jul 31 06:01:28 PM PDT 24
Peak memory 201104 kb
Host smart-a8985164-37d5-431a-87ee-4a45f8e090a3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712029083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.2712029083
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.1044530905
Short name T265
Test name
Test status
Simulation time 34497374 ps
CPU time 0.75 seconds
Started Jul 31 06:01:14 PM PDT 24
Finished Jul 31 06:01:14 PM PDT 24
Peak memory 201016 kb
Host smart-b794071f-4c58-4261-8ef3-e4179c362dbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044530905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1044530905
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1476439504
Short name T159
Test name
Test status
Simulation time 105710578 ps
CPU time 1.17 seconds
Started Jul 31 06:01:28 PM PDT 24
Finished Jul 31 06:01:29 PM PDT 24
Peak memory 201108 kb
Host smart-27e63bae-815a-49ad-9979-d0988b2e31cf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476439504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1476439504
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.1847099950
Short name T390
Test name
Test status
Simulation time 15909480 ps
CPU time 0.77 seconds
Started Jul 31 06:01:02 PM PDT 24
Finished Jul 31 06:01:04 PM PDT 24
Peak memory 201068 kb
Host smart-c41f11fc-453e-4847-a3d1-275b52a7065e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847099950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.1847099950
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1119839178
Short name T371
Test name
Test status
Simulation time 313797830 ps
CPU time 2.97 seconds
Started Jul 31 06:01:03 PM PDT 24
Finished Jul 31 06:01:06 PM PDT 24
Peak memory 201060 kb
Host smart-39ff7a01-8c15-4473-ac40-9c838a10e004
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119839178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1119839178
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.3609166626
Short name T631
Test name
Test status
Simulation time 1334258360 ps
CPU time 9.92 seconds
Started Jul 31 06:01:08 PM PDT 24
Finished Jul 31 06:01:18 PM PDT 24
Peak memory 201208 kb
Host smart-a6b0b43e-f551-4fb9-965a-1bdf1ccc1571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609166626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.3609166626
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.1615301349
Short name T93
Test name
Test status
Simulation time 29517371 ps
CPU time 0.79 seconds
Started Jul 31 06:01:10 PM PDT 24
Finished Jul 31 06:01:11 PM PDT 24
Peak memory 201096 kb
Host smart-268a93b5-443c-43eb-8486-8317220d28df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615301349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.1615301349
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1034976859
Short name T452
Test name
Test status
Simulation time 26990670 ps
CPU time 0.82 seconds
Started Jul 31 06:01:16 PM PDT 24
Finished Jul 31 06:01:17 PM PDT 24
Peak memory 201092 kb
Host smart-9782b84f-068a-4c94-8a7c-41b018702303
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034976859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.1034976859
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.4174169289
Short name T814
Test name
Test status
Simulation time 74367769 ps
CPU time 0.98 seconds
Started Jul 31 06:01:14 PM PDT 24
Finished Jul 31 06:01:16 PM PDT 24
Peak memory 201076 kb
Host smart-15c146ff-186b-469a-88b0-6936fc875191
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174169289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.4174169289
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.8774335
Short name T310
Test name
Test status
Simulation time 23975926 ps
CPU time 0.76 seconds
Started Jul 31 06:01:08 PM PDT 24
Finished Jul 31 06:01:09 PM PDT 24
Peak memory 201068 kb
Host smart-aa92b180-ace9-4994-b1c9-c9cbbaa30c5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8774335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.8774335
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2724023488
Short name T821
Test name
Test status
Simulation time 620809642 ps
CPU time 3.15 seconds
Started Jul 31 06:01:23 PM PDT 24
Finished Jul 31 06:01:26 PM PDT 24
Peak memory 201228 kb
Host smart-92905ba2-225b-41c7-a494-89fb2f542046
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724023488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2724023488
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3655795400
Short name T760
Test name
Test status
Simulation time 26447002 ps
CPU time 0.89 seconds
Started Jul 31 06:00:59 PM PDT 24
Finished Jul 31 06:01:00 PM PDT 24
Peak memory 201092 kb
Host smart-6fa8f6b0-0569-415c-84d7-4ff27d81e4a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655795400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3655795400
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2820376454
Short name T151
Test name
Test status
Simulation time 5799790506 ps
CPU time 23.2 seconds
Started Jul 31 06:01:23 PM PDT 24
Finished Jul 31 06:01:46 PM PDT 24
Peak memory 201452 kb
Host smart-d445f924-e863-4684-ac91-2d11ec469533
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820376454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2820376454
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.3909414080
Short name T507
Test name
Test status
Simulation time 17786677 ps
CPU time 0.8 seconds
Started Jul 31 06:01:02 PM PDT 24
Finished Jul 31 06:01:03 PM PDT 24
Peak memory 201044 kb
Host smart-17afc36b-c060-406e-8071-ca84b8473d77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909414080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.3909414080
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2372872239
Short name T464
Test name
Test status
Simulation time 30019173 ps
CPU time 0.84 seconds
Started Jul 31 06:01:33 PM PDT 24
Finished Jul 31 06:01:34 PM PDT 24
Peak memory 201064 kb
Host smart-826c89be-6d2d-4e23-bc1f-450f8b872949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372872239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2372872239
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.289585106
Short name T728
Test name
Test status
Simulation time 37577143 ps
CPU time 0.83 seconds
Started Jul 31 06:01:33 PM PDT 24
Finished Jul 31 06:01:34 PM PDT 24
Peak memory 201048 kb
Host smart-17afb2ea-db61-4e91-9ad6-d9b6cd205878
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289585106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.289585106
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.2815187366
Short name T564
Test name
Test status
Simulation time 20409852 ps
CPU time 0.69 seconds
Started Jul 31 06:01:30 PM PDT 24
Finished Jul 31 06:01:31 PM PDT 24
Peak memory 200256 kb
Host smart-4e68fe66-0522-4076-af64-88f19b6efa71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815187366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2815187366
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1993973295
Short name T241
Test name
Test status
Simulation time 229176855 ps
CPU time 1.41 seconds
Started Jul 31 06:01:36 PM PDT 24
Finished Jul 31 06:01:38 PM PDT 24
Peak memory 201116 kb
Host smart-4709ae50-86b6-4367-9f9b-dc88720d591f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993973295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1993973295
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.3972809567
Short name T173
Test name
Test status
Simulation time 116658456 ps
CPU time 1.09 seconds
Started Jul 31 06:01:33 PM PDT 24
Finished Jul 31 06:01:34 PM PDT 24
Peak memory 201040 kb
Host smart-25010129-53a2-421a-a0b5-d09e2756adc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972809567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3972809567
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.830134779
Short name T10
Test name
Test status
Simulation time 2245193847 ps
CPU time 13.24 seconds
Started Jul 31 06:01:27 PM PDT 24
Finished Jul 31 06:01:40 PM PDT 24
Peak memory 201392 kb
Host smart-695f02bf-68cf-43ae-afdf-e55ddb2eabb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830134779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.830134779
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.4110850039
Short name T313
Test name
Test status
Simulation time 561952462 ps
CPU time 2.31 seconds
Started Jul 31 06:01:30 PM PDT 24
Finished Jul 31 06:01:33 PM PDT 24
Peak memory 201160 kb
Host smart-80f4a511-f7a9-4e82-8602-b7d3b16c5553
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110850039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.4110850039
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1319527002
Short name T256
Test name
Test status
Simulation time 125107118 ps
CPU time 1.08 seconds
Started Jul 31 06:01:30 PM PDT 24
Finished Jul 31 06:01:31 PM PDT 24
Peak memory 201052 kb
Host smart-f0d682de-dc6c-4f37-a52c-28686a768c2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319527002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1319527002
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2924829622
Short name T706
Test name
Test status
Simulation time 25007595 ps
CPU time 0.75 seconds
Started Jul 31 06:01:32 PM PDT 24
Finished Jul 31 06:01:33 PM PDT 24
Peak memory 201076 kb
Host smart-90d86ab3-d297-4a7d-b028-b90e02aee255
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924829622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2924829622
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2385597689
Short name T426
Test name
Test status
Simulation time 42784034 ps
CPU time 0.94 seconds
Started Jul 31 06:01:30 PM PDT 24
Finished Jul 31 06:01:31 PM PDT 24
Peak memory 201084 kb
Host smart-e675e78b-eff4-4852-ad34-a80370795fd8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385597689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2385597689
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.793417164
Short name T430
Test name
Test status
Simulation time 17202300 ps
CPU time 0.72 seconds
Started Jul 31 06:01:30 PM PDT 24
Finished Jul 31 06:01:31 PM PDT 24
Peak memory 201036 kb
Host smart-c5eb4e7a-4c6d-4998-8954-c6f1dbb41202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793417164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.793417164
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.4203960112
Short name T163
Test name
Test status
Simulation time 60048711 ps
CPU time 0.9 seconds
Started Jul 31 06:01:33 PM PDT 24
Finished Jul 31 06:01:34 PM PDT 24
Peak memory 201044 kb
Host smart-f65a53fa-f17f-4307-aea3-28289941617c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203960112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.4203960112
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.2115466299
Short name T155
Test name
Test status
Simulation time 22595611 ps
CPU time 0.86 seconds
Started Jul 31 06:01:26 PM PDT 24
Finished Jul 31 06:01:27 PM PDT 24
Peak memory 201012 kb
Host smart-87bf121b-aabe-45bd-9ee0-b067e301c05a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115466299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.2115466299
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3280123350
Short name T42
Test name
Test status
Simulation time 7185172470 ps
CPU time 50.4 seconds
Started Jul 31 06:01:36 PM PDT 24
Finished Jul 31 06:02:26 PM PDT 24
Peak memory 201468 kb
Host smart-563ae64f-5b67-495d-932c-70913e1f7808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280123350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3280123350
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3900238166
Short name T393
Test name
Test status
Simulation time 19812781 ps
CPU time 0.87 seconds
Started Jul 31 06:01:31 PM PDT 24
Finished Jul 31 06:01:32 PM PDT 24
Peak memory 201092 kb
Host smart-a74adfb1-fb5b-431c-a406-7d9f3efcde6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900238166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3900238166
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.2236886075
Short name T272
Test name
Test status
Simulation time 26386243 ps
CPU time 0.8 seconds
Started Jul 31 06:01:51 PM PDT 24
Finished Jul 31 06:01:51 PM PDT 24
Peak memory 201120 kb
Host smart-a5e4caf4-eb2c-4a6e-8eee-6736c49d3f5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236886075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.2236886075
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.2044594073
Short name T363
Test name
Test status
Simulation time 315376689 ps
CPU time 1.75 seconds
Started Jul 31 06:01:43 PM PDT 24
Finished Jul 31 06:01:44 PM PDT 24
Peak memory 201060 kb
Host smart-ba8e360e-94c0-44d7-b9a2-6c00089780c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044594073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.2044594073
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1802415687
Short name T316
Test name
Test status
Simulation time 45474722 ps
CPU time 0.79 seconds
Started Jul 31 06:01:36 PM PDT 24
Finished Jul 31 06:01:37 PM PDT 24
Peak memory 201008 kb
Host smart-4d3bef7e-4645-4bd6-bee1-1ec1a5a8a488
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802415687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1802415687
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1877832320
Short name T229
Test name
Test status
Simulation time 355123738 ps
CPU time 1.87 seconds
Started Jul 31 06:01:42 PM PDT 24
Finished Jul 31 06:01:44 PM PDT 24
Peak memory 201080 kb
Host smart-c91d6812-f378-4fc2-9a6b-d625d65c9792
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877832320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1877832320
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2700173667
Short name T598
Test name
Test status
Simulation time 71032880 ps
CPU time 0.93 seconds
Started Jul 31 06:01:32 PM PDT 24
Finished Jul 31 06:01:33 PM PDT 24
Peak memory 200988 kb
Host smart-8a836cd4-0d20-49cc-9fd8-14914337cb9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700173667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2700173667
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.2428201887
Short name T617
Test name
Test status
Simulation time 1884219074 ps
CPU time 11.31 seconds
Started Jul 31 06:01:37 PM PDT 24
Finished Jul 31 06:01:49 PM PDT 24
Peak memory 201308 kb
Host smart-6b6a981a-2068-4787-942e-ee808c704991
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428201887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2428201887
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.364246871
Short name T456
Test name
Test status
Simulation time 1455590375 ps
CPU time 9.38 seconds
Started Jul 31 06:01:37 PM PDT 24
Finished Jul 31 06:01:47 PM PDT 24
Peak memory 201204 kb
Host smart-2e65d35a-199c-4b04-bfc8-bc7ebb4100e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364246871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_ti
meout.364246871
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2913859916
Short name T6
Test name
Test status
Simulation time 52753880 ps
CPU time 1.04 seconds
Started Jul 31 06:01:39 PM PDT 24
Finished Jul 31 06:01:40 PM PDT 24
Peak memory 201012 kb
Host smart-a3a99918-65c6-4936-8d3f-b916518f7409
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913859916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.2913859916
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2646880787
Short name T511
Test name
Test status
Simulation time 25464466 ps
CPU time 0.92 seconds
Started Jul 31 06:01:43 PM PDT 24
Finished Jul 31 06:01:44 PM PDT 24
Peak memory 201080 kb
Host smart-9b4e95fc-b57c-48d1-ba15-ed60dbe37db1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646880787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2646880787
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3559282460
Short name T815
Test name
Test status
Simulation time 34908064 ps
CPU time 0.78 seconds
Started Jul 31 06:01:44 PM PDT 24
Finished Jul 31 06:01:45 PM PDT 24
Peak memory 201088 kb
Host smart-c31f0946-e2a4-4052-8176-05087b9c4f93
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559282460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.3559282460
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1757796762
Short name T74
Test name
Test status
Simulation time 30476138 ps
CPU time 0.74 seconds
Started Jul 31 06:01:37 PM PDT 24
Finished Jul 31 06:01:38 PM PDT 24
Peak memory 201060 kb
Host smart-ce7d9380-5224-4303-8038-00e8b2cb1a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757796762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1757796762
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1697765428
Short name T48
Test name
Test status
Simulation time 177602866 ps
CPU time 1.23 seconds
Started Jul 31 06:01:47 PM PDT 24
Finished Jul 31 06:01:48 PM PDT 24
Peak memory 201012 kb
Host smart-2897f7af-8b81-4fdf-b763-1b0c61747178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697765428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1697765428
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.1951773614
Short name T747
Test name
Test status
Simulation time 22252577 ps
CPU time 0.82 seconds
Started Jul 31 06:01:33 PM PDT 24
Finished Jul 31 06:01:34 PM PDT 24
Peak memory 201060 kb
Host smart-01eea087-6fe4-43a7-89b8-fba815c330f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951773614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1951773614
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.3661311873
Short name T779
Test name
Test status
Simulation time 97209925 ps
CPU time 1.3 seconds
Started Jul 31 06:01:47 PM PDT 24
Finished Jul 31 06:01:48 PM PDT 24
Peak memory 201040 kb
Host smart-f07f2a0f-5afe-4015-b0a6-b37e1181597d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661311873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.3661311873
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.2529526724
Short name T732
Test name
Test status
Simulation time 34777696 ps
CPU time 1.06 seconds
Started Jul 31 06:01:37 PM PDT 24
Finished Jul 31 06:01:39 PM PDT 24
Peak memory 201024 kb
Host smart-d0f58c23-2a3e-4d62-a244-ed1fd171201e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529526724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2529526724
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.1957140716
Short name T713
Test name
Test status
Simulation time 18407282 ps
CPU time 0.8 seconds
Started Jul 31 05:55:39 PM PDT 24
Finished Jul 31 05:55:40 PM PDT 24
Peak memory 201092 kb
Host smart-323077db-7576-4e3a-a5dc-a2595cd95971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957140716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.1957140716
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1769981905
Short name T772
Test name
Test status
Simulation time 15447131 ps
CPU time 0.76 seconds
Started Jul 31 05:55:35 PM PDT 24
Finished Jul 31 05:55:36 PM PDT 24
Peak memory 201056 kb
Host smart-b4d6f618-ef6b-4470-a335-039cc29db6f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769981905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1769981905
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1824575940
Short name T177
Test name
Test status
Simulation time 13989921 ps
CPU time 0.72 seconds
Started Jul 31 05:55:30 PM PDT 24
Finished Jul 31 05:55:31 PM PDT 24
Peak memory 200236 kb
Host smart-8fbdfb70-84e2-46aa-a481-31edc61c4270
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824575940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1824575940
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.365437412
Short name T318
Test name
Test status
Simulation time 26753221 ps
CPU time 0.91 seconds
Started Jul 31 05:55:33 PM PDT 24
Finished Jul 31 05:55:34 PM PDT 24
Peak memory 201032 kb
Host smart-7152c0c6-2ebc-45b3-9a2a-005c11016a82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365437412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.365437412
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.2200539926
Short name T654
Test name
Test status
Simulation time 15548025 ps
CPU time 0.75 seconds
Started Jul 31 05:55:19 PM PDT 24
Finished Jul 31 05:55:20 PM PDT 24
Peak memory 200968 kb
Host smart-1fa4221f-c87e-46d5-87b7-463dae97379c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200539926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2200539926
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2686585662
Short name T570
Test name
Test status
Simulation time 2006530906 ps
CPU time 11.28 seconds
Started Jul 31 05:55:20 PM PDT 24
Finished Jul 31 05:55:31 PM PDT 24
Peak memory 201348 kb
Host smart-fab62732-020e-4090-89c0-a33d892a077d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686585662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2686585662
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.520212683
Short name T640
Test name
Test status
Simulation time 237163813 ps
CPU time 1.44 seconds
Started Jul 31 05:58:58 PM PDT 24
Finished Jul 31 05:58:59 PM PDT 24
Peak memory 201180 kb
Host smart-5c3b0080-8795-4582-a968-60dbaa0b0b15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520212683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim
eout.520212683
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1355624922
Short name T461
Test name
Test status
Simulation time 17983376 ps
CPU time 0.81 seconds
Started Jul 31 05:55:30 PM PDT 24
Finished Jul 31 05:55:31 PM PDT 24
Peak memory 201072 kb
Host smart-98dd3d41-f628-445d-b5c0-b66c3e4a1bbb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355624922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1355624922
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1808602141
Short name T730
Test name
Test status
Simulation time 18757016 ps
CPU time 0.81 seconds
Started Jul 31 05:55:30 PM PDT 24
Finished Jul 31 05:55:31 PM PDT 24
Peak memory 201068 kb
Host smart-ea14371d-9fff-4749-a6b5-953a213517a5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808602141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1808602141
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1251125896
Short name T768
Test name
Test status
Simulation time 14155336 ps
CPU time 0.75 seconds
Started Jul 31 05:55:30 PM PDT 24
Finished Jul 31 05:55:31 PM PDT 24
Peak memory 201036 kb
Host smart-2aa11e28-51f4-43ba-b450-78046e18936e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251125896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.1251125896
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.3160963646
Short name T179
Test name
Test status
Simulation time 89444720 ps
CPU time 0.94 seconds
Started Jul 31 05:55:19 PM PDT 24
Finished Jul 31 05:55:20 PM PDT 24
Peak memory 200996 kb
Host smart-7ba48ca9-d4dc-48ec-b938-e27c9bd9eebb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160963646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.3160963646
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.4086078208
Short name T689
Test name
Test status
Simulation time 817711891 ps
CPU time 3.9 seconds
Started Jul 31 05:55:39 PM PDT 24
Finished Jul 31 05:55:43 PM PDT 24
Peak memory 201284 kb
Host smart-26136f89-b650-48a4-baaf-f41d0c406a04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086078208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.4086078208
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2978878593
Short name T57
Test name
Test status
Simulation time 332474927 ps
CPU time 2.28 seconds
Started Jul 31 05:55:38 PM PDT 24
Finished Jul 31 05:55:41 PM PDT 24
Peak memory 216432 kb
Host smart-0dca17b3-1be3-42be-8860-3754bbc8b785
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978878593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2978878593
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.2737028030
Short name T496
Test name
Test status
Simulation time 15904087 ps
CPU time 0.79 seconds
Started Jul 31 05:55:20 PM PDT 24
Finished Jul 31 05:55:21 PM PDT 24
Peak memory 201104 kb
Host smart-9fba51d1-5720-4244-99d6-37e44360eb77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737028030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2737028030
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.76567309
Short name T523
Test name
Test status
Simulation time 6392258566 ps
CPU time 27.1 seconds
Started Jul 31 05:55:40 PM PDT 24
Finished Jul 31 05:56:08 PM PDT 24
Peak memory 201424 kb
Host smart-4fe4c779-b9d5-42d2-b51a-f23b8d442502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76567309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_stress_all.76567309
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.2127292642
Short name T716
Test name
Test status
Simulation time 139903806 ps
CPU time 1.42 seconds
Started Jul 31 05:55:24 PM PDT 24
Finished Jul 31 05:55:25 PM PDT 24
Peak memory 201072 kb
Host smart-337d4521-c53d-4a16-bc00-c6348c249f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127292642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2127292642
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.1283757261
Short name T208
Test name
Test status
Simulation time 17391446 ps
CPU time 0.77 seconds
Started Jul 31 06:02:13 PM PDT 24
Finished Jul 31 06:02:14 PM PDT 24
Peak memory 201100 kb
Host smart-e4746f77-410e-45e2-9e19-1dd510df9578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283757261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.1283757261
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.965446757
Short name T103
Test name
Test status
Simulation time 30678449 ps
CPU time 0.84 seconds
Started Jul 31 06:02:09 PM PDT 24
Finished Jul 31 06:02:10 PM PDT 24
Peak memory 201096 kb
Host smart-14d00fb1-22ff-4ff5-8e40-daeb8a7cbd65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965446757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.965446757
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1042298251
Short name T737
Test name
Test status
Simulation time 15356379 ps
CPU time 0.73 seconds
Started Jul 31 06:02:03 PM PDT 24
Finished Jul 31 06:02:04 PM PDT 24
Peak memory 201000 kb
Host smart-4752d844-9924-472d-b9ce-7bde6b9c2ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042298251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1042298251
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.504726985
Short name T812
Test name
Test status
Simulation time 44354284 ps
CPU time 0.86 seconds
Started Jul 31 06:02:12 PM PDT 24
Finished Jul 31 06:02:13 PM PDT 24
Peak memory 201116 kb
Host smart-6e9901c9-c08a-418c-bea4-c3f097b70b0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504726985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.504726985
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.4181928532
Short name T296
Test name
Test status
Simulation time 25550363 ps
CPU time 0.75 seconds
Started Jul 31 06:01:51 PM PDT 24
Finished Jul 31 06:01:52 PM PDT 24
Peak memory 201056 kb
Host smart-63d987ab-770b-4f8e-8328-8306a2c10c54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181928532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.4181928532
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1094720305
Short name T721
Test name
Test status
Simulation time 1992280399 ps
CPU time 9.13 seconds
Started Jul 31 06:01:58 PM PDT 24
Finished Jul 31 06:02:07 PM PDT 24
Peak memory 201196 kb
Host smart-1c9d3790-c9a4-4643-87fb-f1978ab7faf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094720305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1094720305
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.2830480525
Short name T590
Test name
Test status
Simulation time 1107668934 ps
CPU time 4.63 seconds
Started Jul 31 06:02:00 PM PDT 24
Finished Jul 31 06:02:05 PM PDT 24
Peak memory 201168 kb
Host smart-c220f936-3539-4dc0-a0b0-47e348961a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830480525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.2830480525
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.559556095
Short name T793
Test name
Test status
Simulation time 65259361 ps
CPU time 1.12 seconds
Started Jul 31 06:02:08 PM PDT 24
Finished Jul 31 06:02:09 PM PDT 24
Peak memory 201076 kb
Host smart-76deaafd-f6ef-4955-8eb7-b39c0ec3aff5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559556095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.559556095
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2598618904
Short name T340
Test name
Test status
Simulation time 65771634 ps
CPU time 0.91 seconds
Started Jul 31 06:02:12 PM PDT 24
Finished Jul 31 06:02:13 PM PDT 24
Peak memory 200876 kb
Host smart-34e82e67-87c9-46a8-b801-ba96d4d683e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598618904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2598618904
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.1580992537
Short name T437
Test name
Test status
Simulation time 27973115 ps
CPU time 0.77 seconds
Started Jul 31 06:02:12 PM PDT 24
Finished Jul 31 06:02:13 PM PDT 24
Peak memory 200852 kb
Host smart-e5586cc1-494b-40ff-aa2d-4c02db7e86f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580992537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.1580992537
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.296798437
Short name T381
Test name
Test status
Simulation time 56113721 ps
CPU time 0.86 seconds
Started Jul 31 06:02:02 PM PDT 24
Finished Jul 31 06:02:03 PM PDT 24
Peak memory 201064 kb
Host smart-49f60775-057a-4d1c-91f4-779a213c2cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296798437 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.296798437
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.3240687764
Short name T495
Test name
Test status
Simulation time 613084543 ps
CPU time 3.65 seconds
Started Jul 31 06:02:06 PM PDT 24
Finished Jul 31 06:02:10 PM PDT 24
Peak memory 201248 kb
Host smart-527c51cc-f7c9-44e6-9a84-4d0532b68af4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240687764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.3240687764
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.1257298356
Short name T168
Test name
Test status
Simulation time 251885172 ps
CPU time 1.61 seconds
Started Jul 31 06:01:56 PM PDT 24
Finished Jul 31 06:01:57 PM PDT 24
Peak memory 201104 kb
Host smart-290bba9f-9883-4b85-995d-1a8adf08e5ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257298356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1257298356
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1917431756
Short name T370
Test name
Test status
Simulation time 1345129813 ps
CPU time 11.12 seconds
Started Jul 31 06:02:13 PM PDT 24
Finished Jul 31 06:02:24 PM PDT 24
Peak memory 201312 kb
Host smart-c57cef1b-383e-4819-80d1-3e5f5d854aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917431756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1917431756
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.4266625897
Short name T818
Test name
Test status
Simulation time 220362091 ps
CPU time 1.57 seconds
Started Jul 31 06:02:04 PM PDT 24
Finished Jul 31 06:02:05 PM PDT 24
Peak memory 201104 kb
Host smart-46b24a20-3858-4cfb-9462-3cb13574444a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266625897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.4266625897
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1194900450
Short name T563
Test name
Test status
Simulation time 17634239 ps
CPU time 0.8 seconds
Started Jul 31 06:02:32 PM PDT 24
Finished Jul 31 06:02:33 PM PDT 24
Peak memory 201052 kb
Host smart-00197520-2118-43d3-990a-eede6aed3483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194900450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1194900450
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.562165961
Short name T348
Test name
Test status
Simulation time 63852349 ps
CPU time 0.98 seconds
Started Jul 31 06:02:23 PM PDT 24
Finished Jul 31 06:02:24 PM PDT 24
Peak memory 201032 kb
Host smart-72ec583d-0fe9-4f71-9e0d-da18dbc05401
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562165961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.562165961
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.4016057792
Short name T547
Test name
Test status
Simulation time 18635079 ps
CPU time 0.71 seconds
Started Jul 31 06:02:24 PM PDT 24
Finished Jul 31 06:02:25 PM PDT 24
Peak memory 200252 kb
Host smart-29ee12f7-7cb3-4e96-94ec-6851a3a4a7b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016057792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.4016057792
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.468422940
Short name T409
Test name
Test status
Simulation time 119713002 ps
CPU time 1.06 seconds
Started Jul 31 06:02:27 PM PDT 24
Finished Jul 31 06:02:28 PM PDT 24
Peak memory 201024 kb
Host smart-78ea3075-d8c1-47a2-a907-09d64cbdd8bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468422940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_div_intersig_mubi.468422940
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.200301616
Short name T341
Test name
Test status
Simulation time 430350759 ps
CPU time 2.04 seconds
Started Jul 31 06:02:12 PM PDT 24
Finished Jul 31 06:02:14 PM PDT 24
Peak memory 201040 kb
Host smart-b178336a-874c-45a4-a31f-30ce2d298307
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200301616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.200301616
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.753236503
Short name T482
Test name
Test status
Simulation time 2094647044 ps
CPU time 8.1 seconds
Started Jul 31 06:02:11 PM PDT 24
Finished Jul 31 06:02:19 PM PDT 24
Peak memory 201288 kb
Host smart-0ded11d2-026d-4a37-8a73-2b86c204523c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753236503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.753236503
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3296878158
Short name T516
Test name
Test status
Simulation time 1240704563 ps
CPU time 5.7 seconds
Started Jul 31 06:02:11 PM PDT 24
Finished Jul 31 06:02:17 PM PDT 24
Peak memory 201164 kb
Host smart-f6fe56a3-50cc-4d15-9ffe-b1608b4ffea5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296878158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3296878158
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.945057617
Short name T326
Test name
Test status
Simulation time 150577603 ps
CPU time 1.26 seconds
Started Jul 31 06:02:26 PM PDT 24
Finished Jul 31 06:02:28 PM PDT 24
Peak memory 201104 kb
Host smart-f0349e42-5110-40d3-b501-45c623940b14
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945057617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.945057617
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2218288904
Short name T438
Test name
Test status
Simulation time 23799491 ps
CPU time 0.88 seconds
Started Jul 31 06:02:22 PM PDT 24
Finished Jul 31 06:02:23 PM PDT 24
Peak memory 201028 kb
Host smart-7c3cb908-2225-4538-b603-5367981aec60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218288904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2218288904
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.2052850611
Short name T20
Test name
Test status
Simulation time 210819211 ps
CPU time 1.32 seconds
Started Jul 31 06:02:23 PM PDT 24
Finished Jul 31 06:02:25 PM PDT 24
Peak memory 201076 kb
Host smart-7f285b22-cb29-48db-aa8f-19caf0c911bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052850611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.2052850611
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3148221177
Short name T545
Test name
Test status
Simulation time 30329836 ps
CPU time 0.83 seconds
Started Jul 31 06:02:15 PM PDT 24
Finished Jul 31 06:02:16 PM PDT 24
Peak memory 201028 kb
Host smart-565e96f4-3cb4-470a-b99c-c8dd6bcbfdf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148221177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3148221177
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.915799959
Short name T449
Test name
Test status
Simulation time 454867220 ps
CPU time 2.83 seconds
Started Jul 31 06:02:27 PM PDT 24
Finished Jul 31 06:02:30 PM PDT 24
Peak memory 201268 kb
Host smart-7c06807d-078b-4ae7-acb5-537b939fe950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915799959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.915799959
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.780708548
Short name T600
Test name
Test status
Simulation time 21320440 ps
CPU time 0.82 seconds
Started Jul 31 06:02:13 PM PDT 24
Finished Jul 31 06:02:14 PM PDT 24
Peak memory 201088 kb
Host smart-93a36120-8e1e-47ed-a6aa-b4961b1df217
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780708548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.780708548
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.4006773490
Short name T9
Test name
Test status
Simulation time 13797917964 ps
CPU time 53.33 seconds
Started Jul 31 06:02:35 PM PDT 24
Finished Jul 31 06:03:28 PM PDT 24
Peak memory 201448 kb
Host smart-25b702d6-39d4-4483-a560-0ab54eb4c29c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006773490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.4006773490
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3131209758
Short name T635
Test name
Test status
Simulation time 117894578 ps
CPU time 1.32 seconds
Started Jul 31 06:02:17 PM PDT 24
Finished Jul 31 06:02:18 PM PDT 24
Peak memory 201088 kb
Host smart-46986dc6-56e9-49a4-aea1-70256919965a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131209758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3131209758
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1836001055
Short name T670
Test name
Test status
Simulation time 27537996 ps
CPU time 0.79 seconds
Started Jul 31 06:02:53 PM PDT 24
Finished Jul 31 06:02:54 PM PDT 24
Peak memory 201100 kb
Host smart-5892eaed-983e-4fa0-95b1-ff3ab31c0fa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836001055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1836001055
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.4072948592
Short name T806
Test name
Test status
Simulation time 20684081 ps
CPU time 0.78 seconds
Started Jul 31 06:02:47 PM PDT 24
Finished Jul 31 06:02:48 PM PDT 24
Peak memory 201032 kb
Host smart-9a21cf6e-dbf7-4ddb-a850-750c5ff5e161
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072948592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.4072948592
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.1757226716
Short name T323
Test name
Test status
Simulation time 33862407 ps
CPU time 0.77 seconds
Started Jul 31 06:02:42 PM PDT 24
Finished Jul 31 06:02:43 PM PDT 24
Peak memory 200276 kb
Host smart-93cf8663-77e1-4bff-aac5-aec04743fca8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757226716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1757226716
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.2179311871
Short name T295
Test name
Test status
Simulation time 28213786 ps
CPU time 0.75 seconds
Started Jul 31 06:02:48 PM PDT 24
Finished Jul 31 06:02:49 PM PDT 24
Peak memory 201088 kb
Host smart-7be11066-2f12-49d3-830e-ff343fab0abf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179311871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.2179311871
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.4217251309
Short name T191
Test name
Test status
Simulation time 17607653 ps
CPU time 0.78 seconds
Started Jul 31 06:02:42 PM PDT 24
Finished Jul 31 06:02:43 PM PDT 24
Peak memory 201084 kb
Host smart-c8621135-fb3c-469e-8683-c080b01940b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217251309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4217251309
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.1695754615
Short name T227
Test name
Test status
Simulation time 2480768168 ps
CPU time 18.43 seconds
Started Jul 31 06:02:45 PM PDT 24
Finished Jul 31 06:03:03 PM PDT 24
Peak memory 201400 kb
Host smart-cceb50e7-4cc5-46c2-950a-57487ec54976
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695754615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1695754615
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3615222267
Short name T789
Test name
Test status
Simulation time 1836320558 ps
CPU time 7.89 seconds
Started Jul 31 06:02:41 PM PDT 24
Finished Jul 31 06:02:49 PM PDT 24
Peak memory 201200 kb
Host smart-fd2e5bcd-65f9-4099-a1d2-58f6f0c88dfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615222267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3615222267
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2431899149
Short name T308
Test name
Test status
Simulation time 103605178 ps
CPU time 1.17 seconds
Started Jul 31 06:02:47 PM PDT 24
Finished Jul 31 06:02:49 PM PDT 24
Peak memory 201040 kb
Host smart-1f81b780-4430-435b-b349-fd49e459f46f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431899149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.2431899149
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2266893865
Short name T693
Test name
Test status
Simulation time 26719675 ps
CPU time 0.94 seconds
Started Jul 31 06:02:47 PM PDT 24
Finished Jul 31 06:02:48 PM PDT 24
Peak memory 201060 kb
Host smart-c8879fc0-76a5-4010-8a39-108918d55253
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266893865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2266893865
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2194588649
Short name T386
Test name
Test status
Simulation time 18334059 ps
CPU time 0.71 seconds
Started Jul 31 06:02:47 PM PDT 24
Finished Jul 31 06:02:48 PM PDT 24
Peak memory 201088 kb
Host smart-2194997b-bd35-4a9b-be1f-214cc5bf211d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194588649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.2194588649
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.1945237540
Short name T797
Test name
Test status
Simulation time 17412956 ps
CPU time 0.75 seconds
Started Jul 31 06:02:43 PM PDT 24
Finished Jul 31 06:02:44 PM PDT 24
Peak memory 201004 kb
Host smart-edb7fdfa-9328-44dd-9b3f-f74cec3f023f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945237540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.1945237540
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.324823841
Short name T642
Test name
Test status
Simulation time 1106376725 ps
CPU time 6.2 seconds
Started Jul 31 06:02:51 PM PDT 24
Finished Jul 31 06:02:57 PM PDT 24
Peak memory 201196 kb
Host smart-6dcfc4ae-a788-4e4b-bf6b-93a4203a4a2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324823841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.324823841
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.1278701987
Short name T153
Test name
Test status
Simulation time 39309306 ps
CPU time 0.93 seconds
Started Jul 31 06:02:37 PM PDT 24
Finished Jul 31 06:02:38 PM PDT 24
Peak memory 201052 kb
Host smart-5338466a-6740-4d6f-b662-b4d62da06131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278701987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1278701987
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3192598317
Short name T357
Test name
Test status
Simulation time 367057444 ps
CPU time 2.49 seconds
Started Jul 31 06:02:49 PM PDT 24
Finished Jul 31 06:02:52 PM PDT 24
Peak memory 201252 kb
Host smart-b899ab55-9b7b-4ac4-8a3b-214831934a4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192598317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3192598317
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.1325386358
Short name T170
Test name
Test status
Simulation time 99944851403 ps
CPU time 598.49 seconds
Started Jul 31 06:02:50 PM PDT 24
Finished Jul 31 06:12:49 PM PDT 24
Peak memory 212652 kb
Host smart-cc67de4f-c2bf-4a11-b7e0-c2353299ccfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1325386358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1325386358
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.1139863297
Short name T700
Test name
Test status
Simulation time 38054081 ps
CPU time 0.81 seconds
Started Jul 31 06:02:44 PM PDT 24
Finished Jul 31 06:02:45 PM PDT 24
Peak memory 201060 kb
Host smart-fc7394a4-5949-42c1-88ea-ab3bf900dc56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139863297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1139863297
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.807246181
Short name T546
Test name
Test status
Simulation time 16382562 ps
CPU time 0.8 seconds
Started Jul 31 06:03:23 PM PDT 24
Finished Jul 31 06:03:24 PM PDT 24
Peak memory 201084 kb
Host smart-1519207d-dc43-4919-8ee7-c6bbaa605431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807246181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkm
gr_alert_test.807246181
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2189791573
Short name T35
Test name
Test status
Simulation time 35724351 ps
CPU time 0.8 seconds
Started Jul 31 06:03:06 PM PDT 24
Finished Jul 31 06:03:07 PM PDT 24
Peak memory 201028 kb
Host smart-96115a22-9226-484d-9110-62637fe629a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189791573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.2189791573
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.2965593741
Short name T801
Test name
Test status
Simulation time 51253464 ps
CPU time 0.75 seconds
Started Jul 31 06:03:03 PM PDT 24
Finished Jul 31 06:03:04 PM PDT 24
Peak memory 200296 kb
Host smart-f47c1746-3a06-47a3-bc2c-bc08184ac6cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965593741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2965593741
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2845190069
Short name T703
Test name
Test status
Simulation time 21319549 ps
CPU time 0.81 seconds
Started Jul 31 06:03:15 PM PDT 24
Finished Jul 31 06:03:16 PM PDT 24
Peak memory 201120 kb
Host smart-b470698a-8eca-4cda-86e1-d9039f821c7d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845190069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2845190069
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.3184961374
Short name T158
Test name
Test status
Simulation time 52786474 ps
CPU time 0.93 seconds
Started Jul 31 06:02:56 PM PDT 24
Finished Jul 31 06:02:57 PM PDT 24
Peak memory 201048 kb
Host smart-ea8664ae-9819-42b8-9a90-a2418697b50e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184961374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3184961374
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.3007923583
Short name T463
Test name
Test status
Simulation time 1303734463 ps
CPU time 5 seconds
Started Jul 31 06:02:58 PM PDT 24
Finished Jul 31 06:03:03 PM PDT 24
Peak memory 201144 kb
Host smart-bfbc2ab8-6755-48c7-b462-fe963a967093
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007923583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.3007923583
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2345473902
Short name T317
Test name
Test status
Simulation time 89642703 ps
CPU time 1.06 seconds
Started Jul 31 06:03:03 PM PDT 24
Finished Jul 31 06:03:04 PM PDT 24
Peak memory 201108 kb
Host smart-1ec1e6de-d4a7-4865-bb8c-bf5ed86fd188
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345473902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.2345473902
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.749720782
Short name T770
Test name
Test status
Simulation time 37252441 ps
CPU time 0.89 seconds
Started Jul 31 06:03:07 PM PDT 24
Finished Jul 31 06:03:08 PM PDT 24
Peak memory 201104 kb
Host smart-c2a1d326-3433-472a-b1e2-d573dae3a5a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749720782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_clk_byp_req_intersig_mubi.749720782
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2884483209
Short name T594
Test name
Test status
Simulation time 58637235 ps
CPU time 0.9 seconds
Started Jul 31 06:03:04 PM PDT 24
Finished Jul 31 06:03:05 PM PDT 24
Peak memory 201084 kb
Host smart-85710df9-9ae1-4d4b-8c58-77405963e2ed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884483209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2884483209
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1499021756
Short name T26
Test name
Test status
Simulation time 15041430 ps
CPU time 0.75 seconds
Started Jul 31 06:03:03 PM PDT 24
Finished Jul 31 06:03:04 PM PDT 24
Peak memory 201004 kb
Host smart-83830f46-9157-443f-9382-9bf9a4b2e55a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499021756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1499021756
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1975627357
Short name T457
Test name
Test status
Simulation time 61534629 ps
CPU time 0.89 seconds
Started Jul 31 06:03:16 PM PDT 24
Finished Jul 31 06:03:17 PM PDT 24
Peak memory 201048 kb
Host smart-ecc6ceb0-4a6a-42cf-b427-8abd131f5e07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975627357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1975627357
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2871968872
Short name T261
Test name
Test status
Simulation time 20336254 ps
CPU time 0.88 seconds
Started Jul 31 06:02:57 PM PDT 24
Finished Jul 31 06:02:58 PM PDT 24
Peak memory 201096 kb
Host smart-66822ef6-9a8e-4ba1-baea-793803138dcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871968872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2871968872
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_trans.4052683203
Short name T193
Test name
Test status
Simulation time 53187768 ps
CPU time 1.04 seconds
Started Jul 31 06:03:02 PM PDT 24
Finished Jul 31 06:03:03 PM PDT 24
Peak memory 201012 kb
Host smart-a7977aae-fd9b-489a-b5e4-b252e8e9956a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052683203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.4052683203
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.4179302107
Short name T433
Test name
Test status
Simulation time 15266245 ps
CPU time 0.77 seconds
Started Jul 31 06:03:40 PM PDT 24
Finished Jul 31 06:03:41 PM PDT 24
Peak memory 201108 kb
Host smart-9e3e51d6-7c69-48d3-881f-e1cae49fa802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179302107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.4179302107
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3108258476
Short name T105
Test name
Test status
Simulation time 21878072 ps
CPU time 0.85 seconds
Started Jul 31 06:03:37 PM PDT 24
Finished Jul 31 06:03:38 PM PDT 24
Peak memory 201064 kb
Host smart-e5e90f26-3a43-47fc-b0b0-fb0a4c546ce9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108258476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3108258476
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.311201800
Short name T687
Test name
Test status
Simulation time 32450999 ps
CPU time 0.74 seconds
Started Jul 31 06:03:27 PM PDT 24
Finished Jul 31 06:03:28 PM PDT 24
Peak memory 200264 kb
Host smart-d5b9f2e4-9baf-4171-b426-d7f6bdac4fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311201800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.311201800
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3899193695
Short name T27
Test name
Test status
Simulation time 80261475 ps
CPU time 1.03 seconds
Started Jul 31 06:03:34 PM PDT 24
Finished Jul 31 06:03:35 PM PDT 24
Peak memory 201000 kb
Host smart-49d08702-31ef-4549-9396-bb99bbccb943
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899193695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3899193695
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.3327488424
Short name T289
Test name
Test status
Simulation time 282238333 ps
CPU time 1.57 seconds
Started Jul 31 06:03:24 PM PDT 24
Finished Jul 31 06:03:26 PM PDT 24
Peak memory 201024 kb
Host smart-7b1b9bf9-197e-4d39-abe8-43a8363b8168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327488424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.3327488424
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3609032506
Short name T745
Test name
Test status
Simulation time 1670877163 ps
CPU time 7.47 seconds
Started Jul 31 06:03:30 PM PDT 24
Finished Jul 31 06:03:37 PM PDT 24
Peak memory 201152 kb
Host smart-4428696d-5559-4cdf-a507-c26ab14260f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609032506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3609032506
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1672930602
Short name T664
Test name
Test status
Simulation time 138777578 ps
CPU time 1.68 seconds
Started Jul 31 06:03:26 PM PDT 24
Finished Jul 31 06:03:28 PM PDT 24
Peak memory 201164 kb
Host smart-9433d2fe-d352-4833-9760-9721f01b56aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672930602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1672930602
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3064901390
Short name T634
Test name
Test status
Simulation time 62389966 ps
CPU time 0.94 seconds
Started Jul 31 06:03:32 PM PDT 24
Finished Jul 31 06:03:33 PM PDT 24
Peak memory 201092 kb
Host smart-5ac638c0-c8fe-426f-b161-03eb30c2da42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064901390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3064901390
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.3525425079
Short name T619
Test name
Test status
Simulation time 37154985 ps
CPU time 0.8 seconds
Started Jul 31 06:03:38 PM PDT 24
Finished Jul 31 06:03:39 PM PDT 24
Peak memory 201060 kb
Host smart-1810f86a-0db2-4cde-a486-1d17782fdd0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525425079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.3525425079
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.4064576821
Short name T414
Test name
Test status
Simulation time 19763966 ps
CPU time 0.82 seconds
Started Jul 31 06:03:33 PM PDT 24
Finished Jul 31 06:03:34 PM PDT 24
Peak memory 200988 kb
Host smart-1b6a5427-d4d5-4850-a898-d4e7e87085dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064576821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.4064576821
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.3234294739
Short name T483
Test name
Test status
Simulation time 64072840 ps
CPU time 0.9 seconds
Started Jul 31 06:03:27 PM PDT 24
Finished Jul 31 06:03:28 PM PDT 24
Peak memory 201056 kb
Host smart-a8013914-464c-4ee0-9d28-28228f144bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234294739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3234294739
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.1897442169
Short name T425
Test name
Test status
Simulation time 590560968 ps
CPU time 3.17 seconds
Started Jul 31 06:03:31 PM PDT 24
Finished Jul 31 06:03:35 PM PDT 24
Peak memory 201232 kb
Host smart-4b912679-d849-46c5-987b-c6fdf9133e58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897442169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1897442169
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.3673095369
Short name T124
Test name
Test status
Simulation time 21633982 ps
CPU time 0.84 seconds
Started Jul 31 06:03:21 PM PDT 24
Finished Jul 31 06:03:22 PM PDT 24
Peak memory 201060 kb
Host smart-298ebbc2-a379-4e57-92a7-4f0377b4db11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673095369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3673095369
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.13519295
Short name T25
Test name
Test status
Simulation time 532159012 ps
CPU time 3.11 seconds
Started Jul 31 06:03:40 PM PDT 24
Finished Jul 31 06:03:43 PM PDT 24
Peak memory 201196 kb
Host smart-4855a8b2-a5a5-4d5e-96e2-111c2f58072f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_stress_all.13519295
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.3719857698
Short name T764
Test name
Test status
Simulation time 29959847 ps
CPU time 0.93 seconds
Started Jul 31 06:03:26 PM PDT 24
Finished Jul 31 06:03:27 PM PDT 24
Peak memory 201080 kb
Host smart-2789cdd5-2815-4873-b280-f2d2423b2696
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719857698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.3719857698
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.4163146111
Short name T247
Test name
Test status
Simulation time 24827584 ps
CPU time 0.76 seconds
Started Jul 31 06:04:05 PM PDT 24
Finished Jul 31 06:04:06 PM PDT 24
Peak memory 200980 kb
Host smart-82efbda5-ea42-4788-ae12-49d1cba2b214
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163146111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.4163146111
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2633132674
Short name T756
Test name
Test status
Simulation time 43308834 ps
CPU time 0.88 seconds
Started Jul 31 06:04:00 PM PDT 24
Finished Jul 31 06:04:01 PM PDT 24
Peak memory 201108 kb
Host smart-7aa11a7b-3f22-424c-9fca-8ef647c4b3ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633132674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2633132674
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.382309420
Short name T240
Test name
Test status
Simulation time 46122499 ps
CPU time 0.8 seconds
Started Jul 31 06:03:58 PM PDT 24
Finished Jul 31 06:03:59 PM PDT 24
Peak memory 200972 kb
Host smart-2508daa7-f2bb-48ea-92f1-f90e55c8903e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382309420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.382309420
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1733401411
Short name T644
Test name
Test status
Simulation time 12868787 ps
CPU time 0.73 seconds
Started Jul 31 06:04:05 PM PDT 24
Finished Jul 31 06:04:06 PM PDT 24
Peak memory 201036 kb
Host smart-9f0a16c5-d4e5-4bb4-b17e-cc0032e849ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733401411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1733401411
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3750899737
Short name T211
Test name
Test status
Simulation time 20198566 ps
CPU time 0.88 seconds
Started Jul 31 06:03:40 PM PDT 24
Finished Jul 31 06:03:41 PM PDT 24
Peak memory 201004 kb
Host smart-480b8257-3680-41c4-80bb-2efdf87439b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750899737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3750899737
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.2757754342
Short name T220
Test name
Test status
Simulation time 1400715143 ps
CPU time 11.42 seconds
Started Jul 31 06:03:45 PM PDT 24
Finished Jul 31 06:03:56 PM PDT 24
Peak memory 201156 kb
Host smart-0f25cd98-457d-4e95-bb62-ad0783d5ce57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757754342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.2757754342
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3208540732
Short name T206
Test name
Test status
Simulation time 862277768 ps
CPU time 4.69 seconds
Started Jul 31 06:03:47 PM PDT 24
Finished Jul 31 06:03:52 PM PDT 24
Peak memory 201196 kb
Host smart-10610fa8-fa3e-4377-bc10-16021bc46b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208540732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3208540732
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3705090276
Short name T99
Test name
Test status
Simulation time 125812811 ps
CPU time 1.35 seconds
Started Jul 31 06:03:58 PM PDT 24
Finished Jul 31 06:04:00 PM PDT 24
Peak memory 201120 kb
Host smart-ce53d3c2-d576-4efc-a014-5feef511f147
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705090276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3705090276
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2440423065
Short name T651
Test name
Test status
Simulation time 24921039 ps
CPU time 0.95 seconds
Started Jul 31 06:04:02 PM PDT 24
Finished Jul 31 06:04:03 PM PDT 24
Peak memory 201052 kb
Host smart-a3b22075-94ee-4800-8b78-227542f43b25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440423065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2440423065
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.223098863
Short name T172
Test name
Test status
Simulation time 43253697 ps
CPU time 0.92 seconds
Started Jul 31 06:04:03 PM PDT 24
Finished Jul 31 06:04:04 PM PDT 24
Peak memory 201108 kb
Host smart-cee40656-1f2f-43f5-8676-18a2bba0fa39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223098863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.223098863
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.349209024
Short name T202
Test name
Test status
Simulation time 23976389 ps
CPU time 0.8 seconds
Started Jul 31 06:03:53 PM PDT 24
Finished Jul 31 06:03:53 PM PDT 24
Peak memory 201048 kb
Host smart-a7fc77ba-e8dd-4901-8353-e429a78285c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349209024 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.349209024
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.607015526
Short name T331
Test name
Test status
Simulation time 412399886 ps
CPU time 2.6 seconds
Started Jul 31 06:04:04 PM PDT 24
Finished Jul 31 06:04:07 PM PDT 24
Peak memory 201044 kb
Host smart-0d70e110-3fe7-4594-8bbc-cedf21f3b711
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607015526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.607015526
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2758911174
Short name T750
Test name
Test status
Simulation time 63223842 ps
CPU time 1.04 seconds
Started Jul 31 06:03:41 PM PDT 24
Finished Jul 31 06:03:42 PM PDT 24
Peak memory 201004 kb
Host smart-1979610c-701c-4c1b-94b7-e1242b4dbc3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758911174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2758911174
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3367470255
Short name T530
Test name
Test status
Simulation time 5714739554 ps
CPU time 22.97 seconds
Started Jul 31 06:04:07 PM PDT 24
Finished Jul 31 06:04:30 PM PDT 24
Peak memory 201472 kb
Host smart-a9b1e8d7-1473-4c68-8d54-a82aca46af90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367470255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3367470255
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.3033375371
Short name T244
Test name
Test status
Simulation time 29626894 ps
CPU time 0.82 seconds
Started Jul 31 06:03:52 PM PDT 24
Finished Jul 31 06:03:53 PM PDT 24
Peak memory 201040 kb
Host smart-ece1a1b4-9f49-47ae-8ccf-0719d3542d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033375371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.3033375371
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3140616667
Short name T262
Test name
Test status
Simulation time 14792643 ps
CPU time 0.75 seconds
Started Jul 31 06:04:24 PM PDT 24
Finished Jul 31 06:04:25 PM PDT 24
Peak memory 201048 kb
Host smart-5df4ffda-6501-4657-bda4-e2e3ba0bda15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140616667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3140616667
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.1536031429
Short name T497
Test name
Test status
Simulation time 33697312 ps
CPU time 0.88 seconds
Started Jul 31 06:04:18 PM PDT 24
Finished Jul 31 06:04:19 PM PDT 24
Peak memory 201024 kb
Host smart-4a88a2cc-6ddf-4280-bfea-cb7d16315583
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536031429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.1536031429
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.3238796000
Short name T217
Test name
Test status
Simulation time 57571686 ps
CPU time 0.81 seconds
Started Jul 31 06:04:15 PM PDT 24
Finished Jul 31 06:04:16 PM PDT 24
Peak memory 200276 kb
Host smart-ccf53ada-dc9f-4f4d-8e86-2678a1540b6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238796000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3238796000
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.2866583803
Short name T477
Test name
Test status
Simulation time 25337584 ps
CPU time 0.84 seconds
Started Jul 31 06:04:18 PM PDT 24
Finished Jul 31 06:04:19 PM PDT 24
Peak memory 201096 kb
Host smart-1a92fb58-5558-4c9c-8c01-50d989816a80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866583803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.2866583803
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.4232336189
Short name T387
Test name
Test status
Simulation time 65877343 ps
CPU time 1.06 seconds
Started Jul 31 06:04:10 PM PDT 24
Finished Jul 31 06:04:11 PM PDT 24
Peak memory 201012 kb
Host smart-2f407c96-aad4-4558-90be-c66b4cbb3848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232336189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.4232336189
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3925119602
Short name T431
Test name
Test status
Simulation time 681603210 ps
CPU time 5.86 seconds
Started Jul 31 06:04:09 PM PDT 24
Finished Jul 31 06:04:15 PM PDT 24
Peak memory 201148 kb
Host smart-bbdf5cff-379e-466b-8a88-409e4ec46574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925119602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3925119602
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.2863524798
Short name T518
Test name
Test status
Simulation time 161287108 ps
CPU time 1.22 seconds
Started Jul 31 06:04:10 PM PDT 24
Finished Jul 31 06:04:11 PM PDT 24
Peak memory 201180 kb
Host smart-cd9681bb-37e5-4642-927e-edfed998de3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863524798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.2863524798
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.4235988300
Short name T787
Test name
Test status
Simulation time 40085663 ps
CPU time 1.07 seconds
Started Jul 31 06:04:12 PM PDT 24
Finished Jul 31 06:04:13 PM PDT 24
Peak memory 201096 kb
Host smart-843a7bb6-d15d-4930-9a74-d5f7c44b76dc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235988300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.4235988300
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3666759478
Short name T31
Test name
Test status
Simulation time 23378453 ps
CPU time 0.89 seconds
Started Jul 31 06:04:18 PM PDT 24
Finished Jul 31 06:04:19 PM PDT 24
Peak memory 201000 kb
Host smart-bbc0c63d-0a1f-4798-9600-a424d8930279
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666759478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3666759478
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1814584894
Short name T209
Test name
Test status
Simulation time 106490790 ps
CPU time 1.03 seconds
Started Jul 31 06:04:17 PM PDT 24
Finished Jul 31 06:04:18 PM PDT 24
Peak memory 201024 kb
Host smart-fe8235d0-7fbe-4f50-800a-17579a71b7f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814584894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1814584894
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.3273019028
Short name T572
Test name
Test status
Simulation time 39080047 ps
CPU time 0.82 seconds
Started Jul 31 06:04:18 PM PDT 24
Finished Jul 31 06:04:19 PM PDT 24
Peak memory 201036 kb
Host smart-9af567ec-3685-424f-98be-c333c7aa50a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273019028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3273019028
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.63930879
Short name T680
Test name
Test status
Simulation time 451061833 ps
CPU time 2.96 seconds
Started Jul 31 06:04:18 PM PDT 24
Finished Jul 31 06:04:21 PM PDT 24
Peak memory 201016 kb
Host smart-9f88ec1a-50e7-4b56-b115-bd65e32747d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63930879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.63930879
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.1163793234
Short name T749
Test name
Test status
Simulation time 212103677 ps
CPU time 1.4 seconds
Started Jul 31 06:04:04 PM PDT 24
Finished Jul 31 06:04:05 PM PDT 24
Peak memory 201108 kb
Host smart-8a72331e-d1f2-41c7-aedf-2f5dba5e6893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163793234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.1163793234
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.1365593561
Short name T819
Test name
Test status
Simulation time 7778527261 ps
CPU time 27.16 seconds
Started Jul 31 06:04:24 PM PDT 24
Finished Jul 31 06:04:52 PM PDT 24
Peak memory 201420 kb
Host smart-4b8ed165-6fc0-4eb2-9ad3-8c068b2e7bcd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365593561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.1365593561
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1885644601
Short name T544
Test name
Test status
Simulation time 47762488 ps
CPU time 1.02 seconds
Started Jul 31 06:04:15 PM PDT 24
Finished Jul 31 06:04:16 PM PDT 24
Peak memory 201100 kb
Host smart-9c95e479-9f83-4c71-8ec3-89de09023f17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885644601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1885644601
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2719332743
Short name T662
Test name
Test status
Simulation time 35185619 ps
CPU time 0.8 seconds
Started Jul 31 06:04:34 PM PDT 24
Finished Jul 31 06:04:35 PM PDT 24
Peak memory 201112 kb
Host smart-dd98eafb-e152-4756-bb5a-2e3921122deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719332743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2719332743
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1597189663
Short name T762
Test name
Test status
Simulation time 26278026 ps
CPU time 0.78 seconds
Started Jul 31 06:04:28 PM PDT 24
Finished Jul 31 06:04:29 PM PDT 24
Peak memory 201012 kb
Host smart-2cd8a71a-f5df-4bb9-80d3-84922338f024
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597189663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.1597189663
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.131200348
Short name T439
Test name
Test status
Simulation time 36229115 ps
CPU time 0.83 seconds
Started Jul 31 06:04:29 PM PDT 24
Finished Jul 31 06:04:30 PM PDT 24
Peak memory 200280 kb
Host smart-a649baec-c92f-434c-8abd-6cdb99116bea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131200348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.131200348
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.272412362
Short name T417
Test name
Test status
Simulation time 32961741 ps
CPU time 0.87 seconds
Started Jul 31 06:04:34 PM PDT 24
Finished Jul 31 06:04:35 PM PDT 24
Peak memory 201064 kb
Host smart-d8942360-066e-4be3-a070-08eb77dee56b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272412362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_div_intersig_mubi.272412362
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.4130219895
Short name T335
Test name
Test status
Simulation time 43936680 ps
CPU time 0.82 seconds
Started Jul 31 06:04:21 PM PDT 24
Finished Jul 31 06:04:22 PM PDT 24
Peak memory 200956 kb
Host smart-444f6d0c-c75e-49f0-bafb-ee4f5bc0b5f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130219895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.4130219895
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.984475247
Short name T23
Test name
Test status
Simulation time 836469825 ps
CPU time 4.26 seconds
Started Jul 31 06:04:25 PM PDT 24
Finished Jul 31 06:04:30 PM PDT 24
Peak memory 201136 kb
Host smart-b4ac313c-d9e9-409c-b31f-ee55eefc678b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984475247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.984475247
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.4090687654
Short name T312
Test name
Test status
Simulation time 982547270 ps
CPU time 7.4 seconds
Started Jul 31 06:04:23 PM PDT 24
Finished Jul 31 06:04:31 PM PDT 24
Peak memory 201212 kb
Host smart-a5769a8c-7bb8-4f63-9cc2-1a7992cbfa76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090687654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.4090687654
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3004528818
Short name T567
Test name
Test status
Simulation time 56881066 ps
CPU time 0.94 seconds
Started Jul 31 06:04:29 PM PDT 24
Finished Jul 31 06:04:30 PM PDT 24
Peak memory 201088 kb
Host smart-0a3a3627-3486-4ebb-9afa-8c3a1dc5c436
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004528818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3004528818
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.2741879751
Short name T131
Test name
Test status
Simulation time 104873129 ps
CPU time 1.04 seconds
Started Jul 31 06:04:26 PM PDT 24
Finished Jul 31 06:04:28 PM PDT 24
Peak memory 201080 kb
Host smart-5f48c9cc-42aa-459f-9913-8cb61a48b8f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741879751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.2741879751
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3319915081
Short name T246
Test name
Test status
Simulation time 27152194 ps
CPU time 0.86 seconds
Started Jul 31 06:04:29 PM PDT 24
Finished Jul 31 06:04:29 PM PDT 24
Peak memory 201092 kb
Host smart-82ee0d1c-e345-4deb-9176-8ea674c38cdf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319915081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.3319915081
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2179067158
Short name T224
Test name
Test status
Simulation time 36841725 ps
CPU time 0.78 seconds
Started Jul 31 06:04:25 PM PDT 24
Finished Jul 31 06:04:26 PM PDT 24
Peak memory 201100 kb
Host smart-67c0874d-3787-4c3b-b4db-0c46fc449f04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179067158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2179067158
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1005444539
Short name T355
Test name
Test status
Simulation time 343351080 ps
CPU time 1.7 seconds
Started Jul 31 06:04:35 PM PDT 24
Finished Jul 31 06:04:36 PM PDT 24
Peak memory 201040 kb
Host smart-1165cdff-ceb4-44ed-bd6d-8d78e8841433
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005444539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1005444539
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1667847669
Short name T152
Test name
Test status
Simulation time 23717035 ps
CPU time 0.85 seconds
Started Jul 31 06:04:24 PM PDT 24
Finished Jul 31 06:04:25 PM PDT 24
Peak memory 200984 kb
Host smart-1438b97d-a666-4d00-9054-d8e998d5d313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667847669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1667847669
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.145086960
Short name T459
Test name
Test status
Simulation time 3287989501 ps
CPU time 13.3 seconds
Started Jul 31 06:04:32 PM PDT 24
Finished Jul 31 06:04:45 PM PDT 24
Peak memory 201472 kb
Host smart-f91c17e8-9883-43a9-8ef0-496fab40b98d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145086960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.145086960
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.33753349
Short name T528
Test name
Test status
Simulation time 117418242855 ps
CPU time 831.45 seconds
Started Jul 31 06:04:35 PM PDT 24
Finished Jul 31 06:18:26 PM PDT 24
Peak memory 217852 kb
Host smart-7aa92eed-7bf3-4ffd-9da9-47fb75c94c58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=33753349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.33753349
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.3569921246
Short name T309
Test name
Test status
Simulation time 89437407 ps
CPU time 1.06 seconds
Started Jul 31 06:04:25 PM PDT 24
Finished Jul 31 06:04:26 PM PDT 24
Peak memory 201108 kb
Host smart-ba276ad8-b198-4240-995f-e1d26a36776d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569921246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3569921246
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1183322113
Short name T79
Test name
Test status
Simulation time 46781487 ps
CPU time 0.85 seconds
Started Jul 31 06:04:47 PM PDT 24
Finished Jul 31 06:04:48 PM PDT 24
Peak memory 201064 kb
Host smart-cf2e5a71-98c2-4990-a3f9-65f6497a9372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183322113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1183322113
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.2591103471
Short name T274
Test name
Test status
Simulation time 34008828 ps
CPU time 0.85 seconds
Started Jul 31 06:04:42 PM PDT 24
Finished Jul 31 06:04:43 PM PDT 24
Peak memory 201108 kb
Host smart-f26320ff-6c44-4c23-b58c-72f2661ad630
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591103471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.2591103471
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.3410515011
Short name T810
Test name
Test status
Simulation time 81389598 ps
CPU time 0.89 seconds
Started Jul 31 06:04:42 PM PDT 24
Finished Jul 31 06:04:43 PM PDT 24
Peak memory 200244 kb
Host smart-9f34271f-f010-450d-9555-18d6f4bd461c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410515011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.3410515011
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.1095401667
Short name T257
Test name
Test status
Simulation time 26029147 ps
CPU time 0.86 seconds
Started Jul 31 06:04:43 PM PDT 24
Finished Jul 31 06:04:44 PM PDT 24
Peak memory 201104 kb
Host smart-c2f058c9-d42a-4368-823e-c51ffcc3e374
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095401667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.1095401667
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.301292971
Short name T473
Test name
Test status
Simulation time 18527306 ps
CPU time 0.72 seconds
Started Jul 31 06:04:37 PM PDT 24
Finished Jul 31 06:04:38 PM PDT 24
Peak memory 201020 kb
Host smart-130f7ce2-f6b2-4016-a9d0-5c10f1b4c4e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301292971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.301292971
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.2517620187
Short name T383
Test name
Test status
Simulation time 567428667 ps
CPU time 3.65 seconds
Started Jul 31 06:04:38 PM PDT 24
Finished Jul 31 06:04:42 PM PDT 24
Peak memory 201120 kb
Host smart-c1bfad43-a359-4bac-bae5-6bb9e0b67ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517620187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.2517620187
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.3022874996
Short name T610
Test name
Test status
Simulation time 1336181927 ps
CPU time 10.4 seconds
Started Jul 31 06:04:38 PM PDT 24
Finished Jul 31 06:04:48 PM PDT 24
Peak memory 201160 kb
Host smart-bdff0f1b-8737-42cc-89c2-81474fc5f008
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022874996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.3022874996
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.3346425884
Short name T757
Test name
Test status
Simulation time 27473313 ps
CPU time 0.78 seconds
Started Jul 31 06:04:42 PM PDT 24
Finished Jul 31 06:04:43 PM PDT 24
Peak memory 201052 kb
Host smart-43fb0299-d508-470e-b55e-239c12d989f3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346425884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.3346425884
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2543905071
Short name T303
Test name
Test status
Simulation time 36738453 ps
CPU time 0.91 seconds
Started Jul 31 06:04:41 PM PDT 24
Finished Jul 31 06:04:42 PM PDT 24
Peak memory 201084 kb
Host smart-a2f83227-bc7e-452c-a416-061929a97ea6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543905071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2543905071
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1205611260
Short name T605
Test name
Test status
Simulation time 15871907 ps
CPU time 0.77 seconds
Started Jul 31 06:04:43 PM PDT 24
Finished Jul 31 06:04:44 PM PDT 24
Peak memory 201112 kb
Host smart-f084253d-17d7-472a-8a8e-ee3e42e74ac2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205611260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.1205611260
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.3311783850
Short name T164
Test name
Test status
Simulation time 16450503 ps
CPU time 0.76 seconds
Started Jul 31 06:04:38 PM PDT 24
Finished Jul 31 06:04:39 PM PDT 24
Peak memory 201044 kb
Host smart-aff5b689-76ad-4543-8acc-298e99598533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311783850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3311783850
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.3564053169
Short name T412
Test name
Test status
Simulation time 846938243 ps
CPU time 4.88 seconds
Started Jul 31 06:04:48 PM PDT 24
Finished Jul 31 06:04:53 PM PDT 24
Peak memory 201284 kb
Host smart-bb762dc3-8a92-4230-bb7a-7466ab700b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564053169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.3564053169
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.1836113363
Short name T629
Test name
Test status
Simulation time 155349595 ps
CPU time 1.24 seconds
Started Jul 31 06:04:38 PM PDT 24
Finished Jul 31 06:04:39 PM PDT 24
Peak memory 201104 kb
Host smart-bb6c553d-710e-4d93-859a-a08da6858444
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836113363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1836113363
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2427679778
Short name T726
Test name
Test status
Simulation time 58201829 ps
CPU time 1.12 seconds
Started Jul 31 06:04:46 PM PDT 24
Finished Jul 31 06:04:47 PM PDT 24
Peak memory 200940 kb
Host smart-b73662e4-53a9-415b-8bd6-a5251088cc81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427679778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2427679778
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3961425544
Short name T699
Test name
Test status
Simulation time 50986065 ps
CPU time 0.83 seconds
Started Jul 31 06:04:37 PM PDT 24
Finished Jul 31 06:04:38 PM PDT 24
Peak memory 201100 kb
Host smart-edb35a78-2b24-49f9-a443-3dd3b84d37eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961425544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3961425544
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.464771070
Short name T235
Test name
Test status
Simulation time 14395806 ps
CPU time 0.71 seconds
Started Jul 31 06:04:57 PM PDT 24
Finished Jul 31 06:04:58 PM PDT 24
Peak memory 201012 kb
Host smart-d036f969-35fb-460f-8a92-8d2c2a2213b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464771070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkm
gr_alert_test.464771070
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3770741646
Short name T332
Test name
Test status
Simulation time 72519446 ps
CPU time 1.03 seconds
Started Jul 31 06:05:00 PM PDT 24
Finished Jul 31 06:05:01 PM PDT 24
Peak memory 201112 kb
Host smart-c0bae96c-e8cd-451c-bc3d-9dbe523683d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770741646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3770741646
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.535798750
Short name T43
Test name
Test status
Simulation time 16412812 ps
CPU time 0.7 seconds
Started Jul 31 06:04:48 PM PDT 24
Finished Jul 31 06:04:48 PM PDT 24
Peak memory 200244 kb
Host smart-fcc1906c-eb77-42cc-b4e7-216c6471643c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535798750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.535798750
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.3632622976
Short name T100
Test name
Test status
Simulation time 18307226 ps
CPU time 0.78 seconds
Started Jul 31 06:04:56 PM PDT 24
Finished Jul 31 06:04:57 PM PDT 24
Peak memory 201084 kb
Host smart-806a85ad-ce64-40aa-91c2-e8c43a1bab72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632622976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.3632622976
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.279680948
Short name T738
Test name
Test status
Simulation time 28489450 ps
CPU time 0.72 seconds
Started Jul 31 06:04:47 PM PDT 24
Finished Jul 31 06:04:48 PM PDT 24
Peak memory 201036 kb
Host smart-1b7c7728-d8ce-4b83-a39f-ee1370b9c1fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279680948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.279680948
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3654197392
Short name T337
Test name
Test status
Simulation time 2006145927 ps
CPU time 12.1 seconds
Started Jul 31 06:04:47 PM PDT 24
Finished Jul 31 06:04:59 PM PDT 24
Peak memory 201328 kb
Host smart-c9f131fc-fbe2-4e64-8ffd-f6dd6b23a318
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654197392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3654197392
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.1805829196
Short name T344
Test name
Test status
Simulation time 619914433 ps
CPU time 4.46 seconds
Started Jul 31 06:04:53 PM PDT 24
Finished Jul 31 06:04:57 PM PDT 24
Peak memory 201152 kb
Host smart-388dc8b8-7923-4827-821f-1fa4f838f0e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805829196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.1805829196
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.114052592
Short name T195
Test name
Test status
Simulation time 39217528 ps
CPU time 0.9 seconds
Started Jul 31 06:04:50 PM PDT 24
Finished Jul 31 06:04:51 PM PDT 24
Peak memory 200732 kb
Host smart-d8acad8c-4254-427a-8960-d67434627249
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114052592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_idle_intersig_mubi.114052592
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1531156060
Short name T277
Test name
Test status
Simulation time 51376945 ps
CPU time 0.83 seconds
Started Jul 31 06:04:52 PM PDT 24
Finished Jul 31 06:04:53 PM PDT 24
Peak memory 201076 kb
Host smart-fe7f1b1f-8f7c-436f-9d4b-04434698d94f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531156060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1531156060
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3619645879
Short name T343
Test name
Test status
Simulation time 55921704 ps
CPU time 0.89 seconds
Started Jul 31 06:04:53 PM PDT 24
Finished Jul 31 06:04:54 PM PDT 24
Peak memory 201016 kb
Host smart-eb9ce61f-355c-4bcd-8ff2-d388ddcba731
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619645879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.3619645879
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.2657370667
Short name T765
Test name
Test status
Simulation time 15223744 ps
CPU time 0.74 seconds
Started Jul 31 06:04:55 PM PDT 24
Finished Jul 31 06:04:56 PM PDT 24
Peak memory 201056 kb
Host smart-e822fe32-5766-49b6-9f7f-0b6af0d5fdfd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657370667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.2657370667
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.3597200509
Short name T476
Test name
Test status
Simulation time 1418125403 ps
CPU time 4.7 seconds
Started Jul 31 06:04:57 PM PDT 24
Finished Jul 31 06:05:02 PM PDT 24
Peak memory 201208 kb
Host smart-d678d71f-6518-4dcf-bbab-7bff95f74edb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597200509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3597200509
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.2842270820
Short name T424
Test name
Test status
Simulation time 25577925 ps
CPU time 0.87 seconds
Started Jul 31 06:04:48 PM PDT 24
Finished Jul 31 06:04:49 PM PDT 24
Peak memory 201064 kb
Host smart-9468f86f-b913-4ff8-8220-ffd1597d30d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842270820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.2842270820
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.1635379833
Short name T733
Test name
Test status
Simulation time 4311007586 ps
CPU time 31.16 seconds
Started Jul 31 06:04:58 PM PDT 24
Finished Jul 31 06:05:29 PM PDT 24
Peak memory 201440 kb
Host smart-dfb59a4f-2c77-4949-b910-2f7d199b4768
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635379833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.1635379833
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.2235280509
Short name T69
Test name
Test status
Simulation time 118311006677 ps
CPU time 1046.57 seconds
Started Jul 31 06:04:57 PM PDT 24
Finished Jul 31 06:22:23 PM PDT 24
Peak memory 215716 kb
Host smart-861b524e-a9cc-4138-96c0-a636832570bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2235280509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.2235280509
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.3657647531
Short name T783
Test name
Test status
Simulation time 70288180 ps
CPU time 1.09 seconds
Started Jul 31 06:04:50 PM PDT 24
Finished Jul 31 06:04:52 PM PDT 24
Peak memory 201084 kb
Host smart-20a9a137-4125-47e3-8c35-e5a55c328d61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657647531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.3657647531
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.3243678717
Short name T722
Test name
Test status
Simulation time 14936992 ps
CPU time 0.79 seconds
Started Jul 31 05:56:06 PM PDT 24
Finished Jul 31 05:56:07 PM PDT 24
Peak memory 201064 kb
Host smart-229fb7fe-81a1-4eb8-af7f-e7beabaffb58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243678717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.3243678717
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3336239212
Short name T692
Test name
Test status
Simulation time 263039727 ps
CPU time 1.56 seconds
Started Jul 31 05:56:00 PM PDT 24
Finished Jul 31 05:56:02 PM PDT 24
Peak memory 201080 kb
Host smart-da84b712-71a0-4dff-8a74-1fb326e01d0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336239212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3336239212
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.3214145185
Short name T255
Test name
Test status
Simulation time 18572553 ps
CPU time 0.74 seconds
Started Jul 31 05:55:49 PM PDT 24
Finished Jul 31 05:55:50 PM PDT 24
Peak memory 200340 kb
Host smart-1437f098-7997-439e-8e2e-2fce32ea2f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214145185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3214145185
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1114629485
Short name T804
Test name
Test status
Simulation time 68887100 ps
CPU time 0.95 seconds
Started Jul 31 05:55:59 PM PDT 24
Finished Jul 31 05:56:00 PM PDT 24
Peak memory 201124 kb
Host smart-24af729a-1197-4b0b-b2f3-154497eb1a4a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114629485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.1114629485
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.1356205185
Short name T626
Test name
Test status
Simulation time 24233439 ps
CPU time 0.86 seconds
Started Jul 31 05:55:42 PM PDT 24
Finished Jul 31 05:55:43 PM PDT 24
Peak memory 200984 kb
Host smart-d3544874-b9c5-464e-812a-19486147a57f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356205185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1356205185
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.2186411767
Short name T389
Test name
Test status
Simulation time 2235360161 ps
CPU time 17.43 seconds
Started Jul 31 05:55:45 PM PDT 24
Finished Jul 31 05:56:02 PM PDT 24
Peak memory 201440 kb
Host smart-d7945291-8fb7-4656-a75f-fe548d271bae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186411767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2186411767
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.3934096908
Short name T339
Test name
Test status
Simulation time 735227530 ps
CPU time 4.92 seconds
Started Jul 31 05:55:47 PM PDT 24
Finished Jul 31 05:55:52 PM PDT 24
Peak memory 201180 kb
Host smart-af5a4378-04d1-42ba-a31d-a412f6b34c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934096908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.3934096908
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2164261964
Short name T658
Test name
Test status
Simulation time 46349077 ps
CPU time 0.95 seconds
Started Jul 31 05:55:50 PM PDT 24
Finished Jul 31 05:55:51 PM PDT 24
Peak memory 200984 kb
Host smart-9afa036a-fb96-470f-a906-6f8d588ac806
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164261964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.2164261964
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.3554818467
Short name T21
Test name
Test status
Simulation time 15581205 ps
CPU time 0.75 seconds
Started Jul 31 05:56:00 PM PDT 24
Finished Jul 31 05:56:01 PM PDT 24
Peak memory 201036 kb
Host smart-d5e70029-4f2f-41f3-9c24-907005123893
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554818467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.3554818467
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.2433616219
Short name T207
Test name
Test status
Simulation time 27922282 ps
CPU time 0.98 seconds
Started Jul 31 05:55:54 PM PDT 24
Finished Jul 31 05:55:55 PM PDT 24
Peak memory 201096 kb
Host smart-d67aceb0-8b06-4f34-92ab-8d14640429a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433616219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.2433616219
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.297158917
Short name T489
Test name
Test status
Simulation time 13874264 ps
CPU time 0.72 seconds
Started Jul 31 05:55:49 PM PDT 24
Finished Jul 31 05:55:50 PM PDT 24
Peak memory 201000 kb
Host smart-2c85a125-1a19-478a-83d4-3022f75cf1b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297158917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.297158917
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3824482559
Short name T378
Test name
Test status
Simulation time 1153844551 ps
CPU time 4.62 seconds
Started Jul 31 05:56:01 PM PDT 24
Finished Jul 31 05:56:06 PM PDT 24
Peak memory 201256 kb
Host smart-963c0db1-26f2-46c3-a940-7a567cf6521f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824482559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3824482559
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.857104529
Short name T56
Test name
Test status
Simulation time 623798778 ps
CPU time 4.07 seconds
Started Jul 31 05:56:01 PM PDT 24
Finished Jul 31 05:56:05 PM PDT 24
Peak memory 221924 kb
Host smart-75ad4f24-16ec-495c-8ee8-6aefee5f79bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857104529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr
_sec_cm.857104529
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.4287881613
Short name T593
Test name
Test status
Simulation time 69857601 ps
CPU time 0.97 seconds
Started Jul 31 05:55:44 PM PDT 24
Finished Jul 31 05:55:45 PM PDT 24
Peak memory 201072 kb
Host smart-4f384091-57e5-447f-90eb-cfaf88667409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287881613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.4287881613
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.1003973998
Short name T742
Test name
Test status
Simulation time 3174011265 ps
CPU time 14.59 seconds
Started Jul 31 05:56:06 PM PDT 24
Finished Jul 31 05:56:21 PM PDT 24
Peak memory 201412 kb
Host smart-4e30c22a-53d4-4b9e-890c-f31497cc6b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003973998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.1003973998
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all_with_rand_reset.2160237700
Short name T543
Test name
Test status
Simulation time 63911669715 ps
CPU time 418.29 seconds
Started Jul 31 05:56:07 PM PDT 24
Finished Jul 31 06:03:05 PM PDT 24
Peak memory 209752 kb
Host smart-5ccdb3f2-df24-44ab-8725-5e3588e1a446
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2160237700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2160237700
Directory /workspace/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.clkmgr_trans.1240229454
Short name T319
Test name
Test status
Simulation time 48544243 ps
CPU time 0.94 seconds
Started Jul 31 05:55:50 PM PDT 24
Finished Jul 31 05:55:51 PM PDT 24
Peak memory 201012 kb
Host smart-584e75a7-1183-4797-a94a-732b91f09dd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240229454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.1240229454
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.2851067692
Short name T557
Test name
Test status
Simulation time 19255306 ps
CPU time 0.79 seconds
Started Jul 31 06:05:07 PM PDT 24
Finished Jul 31 06:05:08 PM PDT 24
Peak memory 201096 kb
Host smart-f5bf7d11-b5e7-4834-998e-abd164f33b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851067692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.2851067692
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2091487267
Short name T614
Test name
Test status
Simulation time 45885161 ps
CPU time 0.81 seconds
Started Jul 31 06:05:07 PM PDT 24
Finished Jul 31 06:05:08 PM PDT 24
Peak memory 201052 kb
Host smart-3bb2208c-03a1-4511-beb4-2412bad7ec21
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091487267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.2091487267
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.610205143
Short name T214
Test name
Test status
Simulation time 13793842 ps
CPU time 0.71 seconds
Started Jul 31 06:05:02 PM PDT 24
Finished Jul 31 06:05:02 PM PDT 24
Peak memory 200256 kb
Host smart-d02270c2-a13c-4f0e-a3bf-7e78a7608a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610205143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.610205143
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2491122704
Short name T611
Test name
Test status
Simulation time 59346750 ps
CPU time 1.1 seconds
Started Jul 31 06:05:07 PM PDT 24
Finished Jul 31 06:05:09 PM PDT 24
Peak memory 201092 kb
Host smart-c40cb790-dd08-44df-a828-5b3ed9870cb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491122704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.2491122704
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1307426073
Short name T576
Test name
Test status
Simulation time 39429854 ps
CPU time 0.97 seconds
Started Jul 31 06:05:02 PM PDT 24
Finished Jul 31 06:05:03 PM PDT 24
Peak memory 201004 kb
Host smart-a3186c92-1cb8-4e07-be67-0db8de95d633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307426073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1307426073
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2961320987
Short name T646
Test name
Test status
Simulation time 437586250 ps
CPU time 3.91 seconds
Started Jul 31 06:05:03 PM PDT 24
Finished Jul 31 06:05:07 PM PDT 24
Peak memory 201100 kb
Host smart-516bec60-07a7-4ce7-a463-f536c86a2278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961320987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2961320987
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2511159617
Short name T712
Test name
Test status
Simulation time 397642308 ps
CPU time 2.21 seconds
Started Jul 31 06:05:01 PM PDT 24
Finished Jul 31 06:05:04 PM PDT 24
Peak memory 201112 kb
Host smart-1689d7cc-1085-42fc-b4e5-0708c23c2994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511159617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2511159617
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.811323348
Short name T222
Test name
Test status
Simulation time 38079829 ps
CPU time 1.07 seconds
Started Jul 31 06:05:07 PM PDT 24
Finished Jul 31 06:05:08 PM PDT 24
Peak memory 201012 kb
Host smart-6052346c-d871-47a3-8586-80672545ffeb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811323348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_idle_intersig_mubi.811323348
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.795207872
Short name T480
Test name
Test status
Simulation time 26306079 ps
CPU time 0.94 seconds
Started Jul 31 06:05:04 PM PDT 24
Finished Jul 31 06:05:05 PM PDT 24
Peak memory 201112 kb
Host smart-015b0b4e-b284-417e-b3a0-094af4b31909
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795207872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.795207872
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.4077953846
Short name T352
Test name
Test status
Simulation time 95895752 ps
CPU time 1.05 seconds
Started Jul 31 06:05:07 PM PDT 24
Finished Jul 31 06:05:08 PM PDT 24
Peak memory 201108 kb
Host smart-b35cb98b-0b97-43b5-8193-836814050369
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077953846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.4077953846
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.2582465607
Short name T76
Test name
Test status
Simulation time 18733377 ps
CPU time 0.88 seconds
Started Jul 31 06:05:02 PM PDT 24
Finished Jul 31 06:05:03 PM PDT 24
Peak memory 201068 kb
Host smart-35052efa-44e0-4928-a0e7-10b81a0a4dff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582465607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2582465607
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.1956393874
Short name T96
Test name
Test status
Simulation time 99745657 ps
CPU time 1.11 seconds
Started Jul 31 06:05:08 PM PDT 24
Finished Jul 31 06:05:09 PM PDT 24
Peak memory 201040 kb
Host smart-e0306920-df8d-432a-a650-e1c0c31b45cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956393874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.1956393874
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.80586626
Short name T327
Test name
Test status
Simulation time 242063113 ps
CPU time 1.53 seconds
Started Jul 31 06:05:02 PM PDT 24
Finished Jul 31 06:05:03 PM PDT 24
Peak memory 201052 kb
Host smart-e76268f8-f87a-4bfb-8b38-7766237f396f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80586626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.80586626
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.4062365985
Short name T454
Test name
Test status
Simulation time 1095321230 ps
CPU time 7.17 seconds
Started Jul 31 06:05:10 PM PDT 24
Finished Jul 31 06:05:17 PM PDT 24
Peak memory 201368 kb
Host smart-a0c5dc9b-828c-4d30-944f-df6997b8f87e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062365985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.4062365985
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.3657204861
Short name T542
Test name
Test status
Simulation time 48307997 ps
CPU time 0.9 seconds
Started Jul 31 06:05:01 PM PDT 24
Finished Jul 31 06:05:02 PM PDT 24
Peak memory 201100 kb
Host smart-bdf95e71-5272-4a33-98ea-7ecdb0664a99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657204861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3657204861
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.169539896
Short name T743
Test name
Test status
Simulation time 66067792 ps
CPU time 0.94 seconds
Started Jul 31 06:05:23 PM PDT 24
Finished Jul 31 06:05:24 PM PDT 24
Peak memory 201112 kb
Host smart-2edaca02-a69c-4fed-96b8-cafc27d84195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169539896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkm
gr_alert_test.169539896
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.268850240
Short name T236
Test name
Test status
Simulation time 13979754 ps
CPU time 0.74 seconds
Started Jul 31 06:05:17 PM PDT 24
Finished Jul 31 06:05:18 PM PDT 24
Peak memory 201056 kb
Host smart-3384cea3-1896-4c26-84df-8568d849db60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268850240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.268850240
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.2707620861
Short name T741
Test name
Test status
Simulation time 13586998 ps
CPU time 0.73 seconds
Started Jul 31 06:05:11 PM PDT 24
Finished Jul 31 06:05:12 PM PDT 24
Peak memory 200272 kb
Host smart-120b2146-ec75-46a0-9b9d-927649f023a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707620861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2707620861
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3949505000
Short name T717
Test name
Test status
Simulation time 50153167 ps
CPU time 1.02 seconds
Started Jul 31 06:05:17 PM PDT 24
Finished Jul 31 06:05:18 PM PDT 24
Peak memory 201100 kb
Host smart-d2ad6c5b-6458-46ec-96d4-90d6e89ef7e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949505000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.3949505000
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.262427627
Short name T494
Test name
Test status
Simulation time 102450710 ps
CPU time 1.2 seconds
Started Jul 31 06:05:11 PM PDT 24
Finished Jul 31 06:05:13 PM PDT 24
Peak memory 201008 kb
Host smart-1d8eefd2-5d02-468c-b6ba-86275afc4c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262427627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.262427627
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.3713263721
Short name T127
Test name
Test status
Simulation time 2240797376 ps
CPU time 9.88 seconds
Started Jul 31 06:05:14 PM PDT 24
Finished Jul 31 06:05:24 PM PDT 24
Peak memory 201412 kb
Host smart-ba96157a-fb89-48ff-85a7-d27455909a41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713263721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3713263721
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3572992533
Short name T491
Test name
Test status
Simulation time 2056287990 ps
CPU time 14.82 seconds
Started Jul 31 06:05:11 PM PDT 24
Finished Jul 31 06:05:26 PM PDT 24
Peak memory 201348 kb
Host smart-9e55c973-4f74-47d8-92fb-d4bd9b27e03b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572992533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3572992533
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.311519562
Short name T338
Test name
Test status
Simulation time 31478424 ps
CPU time 0.98 seconds
Started Jul 31 06:05:19 PM PDT 24
Finished Jul 31 06:05:20 PM PDT 24
Peak memory 200964 kb
Host smart-4d446a8d-1545-4405-b53d-19f5d3032c64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311519562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_idle_intersig_mubi.311519562
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1661846622
Short name T219
Test name
Test status
Simulation time 30659414 ps
CPU time 0.87 seconds
Started Jul 31 06:05:17 PM PDT 24
Finished Jul 31 06:05:18 PM PDT 24
Peak memory 201108 kb
Host smart-2bcca362-97a1-42f2-8e87-c8249c195598
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661846622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1661846622
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1764464695
Short name T281
Test name
Test status
Simulation time 169204150 ps
CPU time 1.36 seconds
Started Jul 31 06:05:18 PM PDT 24
Finished Jul 31 06:05:19 PM PDT 24
Peak memory 201068 kb
Host smart-dbaa9008-3097-4604-bdaa-3e2313315838
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764464695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1764464695
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.1151690892
Short name T200
Test name
Test status
Simulation time 17163071 ps
CPU time 0.76 seconds
Started Jul 31 06:05:11 PM PDT 24
Finished Jul 31 06:05:11 PM PDT 24
Peak memory 201036 kb
Host smart-2c3bdb8c-6801-4e2f-8f2d-12665a5c4014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151690892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1151690892
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.4030322626
Short name T469
Test name
Test status
Simulation time 516151676 ps
CPU time 2.43 seconds
Started Jul 31 06:05:17 PM PDT 24
Finished Jul 31 06:05:19 PM PDT 24
Peak memory 201056 kb
Host smart-f846432c-6be8-43e2-97aa-71b7b122c5c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030322626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.4030322626
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.3319040217
Short name T775
Test name
Test status
Simulation time 43043970 ps
CPU time 0.93 seconds
Started Jul 31 06:05:13 PM PDT 24
Finished Jul 31 06:05:14 PM PDT 24
Peak memory 201044 kb
Host smart-3e4d99c3-6436-46f7-bb4c-00fbabeeaf37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319040217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3319040217
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.550733053
Short name T427
Test name
Test status
Simulation time 6012345706 ps
CPU time 43.54 seconds
Started Jul 31 06:05:20 PM PDT 24
Finished Jul 31 06:06:03 PM PDT 24
Peak memory 201368 kb
Host smart-ee205dab-f3d7-4c1d-bc88-3be06351a972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550733053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.550733053
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.719609036
Short name T253
Test name
Test status
Simulation time 110573311 ps
CPU time 1.27 seconds
Started Jul 31 06:05:13 PM PDT 24
Finished Jul 31 06:05:14 PM PDT 24
Peak memory 201104 kb
Host smart-e4ec4b8a-c04a-4f0b-bee5-501289a82fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719609036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.719609036
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.841207816
Short name T704
Test name
Test status
Simulation time 18766729 ps
CPU time 0.75 seconds
Started Jul 31 06:05:28 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 201112 kb
Host smart-b739f419-08cd-415c-bfe0-f5f0cfae9dbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841207816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm
gr_alert_test.841207816
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.940674446
Short name T798
Test name
Test status
Simulation time 52227969 ps
CPU time 0.85 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 201044 kb
Host smart-5e585b5a-abab-47a7-95d0-85f4bddb6573
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940674446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.940674446
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3413996441
Short name T707
Test name
Test status
Simulation time 39444593 ps
CPU time 0.77 seconds
Started Jul 31 06:05:23 PM PDT 24
Finished Jul 31 06:05:24 PM PDT 24
Peak memory 201020 kb
Host smart-2a9f62a0-6541-4631-a5c6-518be375ab49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413996441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3413996441
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.285562245
Short name T816
Test name
Test status
Simulation time 15543775 ps
CPU time 0.79 seconds
Started Jul 31 06:05:28 PM PDT 24
Finished Jul 31 06:05:29 PM PDT 24
Peak memory 201092 kb
Host smart-01b67ecb-3e59-4604-af89-c85c4ba17096
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285562245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_div_intersig_mubi.285562245
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.1763576262
Short name T659
Test name
Test status
Simulation time 22071538 ps
CPU time 0.84 seconds
Started Jul 31 06:05:24 PM PDT 24
Finished Jul 31 06:05:25 PM PDT 24
Peak memory 201072 kb
Host smart-2ef98183-70e1-4f3a-866a-b70ed8144715
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763576262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.1763576262
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.3122353854
Short name T442
Test name
Test status
Simulation time 650037384 ps
CPU time 2.88 seconds
Started Jul 31 06:05:23 PM PDT 24
Finished Jul 31 06:05:26 PM PDT 24
Peak memory 201136 kb
Host smart-ffedc728-0932-49cb-9799-7cd0c4f99cf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122353854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.3122353854
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.2400054771
Short name T548
Test name
Test status
Simulation time 500370727 ps
CPU time 3.35 seconds
Started Jul 31 06:05:19 PM PDT 24
Finished Jul 31 06:05:23 PM PDT 24
Peak memory 201220 kb
Host smart-5d01e633-790a-4326-a194-a24e66382c9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400054771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.2400054771
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3619041944
Short name T679
Test name
Test status
Simulation time 15855797 ps
CPU time 0.74 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 200988 kb
Host smart-c290273f-fb34-4968-b7fb-e13695b35137
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619041944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.3619041944
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.720243956
Short name T525
Test name
Test status
Simulation time 30490139 ps
CPU time 0.84 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 201084 kb
Host smart-d705e3b5-e04e-4f1b-8026-479802216744
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720243956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.720243956
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3244100045
Short name T415
Test name
Test status
Simulation time 23349521 ps
CPU time 0.77 seconds
Started Jul 31 06:05:23 PM PDT 24
Finished Jul 31 06:05:23 PM PDT 24
Peak memory 201108 kb
Host smart-7a76279e-49ee-41c1-a652-57b72c15331c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244100045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3244100045
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.81685846
Short name T435
Test name
Test status
Simulation time 902377745 ps
CPU time 3.21 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:30 PM PDT 24
Peak memory 201072 kb
Host smart-8f9f8f39-52cb-4307-9f7b-28a8b11be8e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81685846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.81685846
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.3051242194
Short name T526
Test name
Test status
Simulation time 82435047 ps
CPU time 1.03 seconds
Started Jul 31 06:05:24 PM PDT 24
Finished Jul 31 06:05:25 PM PDT 24
Peak memory 201020 kb
Host smart-4bff71f6-eba9-4238-92d4-2fcbdd71ac30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051242194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3051242194
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.214907103
Short name T311
Test name
Test status
Simulation time 136310098 ps
CPU time 1.27 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 201048 kb
Host smart-b26217de-e54f-4059-924e-aaceb26bed60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214907103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.214907103
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2341195125
Short name T5
Test name
Test status
Simulation time 55740476 ps
CPU time 0.97 seconds
Started Jul 31 06:05:22 PM PDT 24
Finished Jul 31 06:05:23 PM PDT 24
Peak memory 201044 kb
Host smart-27485855-a21e-4bfd-bb37-ddac3632c814
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341195125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2341195125
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.556934984
Short name T453
Test name
Test status
Simulation time 20575684 ps
CPU time 0.85 seconds
Started Jul 31 06:05:35 PM PDT 24
Finished Jul 31 06:05:36 PM PDT 24
Peak memory 201092 kb
Host smart-91c8238e-5422-4fa6-95e1-78ffcbad5af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556934984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkm
gr_alert_test.556934984
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.773539283
Short name T466
Test name
Test status
Simulation time 24336891 ps
CPU time 0.88 seconds
Started Jul 31 06:05:37 PM PDT 24
Finished Jul 31 06:05:37 PM PDT 24
Peak memory 201052 kb
Host smart-2da28cee-bfe5-4a77-8af9-8cb84a837533
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773539283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.773539283
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2488848995
Short name T369
Test name
Test status
Simulation time 18082550 ps
CPU time 0.75 seconds
Started Jul 31 06:05:35 PM PDT 24
Finished Jul 31 06:05:36 PM PDT 24
Peak memory 201004 kb
Host smart-b2fd67dd-310d-4597-bedb-1d4473c24290
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488848995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2488848995
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.1157175995
Short name T817
Test name
Test status
Simulation time 16525339 ps
CPU time 0.77 seconds
Started Jul 31 06:05:39 PM PDT 24
Finished Jul 31 06:05:40 PM PDT 24
Peak memory 200996 kb
Host smart-ae7b65ae-c296-49be-8d90-794d2c1f5323
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157175995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.1157175995
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.4194480202
Short name T22
Test name
Test status
Simulation time 64801472 ps
CPU time 0.9 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:28 PM PDT 24
Peak memory 201040 kb
Host smart-493f4c93-38b6-4ad8-a9b2-6264ac358e5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194480202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.4194480202
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2723376696
Short name T128
Test name
Test status
Simulation time 717902117 ps
CPU time 3.67 seconds
Started Jul 31 06:05:27 PM PDT 24
Finished Jul 31 06:05:31 PM PDT 24
Peak memory 201100 kb
Host smart-96d9bece-18bd-4fc6-8d2f-ae0cbce2f060
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723376696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2723376696
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.262414475
Short name T474
Test name
Test status
Simulation time 2175209147 ps
CPU time 15.46 seconds
Started Jul 31 06:05:36 PM PDT 24
Finished Jul 31 06:05:51 PM PDT 24
Peak memory 201352 kb
Host smart-017df2d9-31b8-4c7d-8ac1-56fecff8cd6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262414475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti
meout.262414475
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.255096975
Short name T584
Test name
Test status
Simulation time 23898243 ps
CPU time 0.87 seconds
Started Jul 31 06:05:36 PM PDT 24
Finished Jul 31 06:05:37 PM PDT 24
Peak memory 201088 kb
Host smart-574b6f09-ad57-4451-825f-c01160ed2a6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255096975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.255096975
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1257636903
Short name T755
Test name
Test status
Simulation time 17597195 ps
CPU time 0.81 seconds
Started Jul 31 06:05:40 PM PDT 24
Finished Jul 31 06:05:41 PM PDT 24
Peak memory 201100 kb
Host smart-86776549-bfe9-4fc4-938c-83830e59d685
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257636903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.1257636903
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.2136255669
Short name T188
Test name
Test status
Simulation time 23426277 ps
CPU time 0.86 seconds
Started Jul 31 06:05:36 PM PDT 24
Finished Jul 31 06:05:37 PM PDT 24
Peak memory 201040 kb
Host smart-2f2e9072-e182-4642-8136-f1dceaa6c9e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136255669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.2136255669
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.4124390274
Short name T81
Test name
Test status
Simulation time 24079257 ps
CPU time 0.76 seconds
Started Jul 31 06:05:35 PM PDT 24
Finished Jul 31 06:05:36 PM PDT 24
Peak memory 201056 kb
Host smart-4738b809-b52e-4df4-8933-e9561b6be714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124390274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.4124390274
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1224665961
Short name T422
Test name
Test status
Simulation time 724893558 ps
CPU time 4.32 seconds
Started Jul 31 06:05:40 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 201256 kb
Host smart-696a27a0-c92a-4309-b035-1c419976c510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224665961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1224665961
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.2578508918
Short name T328
Test name
Test status
Simulation time 61509114 ps
CPU time 1 seconds
Started Jul 31 06:05:24 PM PDT 24
Finished Jul 31 06:05:25 PM PDT 24
Peak memory 200996 kb
Host smart-a8f38169-b73c-4588-9ff6-8ae9d0917280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578508918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2578508918
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.1480723412
Short name T571
Test name
Test status
Simulation time 2523140151 ps
CPU time 9.86 seconds
Started Jul 31 06:05:37 PM PDT 24
Finished Jul 31 06:05:47 PM PDT 24
Peak memory 201388 kb
Host smart-df0b11e2-52d7-4658-acb8-0cf692a555ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480723412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.1480723412
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.452709833
Short name T688
Test name
Test status
Simulation time 24234284 ps
CPU time 0.77 seconds
Started Jul 31 06:05:36 PM PDT 24
Finished Jul 31 06:05:37 PM PDT 24
Peak memory 201072 kb
Host smart-bced2373-f543-41a8-8268-aa75072a9748
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452709833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.452709833
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1050007496
Short name T714
Test name
Test status
Simulation time 17898111 ps
CPU time 0.82 seconds
Started Jul 31 06:05:48 PM PDT 24
Finished Jul 31 06:05:49 PM PDT 24
Peak memory 201036 kb
Host smart-fed1d54a-4e60-45da-a55e-056c964410ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050007496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1050007496
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.139668519
Short name T586
Test name
Test status
Simulation time 17270921 ps
CPU time 0.74 seconds
Started Jul 31 06:05:46 PM PDT 24
Finished Jul 31 06:05:47 PM PDT 24
Peak memory 201020 kb
Host smart-2b9dea86-4b15-4443-9f8a-5e299ece8f47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139668519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.139668519
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.3572952044
Short name T53
Test name
Test status
Simulation time 35389784 ps
CPU time 0.76 seconds
Started Jul 31 06:05:44 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 201012 kb
Host smart-01f647a3-4374-4d43-ab12-e0ea14995e47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572952044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3572952044
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.1334509336
Short name T243
Test name
Test status
Simulation time 175073671 ps
CPU time 1.33 seconds
Started Jul 31 06:05:45 PM PDT 24
Finished Jul 31 06:05:46 PM PDT 24
Peak memory 201048 kb
Host smart-4ae7acdc-5632-4109-a98d-94b18b02fac8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334509336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.1334509336
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.4225985716
Short name T353
Test name
Test status
Simulation time 102161214 ps
CPU time 1.14 seconds
Started Jul 31 06:05:41 PM PDT 24
Finished Jul 31 06:05:42 PM PDT 24
Peak memory 201060 kb
Host smart-d21665e0-1a4a-4290-8deb-255e8314d099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225985716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.4225985716
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.567423754
Short name T803
Test name
Test status
Simulation time 2051147359 ps
CPU time 9.17 seconds
Started Jul 31 06:05:44 PM PDT 24
Finished Jul 31 06:05:53 PM PDT 24
Peak memory 201344 kb
Host smart-aab1cb80-e66e-4cc6-9251-9b0fe8fe04dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567423754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.567423754
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.350857593
Short name T517
Test name
Test status
Simulation time 887454551 ps
CPU time 3.37 seconds
Started Jul 31 06:05:41 PM PDT 24
Finished Jul 31 06:05:44 PM PDT 24
Peak memory 201220 kb
Host smart-baf92c72-9117-4ccb-8bb4-2412aa0cc0d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350857593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti
meout.350857593
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.1745706241
Short name T298
Test name
Test status
Simulation time 101993190 ps
CPU time 1.19 seconds
Started Jul 31 06:05:45 PM PDT 24
Finished Jul 31 06:05:47 PM PDT 24
Peak memory 201104 kb
Host smart-7b3aa176-837a-467d-92a1-7881d26aa6d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745706241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.1745706241
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.210831393
Short name T366
Test name
Test status
Simulation time 56802333 ps
CPU time 0.93 seconds
Started Jul 31 06:05:43 PM PDT 24
Finished Jul 31 06:05:44 PM PDT 24
Peak memory 201024 kb
Host smart-b7144bb0-1fe9-4b55-9456-a0ea72bb4700
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210831393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.210831393
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.1627863842
Short name T559
Test name
Test status
Simulation time 13356300 ps
CPU time 0.71 seconds
Started Jul 31 06:05:44 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 201000 kb
Host smart-5362908c-6894-4653-bd04-8243c789035f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627863842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.1627863842
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.1897591466
Short name T210
Test name
Test status
Simulation time 24454151 ps
CPU time 0.74 seconds
Started Jul 31 06:05:44 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 201100 kb
Host smart-7a0f8471-08f7-4617-9f54-c2f885d10081
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897591466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1897591466
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2634934362
Short name T615
Test name
Test status
Simulation time 784367145 ps
CPU time 4.79 seconds
Started Jul 31 06:05:46 PM PDT 24
Finished Jul 31 06:05:51 PM PDT 24
Peak memory 201304 kb
Host smart-970dee1e-173e-4359-85ad-84ec75560a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634934362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2634934362
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2352799702
Short name T405
Test name
Test status
Simulation time 66762633 ps
CPU time 1.01 seconds
Started Jul 31 06:05:43 PM PDT 24
Finished Jul 31 06:05:44 PM PDT 24
Peak memory 201056 kb
Host smart-84e25857-33f5-4746-a8f7-84b9f28d41f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352799702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2352799702
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3704435545
Short name T350
Test name
Test status
Simulation time 8948808627 ps
CPU time 39.43 seconds
Started Jul 31 06:05:48 PM PDT 24
Finished Jul 31 06:06:28 PM PDT 24
Peak memory 201424 kb
Host smart-d69add4f-a8ba-4d66-bf84-2a9b4d8a357b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704435545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3704435545
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.1968725581
Short name T602
Test name
Test status
Simulation time 79096704 ps
CPU time 1.18 seconds
Started Jul 31 06:05:43 PM PDT 24
Finished Jul 31 06:05:45 PM PDT 24
Peak memory 201000 kb
Host smart-dfcaca10-40d0-42ad-b8d7-2c461dcba15a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968725581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1968725581
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3646049851
Short name T77
Test name
Test status
Simulation time 15668523 ps
CPU time 0.74 seconds
Started Jul 31 06:05:58 PM PDT 24
Finished Jul 31 06:05:59 PM PDT 24
Peak memory 201116 kb
Host smart-49da3045-663e-4a14-9b6d-ad2bd5a1f9da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646049851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3646049851
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2749161010
Short name T805
Test name
Test status
Simulation time 20308853 ps
CPU time 0.84 seconds
Started Jul 31 06:05:56 PM PDT 24
Finished Jul 31 06:05:57 PM PDT 24
Peak memory 201088 kb
Host smart-0f9fa993-9c3c-4793-a4ac-8ad2c6210478
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749161010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.2749161010
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.3543450001
Short name T558
Test name
Test status
Simulation time 13655375 ps
CPU time 0.71 seconds
Started Jul 31 06:05:49 PM PDT 24
Finished Jul 31 06:05:50 PM PDT 24
Peak memory 200300 kb
Host smart-1de051f8-1c2b-4543-8eaf-7673c566a6e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543450001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3543450001
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.3426669911
Short name T754
Test name
Test status
Simulation time 17273342 ps
CPU time 0.79 seconds
Started Jul 31 06:05:54 PM PDT 24
Finished Jul 31 06:05:55 PM PDT 24
Peak memory 201092 kb
Host smart-d9a99d7b-d6c6-41f6-96a2-87f9e93fa5d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426669911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.3426669911
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3303937276
Short name T446
Test name
Test status
Simulation time 24152738 ps
CPU time 0.82 seconds
Started Jul 31 06:05:50 PM PDT 24
Finished Jul 31 06:05:51 PM PDT 24
Peak memory 201060 kb
Host smart-537cc137-9c7c-4c39-ba80-292b6e220f25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303937276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3303937276
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.978141094
Short name T486
Test name
Test status
Simulation time 1995451237 ps
CPU time 15.22 seconds
Started Jul 31 06:05:48 PM PDT 24
Finished Jul 31 06:06:04 PM PDT 24
Peak memory 201232 kb
Host smart-8a2ebb53-c711-4739-9d5e-9c71226132b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978141094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.978141094
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3718960026
Short name T748
Test name
Test status
Simulation time 1337081216 ps
CPU time 10.93 seconds
Started Jul 31 06:05:46 PM PDT 24
Finished Jul 31 06:05:57 PM PDT 24
Peak memory 201176 kb
Host smart-b06a738e-b69c-4dc3-b4f7-300171ec94b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718960026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3718960026
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.2996081101
Short name T681
Test name
Test status
Simulation time 28466182 ps
CPU time 0.96 seconds
Started Jul 31 06:05:54 PM PDT 24
Finished Jul 31 06:05:55 PM PDT 24
Peak memory 201096 kb
Host smart-3f9f2a0f-916d-40eb-acc9-7dfdd81f73ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996081101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.2996081101
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2959001832
Short name T167
Test name
Test status
Simulation time 12227770 ps
CPU time 0.7 seconds
Started Jul 31 06:05:55 PM PDT 24
Finished Jul 31 06:05:55 PM PDT 24
Peak memory 201100 kb
Host smart-3c5a7371-49cf-4bfc-9a8c-4a6348b58310
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959001832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2959001832
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1078478087
Short name T515
Test name
Test status
Simulation time 41244281 ps
CPU time 0.94 seconds
Started Jul 31 06:05:51 PM PDT 24
Finished Jul 31 06:05:52 PM PDT 24
Peak memory 201048 kb
Host smart-50e25772-d758-4bbb-b04a-22fed005b2d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078478087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.1078478087
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.1088557691
Short name T380
Test name
Test status
Simulation time 39227263 ps
CPU time 0.77 seconds
Started Jul 31 06:05:47 PM PDT 24
Finished Jul 31 06:05:48 PM PDT 24
Peak memory 200980 kb
Host smart-bd3c4393-d9b6-4c91-a061-2955ba124510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088557691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1088557691
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.1198273062
Short name T122
Test name
Test status
Simulation time 458299246 ps
CPU time 2.04 seconds
Started Jul 31 06:05:54 PM PDT 24
Finished Jul 31 06:05:56 PM PDT 24
Peak memory 201104 kb
Host smart-5e69991a-93c1-49a8-a2ae-12c436e31d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198273062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.1198273062
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.277452118
Short name T490
Test name
Test status
Simulation time 21027323 ps
CPU time 0.87 seconds
Started Jul 31 06:05:49 PM PDT 24
Finished Jul 31 06:05:50 PM PDT 24
Peak memory 201104 kb
Host smart-2aaaab03-e3b5-4bce-9073-c7cadd2d3a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277452118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.277452118
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.1893560351
Short name T790
Test name
Test status
Simulation time 7169279044 ps
CPU time 30.2 seconds
Started Jul 31 06:06:00 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 201428 kb
Host smart-fa8c006d-8f01-4ea2-8a32-4474f7fcc8cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893560351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.1893560351
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.749180937
Short name T622
Test name
Test status
Simulation time 33357751 ps
CPU time 1 seconds
Started Jul 31 06:05:49 PM PDT 24
Finished Jul 31 06:05:50 PM PDT 24
Peak memory 201068 kb
Host smart-b5d690c5-eb03-4975-b7f8-f178f9190c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749180937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.749180937
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3905696248
Short name T388
Test name
Test status
Simulation time 18840850 ps
CPU time 0.82 seconds
Started Jul 31 06:06:06 PM PDT 24
Finished Jul 31 06:06:07 PM PDT 24
Peak memory 201092 kb
Host smart-055e8ac4-b8ed-48f1-a42a-3e9158ec6c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905696248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3905696248
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1894327571
Short name T608
Test name
Test status
Simulation time 19643204 ps
CPU time 0.86 seconds
Started Jul 31 06:06:08 PM PDT 24
Finished Jul 31 06:06:09 PM PDT 24
Peak memory 201104 kb
Host smart-9f10182b-f479-4795-abc7-098d029e3e08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894327571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1894327571
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.136619370
Short name T501
Test name
Test status
Simulation time 15641025 ps
CPU time 0.72 seconds
Started Jul 31 06:06:00 PM PDT 24
Finished Jul 31 06:06:01 PM PDT 24
Peak memory 200244 kb
Host smart-988e66c4-a76a-4b7c-a6a1-820dd2320a71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136619370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.136619370
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.504701223
Short name T250
Test name
Test status
Simulation time 20213284 ps
CPU time 0.81 seconds
Started Jul 31 06:06:05 PM PDT 24
Finished Jul 31 06:06:06 PM PDT 24
Peak memory 201092 kb
Host smart-48231a29-45be-433c-819c-e7ccf2fb8675
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504701223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_div_intersig_mubi.504701223
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.3539513910
Short name T514
Test name
Test status
Simulation time 137587395 ps
CPU time 1.17 seconds
Started Jul 31 06:05:59 PM PDT 24
Finished Jul 31 06:06:00 PM PDT 24
Peak memory 200940 kb
Host smart-e72e99d5-bef4-4a41-b0c7-f4b203209ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539513910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.3539513910
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.129396255
Short name T24
Test name
Test status
Simulation time 555636548 ps
CPU time 4.34 seconds
Started Jul 31 06:06:00 PM PDT 24
Finished Jul 31 06:06:04 PM PDT 24
Peak memory 201128 kb
Host smart-4d78fab1-3f23-434a-9ee3-3c93f3aa363c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129396255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.129396255
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.2793412547
Short name T595
Test name
Test status
Simulation time 2175637914 ps
CPU time 15.69 seconds
Started Jul 31 06:06:00 PM PDT 24
Finished Jul 31 06:06:15 PM PDT 24
Peak memory 201392 kb
Host smart-9f7a7a5d-0c98-40b9-832d-90e21b34d3c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793412547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.2793412547
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1115024643
Short name T607
Test name
Test status
Simulation time 48029233 ps
CPU time 0.93 seconds
Started Jul 31 06:06:00 PM PDT 24
Finished Jul 31 06:06:01 PM PDT 24
Peak memory 201076 kb
Host smart-00d60741-117c-42c7-9080-023a9ce70fd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115024643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1115024643
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.89284585
Short name T534
Test name
Test status
Simulation time 21927072 ps
CPU time 0.87 seconds
Started Jul 31 06:06:01 PM PDT 24
Finished Jul 31 06:06:02 PM PDT 24
Peak memory 201092 kb
Host smart-1b49ca32-194b-42ff-8815-d75e408e56fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89284585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_lc_clk_byp_req_intersig_mubi.89284585
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1974364974
Short name T697
Test name
Test status
Simulation time 34483359 ps
CPU time 0.87 seconds
Started Jul 31 06:05:59 PM PDT 24
Finished Jul 31 06:06:00 PM PDT 24
Peak memory 201072 kb
Host smart-63bfa1fa-f07c-4382-bca1-f9fc31f23007
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974364974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.1974364974
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1370860249
Short name T521
Test name
Test status
Simulation time 16963028 ps
CPU time 0.77 seconds
Started Jul 31 06:05:59 PM PDT 24
Finished Jul 31 06:06:00 PM PDT 24
Peak memory 201028 kb
Host smart-a32e8958-ce8c-45e1-bdcb-6e16e82d075d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370860249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1370860249
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.1416467570
Short name T161
Test name
Test status
Simulation time 118445288 ps
CPU time 1.25 seconds
Started Jul 31 06:06:02 PM PDT 24
Finished Jul 31 06:06:03 PM PDT 24
Peak memory 201000 kb
Host smart-aba87fda-31c3-4489-ab78-1900614dc77b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416467570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.1416467570
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.1566263664
Short name T533
Test name
Test status
Simulation time 44202478 ps
CPU time 0.93 seconds
Started Jul 31 06:05:59 PM PDT 24
Finished Jul 31 06:06:00 PM PDT 24
Peak memory 201060 kb
Host smart-b1189ad7-89e4-47b1-8cb2-7c0be5b0426e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566263664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1566263664
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.1029051660
Short name T3
Test name
Test status
Simulation time 21431893495 ps
CPU time 76.41 seconds
Started Jul 31 06:06:06 PM PDT 24
Finished Jul 31 06:07:23 PM PDT 24
Peak memory 201484 kb
Host smart-f5b83679-db84-4af3-a8b2-43279665f626
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029051660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.1029051660
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.842916649
Short name T44
Test name
Test status
Simulation time 184788985958 ps
CPU time 1202.05 seconds
Started Jul 31 06:06:05 PM PDT 24
Finished Jul 31 06:26:07 PM PDT 24
Peak memory 215028 kb
Host smart-ec3a8d3a-e291-46da-a584-fef3f10e4359
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=842916649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.842916649
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.3593667785
Short name T230
Test name
Test status
Simulation time 31188723 ps
CPU time 0.78 seconds
Started Jul 31 06:06:01 PM PDT 24
Finished Jul 31 06:06:02 PM PDT 24
Peak memory 201072 kb
Host smart-bd58a3a8-1a6b-403b-9b75-c29fa032a380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593667785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3593667785
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3583782001
Short name T320
Test name
Test status
Simulation time 19016034 ps
CPU time 0.81 seconds
Started Jul 31 06:06:16 PM PDT 24
Finished Jul 31 06:06:16 PM PDT 24
Peak memory 200988 kb
Host smart-655b5de8-b900-4664-9d5f-feabdc46c76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583782001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3583782001
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.274836266
Short name T562
Test name
Test status
Simulation time 13152407 ps
CPU time 0.74 seconds
Started Jul 31 06:06:08 PM PDT 24
Finished Jul 31 06:06:09 PM PDT 24
Peak memory 201100 kb
Host smart-d34728f1-b5c0-48d4-9f45-d47040b898b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274836266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.274836266
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.1466487694
Short name T279
Test name
Test status
Simulation time 17449686 ps
CPU time 0.76 seconds
Started Jul 31 06:06:08 PM PDT 24
Finished Jul 31 06:06:09 PM PDT 24
Peak memory 200272 kb
Host smart-66fb3f00-66d0-4c5f-a4ef-b971504c270c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466487694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1466487694
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.2401636325
Short name T604
Test name
Test status
Simulation time 119852423 ps
CPU time 1.1 seconds
Started Jul 31 06:06:09 PM PDT 24
Finished Jul 31 06:06:10 PM PDT 24
Peak memory 201056 kb
Host smart-5b407998-405f-4398-ad62-a1d9a5576f03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401636325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.2401636325
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.1012095682
Short name T183
Test name
Test status
Simulation time 90855677 ps
CPU time 0.99 seconds
Started Jul 31 06:06:04 PM PDT 24
Finished Jul 31 06:06:05 PM PDT 24
Peak memory 201096 kb
Host smart-8a7648d2-c066-4793-95a2-41064211a34d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012095682 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1012095682
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.3315173111
Short name T129
Test name
Test status
Simulation time 1109236065 ps
CPU time 5.46 seconds
Started Jul 31 06:06:03 PM PDT 24
Finished Jul 31 06:06:09 PM PDT 24
Peak memory 201148 kb
Host smart-275e7a0f-7c8f-496a-bf83-d531ccb41200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315173111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3315173111
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2872469668
Short name T434
Test name
Test status
Simulation time 2060560431 ps
CPU time 15.66 seconds
Started Jul 31 06:06:08 PM PDT 24
Finished Jul 31 06:06:24 PM PDT 24
Peak memory 201352 kb
Host smart-c2fdb351-644c-4350-a05c-dedc556381cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872469668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2872469668
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2201714611
Short name T650
Test name
Test status
Simulation time 38146002 ps
CPU time 1.02 seconds
Started Jul 31 06:06:05 PM PDT 24
Finished Jul 31 06:06:06 PM PDT 24
Peak memory 201092 kb
Host smart-9d485a19-14d2-41da-8ec6-b881e0e2220c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201714611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2201714611
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.771750419
Short name T199
Test name
Test status
Simulation time 24825587 ps
CPU time 0.99 seconds
Started Jul 31 06:06:01 PM PDT 24
Finished Jul 31 06:06:02 PM PDT 24
Peak memory 201144 kb
Host smart-5de58c88-7029-46f7-b74d-fbc9bfd217ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771750419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_clk_byp_req_intersig_mubi.771750419
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1391906679
Short name T660
Test name
Test status
Simulation time 34636984 ps
CPU time 0.9 seconds
Started Jul 31 06:06:06 PM PDT 24
Finished Jul 31 06:06:07 PM PDT 24
Peak memory 201056 kb
Host smart-a9f8d744-f444-4f62-9a62-51e10d31a3bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391906679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1391906679
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.2062390076
Short name T268
Test name
Test status
Simulation time 31124781 ps
CPU time 0.81 seconds
Started Jul 31 06:06:05 PM PDT 24
Finished Jul 31 06:06:06 PM PDT 24
Peak memory 201028 kb
Host smart-3ef26ced-38e3-438b-b5ef-5d3319fb1973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062390076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.2062390076
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.984399863
Short name T263
Test name
Test status
Simulation time 1168672854 ps
CPU time 4.56 seconds
Started Jul 31 06:06:09 PM PDT 24
Finished Jul 31 06:06:14 PM PDT 24
Peak memory 201296 kb
Host smart-b86fecd2-4f7a-4f3e-90b9-6235a0769691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984399863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.984399863
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.2221312798
Short name T609
Test name
Test status
Simulation time 15380489 ps
CPU time 0.84 seconds
Started Jul 31 06:06:08 PM PDT 24
Finished Jul 31 06:06:09 PM PDT 24
Peak memory 201052 kb
Host smart-23a0c3c4-5b62-4e66-9dd7-02551358ad40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221312798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.2221312798
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.994614476
Short name T592
Test name
Test status
Simulation time 6472618951 ps
CPU time 35.24 seconds
Started Jul 31 06:06:14 PM PDT 24
Finished Jul 31 06:06:50 PM PDT 24
Peak memory 201388 kb
Host smart-15f8bd08-26a6-42d2-ab26-6bd1ac13fcb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994614476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.994614476
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.2848811676
Short name T192
Test name
Test status
Simulation time 91590643 ps
CPU time 1.14 seconds
Started Jul 31 06:06:05 PM PDT 24
Finished Jul 31 06:06:07 PM PDT 24
Peak memory 201108 kb
Host smart-0344c6e5-af8f-421c-bad4-589c47d452e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848811676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2848811676
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.3122296626
Short name T672
Test name
Test status
Simulation time 17987904 ps
CPU time 0.78 seconds
Started Jul 31 06:06:20 PM PDT 24
Finished Jul 31 06:06:20 PM PDT 24
Peak memory 201044 kb
Host smart-eeabfeba-43d8-4478-aea2-47c4ff6377a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122296626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.3122296626
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1112338070
Short name T204
Test name
Test status
Simulation time 25753896 ps
CPU time 0.88 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 200768 kb
Host smart-d4ea7bd6-8ff3-495c-a97d-0a6eaa44a713
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112338070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.1112338070
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.1787827313
Short name T458
Test name
Test status
Simulation time 107978460 ps
CPU time 0.99 seconds
Started Jul 31 06:06:21 PM PDT 24
Finished Jul 31 06:06:22 PM PDT 24
Peak memory 200264 kb
Host smart-f36aac01-6279-4e2c-a3cf-b6e14d7ee829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787827313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1787827313
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.3662174933
Short name T444
Test name
Test status
Simulation time 28707755 ps
CPU time 0.93 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 200748 kb
Host smart-08607f1a-f3fe-455a-a4a8-4fffe63f60e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662174933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.3662174933
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.109083657
Short name T50
Test name
Test status
Simulation time 53783798 ps
CPU time 0.95 seconds
Started Jul 31 06:06:16 PM PDT 24
Finished Jul 31 06:06:17 PM PDT 24
Peak memory 201076 kb
Host smart-0b02497a-02a5-4a4f-8a9b-c17c1fdd668d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109083657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.109083657
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.2105836335
Short name T443
Test name
Test status
Simulation time 2480961020 ps
CPU time 18.51 seconds
Started Jul 31 06:06:12 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 201408 kb
Host smart-82fa6c04-c50e-4bc9-a79b-19149a9657c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105836335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2105836335
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.2209600539
Short name T487
Test name
Test status
Simulation time 2103125625 ps
CPU time 7.98 seconds
Started Jul 31 06:06:15 PM PDT 24
Finished Jul 31 06:06:23 PM PDT 24
Peak memory 201176 kb
Host smart-b9d4ff5c-fd05-4c21-b152-33857b55c273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209600539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.2209600539
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1909607593
Short name T668
Test name
Test status
Simulation time 14931946 ps
CPU time 0.73 seconds
Started Jul 31 06:06:23 PM PDT 24
Finished Jul 31 06:06:24 PM PDT 24
Peak memory 201044 kb
Host smart-cc2773d6-4aed-469a-97be-f47b58125bc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909607593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1909607593
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.3788073365
Short name T448
Test name
Test status
Simulation time 61783694 ps
CPU time 0.94 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 201112 kb
Host smart-dbc0ec84-587c-4bd5-bf64-a9b73009b398
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788073365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.3788073365
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1971727635
Short name T552
Test name
Test status
Simulation time 15108332 ps
CPU time 0.78 seconds
Started Jul 31 06:06:21 PM PDT 24
Finished Jul 31 06:06:21 PM PDT 24
Peak memory 201024 kb
Host smart-be91545d-a108-41bc-ac56-c6fa94bbfd60
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971727635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.1971727635
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3296582644
Short name T178
Test name
Test status
Simulation time 13808441 ps
CPU time 0.75 seconds
Started Jul 31 06:06:15 PM PDT 24
Finished Jul 31 06:06:16 PM PDT 24
Peak memory 201088 kb
Host smart-93c4a0c9-c008-4224-83c5-adbe6cb9fdb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296582644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3296582644
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.2783426994
Short name T508
Test name
Test status
Simulation time 824724103 ps
CPU time 2.98 seconds
Started Jul 31 06:06:20 PM PDT 24
Finished Jul 31 06:06:23 PM PDT 24
Peak memory 201224 kb
Host smart-8965bfdd-c05c-4ca7-9e56-ebaab0af3258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783426994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2783426994
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.1866803838
Short name T333
Test name
Test status
Simulation time 20069688 ps
CPU time 0.86 seconds
Started Jul 31 06:06:14 PM PDT 24
Finished Jul 31 06:06:15 PM PDT 24
Peak memory 201004 kb
Host smart-2d9c2f54-54ff-4dc8-ab93-e6ed17bb761f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866803838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.1866803838
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.886861406
Short name T820
Test name
Test status
Simulation time 1306381576 ps
CPU time 11.18 seconds
Started Jul 31 06:06:20 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 201352 kb
Host smart-6d9a1e09-546c-4e21-97c9-3dceea82da38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886861406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.886861406
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.2751789111
Short name T643
Test name
Test status
Simulation time 31639928 ps
CPU time 0.95 seconds
Started Jul 31 06:06:22 PM PDT 24
Finished Jul 31 06:06:23 PM PDT 24
Peak memory 201024 kb
Host smart-11686fb6-2d4b-4d1f-aa4b-09bbf3dafdeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751789111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2751789111
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.2323869905
Short name T321
Test name
Test status
Simulation time 16470677 ps
CPU time 0.79 seconds
Started Jul 31 06:06:30 PM PDT 24
Finished Jul 31 06:06:30 PM PDT 24
Peak memory 201108 kb
Host smart-7d9f25d1-6df3-4a47-982e-aa3c40990d06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323869905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.2323869905
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.2892316209
Short name T280
Test name
Test status
Simulation time 14967898 ps
CPU time 0.73 seconds
Started Jul 31 06:06:30 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 201000 kb
Host smart-03e032fe-1e85-4bb3-95e4-a2048fd11108
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892316209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.2892316209
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.3366219013
Short name T29
Test name
Test status
Simulation time 19482017 ps
CPU time 0.79 seconds
Started Jul 31 06:06:26 PM PDT 24
Finished Jul 31 06:06:27 PM PDT 24
Peak memory 200272 kb
Host smart-2a92c909-1884-471e-9ae8-00257eb3ce4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366219013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.3366219013
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.1565134287
Short name T376
Test name
Test status
Simulation time 40379041 ps
CPU time 0.91 seconds
Started Jul 31 06:06:30 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 201072 kb
Host smart-2d1ea469-7d81-4e11-b495-6d0c384efa41
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565134287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.1565134287
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.49023571
Short name T736
Test name
Test status
Simulation time 68700403 ps
CPU time 0.97 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 201100 kb
Host smart-a1b389f3-6d70-4ca5-a8c2-283ed6902786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49023571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.49023571
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.1532494046
Short name T566
Test name
Test status
Simulation time 562044865 ps
CPU time 5.03 seconds
Started Jul 31 06:06:21 PM PDT 24
Finished Jul 31 06:06:26 PM PDT 24
Peak memory 201208 kb
Host smart-1bd6d582-c801-400e-a4a8-ac249ca21aa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532494046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1532494046
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.2063208295
Short name T591
Test name
Test status
Simulation time 498734023 ps
CPU time 3.97 seconds
Started Jul 31 06:06:25 PM PDT 24
Finished Jul 31 06:06:29 PM PDT 24
Peak memory 201108 kb
Host smart-f68e316b-d59c-4296-a44b-91c71d67d8d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063208295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.2063208295
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.2727574301
Short name T641
Test name
Test status
Simulation time 28003059 ps
CPU time 0.83 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 201092 kb
Host smart-6bf86ccb-d488-4d65-8d96-84af74999f10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727574301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.2727574301
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.561553133
Short name T800
Test name
Test status
Simulation time 25773946 ps
CPU time 0.81 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 201016 kb
Host smart-bc944eb7-bbb8-4f55-bd57-e1e56ee8aeab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561553133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.561553133
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.34338122
Short name T603
Test name
Test status
Simulation time 28963676 ps
CPU time 0.77 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:25 PM PDT 24
Peak memory 201100 kb
Host smart-02f2b9ec-0b57-454e-ac92-1fe511fe7124
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34338122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_lc_ctrl_intersig_mubi.34338122
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.2995871003
Short name T685
Test name
Test status
Simulation time 45546244 ps
CPU time 0.88 seconds
Started Jul 31 06:06:26 PM PDT 24
Finished Jul 31 06:06:27 PM PDT 24
Peak memory 201024 kb
Host smart-090eb83f-8504-480d-92ce-ab28ad395555
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995871003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2995871003
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.372629465
Short name T661
Test name
Test status
Simulation time 1001040669 ps
CPU time 5.82 seconds
Started Jul 31 06:06:30 PM PDT 24
Finished Jul 31 06:06:36 PM PDT 24
Peak memory 201236 kb
Host smart-006e2526-65fd-4d0e-ae5a-78fa18116017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372629465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.372629465
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.1894928262
Short name T287
Test name
Test status
Simulation time 14856842 ps
CPU time 0.78 seconds
Started Jul 31 06:06:23 PM PDT 24
Finished Jul 31 06:06:23 PM PDT 24
Peak memory 201040 kb
Host smart-471a443f-f3c1-486f-b415-722957076ca9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894928262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1894928262
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.2028998049
Short name T223
Test name
Test status
Simulation time 410975837 ps
CPU time 2.15 seconds
Started Jul 31 06:06:29 PM PDT 24
Finished Jul 31 06:06:32 PM PDT 24
Peak memory 201140 kb
Host smart-99886023-7f7a-43b1-888c-683ee4003239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028998049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.2028998049
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.4229434548
Short name T34
Test name
Test status
Simulation time 20512128552 ps
CPU time 293.1 seconds
Started Jul 31 06:06:29 PM PDT 24
Finished Jul 31 06:11:22 PM PDT 24
Peak memory 217944 kb
Host smart-50555c91-6115-4db9-ac52-28d9347ba355
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4229434548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.4229434548
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.3579462383
Short name T696
Test name
Test status
Simulation time 164562239 ps
CPU time 1.17 seconds
Started Jul 31 06:06:24 PM PDT 24
Finished Jul 31 06:06:26 PM PDT 24
Peak memory 201040 kb
Host smart-517d8347-41c1-4650-8e5f-c469bf2d741e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579462383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.3579462383
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2678637168
Short name T597
Test name
Test status
Simulation time 15682914 ps
CPU time 0.78 seconds
Started Jul 31 05:56:29 PM PDT 24
Finished Jul 31 05:56:30 PM PDT 24
Peak memory 201016 kb
Host smart-aeb4e971-7cc3-45d3-944e-0381ca0af395
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678637168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2678637168
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1742950587
Short name T739
Test name
Test status
Simulation time 19485737 ps
CPU time 0.85 seconds
Started Jul 31 05:56:24 PM PDT 24
Finished Jul 31 05:56:25 PM PDT 24
Peak memory 201060 kb
Host smart-5c24f0bd-5079-4d03-a0f1-34054e25cafd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742950587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1742950587
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.1176808906
Short name T28
Test name
Test status
Simulation time 15771822 ps
CPU time 0.71 seconds
Started Jul 31 05:56:17 PM PDT 24
Finished Jul 31 05:56:18 PM PDT 24
Peak memory 200300 kb
Host smart-8b6c266d-a3c1-4e85-b7d3-6d2cfd062dbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176808906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.1176808906
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.1316127128
Short name T512
Test name
Test status
Simulation time 92088229 ps
CPU time 1.11 seconds
Started Jul 31 05:56:19 PM PDT 24
Finished Jul 31 05:56:21 PM PDT 24
Peak memory 201100 kb
Host smart-619775de-01b8-4437-85c3-2adfa7d5820b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316127128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.1316127128
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3806431080
Short name T725
Test name
Test status
Simulation time 18324005 ps
CPU time 0.81 seconds
Started Jul 31 05:56:11 PM PDT 24
Finished Jul 31 05:56:12 PM PDT 24
Peak memory 201060 kb
Host smart-07083c70-bc73-44c9-9476-c1c942424a48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806431080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3806431080
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1531124571
Short name T710
Test name
Test status
Simulation time 1524267253 ps
CPU time 9.91 seconds
Started Jul 31 05:56:09 PM PDT 24
Finished Jul 31 05:56:19 PM PDT 24
Peak memory 201176 kb
Host smart-decf989a-1d9b-413d-a1a0-ca451de55cd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531124571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1531124571
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2120079320
Short name T80
Test name
Test status
Simulation time 2298311843 ps
CPU time 16.98 seconds
Started Jul 31 05:56:12 PM PDT 24
Finished Jul 31 05:56:29 PM PDT 24
Peak memory 201376 kb
Host smart-cd05c8b6-a8c4-4c1c-9654-67b1b6c1e375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120079320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2120079320
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1196673036
Short name T18
Test name
Test status
Simulation time 108517676 ps
CPU time 1.26 seconds
Started Jul 31 05:56:17 PM PDT 24
Finished Jul 31 05:56:19 PM PDT 24
Peak memory 201104 kb
Host smart-4c1a59a4-2f90-4040-a65a-05e359c42031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196673036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1196673036
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2761642505
Short name T351
Test name
Test status
Simulation time 40477919 ps
CPU time 0.93 seconds
Started Jul 31 05:56:23 PM PDT 24
Finished Jul 31 05:56:24 PM PDT 24
Peak memory 201092 kb
Host smart-3ffee788-13c7-4c47-8a98-bff687b3e385
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761642505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2761642505
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3139715071
Short name T94
Test name
Test status
Simulation time 16995859 ps
CPU time 0.79 seconds
Started Jul 31 05:56:20 PM PDT 24
Finished Jul 31 05:56:20 PM PDT 24
Peak memory 201044 kb
Host smart-e8f9d352-275d-4958-bb55-063ec7336905
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139715071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.3139715071
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.1935824958
Short name T205
Test name
Test status
Simulation time 22137578 ps
CPU time 0.76 seconds
Started Jul 31 05:56:11 PM PDT 24
Finished Jul 31 05:56:12 PM PDT 24
Peak memory 201060 kb
Host smart-06772bb1-07ec-4595-8262-889fe6676b70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935824958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1935824958
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.1747145586
Short name T674
Test name
Test status
Simulation time 80922371 ps
CPU time 0.91 seconds
Started Jul 31 05:56:21 PM PDT 24
Finished Jul 31 05:56:22 PM PDT 24
Peak memory 200964 kb
Host smart-c1c1a093-6c10-46a7-93c2-15f312c260d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747145586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1747145586
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.3422255592
Short name T447
Test name
Test status
Simulation time 56917525 ps
CPU time 0.96 seconds
Started Jul 31 05:56:11 PM PDT 24
Finished Jul 31 05:56:12 PM PDT 24
Peak memory 201044 kb
Host smart-6fca1ded-25c9-4d7c-be5f-81297b4d5017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422255592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3422255592
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2499121526
Short name T532
Test name
Test status
Simulation time 9467992463 ps
CPU time 41.8 seconds
Started Jul 31 05:56:28 PM PDT 24
Finished Jul 31 05:57:10 PM PDT 24
Peak memory 201424 kb
Host smart-c6a5f4d8-40a7-4e49-a3d4-c404a5fa7ef4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499121526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2499121526
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.363486301
Short name T711
Test name
Test status
Simulation time 135868597 ps
CPU time 1.18 seconds
Started Jul 31 05:56:20 PM PDT 24
Finished Jul 31 05:56:21 PM PDT 24
Peak memory 201076 kb
Host smart-5ccb25f7-4d0b-4b31-bd39-4936fbb0ae27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363486301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.363486301
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1203821960
Short name T727
Test name
Test status
Simulation time 17744980 ps
CPU time 0.75 seconds
Started Jul 31 06:06:39 PM PDT 24
Finished Jul 31 06:06:40 PM PDT 24
Peak memory 201044 kb
Host smart-800b5b45-eabe-47af-a5f5-0a2a906211ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203821960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1203821960
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2497859469
Short name T106
Test name
Test status
Simulation time 20008845 ps
CPU time 0.89 seconds
Started Jul 31 06:06:32 PM PDT 24
Finished Jul 31 06:06:33 PM PDT 24
Peak memory 201096 kb
Host smart-a8c45154-6ab9-4019-8ca0-e40bb235f8ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497859469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.2497859469
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1831079865
Short name T166
Test name
Test status
Simulation time 14406257 ps
CPU time 0.72 seconds
Started Jul 31 06:06:35 PM PDT 24
Finished Jul 31 06:06:36 PM PDT 24
Peak memory 200272 kb
Host smart-b8388b22-6f99-410b-9bfd-46f22ed94097
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831079865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1831079865
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.3235797561
Short name T524
Test name
Test status
Simulation time 32275563 ps
CPU time 0.81 seconds
Started Jul 31 06:06:33 PM PDT 24
Finished Jul 31 06:06:34 PM PDT 24
Peak memory 201096 kb
Host smart-4c6db295-df21-4e75-9820-0c64e422657b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235797561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.3235797561
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.341864309
Short name T95
Test name
Test status
Simulation time 37067909 ps
CPU time 0.85 seconds
Started Jul 31 06:06:31 PM PDT 24
Finished Jul 31 06:06:32 PM PDT 24
Peak memory 200952 kb
Host smart-d78e637b-d73e-4ef4-aa79-38d17d5ba7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341864309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.341864309
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.2183760572
Short name T14
Test name
Test status
Simulation time 1155585396 ps
CPU time 9.44 seconds
Started Jul 31 06:06:31 PM PDT 24
Finished Jul 31 06:06:40 PM PDT 24
Peak memory 201116 kb
Host smart-cbe09d66-4da9-4205-9bfc-2e2ec6aaeb5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183760572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.2183760572
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.3771519120
Short name T690
Test name
Test status
Simulation time 614391253 ps
CPU time 4.89 seconds
Started Jul 31 06:06:28 PM PDT 24
Finished Jul 31 06:06:33 PM PDT 24
Peak memory 201208 kb
Host smart-cc98bf0d-659f-4026-8eca-5f16967fff2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771519120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.3771519120
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.97571016
Short name T411
Test name
Test status
Simulation time 31259712 ps
CPU time 0.83 seconds
Started Jul 31 06:06:34 PM PDT 24
Finished Jul 31 06:06:35 PM PDT 24
Peak memory 201104 kb
Host smart-97f0de1f-6c29-4973-adb8-c97bb7fd656e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97571016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.clkmgr_idle_intersig_mubi.97571016
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3981844013
Short name T638
Test name
Test status
Simulation time 19821818 ps
CPU time 0.91 seconds
Started Jul 31 06:06:31 PM PDT 24
Finished Jul 31 06:06:32 PM PDT 24
Peak memory 201048 kb
Host smart-54616611-59b0-4fd9-8745-be7764d2af0f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981844013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3981844013
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2603140675
Short name T364
Test name
Test status
Simulation time 41643523 ps
CPU time 0.86 seconds
Started Jul 31 06:06:35 PM PDT 24
Finished Jul 31 06:06:36 PM PDT 24
Peak memory 201080 kb
Host smart-1bc48bb2-0dee-492c-8ead-466ffd9fdea6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603140675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2603140675
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2907048890
Short name T715
Test name
Test status
Simulation time 40818128 ps
CPU time 0.89 seconds
Started Jul 31 06:06:36 PM PDT 24
Finished Jul 31 06:06:37 PM PDT 24
Peak memory 201004 kb
Host smart-b600ca5e-21f4-4c82-8a30-0687d6943d81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907048890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2907048890
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.367521300
Short name T197
Test name
Test status
Simulation time 1124852157 ps
CPU time 4.37 seconds
Started Jul 31 06:06:35 PM PDT 24
Finished Jul 31 06:06:39 PM PDT 24
Peak memory 201276 kb
Host smart-e636bb64-447d-4f27-bea4-db33ab4e40c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367521300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.367521300
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.3287932325
Short name T156
Test name
Test status
Simulation time 66362217 ps
CPU time 1 seconds
Started Jul 31 06:06:30 PM PDT 24
Finished Jul 31 06:06:31 PM PDT 24
Peak memory 200980 kb
Host smart-f84a34ba-9606-4a85-a775-4981d0793727
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287932325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.3287932325
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2622508451
Short name T583
Test name
Test status
Simulation time 10003535750 ps
CPU time 38.72 seconds
Started Jul 31 06:06:39 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201460 kb
Host smart-309437f0-06db-4b83-8f9c-80fad8e020b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622508451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2622508451
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.3134327843
Short name T239
Test name
Test status
Simulation time 27212413 ps
CPU time 0.97 seconds
Started Jul 31 06:06:35 PM PDT 24
Finished Jul 31 06:06:36 PM PDT 24
Peak memory 201088 kb
Host smart-1df154e5-7211-4505-9f9f-c3cd3b4fe829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134327843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3134327843
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.4010366088
Short name T423
Test name
Test status
Simulation time 40247741 ps
CPU time 0.86 seconds
Started Jul 31 06:06:45 PM PDT 24
Finished Jul 31 06:06:46 PM PDT 24
Peak memory 201108 kb
Host smart-5275a7cf-9d41-409a-8aff-794617688575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010366088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.4010366088
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1087935953
Short name T91
Test name
Test status
Simulation time 75715402 ps
CPU time 1 seconds
Started Jul 31 06:06:40 PM PDT 24
Finished Jul 31 06:06:41 PM PDT 24
Peak memory 201084 kb
Host smart-256c80c1-aab0-4152-a94a-db87e032f0e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087935953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.1087935953
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.825964933
Short name T676
Test name
Test status
Simulation time 33031946 ps
CPU time 0.72 seconds
Started Jul 31 06:06:39 PM PDT 24
Finished Jul 31 06:06:40 PM PDT 24
Peak memory 200204 kb
Host smart-d65c3163-5cb8-43cb-b549-bd287ff9de39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825964933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.825964933
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.4212607754
Short name T485
Test name
Test status
Simulation time 30603701 ps
CPU time 0.84 seconds
Started Jul 31 06:06:45 PM PDT 24
Finished Jul 31 06:06:46 PM PDT 24
Peak memory 201048 kb
Host smart-097e4224-6fea-4002-ac90-2c09077c4b28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212607754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.4212607754
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.405485401
Short name T271
Test name
Test status
Simulation time 23353567 ps
CPU time 0.8 seconds
Started Jul 31 06:06:41 PM PDT 24
Finished Jul 31 06:06:42 PM PDT 24
Peak memory 201008 kb
Host smart-80fe9d3e-7040-405f-8b7a-baef1e4468c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405485401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.405485401
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.153392260
Short name T302
Test name
Test status
Simulation time 2116492121 ps
CPU time 16.1 seconds
Started Jul 31 06:06:40 PM PDT 24
Finished Jul 31 06:06:57 PM PDT 24
Peak memory 201316 kb
Host smart-5e3593d4-b510-4242-9990-540ae9de6575
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153392260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.153392260
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.484815504
Short name T399
Test name
Test status
Simulation time 1099450364 ps
CPU time 5.86 seconds
Started Jul 31 06:06:41 PM PDT 24
Finished Jul 31 06:06:47 PM PDT 24
Peak memory 201120 kb
Host smart-d2a99aa9-12a9-4c57-8241-4e174ff0e40d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484815504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.484815504
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.2950791350
Short name T221
Test name
Test status
Simulation time 106177373 ps
CPU time 1.28 seconds
Started Jul 31 06:06:38 PM PDT 24
Finished Jul 31 06:06:40 PM PDT 24
Peak memory 201004 kb
Host smart-6299388e-397f-4305-80a8-a1616c9ef631
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950791350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.2950791350
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.180099560
Short name T657
Test name
Test status
Simulation time 15386270 ps
CPU time 0.79 seconds
Started Jul 31 06:06:41 PM PDT 24
Finished Jul 31 06:06:42 PM PDT 24
Peak memory 201072 kb
Host smart-0833b0d1-a02d-49d1-b9c3-2047fce64a22
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180099560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_clk_byp_req_intersig_mubi.180099560
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.2555763185
Short name T306
Test name
Test status
Simulation time 63562012 ps
CPU time 0.93 seconds
Started Jul 31 06:06:38 PM PDT 24
Finished Jul 31 06:06:39 PM PDT 24
Peak memory 201052 kb
Host smart-b7be4c87-4532-49d3-bfc7-f2af2c438a99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555763185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.2555763185
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.1529965666
Short name T613
Test name
Test status
Simulation time 16253805 ps
CPU time 0.76 seconds
Started Jul 31 06:06:41 PM PDT 24
Finished Jul 31 06:06:42 PM PDT 24
Peak memory 201080 kb
Host smart-acc0d5de-59f4-4f51-92a2-1a7ad1f28142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529965666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1529965666
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.2103382023
Short name T502
Test name
Test status
Simulation time 1549822119 ps
CPU time 5.72 seconds
Started Jul 31 06:06:46 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 201304 kb
Host smart-8d5b0c78-59bb-4027-85d5-14409f55207f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103382023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.2103382023
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1847073056
Short name T504
Test name
Test status
Simulation time 21392921 ps
CPU time 0.87 seconds
Started Jul 31 06:06:37 PM PDT 24
Finished Jul 31 06:06:38 PM PDT 24
Peak memory 201060 kb
Host smart-26888613-4e39-46d9-83c9-8a0bff05c7fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847073056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1847073056
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.2633393833
Short name T428
Test name
Test status
Simulation time 6482721092 ps
CPU time 46.93 seconds
Started Jul 31 06:06:44 PM PDT 24
Finished Jul 31 06:07:31 PM PDT 24
Peak memory 201444 kb
Host smart-7fd079d1-8c84-4117-9323-852e6bba78cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633393833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.2633393833
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.199327387
Short name T675
Test name
Test status
Simulation time 24167998 ps
CPU time 0.77 seconds
Started Jul 31 06:06:40 PM PDT 24
Finished Jul 31 06:06:41 PM PDT 24
Peak memory 201088 kb
Host smart-3fb91f4a-3bf2-4124-b346-63ae94e047ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199327387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.199327387
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.2942622151
Short name T519
Test name
Test status
Simulation time 15401766 ps
CPU time 0.78 seconds
Started Jul 31 06:06:55 PM PDT 24
Finished Jul 31 06:06:56 PM PDT 24
Peak memory 201116 kb
Host smart-d184f8e2-2934-46c6-ad09-6a8023cbff72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942622151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.2942622151
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2495973406
Short name T270
Test name
Test status
Simulation time 16848110 ps
CPU time 0.77 seconds
Started Jul 31 06:06:51 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 201056 kb
Host smart-6edeceee-d365-4642-ba58-317101751d95
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495973406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2495973406
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2334800218
Short name T365
Test name
Test status
Simulation time 28812547 ps
CPU time 0.76 seconds
Started Jul 31 06:06:45 PM PDT 24
Finished Jul 31 06:06:46 PM PDT 24
Peak memory 200300 kb
Host smart-ffa75afe-f4d6-4a7c-be30-80ded9a0fc2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334800218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2334800218
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.422074117
Short name T413
Test name
Test status
Simulation time 89117617 ps
CPU time 1.04 seconds
Started Jul 31 06:06:49 PM PDT 24
Finished Jul 31 06:06:50 PM PDT 24
Peak memory 201092 kb
Host smart-d85bd140-0f5d-4bfa-849d-b0d774b74cb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422074117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_div_intersig_mubi.422074117
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.3731966139
Short name T282
Test name
Test status
Simulation time 32113815 ps
CPU time 0.83 seconds
Started Jul 31 06:06:44 PM PDT 24
Finished Jul 31 06:06:45 PM PDT 24
Peak memory 200988 kb
Host smart-19b9508c-9c3b-448a-83f0-1c643a0d9a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731966139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.3731966139
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3067642449
Short name T683
Test name
Test status
Simulation time 583368691 ps
CPU time 3.13 seconds
Started Jul 31 06:06:41 PM PDT 24
Finished Jul 31 06:06:45 PM PDT 24
Peak memory 201212 kb
Host smart-2dfe969f-1b5d-4efd-86cf-0ed4a5005664
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067642449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3067642449
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.1030415015
Short name T744
Test name
Test status
Simulation time 1497592732 ps
CPU time 5.69 seconds
Started Jul 31 06:06:46 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 201184 kb
Host smart-98e37c3e-d023-43c4-8685-ca73a0a0d9a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030415015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.1030415015
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.649594774
Short name T686
Test name
Test status
Simulation time 21667162 ps
CPU time 0.8 seconds
Started Jul 31 06:06:48 PM PDT 24
Finished Jul 31 06:06:49 PM PDT 24
Peak memory 201096 kb
Host smart-6e2c3ce9-216d-49ac-abe6-e7bc4b5ae82b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649594774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_idle_intersig_mubi.649594774
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3990654168
Short name T478
Test name
Test status
Simulation time 199989231 ps
CPU time 1.39 seconds
Started Jul 31 06:06:50 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 201052 kb
Host smart-4e3da418-31f3-4bf3-9bff-d7e377a56b2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990654168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3990654168
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3460256640
Short name T367
Test name
Test status
Simulation time 22721176 ps
CPU time 0.86 seconds
Started Jul 31 06:06:51 PM PDT 24
Finished Jul 31 06:06:52 PM PDT 24
Peak memory 201016 kb
Host smart-2b543c93-fb81-4eea-8dac-cfbe0e46066c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460256640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.3460256640
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.435377715
Short name T488
Test name
Test status
Simulation time 51250087 ps
CPU time 0.84 seconds
Started Jul 31 06:06:43 PM PDT 24
Finished Jul 31 06:06:43 PM PDT 24
Peak memory 201076 kb
Host smart-ba94f58c-dfbe-46bc-a881-e12eb8dbafe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435377715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.435377715
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2573372181
Short name T37
Test name
Test status
Simulation time 564793264 ps
CPU time 2.57 seconds
Started Jul 31 06:06:55 PM PDT 24
Finished Jul 31 06:06:57 PM PDT 24
Peak memory 201188 kb
Host smart-1683821a-4b8b-4491-adc7-4fcd8e07e3ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573372181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2573372181
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.1192269245
Short name T695
Test name
Test status
Simulation time 63759901 ps
CPU time 0.95 seconds
Started Jul 31 06:06:44 PM PDT 24
Finished Jul 31 06:06:46 PM PDT 24
Peak memory 201112 kb
Host smart-c2ec8264-c2b1-4f7f-a1ae-27523d426aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192269245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1192269245
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1085068489
Short name T569
Test name
Test status
Simulation time 167797845 ps
CPU time 1.41 seconds
Started Jul 31 06:06:55 PM PDT 24
Finished Jul 31 06:06:56 PM PDT 24
Peak memory 200988 kb
Host smart-fe310c6b-628e-4003-bd85-db42de26c81a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085068489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1085068489
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1612201861
Short name T541
Test name
Test status
Simulation time 35986898 ps
CPU time 0.98 seconds
Started Jul 31 06:06:44 PM PDT 24
Finished Jul 31 06:06:45 PM PDT 24
Peak memory 201088 kb
Host smart-eee8d3d9-850b-4a85-8752-472355c7a198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612201861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1612201861
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.1713754981
Short name T734
Test name
Test status
Simulation time 13711618 ps
CPU time 0.71 seconds
Started Jul 31 06:06:59 PM PDT 24
Finished Jul 31 06:07:00 PM PDT 24
Peak memory 201040 kb
Host smart-92f5fdea-2723-481b-866e-c44584c57094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713754981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.1713754981
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.337696423
Short name T334
Test name
Test status
Simulation time 38237418 ps
CPU time 0.91 seconds
Started Jul 31 06:07:00 PM PDT 24
Finished Jul 31 06:07:01 PM PDT 24
Peak memory 201112 kb
Host smart-d7dd06e9-58a5-4e07-8e7d-46d952ef6004
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337696423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.337696423
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.2427184289
Short name T299
Test name
Test status
Simulation time 16771517 ps
CPU time 0.78 seconds
Started Jul 31 06:07:06 PM PDT 24
Finished Jul 31 06:07:07 PM PDT 24
Peak memory 200980 kb
Host smart-0e4a005d-7a3f-4901-83a3-b1c1b8953c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427184289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.2427184289
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2152428121
Short name T472
Test name
Test status
Simulation time 63389382 ps
CPU time 0.94 seconds
Started Jul 31 06:07:00 PM PDT 24
Finished Jul 31 06:07:01 PM PDT 24
Peak memory 201036 kb
Host smart-5aac8e43-d81b-43b2-838d-6129b7a79b76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152428121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2152428121
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.4172849830
Short name T347
Test name
Test status
Simulation time 22118233 ps
CPU time 0.89 seconds
Started Jul 31 06:06:55 PM PDT 24
Finished Jul 31 06:06:56 PM PDT 24
Peak memory 201028 kb
Host smart-17765b77-ec9f-4bef-98d1-ee6fb6cb95a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172849830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.4172849830
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.610180343
Short name T753
Test name
Test status
Simulation time 1118151485 ps
CPU time 4.4 seconds
Started Jul 31 06:06:56 PM PDT 24
Finished Jul 31 06:07:00 PM PDT 24
Peak memory 201140 kb
Host smart-389a2a1c-713b-4992-9d7a-a58693e9a678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610180343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.610180343
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3749214990
Short name T720
Test name
Test status
Simulation time 2027442388 ps
CPU time 7.63 seconds
Started Jul 31 06:07:00 PM PDT 24
Finished Jul 31 06:07:08 PM PDT 24
Peak memory 201188 kb
Host smart-08afcea5-9f7a-4262-a076-3698553bdf4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749214990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3749214990
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.2381344482
Short name T362
Test name
Test status
Simulation time 176241952 ps
CPU time 1.34 seconds
Started Jul 31 06:07:00 PM PDT 24
Finished Jul 31 06:07:02 PM PDT 24
Peak memory 201016 kb
Host smart-f08823ce-362b-4a11-b4f9-6b1e691432b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381344482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.2381344482
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.806565151
Short name T531
Test name
Test status
Simulation time 18025184 ps
CPU time 0.78 seconds
Started Jul 31 06:06:59 PM PDT 24
Finished Jul 31 06:07:00 PM PDT 24
Peak memory 201084 kb
Host smart-34c16b7d-9d4a-4b70-b68b-35b417797625
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806565151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_clk_byp_req_intersig_mubi.806565151
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.2553296697
Short name T273
Test name
Test status
Simulation time 35779052 ps
CPU time 0.88 seconds
Started Jul 31 06:07:06 PM PDT 24
Finished Jul 31 06:07:07 PM PDT 24
Peak memory 201036 kb
Host smart-95a9befb-5d8c-46fb-b3f9-7011b72150d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553296697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.2553296697
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2720478664
Short name T226
Test name
Test status
Simulation time 25868362 ps
CPU time 0.82 seconds
Started Jul 31 06:07:00 PM PDT 24
Finished Jul 31 06:07:01 PM PDT 24
Peak memory 201056 kb
Host smart-2c98fc0b-3d14-4f5c-bb15-738d6a082196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720478664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2720478664
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.771235379
Short name T587
Test name
Test status
Simulation time 723939862 ps
CPU time 3.12 seconds
Started Jul 31 06:06:59 PM PDT 24
Finished Jul 31 06:07:02 PM PDT 24
Peak memory 201276 kb
Host smart-70641fb6-c5ef-486b-ab86-24cabc370c8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771235379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.771235379
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2145560143
Short name T616
Test name
Test status
Simulation time 24255701 ps
CPU time 0.87 seconds
Started Jul 31 06:06:55 PM PDT 24
Finished Jul 31 06:06:56 PM PDT 24
Peak memory 201092 kb
Host smart-000f551c-f8fa-41cf-af2a-1a6b94b036f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145560143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2145560143
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.567453070
Short name T154
Test name
Test status
Simulation time 2914710600 ps
CPU time 18.71 seconds
Started Jul 31 06:07:01 PM PDT 24
Finished Jul 31 06:07:20 PM PDT 24
Peak memory 201436 kb
Host smart-beef23e9-e524-4994-84dd-7772d527b7d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567453070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.567453070
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.174284133
Short name T304
Test name
Test status
Simulation time 41942717 ps
CPU time 1.16 seconds
Started Jul 31 06:07:02 PM PDT 24
Finished Jul 31 06:07:03 PM PDT 24
Peak memory 201104 kb
Host smart-667e60df-ec15-48da-b2d9-ef186ea90a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174284133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.174284133
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.801964609
Short name T40
Test name
Test status
Simulation time 15458540 ps
CPU time 0.78 seconds
Started Jul 31 06:07:09 PM PDT 24
Finished Jul 31 06:07:10 PM PDT 24
Peak memory 201060 kb
Host smart-8ff35955-4e65-409a-9fa8-5f98dc171c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801964609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.801964609
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.2457451946
Short name T781
Test name
Test status
Simulation time 28422965 ps
CPU time 0.95 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 201064 kb
Host smart-89bc19e5-f6c8-4bde-bbcb-e3df0f205f47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457451946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.2457451946
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2643066628
Short name T51
Test name
Test status
Simulation time 14202271 ps
CPU time 0.69 seconds
Started Jul 31 06:07:04 PM PDT 24
Finished Jul 31 06:07:05 PM PDT 24
Peak memory 200244 kb
Host smart-e5ec8415-2bbf-476d-b8de-f1ecc9bd4a33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643066628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2643066628
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.1188718273
Short name T394
Test name
Test status
Simulation time 36831526 ps
CPU time 0.84 seconds
Started Jul 31 06:07:04 PM PDT 24
Finished Jul 31 06:07:05 PM PDT 24
Peak memory 201084 kb
Host smart-a811f7c3-17c8-4438-9a0f-be316660fb99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188718273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.1188718273
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.3902071015
Short name T492
Test name
Test status
Simulation time 33263937 ps
CPU time 0.83 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 200996 kb
Host smart-b3ba00c4-a8b2-48e5-9a65-3078eca0addc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902071015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3902071015
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.3321129134
Short name T377
Test name
Test status
Simulation time 1607615187 ps
CPU time 7.61 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:12 PM PDT 24
Peak memory 201088 kb
Host smart-6bb7922f-7dbe-41e0-a89e-9b8a39b7eff9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321129134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3321129134
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.1373111396
Short name T391
Test name
Test status
Simulation time 686525384 ps
CPU time 3.05 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:08 PM PDT 24
Peak memory 201100 kb
Host smart-667de86a-5353-4a52-aa88-37b53d4cff96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373111396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.1373111396
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3202844917
Short name T419
Test name
Test status
Simulation time 55951046 ps
CPU time 1.03 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:06 PM PDT 24
Peak memory 201052 kb
Host smart-2504e7da-b4d4-4a9c-a447-e0cbdd236891
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202844917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.3202844917
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1655749545
Short name T432
Test name
Test status
Simulation time 39458354 ps
CPU time 0.88 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:06 PM PDT 24
Peak memory 201040 kb
Host smart-b924e6cc-7698-476a-99ee-1fd16f585d0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655749545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1655749545
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.258479069
Short name T723
Test name
Test status
Simulation time 19723661 ps
CPU time 0.83 seconds
Started Jul 31 06:07:04 PM PDT 24
Finished Jul 31 06:07:05 PM PDT 24
Peak memory 201048 kb
Host smart-376d9267-0cec-4bca-b069-aa93303ecc34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258479069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 44.clkmgr_lc_ctrl_intersig_mubi.258479069
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.3419373520
Short name T506
Test name
Test status
Simulation time 42885981 ps
CPU time 0.9 seconds
Started Jul 31 06:07:04 PM PDT 24
Finished Jul 31 06:07:05 PM PDT 24
Peak memory 201036 kb
Host smart-3b0db0d7-0d8f-4322-9c79-f42bc7c91b01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419373520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3419373520
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.64098627
Short name T324
Test name
Test status
Simulation time 345032167 ps
CPU time 2.48 seconds
Started Jul 31 06:07:01 PM PDT 24
Finished Jul 31 06:07:03 PM PDT 24
Peak memory 201116 kb
Host smart-90929382-30d4-4e23-835f-800d67d2ed5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64098627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.64098627
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.3888060088
Short name T384
Test name
Test status
Simulation time 16554287 ps
CPU time 0.84 seconds
Started Jul 31 06:07:07 PM PDT 24
Finished Jul 31 06:07:08 PM PDT 24
Peak memory 201012 kb
Host smart-273d2b2d-9448-4154-b3bf-3cd3d63f78f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888060088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3888060088
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.3983362671
Short name T225
Test name
Test status
Simulation time 3013165997 ps
CPU time 12.46 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:21 PM PDT 24
Peak memory 201424 kb
Host smart-bdc5cb99-5fe2-4146-b5f8-383f8ed24f44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983362671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.3983362671
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.1412132210
Short name T251
Test name
Test status
Simulation time 148061689 ps
CPU time 1.37 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:07 PM PDT 24
Peak memory 201052 kb
Host smart-320c110a-bb1f-46d7-8c0e-877bdfa85384
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412132210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1412132210
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.4130765002
Short name T809
Test name
Test status
Simulation time 17170721 ps
CPU time 0.77 seconds
Started Jul 31 06:07:14 PM PDT 24
Finished Jul 31 06:07:15 PM PDT 24
Peak memory 201056 kb
Host smart-5857c117-3800-48ed-b77f-61e689caa6ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130765002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.4130765002
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2687464266
Short name T231
Test name
Test status
Simulation time 67091923 ps
CPU time 0.88 seconds
Started Jul 31 06:07:09 PM PDT 24
Finished Jul 31 06:07:10 PM PDT 24
Peak memory 201036 kb
Host smart-46f89437-b423-4f5f-8813-947af3af66de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687464266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.2687464266
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3264956037
Short name T408
Test name
Test status
Simulation time 26923313 ps
CPU time 0.77 seconds
Started Jul 31 06:07:05 PM PDT 24
Finished Jul 31 06:07:06 PM PDT 24
Peak memory 200304 kb
Host smart-3e22e645-8e6d-4892-8bc4-042497dbc176
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264956037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3264956037
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.3376186744
Short name T258
Test name
Test status
Simulation time 50623982 ps
CPU time 0.82 seconds
Started Jul 31 06:07:11 PM PDT 24
Finished Jul 31 06:07:12 PM PDT 24
Peak memory 201060 kb
Host smart-558898c4-8bc8-4e81-be0f-bee9b1e4b83a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376186744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.3376186744
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.1849286062
Short name T30
Test name
Test status
Simulation time 16856374 ps
CPU time 0.76 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 201036 kb
Host smart-2279691a-2c86-4657-8df8-d1797f62d46a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849286062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1849286062
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.3928989699
Short name T329
Test name
Test status
Simulation time 2362459026 ps
CPU time 18.32 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:26 PM PDT 24
Peak memory 201104 kb
Host smart-9a53cee2-358d-4974-8842-6bb0cfd3d2bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928989699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.3928989699
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.3995816083
Short name T249
Test name
Test status
Simulation time 1370411945 ps
CPU time 5.87 seconds
Started Jul 31 06:07:09 PM PDT 24
Finished Jul 31 06:07:15 PM PDT 24
Peak memory 201192 kb
Host smart-78b3b017-f838-4bde-9729-f3a319905259
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995816083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.3995816083
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.1291673320
Short name T671
Test name
Test status
Simulation time 72361285 ps
CPU time 1.22 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 200976 kb
Host smart-f0676731-3f16-4f44-a900-3c5212ac36c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291673320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.1291673320
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1550705612
Short name T628
Test name
Test status
Simulation time 53064497 ps
CPU time 0.95 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 201008 kb
Host smart-def873fa-9d14-4573-80a4-a0bbcdd2f8fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550705612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1550705612
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1071859330
Short name T624
Test name
Test status
Simulation time 32409438 ps
CPU time 0.78 seconds
Started Jul 31 06:07:09 PM PDT 24
Finished Jul 31 06:07:10 PM PDT 24
Peak memory 201084 kb
Host smart-999dd629-8728-4039-8076-34eecea56857
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071859330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.1071859330
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.189698997
Short name T649
Test name
Test status
Simulation time 36295639 ps
CPU time 0.8 seconds
Started Jul 31 06:07:15 PM PDT 24
Finished Jul 31 06:07:16 PM PDT 24
Peak memory 201056 kb
Host smart-e0b76344-354f-41b6-bf50-cfa4d9faa020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189698997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.189698997
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2453658694
Short name T554
Test name
Test status
Simulation time 24004925 ps
CPU time 0.9 seconds
Started Jul 31 06:07:07 PM PDT 24
Finished Jul 31 06:07:08 PM PDT 24
Peak memory 201040 kb
Host smart-52b9afc4-8757-4836-8d35-69e17684aa86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453658694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2453658694
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3327671141
Short name T612
Test name
Test status
Simulation time 7524614887 ps
CPU time 31.85 seconds
Started Jul 31 06:07:13 PM PDT 24
Finished Jul 31 06:07:45 PM PDT 24
Peak memory 201456 kb
Host smart-611e88f9-d782-488a-aea1-8f0a6ba46af3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327671141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3327671141
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1210853628
Short name T32
Test name
Test status
Simulation time 17480644 ps
CPU time 0.69 seconds
Started Jul 31 06:07:08 PM PDT 24
Finished Jul 31 06:07:09 PM PDT 24
Peak memory 200752 kb
Host smart-c26017ef-e080-4e62-b335-3882697ed763
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210853628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1210853628
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.2011222088
Short name T601
Test name
Test status
Simulation time 113965844 ps
CPU time 1.02 seconds
Started Jul 31 06:07:19 PM PDT 24
Finished Jul 31 06:07:20 PM PDT 24
Peak memory 201088 kb
Host smart-4ebd1c40-3876-4c31-b430-244b46c84b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011222088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.2011222088
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.2920811374
Short name T535
Test name
Test status
Simulation time 40137147 ps
CPU time 0.91 seconds
Started Jul 31 06:07:16 PM PDT 24
Finished Jul 31 06:07:17 PM PDT 24
Peak memory 201100 kb
Host smart-1a2c3415-6fe8-4083-929b-84e299864fb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920811374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.2920811374
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.875713566
Short name T618
Test name
Test status
Simulation time 23932270 ps
CPU time 0.75 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:07:19 PM PDT 24
Peak memory 200952 kb
Host smart-3705f0e6-f2d6-43c4-bdf5-dce2f33a1703
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875713566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.875713566
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.256965228
Short name T385
Test name
Test status
Simulation time 56931405 ps
CPU time 1.04 seconds
Started Jul 31 06:07:17 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201016 kb
Host smart-6db78a90-c2b5-44cf-a117-4c01c7042b9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256965228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.256965228
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.120139406
Short name T276
Test name
Test status
Simulation time 70747818 ps
CPU time 1.07 seconds
Started Jul 31 06:07:13 PM PDT 24
Finished Jul 31 06:07:14 PM PDT 24
Peak memory 201100 kb
Host smart-2659306b-fd3e-4690-a3fb-e70505510ad8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120139406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.120139406
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.149034793
Short name T451
Test name
Test status
Simulation time 1645312786 ps
CPU time 9.58 seconds
Started Jul 31 06:07:13 PM PDT 24
Finished Jul 31 06:07:23 PM PDT 24
Peak memory 201136 kb
Host smart-7fe71782-4418-4279-be52-ac0a9d68a46d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149034793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.149034793
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.2299137791
Short name T468
Test name
Test status
Simulation time 133782682 ps
CPU time 1.64 seconds
Started Jul 31 06:07:19 PM PDT 24
Finished Jul 31 06:07:21 PM PDT 24
Peak memory 201196 kb
Host smart-97e38480-f644-4bfb-aadf-c044c9b8bd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299137791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.2299137791
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.3840958680
Short name T636
Test name
Test status
Simulation time 29589110 ps
CPU time 1.02 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:07:19 PM PDT 24
Peak memory 201048 kb
Host smart-8c70c82e-a21c-4f0e-8130-e18f077c31d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840958680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.3840958680
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3440945965
Short name T735
Test name
Test status
Simulation time 20557741 ps
CPU time 0.88 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:07:19 PM PDT 24
Peak memory 201052 kb
Host smart-5736ac65-4e19-4e95-a0af-42335e12e783
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440945965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3440945965
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2594623994
Short name T441
Test name
Test status
Simulation time 23391803 ps
CPU time 0.86 seconds
Started Jul 31 06:07:17 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201096 kb
Host smart-f7c0315e-8d7b-422c-bfec-9826f3ea5499
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594623994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2594623994
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.3195866818
Short name T407
Test name
Test status
Simulation time 68871398 ps
CPU time 0.87 seconds
Started Jul 31 06:07:17 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201068 kb
Host smart-51a5b437-4f7e-469c-8680-fb62c730e3fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195866818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3195866818
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2736421285
Short name T784
Test name
Test status
Simulation time 1204420027 ps
CPU time 7.09 seconds
Started Jul 31 06:07:19 PM PDT 24
Finished Jul 31 06:07:26 PM PDT 24
Peak memory 201284 kb
Host smart-ff83b815-ddd2-4b2c-840f-b72f03c268bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736421285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2736421285
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.911119869
Short name T553
Test name
Test status
Simulation time 74184048 ps
CPU time 1.05 seconds
Started Jul 31 06:07:16 PM PDT 24
Finished Jul 31 06:07:17 PM PDT 24
Peak memory 201028 kb
Host smart-08bf9759-b9f8-4365-b1e7-19d9d568de2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911119869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.911119869
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_trans.3093947741
Short name T356
Test name
Test status
Simulation time 44773164 ps
CPU time 1.03 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:07:19 PM PDT 24
Peak memory 201008 kb
Host smart-5e2d9862-c3b7-4bc7-add9-f219f6a26c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093947741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.3093947741
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.4254918466
Short name T589
Test name
Test status
Simulation time 14267894 ps
CPU time 0.73 seconds
Started Jul 31 06:07:28 PM PDT 24
Finished Jul 31 06:07:29 PM PDT 24
Peak memory 201024 kb
Host smart-eef0b6f1-1b69-4388-8723-a3e19dc345bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254918466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.4254918466
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.123667510
Short name T104
Test name
Test status
Simulation time 48093169 ps
CPU time 0.97 seconds
Started Jul 31 06:07:19 PM PDT 24
Finished Jul 31 06:07:20 PM PDT 24
Peak memory 201156 kb
Host smart-b25cf4b2-e171-4f23-8b74-242268aa617c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123667510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.123667510
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1014581169
Short name T174
Test name
Test status
Simulation time 15614693 ps
CPU time 0.72 seconds
Started Jul 31 06:07:25 PM PDT 24
Finished Jul 31 06:07:26 PM PDT 24
Peak memory 200208 kb
Host smart-472ce319-5082-4a1e-bb74-8cec80158b5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014581169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1014581169
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.2272546968
Short name T186
Test name
Test status
Simulation time 65173768 ps
CPU time 0.96 seconds
Started Jul 31 06:07:24 PM PDT 24
Finished Jul 31 06:07:25 PM PDT 24
Peak memory 201100 kb
Host smart-779f99aa-3b55-41d3-a468-363a04a9f4e0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272546968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.2272546968
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1820629202
Short name T470
Test name
Test status
Simulation time 16988035 ps
CPU time 0.77 seconds
Started Jul 31 06:07:17 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 200996 kb
Host smart-f7ed7b07-bcb4-4e9c-a8b5-c0bf2bc52f12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820629202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1820629202
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.792934662
Short name T372
Test name
Test status
Simulation time 2476139350 ps
CPU time 18.79 seconds
Started Jul 31 06:07:18 PM PDT 24
Finished Jul 31 06:07:37 PM PDT 24
Peak memory 201372 kb
Host smart-d61d98a2-c836-45e0-ac0c-09b81b4705eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792934662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.792934662
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.90635563
Short name T196
Test name
Test status
Simulation time 1104300948 ps
CPU time 5.96 seconds
Started Jul 31 06:07:22 PM PDT 24
Finished Jul 31 06:07:28 PM PDT 24
Peak memory 201124 kb
Host smart-d053790d-18bb-4a82-828d-9137a0c8ccfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90635563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_tim
eout.90635563
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.924150266
Short name T637
Test name
Test status
Simulation time 35146650 ps
CPU time 0.97 seconds
Started Jul 31 06:07:26 PM PDT 24
Finished Jul 31 06:07:27 PM PDT 24
Peak memory 201088 kb
Host smart-e51253aa-96e0-411e-b7a4-409c12b6f6a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924150266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_idle_intersig_mubi.924150266
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.91132536
Short name T565
Test name
Test status
Simulation time 100699051 ps
CPU time 1 seconds
Started Jul 31 06:07:22 PM PDT 24
Finished Jul 31 06:07:23 PM PDT 24
Peak memory 201112 kb
Host smart-bb17cb3b-5b99-4c8b-963d-8e19cd2cae02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91132536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_lc_clk_byp_req_intersig_mubi.91132536
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.4110987760
Short name T286
Test name
Test status
Simulation time 17427495 ps
CPU time 0.81 seconds
Started Jul 31 06:07:22 PM PDT 24
Finished Jul 31 06:07:23 PM PDT 24
Peak memory 201100 kb
Host smart-e35c53ab-8569-4820-b39b-546bea010470
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110987760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.4110987760
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.4142563459
Short name T579
Test name
Test status
Simulation time 36475853 ps
CPU time 0.8 seconds
Started Jul 31 06:07:24 PM PDT 24
Finished Jul 31 06:07:25 PM PDT 24
Peak memory 201036 kb
Host smart-0975dc1e-0c3a-487e-ba01-9c5005d895fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142563459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.4142563459
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.3726452196
Short name T759
Test name
Test status
Simulation time 1453208333 ps
CPU time 5.31 seconds
Started Jul 31 06:07:26 PM PDT 24
Finished Jul 31 06:07:31 PM PDT 24
Peak memory 201280 kb
Host smart-5a19dadc-bb07-48b1-8fff-32103ff27b92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726452196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.3726452196
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.1758123547
Short name T402
Test name
Test status
Simulation time 89099373 ps
CPU time 1.01 seconds
Started Jul 31 06:07:17 PM PDT 24
Finished Jul 31 06:07:18 PM PDT 24
Peak memory 201108 kb
Host smart-0fa87cd1-c2ea-4b67-9489-b250438a61f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758123547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1758123547
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.330664908
Short name T669
Test name
Test status
Simulation time 8731064677 ps
CPU time 32.04 seconds
Started Jul 31 06:07:30 PM PDT 24
Finished Jul 31 06:08:02 PM PDT 24
Peak memory 201368 kb
Host smart-6fc674da-b261-455e-a64c-d1bfa9b3fab3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330664908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.330664908
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.79143565
Short name T169
Test name
Test status
Simulation time 88797733722 ps
CPU time 540.23 seconds
Started Jul 31 06:07:28 PM PDT 24
Finished Jul 31 06:16:28 PM PDT 24
Peak memory 217884 kb
Host smart-98e2f54f-cb4c-49da-9c5c-f60d7ad64b0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=79143565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.79143565
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.443005541
Short name T97
Test name
Test status
Simulation time 63124465 ps
CPU time 0.95 seconds
Started Jul 31 06:07:23 PM PDT 24
Finished Jul 31 06:07:24 PM PDT 24
Peak memory 201112 kb
Host smart-266944ea-1524-4ed8-a0d8-1e71e5d7ecff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443005541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.443005541
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.1115079627
Short name T556
Test name
Test status
Simulation time 14663800 ps
CPU time 0.77 seconds
Started Jul 31 06:07:38 PM PDT 24
Finished Jul 31 06:07:38 PM PDT 24
Peak memory 201036 kb
Host smart-c14cc28e-2ebb-47f3-a2ca-7e8f8f2d93c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115079627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.1115079627
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.3712197238
Short name T767
Test name
Test status
Simulation time 54447137 ps
CPU time 0.92 seconds
Started Jul 31 06:07:33 PM PDT 24
Finished Jul 31 06:07:34 PM PDT 24
Peak memory 201064 kb
Host smart-08ef1e23-cbd4-4ec3-8216-c2faff456a82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712197238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.3712197238
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.1684598411
Short name T551
Test name
Test status
Simulation time 17975505 ps
CPU time 0.71 seconds
Started Jul 31 06:07:32 PM PDT 24
Finished Jul 31 06:07:33 PM PDT 24
Peak memory 200960 kb
Host smart-3f45de7e-e82b-49f6-8bf7-ded789a0316c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684598411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1684598411
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.1317303493
Short name T157
Test name
Test status
Simulation time 50250930 ps
CPU time 0.92 seconds
Started Jul 31 06:07:34 PM PDT 24
Finished Jul 31 06:07:35 PM PDT 24
Peak memory 201092 kb
Host smart-a9379278-24ab-462d-af4d-a21c11b3e42b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317303493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.1317303493
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.2081891119
Short name T666
Test name
Test status
Simulation time 13593862 ps
CPU time 0.74 seconds
Started Jul 31 06:07:26 PM PDT 24
Finished Jul 31 06:07:27 PM PDT 24
Peak memory 200908 kb
Host smart-3d5aced5-f9d5-48cb-a281-937fb22b308c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081891119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.2081891119
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.3570499770
Short name T237
Test name
Test status
Simulation time 1086578617 ps
CPU time 5.88 seconds
Started Jul 31 06:07:27 PM PDT 24
Finished Jul 31 06:07:33 PM PDT 24
Peak memory 201188 kb
Host smart-485e4bc3-828a-479e-b30e-d5b3a11add21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570499770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3570499770
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3718849839
Short name T293
Test name
Test status
Simulation time 1945355066 ps
CPU time 10.23 seconds
Started Jul 31 06:07:28 PM PDT 24
Finished Jul 31 06:07:38 PM PDT 24
Peak memory 201192 kb
Host smart-8988eddf-a199-446c-8bdf-1350e0c42bc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718849839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3718849839
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2997109037
Short name T577
Test name
Test status
Simulation time 41976890 ps
CPU time 0.94 seconds
Started Jul 31 06:07:33 PM PDT 24
Finished Jul 31 06:07:34 PM PDT 24
Peak memory 201120 kb
Host smart-24a90b95-eae1-4528-a5ad-f81b07baa62d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997109037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2997109037
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.2508154482
Short name T398
Test name
Test status
Simulation time 15923873 ps
CPU time 0.71 seconds
Started Jul 31 06:07:33 PM PDT 24
Finished Jul 31 06:07:33 PM PDT 24
Peak memory 201068 kb
Host smart-aeac8d19-b738-4443-a053-05376783a75d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508154482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.2508154482
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2652499713
Short name T620
Test name
Test status
Simulation time 48633222 ps
CPU time 0.9 seconds
Started Jul 31 06:07:33 PM PDT 24
Finished Jul 31 06:07:34 PM PDT 24
Peak memory 201056 kb
Host smart-6db04e1a-ee81-4cf4-82c4-0384773aa670
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652499713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2652499713
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3020130714
Short name T201
Test name
Test status
Simulation time 15597945 ps
CPU time 0.76 seconds
Started Jul 31 06:07:31 PM PDT 24
Finished Jul 31 06:07:31 PM PDT 24
Peak memory 201056 kb
Host smart-dba89044-5c64-4eed-befd-481b3471dd85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020130714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3020130714
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.1419803341
Short name T678
Test name
Test status
Simulation time 560293692 ps
CPU time 2.46 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:07:40 PM PDT 24
Peak memory 201192 kb
Host smart-ac0f750b-1103-4735-b240-cad29ee63f59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419803341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1419803341
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.931205258
Short name T445
Test name
Test status
Simulation time 55620167 ps
CPU time 0.94 seconds
Started Jul 31 06:07:30 PM PDT 24
Finished Jul 31 06:07:31 PM PDT 24
Peak memory 200960 kb
Host smart-d9ab6060-80fd-4bb9-a8ae-17f38cb7ffe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931205258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.931205258
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.710535837
Short name T238
Test name
Test status
Simulation time 10174515052 ps
CPU time 55.16 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:08:32 PM PDT 24
Peak memory 201428 kb
Host smart-73394646-4d68-4962-a413-c04500eec8e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710535837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.710535837
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.2092098364
Short name T72
Test name
Test status
Simulation time 56552115729 ps
CPU time 388.02 seconds
Started Jul 31 06:07:38 PM PDT 24
Finished Jul 31 06:14:06 PM PDT 24
Peak memory 217852 kb
Host smart-a76dca7b-ee3b-4cc6-9301-316cfd1a86be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2092098364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.2092098364
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3085306168
Short name T773
Test name
Test status
Simulation time 28026889 ps
CPU time 0.95 seconds
Started Jul 31 06:07:25 PM PDT 24
Finished Jul 31 06:07:26 PM PDT 24
Peak memory 201092 kb
Host smart-323c565d-8b0f-40a1-8bc8-81a48ef9f841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085306168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3085306168
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.3046533315
Short name T467
Test name
Test status
Simulation time 17127619 ps
CPU time 0.75 seconds
Started Jul 31 06:07:42 PM PDT 24
Finished Jul 31 06:07:43 PM PDT 24
Peak memory 201112 kb
Host smart-edbf6da3-a6e4-4b88-b344-e648743460d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046533315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.3046533315
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1733794071
Short name T234
Test name
Test status
Simulation time 35560198 ps
CPU time 0.91 seconds
Started Jul 31 06:07:43 PM PDT 24
Finished Jul 31 06:07:44 PM PDT 24
Peak memory 201084 kb
Host smart-3932edd4-f6e1-42b3-8ab1-6577f20eb3bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733794071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1733794071
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.929168163
Short name T440
Test name
Test status
Simulation time 18519515 ps
CPU time 0.77 seconds
Started Jul 31 06:07:46 PM PDT 24
Finished Jul 31 06:07:47 PM PDT 24
Peak memory 200252 kb
Host smart-5cee671f-62c1-4c10-b3a1-4d8658bc103c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929168163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.929168163
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.233012921
Short name T471
Test name
Test status
Simulation time 87407157 ps
CPU time 1.04 seconds
Started Jul 31 06:07:42 PM PDT 24
Finished Jul 31 06:07:43 PM PDT 24
Peak memory 201092 kb
Host smart-2bb4c5f5-98dc-4c9c-83bf-ec6ee1ad0a02
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233012921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_div_intersig_mubi.233012921
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2757924666
Short name T291
Test name
Test status
Simulation time 195568432 ps
CPU time 1.24 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:07:38 PM PDT 24
Peak memory 200984 kb
Host smart-b3c3a49e-fc02-47ba-a7a5-4106fc6e14ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757924666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2757924666
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.1305213820
Short name T550
Test name
Test status
Simulation time 2004995129 ps
CPU time 11.2 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:07:48 PM PDT 24
Peak memory 201368 kb
Host smart-53840a8d-8f0c-40a0-975e-8930291c6950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305213820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.1305213820
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.3010959553
Short name T315
Test name
Test status
Simulation time 2062260185 ps
CPU time 14.2 seconds
Started Jul 31 06:07:38 PM PDT 24
Finished Jul 31 06:07:52 PM PDT 24
Peak memory 201368 kb
Host smart-1a65f144-88d5-4b8e-af88-d5a6313a9b55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010959553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.3010959553
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1266830824
Short name T165
Test name
Test status
Simulation time 95578183 ps
CPU time 1.17 seconds
Started Jul 31 06:07:42 PM PDT 24
Finished Jul 31 06:07:43 PM PDT 24
Peak memory 200980 kb
Host smart-9e522ef5-95ce-40d1-8a28-98a5f1884a4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266830824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.1266830824
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1553649578
Short name T708
Test name
Test status
Simulation time 116887346 ps
CPU time 1.06 seconds
Started Jul 31 06:07:42 PM PDT 24
Finished Jul 31 06:07:43 PM PDT 24
Peak memory 201044 kb
Host smart-9ad6d063-c956-4e18-9190-bc900504cfc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553649578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1553649578
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3703709950
Short name T436
Test name
Test status
Simulation time 30064417 ps
CPU time 0.85 seconds
Started Jul 31 06:07:41 PM PDT 24
Finished Jul 31 06:07:42 PM PDT 24
Peak memory 201072 kb
Host smart-d0940b62-6022-4a3e-a657-ecab18ad791f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703709950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3703709950
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.975378732
Short name T462
Test name
Test status
Simulation time 49406035 ps
CPU time 0.85 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:07:38 PM PDT 24
Peak memory 200980 kb
Host smart-3e385f62-7757-44a9-85bc-00cf45ce1ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975378732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.975378732
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.321574620
Short name T777
Test name
Test status
Simulation time 1099140610 ps
CPU time 5.02 seconds
Started Jul 31 06:07:43 PM PDT 24
Finished Jul 31 06:07:48 PM PDT 24
Peak memory 201228 kb
Host smart-c9eb10a2-3cc9-4a2b-abaf-5aaf652899f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321574620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.321574620
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.2519096656
Short name T758
Test name
Test status
Simulation time 58526161 ps
CPU time 0.96 seconds
Started Jul 31 06:07:37 PM PDT 24
Finished Jul 31 06:07:38 PM PDT 24
Peak memory 201052 kb
Host smart-cc69e30b-4091-4e37-a41c-960d93427be7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519096656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2519096656
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1901809628
Short name T342
Test name
Test status
Simulation time 6324614816 ps
CPU time 46.81 seconds
Started Jul 31 06:07:43 PM PDT 24
Finished Jul 31 06:08:30 PM PDT 24
Peak memory 201444 kb
Host smart-39d7f6ed-3403-4752-8640-ec0b00c28d89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901809628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1901809628
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1337580546
Short name T228
Test name
Test status
Simulation time 25544550 ps
CPU time 0.78 seconds
Started Jul 31 06:07:42 PM PDT 24
Finished Jul 31 06:07:43 PM PDT 24
Peak memory 201088 kb
Host smart-c2860958-618b-434c-b49c-e0ecd61741fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337580546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1337580546
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.3663176402
Short name T691
Test name
Test status
Simulation time 56068446 ps
CPU time 0.88 seconds
Started Jul 31 05:56:57 PM PDT 24
Finished Jul 31 05:56:58 PM PDT 24
Peak memory 201072 kb
Host smart-ef1ea78b-ef71-4dc5-a714-57a0218f4f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663176402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.3663176402
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.4053550854
Short name T101
Test name
Test status
Simulation time 67391999 ps
CPU time 1 seconds
Started Jul 31 05:56:47 PM PDT 24
Finished Jul 31 05:56:48 PM PDT 24
Peak memory 201040 kb
Host smart-f2ef5eea-e9a9-4d57-bf2d-5a8844f6ccc1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053550854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.4053550854
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.4290652573
Short name T465
Test name
Test status
Simulation time 16275202 ps
CPU time 0.69 seconds
Started Jul 31 05:56:39 PM PDT 24
Finished Jul 31 05:56:40 PM PDT 24
Peak memory 200224 kb
Host smart-00c9acc1-c472-454d-a17b-1a0be76d39d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290652573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.4290652573
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.4212223806
Short name T185
Test name
Test status
Simulation time 19066433 ps
CPU time 0.83 seconds
Started Jul 31 05:56:50 PM PDT 24
Finished Jul 31 05:56:51 PM PDT 24
Peak memory 201048 kb
Host smart-cb6dde27-9e0a-44a9-9308-9759f09aebf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212223806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.4212223806
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.609776619
Short name T284
Test name
Test status
Simulation time 49114435 ps
CPU time 0.85 seconds
Started Jul 31 05:56:31 PM PDT 24
Finished Jul 31 05:56:32 PM PDT 24
Peak memory 201108 kb
Host smart-089528b1-e3fa-4535-9e13-cb56b640f05d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609776619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.609776619
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2400205731
Short name T503
Test name
Test status
Simulation time 1076026336 ps
CPU time 5.23 seconds
Started Jul 31 05:56:33 PM PDT 24
Finished Jul 31 05:56:38 PM PDT 24
Peak memory 201040 kb
Host smart-3ae95c7c-cfbf-46a0-9d0a-44701383dc2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400205731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2400205731
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.2445223887
Short name T539
Test name
Test status
Simulation time 2318570783 ps
CPU time 9.48 seconds
Started Jul 31 05:56:39 PM PDT 24
Finished Jul 31 05:56:49 PM PDT 24
Peak memory 201400 kb
Host smart-f6624a0f-07a3-4d06-be5f-52e7dde4a7eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445223887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.2445223887
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3542073350
Short name T769
Test name
Test status
Simulation time 18894472 ps
CPU time 0.81 seconds
Started Jul 31 05:56:41 PM PDT 24
Finished Jul 31 05:56:42 PM PDT 24
Peak memory 201068 kb
Host smart-31c0cc12-4d4e-4c64-b558-137d3ed572c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542073350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3542073350
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2984376886
Short name T561
Test name
Test status
Simulation time 63281842 ps
CPU time 0.94 seconds
Started Jul 31 05:56:44 PM PDT 24
Finished Jul 31 05:56:45 PM PDT 24
Peak memory 201056 kb
Host smart-9bc54222-9db8-4bf7-a5ec-c3c257b94ae5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984376886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2984376886
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3997002685
Short name T581
Test name
Test status
Simulation time 23045444 ps
CPU time 0.84 seconds
Started Jul 31 05:56:44 PM PDT 24
Finished Jul 31 05:56:45 PM PDT 24
Peak memory 201068 kb
Host smart-fca83152-1905-47a5-9492-382d8a425c7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997002685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.3997002685
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3655150068
Short name T799
Test name
Test status
Simulation time 36204700 ps
CPU time 0.76 seconds
Started Jul 31 05:56:38 PM PDT 24
Finished Jul 31 05:56:39 PM PDT 24
Peak memory 201012 kb
Host smart-7708f7e5-91a0-4b8a-98d5-7ffc7d595c33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655150068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3655150068
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.534853099
Short name T513
Test name
Test status
Simulation time 1553709983 ps
CPU time 5.84 seconds
Started Jul 31 05:56:52 PM PDT 24
Finished Jul 31 05:56:58 PM PDT 24
Peak memory 201240 kb
Host smart-408c2ec8-a9ec-40c7-9846-d9fe306f39da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534853099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.534853099
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2843095382
Short name T125
Test name
Test status
Simulation time 16493565 ps
CPU time 0.82 seconds
Started Jul 31 05:56:26 PM PDT 24
Finished Jul 31 05:56:27 PM PDT 24
Peak memory 201056 kb
Host smart-00d2ed54-4891-4e2b-a21c-3c8e1a94c6ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843095382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2843095382
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.3309602746
Short name T520
Test name
Test status
Simulation time 3803767582 ps
CPU time 17.11 seconds
Started Jul 31 05:56:57 PM PDT 24
Finished Jul 31 05:57:14 PM PDT 24
Peak memory 201432 kb
Host smart-da6a9bc2-63f1-4ad3-81e3-47a96c635b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309602746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.3309602746
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.786853094
Short name T345
Test name
Test status
Simulation time 100464934 ps
CPU time 1.18 seconds
Started Jul 31 05:56:40 PM PDT 24
Finished Jul 31 05:56:41 PM PDT 24
Peak memory 201144 kb
Host smart-976eb184-90c3-4587-aeea-f86f3926e8a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786853094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.786853094
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.663618521
Short name T374
Test name
Test status
Simulation time 21033537 ps
CPU time 0.78 seconds
Started Jul 31 05:57:16 PM PDT 24
Finished Jul 31 05:57:17 PM PDT 24
Peak memory 201124 kb
Host smart-38e73be4-2454-47b1-be00-474339a3fe6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663618521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.663618521
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2070689247
Short name T109
Test name
Test status
Simulation time 21769365 ps
CPU time 0.84 seconds
Started Jul 31 05:57:11 PM PDT 24
Finished Jul 31 05:57:12 PM PDT 24
Peak memory 201092 kb
Host smart-e829e60e-ef94-4958-9a53-36b8ee5d774f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070689247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2070689247
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2772726335
Short name T307
Test name
Test status
Simulation time 46366146 ps
CPU time 0.78 seconds
Started Jul 31 05:57:06 PM PDT 24
Finished Jul 31 05:57:07 PM PDT 24
Peak memory 200304 kb
Host smart-b465d77b-790d-4c42-be0a-5cc974c3949c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772726335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2772726335
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3595396601
Short name T780
Test name
Test status
Simulation time 18354611 ps
CPU time 0.79 seconds
Started Jul 31 05:57:08 PM PDT 24
Finished Jul 31 05:57:09 PM PDT 24
Peak memory 201104 kb
Host smart-d3bd7aeb-579f-4518-a446-6a63275589ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595396601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3595396601
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3631196624
Short name T538
Test name
Test status
Simulation time 27574435 ps
CPU time 0.93 seconds
Started Jul 31 05:57:00 PM PDT 24
Finished Jul 31 05:57:01 PM PDT 24
Peak memory 201100 kb
Host smart-afff8a58-02d2-444a-8913-d081ed2756c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631196624 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3631196624
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.316309473
Short name T808
Test name
Test status
Simulation time 2204655939 ps
CPU time 8.23 seconds
Started Jul 31 05:57:02 PM PDT 24
Finished Jul 31 05:57:10 PM PDT 24
Peak memory 201360 kb
Host smart-5491167b-cd0b-4859-8a93-f17cff17293a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316309473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.316309473
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.4073938792
Short name T361
Test name
Test status
Simulation time 1667284265 ps
CPU time 7.24 seconds
Started Jul 31 05:57:00 PM PDT 24
Finished Jul 31 05:57:07 PM PDT 24
Peak memory 201204 kb
Host smart-8939aa30-47f9-4e30-b17e-d06ea31b08ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073938792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.4073938792
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.2700150418
Short name T49
Test name
Test status
Simulation time 41043994 ps
CPU time 0.87 seconds
Started Jul 31 05:57:03 PM PDT 24
Finished Jul 31 05:57:04 PM PDT 24
Peak memory 201052 kb
Host smart-0e0ce91f-f0a8-4be2-bab5-703351827168
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700150418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.2700150418
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.821923978
Short name T667
Test name
Test status
Simulation time 16228189 ps
CPU time 0.78 seconds
Started Jul 31 05:57:11 PM PDT 24
Finished Jul 31 05:57:12 PM PDT 24
Peak memory 201036 kb
Host smart-1f22cb62-86b7-4caa-b413-2c1d0cf670c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821923978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_clk_byp_req_intersig_mubi.821923978
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.214201433
Short name T373
Test name
Test status
Simulation time 27062437 ps
CPU time 0.77 seconds
Started Jul 31 05:57:07 PM PDT 24
Finished Jul 31 05:57:08 PM PDT 24
Peak memory 201052 kb
Host smart-7e3404da-110d-4766-93b4-76e4ca132a17
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214201433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.clkmgr_lc_ctrl_intersig_mubi.214201433
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.2915989473
Short name T55
Test name
Test status
Simulation time 50339738 ps
CPU time 0.86 seconds
Started Jul 31 05:56:58 PM PDT 24
Finished Jul 31 05:56:59 PM PDT 24
Peak memory 201048 kb
Host smart-200c6e57-add2-4c54-a10e-d00d5acbc036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915989473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.2915989473
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.846469804
Short name T264
Test name
Test status
Simulation time 464267874 ps
CPU time 2.21 seconds
Started Jul 31 05:57:11 PM PDT 24
Finished Jul 31 05:57:13 PM PDT 24
Peak memory 201072 kb
Host smart-88d5594c-29ec-4907-b2d0-a60281c74c93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846469804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.846469804
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1280105861
Short name T190
Test name
Test status
Simulation time 133639137 ps
CPU time 1.11 seconds
Started Jul 31 05:56:57 PM PDT 24
Finished Jul 31 05:56:59 PM PDT 24
Peak memory 201064 kb
Host smart-c15473f4-06e1-4864-adb0-f8fb048dff03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280105861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1280105861
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2098286442
Short name T82
Test name
Test status
Simulation time 1924319870 ps
CPU time 7.16 seconds
Started Jul 31 05:57:16 PM PDT 24
Finished Jul 31 05:57:24 PM PDT 24
Peak memory 201368 kb
Host smart-1c0df753-2748-4129-a709-6bb79126aeba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098286442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2098286442
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.2439762461
Short name T677
Test name
Test status
Simulation time 34560307 ps
CPU time 0.84 seconds
Started Jul 31 05:57:01 PM PDT 24
Finished Jul 31 05:57:02 PM PDT 24
Peak memory 201044 kb
Host smart-f4460b94-9ba5-4a8b-8e52-8f0349fdcb6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439762461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.2439762461
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3402802825
Short name T336
Test name
Test status
Simulation time 12212354 ps
CPU time 0.75 seconds
Started Jul 31 05:57:47 PM PDT 24
Finished Jul 31 05:57:48 PM PDT 24
Peak memory 201072 kb
Host smart-17ba9cd8-6b7b-4e8a-a1a0-d9cd5b0552bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402802825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3402802825
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.291837422
Short name T114
Test name
Test status
Simulation time 17281333 ps
CPU time 0.8 seconds
Started Jul 31 05:57:39 PM PDT 24
Finished Jul 31 05:57:40 PM PDT 24
Peak memory 201112 kb
Host smart-f06f9791-2c67-438c-8689-a04e8584222c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291837422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.291837422
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.217701833
Short name T418
Test name
Test status
Simulation time 15353495 ps
CPU time 0.72 seconds
Started Jul 31 05:57:39 PM PDT 24
Finished Jul 31 05:57:39 PM PDT 24
Peak memory 201000 kb
Host smart-be15658c-bec1-41b8-91e5-be4288b4a003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217701833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.217701833
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1622941177
Short name T198
Test name
Test status
Simulation time 34407072 ps
CPU time 0.91 seconds
Started Jul 31 05:57:39 PM PDT 24
Finished Jul 31 05:57:40 PM PDT 24
Peak memory 201068 kb
Host smart-9576e8bb-b165-421b-adc9-18390c192a2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622941177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1622941177
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3493866119
Short name T354
Test name
Test status
Simulation time 24810534 ps
CPU time 0.86 seconds
Started Jul 31 05:57:23 PM PDT 24
Finished Jul 31 05:57:24 PM PDT 24
Peak memory 200968 kb
Host smart-d5abf19c-43af-4903-b9f8-f662e4fcb2bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493866119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3493866119
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3756813461
Short name T322
Test name
Test status
Simulation time 252359660 ps
CPU time 1.65 seconds
Started Jul 31 05:57:21 PM PDT 24
Finished Jul 31 05:57:23 PM PDT 24
Peak memory 201132 kb
Host smart-ca0b59c1-bfc6-4fd4-a880-2e92d011e03c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756813461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3756813461
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.1571336062
Short name T400
Test name
Test status
Simulation time 498784477 ps
CPU time 2.98 seconds
Started Jul 31 05:57:37 PM PDT 24
Finished Jul 31 05:57:40 PM PDT 24
Peak memory 201216 kb
Host smart-199396fb-574e-4818-9214-62a087b64c9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571336062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.1571336062
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.505984926
Short name T325
Test name
Test status
Simulation time 89788798 ps
CPU time 0.99 seconds
Started Jul 31 05:57:35 PM PDT 24
Finished Jul 31 05:57:36 PM PDT 24
Peak memory 201100 kb
Host smart-81d91591-86cd-4c9b-96f4-af5e911a0a35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505984926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.clkmgr_idle_intersig_mubi.505984926
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1068823527
Short name T529
Test name
Test status
Simulation time 35838447 ps
CPU time 0.86 seconds
Started Jul 31 05:57:37 PM PDT 24
Finished Jul 31 05:57:38 PM PDT 24
Peak memory 201088 kb
Host smart-a83bd70a-2025-4b0b-9c8d-7572415d2fc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068823527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1068823527
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.4133500584
Short name T510
Test name
Test status
Simulation time 13727210 ps
CPU time 0.76 seconds
Started Jul 31 05:57:36 PM PDT 24
Finished Jul 31 05:57:37 PM PDT 24
Peak memory 201028 kb
Host smart-37970d42-3647-42ce-8f44-fc628a328f01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133500584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.4133500584
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.579816244
Short name T421
Test name
Test status
Simulation time 148716285 ps
CPU time 1.13 seconds
Started Jul 31 05:57:37 PM PDT 24
Finished Jul 31 05:57:38 PM PDT 24
Peak memory 201108 kb
Host smart-37195e44-2f4b-4b83-ae9b-14e838854206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579816244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.579816244
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.8130370
Short name T38
Test name
Test status
Simulation time 1472268468 ps
CPU time 5.38 seconds
Started Jul 31 05:57:39 PM PDT 24
Finished Jul 31 05:57:45 PM PDT 24
Peak memory 201244 kb
Host smart-061c8e55-7e4c-44e1-b1ea-5ed8baa73952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8130370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.8130370
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.2526313002
Short name T150
Test name
Test status
Simulation time 40511005 ps
CPU time 0.97 seconds
Started Jul 31 05:57:23 PM PDT 24
Finished Jul 31 05:57:24 PM PDT 24
Peak memory 201012 kb
Host smart-ab01a27a-8bc6-4715-9b7c-71714422abdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526313002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2526313002
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.884196817
Short name T13
Test name
Test status
Simulation time 12543282069 ps
CPU time 91.49 seconds
Started Jul 31 05:57:38 PM PDT 24
Finished Jul 31 05:59:09 PM PDT 24
Peak memory 201428 kb
Host smart-233de253-6494-4bf7-bb5c-e1213ff083bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884196817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.884196817
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.4114847468
Short name T187
Test name
Test status
Simulation time 71417774369 ps
CPU time 510.63 seconds
Started Jul 31 05:57:40 PM PDT 24
Finished Jul 31 06:06:11 PM PDT 24
Peak memory 209760 kb
Host smart-53b84155-3e3a-4bfd-b733-bee8fae7429c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4114847468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.4114847468
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.2354455982
Short name T505
Test name
Test status
Simulation time 52700781 ps
CPU time 0.94 seconds
Started Jul 31 05:57:37 PM PDT 24
Finished Jul 31 05:57:38 PM PDT 24
Peak memory 201024 kb
Host smart-f24b19b5-c569-48a1-bae0-c3aab50362a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354455982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2354455982
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.2767449126
Short name T420
Test name
Test status
Simulation time 25501985 ps
CPU time 0.77 seconds
Started Jul 31 05:58:06 PM PDT 24
Finished Jul 31 05:58:07 PM PDT 24
Peak memory 201044 kb
Host smart-29e6b4ee-c823-44d9-b589-ecdc778c7eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767449126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.2767449126
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3089514013
Short name T108
Test name
Test status
Simulation time 21826546 ps
CPU time 0.91 seconds
Started Jul 31 05:57:58 PM PDT 24
Finished Jul 31 05:57:59 PM PDT 24
Peak memory 201064 kb
Host smart-85c6d532-ef50-4ecb-98fa-c123e0447130
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089514013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3089514013
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.3572328098
Short name T647
Test name
Test status
Simulation time 18008882 ps
CPU time 0.71 seconds
Started Jul 31 05:57:49 PM PDT 24
Finished Jul 31 05:57:50 PM PDT 24
Peak memory 200284 kb
Host smart-589f8514-d2c5-456e-a831-a55225b2de9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572328098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.3572328098
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.3714764873
Short name T406
Test name
Test status
Simulation time 26485273 ps
CPU time 0.98 seconds
Started Jul 31 05:58:01 PM PDT 24
Finished Jul 31 05:58:02 PM PDT 24
Peak memory 201044 kb
Host smart-1caa307c-de7c-4cf7-bea6-2c4a3ea5a30d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714764873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.3714764873
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.1604091495
Short name T555
Test name
Test status
Simulation time 86074944 ps
CPU time 1.1 seconds
Started Jul 31 05:57:42 PM PDT 24
Finished Jul 31 05:57:44 PM PDT 24
Peak memory 201104 kb
Host smart-c6d80ee1-69fd-4b64-a0f4-edb78f860014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604091495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1604091495
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.3094141912
Short name T813
Test name
Test status
Simulation time 2001516733 ps
CPU time 16.21 seconds
Started Jul 31 05:57:42 PM PDT 24
Finished Jul 31 05:57:58 PM PDT 24
Peak memory 201292 kb
Host smart-32280a99-a1c5-4534-9489-9d4f16a6244f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094141912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.3094141912
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.2705306209
Short name T795
Test name
Test status
Simulation time 266610846 ps
CPU time 1.68 seconds
Started Jul 31 05:57:45 PM PDT 24
Finished Jul 31 05:57:46 PM PDT 24
Peak memory 201148 kb
Host smart-6521ce93-9ca2-4310-8142-5ea7bf62d266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705306209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.2705306209
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2858588958
Short name T536
Test name
Test status
Simulation time 90041035 ps
CPU time 1.2 seconds
Started Jul 31 05:57:50 PM PDT 24
Finished Jul 31 05:57:51 PM PDT 24
Peak memory 200980 kb
Host smart-57c70904-ac05-45bc-9c8a-b93c7d509a04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858588958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.2858588958
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1712423777
Short name T267
Test name
Test status
Simulation time 24496390 ps
CPU time 0.91 seconds
Started Jul 31 05:57:53 PM PDT 24
Finished Jul 31 05:57:54 PM PDT 24
Peak memory 201064 kb
Host smart-8b9a26ae-4ff7-40ab-9a95-7d31b17ee59b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712423777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1712423777
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3366857687
Short name T300
Test name
Test status
Simulation time 27383500 ps
CPU time 0.92 seconds
Started Jul 31 05:57:49 PM PDT 24
Finished Jul 31 05:57:50 PM PDT 24
Peak memory 201040 kb
Host smart-30f79521-bd6b-4cc8-a131-f6fac391d765
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366857687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3366857687
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.2242313511
Short name T578
Test name
Test status
Simulation time 11633839 ps
CPU time 0.71 seconds
Started Jul 31 05:57:46 PM PDT 24
Finished Jul 31 05:57:47 PM PDT 24
Peak memory 201108 kb
Host smart-ec9bf610-0415-486b-9eb2-7d473d530864
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242313511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2242313511
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.4169373042
Short name T218
Test name
Test status
Simulation time 1457610589 ps
CPU time 5.09 seconds
Started Jul 31 05:58:00 PM PDT 24
Finished Jul 31 05:58:06 PM PDT 24
Peak memory 201252 kb
Host smart-7e2b16a2-5374-47f4-b2b6-b731827dcd8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169373042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.4169373042
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.78973643
Short name T575
Test name
Test status
Simulation time 89959263 ps
CPU time 1.07 seconds
Started Jul 31 05:57:46 PM PDT 24
Finished Jul 31 05:57:47 PM PDT 24
Peak memory 200976 kb
Host smart-29e8bcac-98fb-4a2a-9619-4cf6d644b4cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78973643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.78973643
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.3439067181
Short name T395
Test name
Test status
Simulation time 73405921 ps
CPU time 1.06 seconds
Started Jul 31 05:58:02 PM PDT 24
Finished Jul 31 05:58:03 PM PDT 24
Peak memory 201084 kb
Host smart-200bea35-68b6-4bbc-be10-1cdb63db8af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439067181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.3439067181
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.2927204769
Short name T498
Test name
Test status
Simulation time 182791981 ps
CPU time 1.51 seconds
Started Jul 31 05:57:48 PM PDT 24
Finished Jul 31 05:57:50 PM PDT 24
Peak memory 201112 kb
Host smart-a6967253-acbd-49d2-a3f2-f414282f798b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927204769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2927204769
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.4044269906
Short name T52
Test name
Test status
Simulation time 16439303 ps
CPU time 0.73 seconds
Started Jul 31 05:58:21 PM PDT 24
Finished Jul 31 05:58:21 PM PDT 24
Peak memory 201108 kb
Host smart-7f38e15b-2b76-4b83-97c4-2d0d2b85d0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044269906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.4044269906
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.4214659376
Short name T751
Test name
Test status
Simulation time 35901755 ps
CPU time 0.8 seconds
Started Jul 31 05:58:22 PM PDT 24
Finished Jul 31 05:58:23 PM PDT 24
Peak memory 201100 kb
Host smart-2372b1af-54b4-495f-b105-8d148662b735
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214659376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.4214659376
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.2566968368
Short name T663
Test name
Test status
Simulation time 21630591 ps
CPU time 0.71 seconds
Started Jul 31 05:58:15 PM PDT 24
Finished Jul 31 05:58:17 PM PDT 24
Peak memory 200240 kb
Host smart-58f7cd24-c2e9-4d2f-9657-fa99c043e7b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566968368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.2566968368
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.799691908
Short name T275
Test name
Test status
Simulation time 15013912 ps
CPU time 0.77 seconds
Started Jul 31 05:58:24 PM PDT 24
Finished Jul 31 05:58:25 PM PDT 24
Peak memory 201116 kb
Host smart-aab9cdc4-e3ad-4404-96b1-23d12838048f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799691908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_div_intersig_mubi.799691908
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.487647548
Short name T397
Test name
Test status
Simulation time 68952142 ps
CPU time 0.97 seconds
Started Jul 31 05:58:13 PM PDT 24
Finished Jul 31 05:58:14 PM PDT 24
Peak memory 201096 kb
Host smart-5abf4a09-85fe-4493-a374-58b3449a1fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487647548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.487647548
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.2157032173
Short name T305
Test name
Test status
Simulation time 1881387474 ps
CPU time 10.88 seconds
Started Jul 31 05:58:11 PM PDT 24
Finished Jul 31 05:58:22 PM PDT 24
Peak memory 201320 kb
Host smart-a79afa90-6f85-4d77-8f83-e65346652bd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157032173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2157032173
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.333636434
Short name T278
Test name
Test status
Simulation time 1815958298 ps
CPU time 13.28 seconds
Started Jul 31 05:58:10 PM PDT 24
Finished Jul 31 05:58:24 PM PDT 24
Peak memory 201208 kb
Host smart-bb0ba267-8b82-41c2-b6cd-074724f94c0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333636434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.333636434
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.408642988
Short name T585
Test name
Test status
Simulation time 33604761 ps
CPU time 1.02 seconds
Started Jul 31 05:58:28 PM PDT 24
Finished Jul 31 05:58:29 PM PDT 24
Peak memory 201116 kb
Host smart-ba15d4f2-302b-4cf1-944e-735e8571ee39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408642988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9
.clkmgr_idle_intersig_mubi.408642988
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.425366787
Short name T645
Test name
Test status
Simulation time 112514553 ps
CPU time 1.06 seconds
Started Jul 31 05:58:19 PM PDT 24
Finished Jul 31 05:58:20 PM PDT 24
Peak memory 201108 kb
Host smart-8934bd89-50ec-4408-b518-aee46805092a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425366787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_clk_byp_req_intersig_mubi.425366787
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3084477344
Short name T782
Test name
Test status
Simulation time 122188167 ps
CPU time 1.12 seconds
Started Jul 31 05:58:15 PM PDT 24
Finished Jul 31 05:58:17 PM PDT 24
Peak memory 201092 kb
Host smart-7aede671-f8df-4bad-8773-a73c2bd85970
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084477344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.3084477344
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.337753554
Short name T349
Test name
Test status
Simulation time 19377740 ps
CPU time 0.82 seconds
Started Jul 31 05:58:10 PM PDT 24
Finished Jul 31 05:58:11 PM PDT 24
Peak memory 200988 kb
Host smart-c3632b74-d7ca-4eda-a3a4-7158384b190b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337753554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.337753554
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.2532838349
Short name T702
Test name
Test status
Simulation time 189110651 ps
CPU time 1.4 seconds
Started Jul 31 05:58:20 PM PDT 24
Finished Jul 31 05:58:21 PM PDT 24
Peak memory 201088 kb
Host smart-956b2367-e226-4e25-baa9-81c446ba5421
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532838349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2532838349
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.147272828
Short name T771
Test name
Test status
Simulation time 24765772 ps
CPU time 0.84 seconds
Started Jul 31 05:58:04 PM PDT 24
Finished Jul 31 05:58:05 PM PDT 24
Peak memory 201144 kb
Host smart-1a928b3c-c46b-42d2-9e7e-4ecc55ed830d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147272828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.147272828
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1086540483
Short name T774
Test name
Test status
Simulation time 14004763113 ps
CPU time 72.74 seconds
Started Jul 31 05:58:18 PM PDT 24
Finished Jul 31 05:59:31 PM PDT 24
Peak memory 201480 kb
Host smart-18b043be-223c-446b-bc2c-efeb20ba46a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086540483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1086540483
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.4270657289
Short name T245
Test name
Test status
Simulation time 23874512 ps
CPU time 0.75 seconds
Started Jul 31 05:58:16 PM PDT 24
Finished Jul 31 05:58:17 PM PDT 24
Peak memory 201024 kb
Host smart-fe7535d1-bd5a-4de9-8094-da674657df04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270657289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.4270657289
Directory /workspace/9.clkmgr_trans/latest
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