Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183756752

1

T5

4336

T6

2772

T1

99446

auto[1]

269112

1

T6

566

T19

608

T20

848

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183731384

1

T5

4336

T6

2874

T1

99446

auto[1]

294480

1

T6

464

T19

416

T20

664

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183656660

1

T5

4336

T6

2760

T1

99446

auto[1]

369204

1

T6

578

T19

616

T20

778

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

174110180

1

T5

4336

T6

658

T1

99446

auto[1]

9915684

1

T6

2680

T19

2186

T20

2966

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104247180

1

T5

876

T6

2822

T1

97228

auto[1]

79778684

1

T5

3460

T6

516

T1

2218

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

97237658

1

T5

876

T6

298

T1

97228

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

76597728

1

T5

3460

T6

128

T1

2218

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20764

1

T6

16

T19

60

T20

112

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5500

1

T3

102

T10

236

T11

18

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6585442

1

T6

2000

T19

1762

T20

2124

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3100978

1

T6

156

T19

84

T20

232

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

29298

1

T6

26

T19

78

T94

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8336

1

T6

38

T19

14

T20

82

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

33412

1

T20

50

T111

8

T3

98

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

684

1

T3

50

T10

8

T11

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7950

1

T111

70

T10

136

T140

54

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2372

1

T3

116

T11

60

T15

88

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8170

1

T6

36

T94

2

T111

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2216

1

T20

22

T3

18

T29

32

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12790

1

T6

62

T94

66

T111

142

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3362

1

T20

62

T3

84

T29

154

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

49676

1

T6

10

T19

32

T20

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2718

1

T3

22

T10

32

T71

26

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21542

1

T6

54

T19

168

T20

74

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5846

1

T3

96

T10

114

T11

104

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

17194

1

T6

36

T94

12

T112

32

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5022

1

T6

22

T20

8

T111

78

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33666

1

T6

48

T94

36

T112

158

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10016

1

T6

42

T20

158

T3

90

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76744

1

T6

18

T19

22

T20

18

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4788

1

T6

16

T3

130

T10

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34560

1

T6

64

T19

146

T20

234

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8238

1

T6

54

T3

90

T10

178

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27706

1

T6

42

T19

92

T20

152

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6616

1

T6

10

T19

14

T111

48

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

50608

1

T6

112

T19

66

T20

126

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14264

1

T6

50

T19

76

T111

78