Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 983
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T801 /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1857392535 Aug 01 06:50:04 PM PDT 24 Aug 01 06:50:05 PM PDT 24 51566138 ps
T802 /workspace/coverage/default/12.clkmgr_smoke.474055543 Aug 01 06:49:33 PM PDT 24 Aug 01 06:49:34 PM PDT 24 78258426 ps
T803 /workspace/coverage/default/31.clkmgr_div_intersig_mubi.130062025 Aug 01 06:50:15 PM PDT 24 Aug 01 06:50:16 PM PDT 24 16724613 ps
T804 /workspace/coverage/default/22.clkmgr_clk_status.1577562656 Aug 01 06:49:53 PM PDT 24 Aug 01 06:49:54 PM PDT 24 42895521 ps
T805 /workspace/coverage/default/15.clkmgr_trans.507307863 Aug 01 06:49:29 PM PDT 24 Aug 01 06:49:30 PM PDT 24 28877981 ps
T806 /workspace/coverage/default/28.clkmgr_smoke.1249640616 Aug 01 06:50:11 PM PDT 24 Aug 01 06:50:12 PM PDT 24 24026449 ps
T807 /workspace/coverage/default/38.clkmgr_smoke.3679878482 Aug 01 06:50:33 PM PDT 24 Aug 01 06:50:34 PM PDT 24 30449129 ps
T808 /workspace/coverage/default/48.clkmgr_stress_all.2890302144 Aug 01 06:50:58 PM PDT 24 Aug 01 06:51:25 PM PDT 24 6274304133 ps
T809 /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1691135973 Aug 01 06:49:10 PM PDT 24 Aug 01 06:49:11 PM PDT 24 49615253 ps
T810 /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3443636466 Aug 01 06:49:38 PM PDT 24 Aug 01 06:49:39 PM PDT 24 18640098 ps
T811 /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.4225526988 Aug 01 06:49:29 PM PDT 24 Aug 01 06:49:30 PM PDT 24 62629635 ps
T812 /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1548694544 Aug 01 06:50:14 PM PDT 24 Aug 01 06:50:15 PM PDT 24 22305020 ps
T813 /workspace/coverage/default/27.clkmgr_alert_test.2548443466 Aug 01 06:50:06 PM PDT 24 Aug 01 06:50:08 PM PDT 24 49360287 ps
T814 /workspace/coverage/default/16.clkmgr_frequency_timeout.1807778693 Aug 01 06:49:35 PM PDT 24 Aug 01 06:49:41 PM PDT 24 1539271190 ps
T815 /workspace/coverage/default/3.clkmgr_peri.1766057563 Aug 01 06:49:13 PM PDT 24 Aug 01 06:49:14 PM PDT 24 45959527 ps
T816 /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1608694017 Aug 01 06:49:53 PM PDT 24 Aug 01 06:49:54 PM PDT 24 72520011 ps
T817 /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2391266442 Aug 01 06:49:06 PM PDT 24 Aug 01 06:49:07 PM PDT 24 73190274 ps
T818 /workspace/coverage/default/4.clkmgr_frequency.1781997512 Aug 01 06:49:19 PM PDT 24 Aug 01 06:49:24 PM PDT 24 804870394 ps
T819 /workspace/coverage/default/19.clkmgr_smoke.2314274805 Aug 01 06:49:41 PM PDT 24 Aug 01 06:49:42 PM PDT 24 41229145 ps
T820 /workspace/coverage/default/8.clkmgr_alert_test.487996912 Aug 01 06:49:21 PM PDT 24 Aug 01 06:49:23 PM PDT 24 38017222 ps
T821 /workspace/coverage/default/30.clkmgr_stress_all.4147076548 Aug 01 06:50:14 PM PDT 24 Aug 01 06:50:56 PM PDT 24 5471834780 ps
T822 /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.2931473692 Aug 01 06:50:43 PM PDT 24 Aug 01 07:01:07 PM PDT 24 57191337696 ps
T823 /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2070157493 Aug 01 06:49:16 PM PDT 24 Aug 01 06:49:17 PM PDT 24 26602552 ps
T824 /workspace/coverage/default/49.clkmgr_trans.76030567 Aug 01 06:50:58 PM PDT 24 Aug 01 06:51:00 PM PDT 24 48764955 ps
T825 /workspace/coverage/default/29.clkmgr_frequency_timeout.3035022489 Aug 01 06:50:04 PM PDT 24 Aug 01 06:50:12 PM PDT 24 2289008459 ps
T826 /workspace/coverage/default/11.clkmgr_smoke.1278221497 Aug 01 06:49:22 PM PDT 24 Aug 01 06:49:23 PM PDT 24 41789926 ps
T827 /workspace/coverage/default/21.clkmgr_regwen.4030779185 Aug 01 06:49:53 PM PDT 24 Aug 01 06:49:58 PM PDT 24 807177729 ps
T828 /workspace/coverage/default/19.clkmgr_frequency_timeout.1611677866 Aug 01 06:49:46 PM PDT 24 Aug 01 06:50:03 PM PDT 24 2296747562 ps
T77 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3305321898 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 66485145 ps
T54 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.878447617 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 57964077 ps
T78 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4156744523 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 115256690 ps
T150 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2083735876 Aug 01 06:58:44 PM PDT 24 Aug 01 06:58:46 PM PDT 24 60080184 ps
T101 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1602082779 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 20638113 ps
T55 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.822280678 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:46 PM PDT 24 609089009 ps
T79 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.838715123 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 50305665 ps
T95 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3268694960 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:35 PM PDT 24 444898388 ps
T829 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.960400261 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 24359548 ps
T56 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3278467686 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:48 PM PDT 24 86800706 ps
T830 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3451061779 Aug 01 06:59:01 PM PDT 24 Aug 01 06:59:01 PM PDT 24 37233951 ps
T831 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.885735719 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:52 PM PDT 24 30439180 ps
T832 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1218294400 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 35192107 ps
T80 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.4289911766 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:50 PM PDT 24 296312952 ps
T81 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.977674458 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 30485994 ps
T61 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2596742987 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 105001094 ps
T833 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4242548646 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 77613738 ps
T151 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3666863120 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 45494250 ps
T59 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2348467698 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:32 PM PDT 24 179296442 ps
T834 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4281984168 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 16649123 ps
T57 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.4097488826 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:43 PM PDT 24 199982190 ps
T835 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1538111352 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 18811924 ps
T836 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2535014063 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 61256946 ps
T82 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3117304636 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:44 PM PDT 24 51466405 ps
T96 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3923233066 Aug 01 06:58:48 PM PDT 24 Aug 01 06:58:49 PM PDT 24 86799580 ps
T83 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2095306900 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:42 PM PDT 24 22470288 ps
T84 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2999339265 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:31 PM PDT 24 18496883 ps
T62 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3702737621 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:18 PM PDT 24 69122031 ps
T837 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3923803802 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 64858416 ps
T838 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.978362292 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 34453877 ps
T130 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4211484325 Aug 01 06:58:11 PM PDT 24 Aug 01 06:58:13 PM PDT 24 81732480 ps
T97 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2533665527 Aug 01 06:58:29 PM PDT 24 Aug 01 06:58:35 PM PDT 24 1263419388 ps
T839 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3960528363 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:50 PM PDT 24 24123532 ps
T840 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.446921774 Aug 01 06:59:02 PM PDT 24 Aug 01 06:59:03 PM PDT 24 15382632 ps
T159 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3806575086 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:17 PM PDT 24 232618855 ps
T841 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1025099889 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:44 PM PDT 24 136540853 ps
T842 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2091545360 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:44 PM PDT 24 18615021 ps
T843 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.37330953 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 104985778 ps
T844 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.817887062 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 40243806 ps
T845 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3523815447 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 21937557 ps
T58 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2604083743 Aug 01 06:58:40 PM PDT 24 Aug 01 06:58:42 PM PDT 24 159995506 ps
T846 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1038014981 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:13 PM PDT 24 14681666 ps
T847 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.4033951320 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:45 PM PDT 24 115826053 ps
T848 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.323593094 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:52 PM PDT 24 34099204 ps
T849 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1664189409 Aug 01 06:59:02 PM PDT 24 Aug 01 06:59:03 PM PDT 24 19140381 ps
T850 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3730958086 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:16 PM PDT 24 104113984 ps
T851 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2766360696 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 14057365 ps
T852 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1725873915 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 32171636 ps
T853 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3083022286 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:43 PM PDT 24 138693459 ps
T854 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1914502363 Aug 01 06:57:55 PM PDT 24 Aug 01 06:57:58 PM PDT 24 60354420 ps
T855 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.907061423 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 37932605 ps
T856 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.104219300 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:32 PM PDT 24 21896591 ps
T857 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.44029224 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 31902972 ps
T858 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.4088038979 Aug 01 06:58:17 PM PDT 24 Aug 01 06:58:27 PM PDT 24 1496943928 ps
T102 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3695455594 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:51 PM PDT 24 760282410 ps
T859 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3190710199 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:36 PM PDT 24 286225669 ps
T860 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3262635238 Aug 01 06:58:45 PM PDT 24 Aug 01 06:58:47 PM PDT 24 25179148 ps
T861 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3595387 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 41657319 ps
T60 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1359470808 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:33 PM PDT 24 179599236 ps
T862 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.194924821 Aug 01 06:58:45 PM PDT 24 Aug 01 06:58:46 PM PDT 24 33759510 ps
T863 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3139360893 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 39282055 ps
T864 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2437261763 Aug 01 06:59:04 PM PDT 24 Aug 01 06:59:05 PM PDT 24 28167022 ps
T865 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1927459166 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:50 PM PDT 24 258955142 ps
T866 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.4271805587 Aug 01 06:58:32 PM PDT 24 Aug 01 06:58:33 PM PDT 24 16116125 ps
T115 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1442882847 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 111999126 ps
T867 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.373382870 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 36326653 ps
T116 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1962858416 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 97514413 ps
T868 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4082223663 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 54451692 ps
T869 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1459338656 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 37771201 ps
T122 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3018482188 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:34 PM PDT 24 288181278 ps
T870 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1049481181 Aug 01 06:59:04 PM PDT 24 Aug 01 06:59:05 PM PDT 24 19887706 ps
T871 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3390968436 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 24832279 ps
T872 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1092262376 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:52 PM PDT 24 101012152 ps
T117 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.325502661 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:59 PM PDT 24 91026065 ps
T107 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1186872240 Aug 01 06:58:34 PM PDT 24 Aug 01 06:58:36 PM PDT 24 92440369 ps
T873 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1382560949 Aug 01 06:58:59 PM PDT 24 Aug 01 06:59:01 PM PDT 24 150996004 ps
T874 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.856323640 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:45 PM PDT 24 56777054 ps
T875 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3349090437 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 28012706 ps
T876 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3922654227 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 60945376 ps
T877 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.978203827 Aug 01 06:58:00 PM PDT 24 Aug 01 06:58:01 PM PDT 24 16064892 ps
T118 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.961409188 Aug 01 06:58:32 PM PDT 24 Aug 01 06:58:34 PM PDT 24 253193917 ps
T878 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1353096878 Aug 01 06:58:59 PM PDT 24 Aug 01 06:59:00 PM PDT 24 11998585 ps
T879 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1089903314 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:32 PM PDT 24 228543643 ps
T880 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3952653927 Aug 01 06:59:04 PM PDT 24 Aug 01 06:59:05 PM PDT 24 18006404 ps
T881 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.351151674 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 49077505 ps
T882 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3470510455 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 40134512 ps
T883 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3538338431 Aug 01 06:58:29 PM PDT 24 Aug 01 06:58:30 PM PDT 24 17112193 ps
T884 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2069626211 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 21980457 ps
T885 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3454342972 Aug 01 06:58:48 PM PDT 24 Aug 01 06:58:48 PM PDT 24 29321509 ps
T129 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3908453363 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 116477624 ps
T886 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.888722460 Aug 01 06:58:29 PM PDT 24 Aug 01 06:58:32 PM PDT 24 49018477 ps
T887 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1694236075 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 97866301 ps
T888 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3453813694 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:15 PM PDT 24 80631911 ps
T889 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2233979350 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:50 PM PDT 24 19160785 ps
T890 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1338445261 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:45 PM PDT 24 41589404 ps
T891 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2043322652 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:17 PM PDT 24 16216633 ps
T892 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2311335549 Aug 01 06:57:57 PM PDT 24 Aug 01 06:58:02 PM PDT 24 672815498 ps
T893 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4062136239 Aug 01 06:58:17 PM PDT 24 Aug 01 06:58:21 PM PDT 24 452706369 ps
T894 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.156846885 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 12976955 ps
T99 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3654110596 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:48 PM PDT 24 186698373 ps
T895 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2632317592 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:19 PM PDT 24 261698232 ps
T896 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3313366659 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 29717652 ps
T897 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3962101634 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:37 PM PDT 24 826077202 ps
T160 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3362159745 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 244579396 ps
T898 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.326544660 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:47 PM PDT 24 46558031 ps
T123 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1357617477 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 330442393 ps
T899 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2283623695 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 20666349 ps
T900 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.86754596 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:31 PM PDT 24 34526550 ps
T901 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2097711202 Aug 01 06:59:00 PM PDT 24 Aug 01 06:59:01 PM PDT 24 35582482 ps
T119 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1168844062 Aug 01 06:58:40 PM PDT 24 Aug 01 06:58:42 PM PDT 24 89051988 ps
T902 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.4088465358 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 36082354 ps
T120 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.463588504 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:52 PM PDT 24 498412454 ps
T903 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2828459056 Aug 01 06:58:44 PM PDT 24 Aug 01 06:58:45 PM PDT 24 76153826 ps
T904 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2229908358 Aug 01 06:58:49 PM PDT 24 Aug 01 06:58:50 PM PDT 24 40356829 ps
T905 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2482492675 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:17 PM PDT 24 149333575 ps
T121 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1324065716 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:43 PM PDT 24 94341898 ps
T906 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2891154278 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 31297924 ps
T907 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.23967377 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 27611233 ps
T908 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2188972124 Aug 01 06:57:58 PM PDT 24 Aug 01 06:57:59 PM PDT 24 28681442 ps
T127 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3074721264 Aug 01 06:58:44 PM PDT 24 Aug 01 06:58:45 PM PDT 24 59754373 ps
T909 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3976764295 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 32540090 ps
T124 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.4235341357 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:16 PM PDT 24 114996637 ps
T910 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3165025385 Aug 01 06:58:49 PM PDT 24 Aug 01 06:58:50 PM PDT 24 39007514 ps
T911 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2627910647 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 19170495 ps
T912 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.599460004 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 68640759 ps
T913 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3274668057 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 78287344 ps
T125 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3074486974 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:55 PM PDT 24 741734095 ps
T914 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.381944557 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:47 PM PDT 24 531504506 ps
T915 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.669228682 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:42 PM PDT 24 144721142 ps
T128 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3687636581 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:34 PM PDT 24 188125447 ps
T916 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.449294405 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 19423454 ps
T917 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1642820546 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:32 PM PDT 24 53672474 ps
T161 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3794839113 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:33 PM PDT 24 243995725 ps
T918 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3833295329 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:32 PM PDT 24 27166143 ps
T919 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1904681768 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 12673304 ps
T920 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.787218003 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:52 PM PDT 24 24975070 ps
T921 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1963834495 Aug 01 06:57:55 PM PDT 24 Aug 01 06:57:56 PM PDT 24 25611810 ps
T922 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1695206560 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 124085669 ps
T923 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1255740454 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:33 PM PDT 24 304407361 ps
T924 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3332479901 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 24306635 ps
T925 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3587810450 Aug 01 06:58:12 PM PDT 24 Aug 01 06:58:16 PM PDT 24 784906481 ps
T926 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.962990111 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 53860613 ps
T927 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.28369164 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:44 PM PDT 24 33294276 ps
T928 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.882537976 Aug 01 06:58:59 PM PDT 24 Aug 01 06:59:00 PM PDT 24 12725026 ps
T929 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3540949145 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:47 PM PDT 24 144441199 ps
T930 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3895747840 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:48 PM PDT 24 248539411 ps
T931 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2974160325 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:36 PM PDT 24 480626705 ps
T103 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.194660845 Aug 01 06:58:41 PM PDT 24 Aug 01 06:58:43 PM PDT 24 106181460 ps
T932 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3266393 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 70556279 ps
T933 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2965869738 Aug 01 06:58:46 PM PDT 24 Aug 01 06:58:48 PM PDT 24 71449815 ps
T934 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1389224297 Aug 01 06:58:34 PM PDT 24 Aug 01 06:58:39 PM PDT 24 895444242 ps
T935 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.937434161 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:25 PM PDT 24 971345990 ps
T936 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1160112435 Aug 01 06:58:30 PM PDT 24 Aug 01 06:58:32 PM PDT 24 168883541 ps
T937 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2080224275 Aug 01 06:59:01 PM PDT 24 Aug 01 06:59:02 PM PDT 24 20691598 ps
T938 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4028249481 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 29968706 ps
T939 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1924577431 Aug 01 06:58:32 PM PDT 24 Aug 01 06:58:34 PM PDT 24 95079066 ps
T104 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2983366794 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:36 PM PDT 24 140808573 ps
T940 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.193211156 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:47 PM PDT 24 21869204 ps
T941 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.115773393 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:21 PM PDT 24 393588580 ps
T942 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.556545958 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:57 PM PDT 24 100120272 ps
T943 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.608880765 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 151395301 ps
T944 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.4041280351 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 37835823 ps
T945 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3694174052 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:53 PM PDT 24 125955599 ps
T946 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2266482266 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:47 PM PDT 24 22501890 ps
T947 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4251183093 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:16 PM PDT 24 59526824 ps
T948 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2493767547 Aug 01 06:58:48 PM PDT 24 Aug 01 06:58:49 PM PDT 24 15335308 ps
T126 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1894119989 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:44 PM PDT 24 50599594 ps
T949 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1724493356 Aug 01 06:57:57 PM PDT 24 Aug 01 06:57:58 PM PDT 24 58488800 ps
T950 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3913597254 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:45 PM PDT 24 169732459 ps
T951 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1458056915 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 52574440 ps
T952 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3601986893 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 15379561 ps
T953 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.528916713 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 32250947 ps
T954 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.823184913 Aug 01 06:58:32 PM PDT 24 Aug 01 06:58:35 PM PDT 24 241627499 ps
T955 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3500912652 Aug 01 06:58:29 PM PDT 24 Aug 01 06:58:31 PM PDT 24 85693059 ps
T956 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2700767002 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:18 PM PDT 24 138101800 ps
T957 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4089174490 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:52 PM PDT 24 24159951 ps
T105 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.995584027 Aug 01 06:58:00 PM PDT 24 Aug 01 06:58:03 PM PDT 24 247132134 ps
T958 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2529639100 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 40009203 ps
T959 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.557550987 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:18 PM PDT 24 919963478 ps
T960 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2204578744 Aug 01 06:57:56 PM PDT 24 Aug 01 06:57:58 PM PDT 24 158572516 ps
T961 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3060080932 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:49 PM PDT 24 61396509 ps
T962 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4004074352 Aug 01 06:58:34 PM PDT 24 Aug 01 06:58:36 PM PDT 24 431677165 ps
T963 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2971605327 Aug 01 06:58:43 PM PDT 24 Aug 01 06:58:45 PM PDT 24 13056191 ps
T964 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2738641182 Aug 01 06:58:32 PM PDT 24 Aug 01 06:58:35 PM PDT 24 377579120 ps
T965 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3235063742 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:14 PM PDT 24 36490953 ps
T966 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1245009309 Aug 01 06:58:14 PM PDT 24 Aug 01 06:58:15 PM PDT 24 61328532 ps
T100 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1861335783 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:35 PM PDT 24 433955977 ps
T967 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2154163428 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:34 PM PDT 24 74988456 ps
T106 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3089386318 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:16 PM PDT 24 341016610 ps
T968 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.4287011119 Aug 01 06:58:33 PM PDT 24 Aug 01 06:58:35 PM PDT 24 111089246 ps
T969 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2647488312 Aug 01 06:58:42 PM PDT 24 Aug 01 06:58:43 PM PDT 24 17093341 ps
T970 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4126640261 Aug 01 06:58:47 PM PDT 24 Aug 01 06:58:48 PM PDT 24 69138276 ps
T971 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2577634917 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:17 PM PDT 24 13315817 ps
T972 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2793283486 Aug 01 06:57:57 PM PDT 24 Aug 01 06:58:00 PM PDT 24 209978730 ps
T973 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2844808417 Aug 01 06:58:59 PM PDT 24 Aug 01 06:59:00 PM PDT 24 17542177 ps
T974 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3137514586 Aug 01 06:57:58 PM PDT 24 Aug 01 06:58:01 PM PDT 24 195180852 ps
T975 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3238460093 Aug 01 06:58:13 PM PDT 24 Aug 01 06:58:15 PM PDT 24 117049590 ps
T976 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3068772952 Aug 01 06:58:44 PM PDT 24 Aug 01 06:58:46 PM PDT 24 93904114 ps
T977 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2220497972 Aug 01 06:58:12 PM PDT 24 Aug 01 06:58:14 PM PDT 24 64850470 ps
T978 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.4132430935 Aug 01 06:58:34 PM PDT 24 Aug 01 06:58:36 PM PDT 24 91992135 ps
T979 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1620968322 Aug 01 06:58:15 PM PDT 24 Aug 01 06:58:16 PM PDT 24 35640918 ps
T980 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.96349731 Aug 01 06:58:34 PM PDT 24 Aug 01 06:58:35 PM PDT 24 41163849 ps
T981 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.40847029 Aug 01 06:58:31 PM PDT 24 Aug 01 06:58:33 PM PDT 24 228560638 ps
T982 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2122166339 Aug 01 06:58:50 PM PDT 24 Aug 01 06:58:51 PM PDT 24 42261470 ps
T983 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3687989325 Aug 01 06:58:16 PM PDT 24 Aug 01 06:58:17 PM PDT 24 83418227 ps

Test location /workspace/coverage/default/27.clkmgr_stress_all.698792595
Short name T1
Test name
Test status
Simulation time 2075250184 ps
CPU time 9.41 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:16 PM PDT 24
Peak memory 201344 kb
Host smart-33d1a1d2-2294-4356-b74f-a1e4e81f7723
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698792595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.698792595
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.3222793698
Short name T3
Test name
Test status
Simulation time 182419902109 ps
CPU time 1029.11 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 07:06:14 PM PDT 24
Peak memory 214068 kb
Host smart-87069bc6-7f6d-4eee-ae3e-efb0dc69c679
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3222793698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3222793698
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2285457878
Short name T73
Test name
Test status
Simulation time 936822148 ps
CPU time 3.87 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 201276 kb
Host smart-c68b8acb-f597-418d-8109-818bb575b106
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285457878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2285457878
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2604083743
Short name T58
Test name
Test status
Simulation time 159995506 ps
CPU time 1.87 seconds
Started Aug 01 06:58:40 PM PDT 24
Finished Aug 01 06:58:42 PM PDT 24
Peak memory 217160 kb
Host smart-06be9a30-107d-439e-8fce-268cdae0114c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604083743 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.2604083743
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.191949250
Short name T18
Test name
Test status
Simulation time 28415571 ps
CPU time 0.73 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 200312 kb
Host smart-6cdbc153-fae6-49ec-a854-ee48b85a9cb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191949250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.191949250
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.3963396466
Short name T41
Test name
Test status
Simulation time 586869296 ps
CPU time 4.03 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 221928 kb
Host smart-9a7255ad-6930-445a-b86c-6ddc64b575bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963396466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.3963396466
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.1963477876
Short name T21
Test name
Test status
Simulation time 90563818 ps
CPU time 1.17 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 200836 kb
Host smart-fd750d10-2be7-4228-b14b-7fb4dad70779
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963477876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.1963477876
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3268694960
Short name T95
Test name
Test status
Simulation time 444898388 ps
CPU time 3.27 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 200500 kb
Host smart-235edf3d-aa41-4d8b-813b-33a66ad9994a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268694960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.3268694960
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1218587718
Short name T23
Test name
Test status
Simulation time 22094214 ps
CPU time 0.85 seconds
Started Aug 01 06:50:38 PM PDT 24
Finished Aug 01 06:50:39 PM PDT 24
Peak memory 201016 kb
Host smart-9e2db3df-54d9-485e-b97d-adea8fc2c6cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218587718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1218587718
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.177132449
Short name T111
Test name
Test status
Simulation time 85869024 ps
CPU time 1.05 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201032 kb
Host smart-fb029637-f739-4eb4-bb90-ee08b761fc30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177132449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_div_intersig_mubi.177132449
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2857429709
Short name T197
Test name
Test status
Simulation time 9162014378 ps
CPU time 68.32 seconds
Started Aug 01 06:50:31 PM PDT 24
Finished Aug 01 06:51:40 PM PDT 24
Peak memory 201412 kb
Host smart-e7e6731f-9388-46ed-83b1-70e610d22f8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857429709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2857429709
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1359470808
Short name T60
Test name
Test status
Simulation time 179599236 ps
CPU time 2 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 216604 kb
Host smart-60b91b4d-b16b-4a14-a774-577b924f4a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359470808 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1359470808
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1687011232
Short name T147
Test name
Test status
Simulation time 173943400505 ps
CPU time 1122.21 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 07:08:20 PM PDT 24
Peak memory 217868 kb
Host smart-11ad8b2f-c80f-4e91-b24c-4a7aee48be87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1687011232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1687011232
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.330163681
Short name T71
Test name
Test status
Simulation time 87833900 ps
CPU time 0.97 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 201080 kb
Host smart-cdec3eff-911f-4355-90d9-3dea16153c6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330163681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_clk_byp_req_intersig_mubi.330163681
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.77916575
Short name T7
Test name
Test status
Simulation time 1075159649 ps
CPU time 6.44 seconds
Started Aug 01 06:49:37 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201200 kb
Host smart-786c6b39-374b-41c2-a719-e89304e22f8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77916575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.77916575
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3687636581
Short name T128
Test name
Test status
Simulation time 188125447 ps
CPU time 2.09 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 217160 kb
Host smart-ad19d77c-de09-4f1e-a69d-bb09a8208c7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687636581 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.3687636581
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2220497972
Short name T977
Test name
Test status
Simulation time 64850470 ps
CPU time 1.6 seconds
Started Aug 01 06:58:12 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200552 kb
Host smart-6cc3d652-2d2a-4854-9d8a-5d369c304da8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220497972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.2220497972
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2999339265
Short name T84
Test name
Test status
Simulation time 18496883 ps
CPU time 0.74 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:31 PM PDT 24
Peak memory 200372 kb
Host smart-45914fbd-5695-47b9-a95a-b7cf1dc7be4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999339265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.2999339265
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.311301814
Short name T89
Test name
Test status
Simulation time 45600552 ps
CPU time 0.99 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 201060 kb
Host smart-65a64b1b-a009-4094-bfcf-7c7f15aefebd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311301814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.311301814
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3137514586
Short name T974
Test name
Test status
Simulation time 195180852 ps
CPU time 2.24 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:58:01 PM PDT 24
Peak memory 217116 kb
Host smart-b9f9ff48-848b-47c7-8176-102e8d406150
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137514586 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.3137514586
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2204578744
Short name T960
Test name
Test status
Simulation time 158572516 ps
CPU time 2.04 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 200804 kb
Host smart-080225ad-407b-4e16-a54e-32bb58b5e557
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204578744 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2204578744
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.2983366794
Short name T104
Test name
Test status
Simulation time 140808573 ps
CPU time 2.8 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200612 kb
Host smart-17f5b656-0283-4814-93fd-af8a4789453b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983366794 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.2983366794
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.1323992707
Short name T652
Test name
Test status
Simulation time 159030413559 ps
CPU time 963.56 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 07:05:37 PM PDT 24
Peak memory 217836 kb
Host smart-1aff9a4a-79ee-4ffa-90e3-e5e0202d19d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1323992707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.1323992707
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.995584027
Short name T105
Test name
Test status
Simulation time 247132134 ps
CPU time 3.25 seconds
Started Aug 01 06:58:00 PM PDT 24
Finished Aug 01 06:58:03 PM PDT 24
Peak memory 200540 kb
Host smart-da9038b9-49af-448a-bf3f-1ef050b3fe62
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995584027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_tl_intg_err.995584027
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.1005243814
Short name T299
Test name
Test status
Simulation time 2167057759 ps
CPU time 6.92 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:27 PM PDT 24
Peak memory 201288 kb
Host smart-2179b30e-5376-4495-8efc-358ea051f588
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005243814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1005243814
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2069626211
Short name T884
Test name
Test status
Simulation time 21980457 ps
CPU time 1.14 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 200368 kb
Host smart-fa6d3630-e976-43d3-af89-d8ee9e18bfef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069626211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.2069626211
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.2311335549
Short name T892
Test name
Test status
Simulation time 672815498 ps
CPU time 4.97 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:58:02 PM PDT 24
Peak memory 200500 kb
Host smart-f27d2939-e6ad-4368-ad2e-0a5497205227
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311335549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.2311335549
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3332479901
Short name T924
Test name
Test status
Simulation time 24306635 ps
CPU time 0.84 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 200388 kb
Host smart-30e8d9d4-70a1-41cf-9bd7-2667d7dc71f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332479901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.3332479901
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2188972124
Short name T908
Test name
Test status
Simulation time 28681442 ps
CPU time 1.32 seconds
Started Aug 01 06:57:58 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 200648 kb
Host smart-286c63aa-36f9-4238-9d2b-7ddeaa28e73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188972124 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2188972124
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.978203827
Short name T877
Test name
Test status
Simulation time 16064892 ps
CPU time 0.79 seconds
Started Aug 01 06:58:00 PM PDT 24
Finished Aug 01 06:58:01 PM PDT 24
Peak memory 200236 kb
Host smart-dcab18a8-9dde-4abe-bca0-2b5754c64544
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978203827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.c
lkmgr_csr_rw.978203827
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1963834495
Short name T921
Test name
Test status
Simulation time 25611810 ps
CPU time 0.67 seconds
Started Aug 01 06:57:55 PM PDT 24
Finished Aug 01 06:57:56 PM PDT 24
Peak memory 198968 kb
Host smart-022649bf-517e-4b1c-8a88-baa813699ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963834495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1963834495
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1724493356
Short name T949
Test name
Test status
Simulation time 58488800 ps
CPU time 1 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 200392 kb
Host smart-5bf37b98-76de-40c7-8695-170d381b822e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724493356 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1724493356
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.556545958
Short name T942
Test name
Test status
Simulation time 100120272 ps
CPU time 1.49 seconds
Started Aug 01 06:57:56 PM PDT 24
Finished Aug 01 06:57:57 PM PDT 24
Peak memory 217112 kb
Host smart-e06e95c4-b28c-403f-b6d5-901ff551d1c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556545958 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.556545958
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.1914502363
Short name T854
Test name
Test status
Simulation time 60354420 ps
CPU time 1.92 seconds
Started Aug 01 06:57:55 PM PDT 24
Finished Aug 01 06:57:58 PM PDT 24
Peak memory 200580 kb
Host smart-3b069d4d-9c2f-445f-886e-f80b2349d8f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914502363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.1914502363
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.817887062
Short name T844
Test name
Test status
Simulation time 40243806 ps
CPU time 1.24 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200340 kb
Host smart-50929ba6-b55a-46fc-9739-b4f94a2af67a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817887062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.817887062
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.4088038979
Short name T858
Test name
Test status
Simulation time 1496943928 ps
CPU time 10.59 seconds
Started Aug 01 06:58:17 PM PDT 24
Finished Aug 01 06:58:27 PM PDT 24
Peak memory 200548 kb
Host smart-a97e1e6e-0117-4f41-9bc7-8be89580443d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088038979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.4088038979
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1602082779
Short name T101
Test name
Test status
Simulation time 20638113 ps
CPU time 0.83 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200368 kb
Host smart-8e6523af-8229-4186-957d-77ed42791208
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602082779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.1602082779
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3349090437
Short name T875
Test name
Test status
Simulation time 28012706 ps
CPU time 0.92 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200464 kb
Host smart-d76ec7af-0495-45e8-afcc-f755b5c3788e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349090437 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3349090437
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.3235063742
Short name T965
Test name
Test status
Simulation time 36490953 ps
CPU time 0.79 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200308 kb
Host smart-8ca0c1a8-5d9b-44dc-957e-d629733cd9f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235063742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.3235063742
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2577634917
Short name T971
Test name
Test status
Simulation time 13315817 ps
CPU time 0.69 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 198936 kb
Host smart-a5c89fc3-f475-4aa6-9116-1f113b51cbe2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577634917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2577634917
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.351151674
Short name T881
Test name
Test status
Simulation time 49077505 ps
CPU time 1.37 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200552 kb
Host smart-cb26f8d5-b08c-41fb-acf7-4411b0a888d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351151674 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.clkmgr_same_csr_outstanding.351151674
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.325502661
Short name T117
Test name
Test status
Simulation time 91026065 ps
CPU time 2.46 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:57:59 PM PDT 24
Peak memory 209036 kb
Host smart-fa25a956-e6a9-42d6-81dd-e82b8b6dd3b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325502661 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.325502661
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2793283486
Short name T972
Test name
Test status
Simulation time 209978730 ps
CPU time 2.07 seconds
Started Aug 01 06:57:57 PM PDT 24
Finished Aug 01 06:58:00 PM PDT 24
Peak memory 200544 kb
Host smart-2c4e4017-cc0a-424d-b83e-2ff63a1c4d67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793283486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.2793283486
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3806575086
Short name T159
Test name
Test status
Simulation time 232618855 ps
CPU time 2.75 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200564 kb
Host smart-869b2713-5214-4525-b705-824fe12dd6a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806575086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3806575086
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.96349731
Short name T980
Test name
Test status
Simulation time 41163849 ps
CPU time 1 seconds
Started Aug 01 06:58:34 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 200440 kb
Host smart-6015d092-841e-4656-a471-99b13af7b0ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96349731 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.96349731
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1904681768
Short name T919
Test name
Test status
Simulation time 12673304 ps
CPU time 0.64 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 198976 kb
Host smart-049350e8-45b3-471c-a4e4-3c83a1f8e074
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904681768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1904681768
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.104219300
Short name T856
Test name
Test status
Simulation time 21896591 ps
CPU time 0.95 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200376 kb
Host smart-9b19761d-186f-4b62-8c16-f0bc24c35d62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104219300 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 10.clkmgr_same_csr_outstanding.104219300
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.3018482188
Short name T122
Test name
Test status
Simulation time 288181278 ps
CPU time 2.77 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 217184 kb
Host smart-460b1726-c96b-460d-9a37-7a9184a70a0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018482188 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.3018482188
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1924577431
Short name T939
Test name
Test status
Simulation time 95079066 ps
CPU time 1.84 seconds
Started Aug 01 06:58:32 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 200556 kb
Host smart-084e8215-f885-4bfd-b707-ae7b628416d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924577431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.1924577431
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2533665527
Short name T97
Test name
Test status
Simulation time 1263419388 ps
CPU time 5.22 seconds
Started Aug 01 06:58:29 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 200524 kb
Host smart-75057e7e-25ae-4916-90b0-79dc346862da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533665527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.2533665527
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.1089903314
Short name T879
Test name
Test status
Simulation time 228543643 ps
CPU time 1.62 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200472 kb
Host smart-a3a19f61-6d3b-46ed-8aea-04a0260c0a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089903314 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.1089903314
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.907061423
Short name T855
Test name
Test status
Simulation time 37932605 ps
CPU time 0.77 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200276 kb
Host smart-a6d610e1-61ec-4cb5-9c4b-5974fa0eb77b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907061423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
clkmgr_csr_rw.907061423
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.2766360696
Short name T851
Test name
Test status
Simulation time 14057365 ps
CPU time 0.63 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 198968 kb
Host smart-4a5f33b5-25a0-424b-89b5-95541a1d91de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766360696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.2766360696
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2529639100
Short name T958
Test name
Test status
Simulation time 40009203 ps
CPU time 1.02 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 200368 kb
Host smart-ae6812f7-4246-41c3-9dc9-beed4e6b0a6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529639100 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.2529639100
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2596742987
Short name T61
Test name
Test status
Simulation time 105001094 ps
CPU time 1.73 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 217132 kb
Host smart-7e482c70-ce05-4514-a0c1-722274940eda
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596742987 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2596742987
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.4287011119
Short name T968
Test name
Test status
Simulation time 111089246 ps
CPU time 1.97 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 200800 kb
Host smart-d76f1f5b-d679-42a7-a7e8-6c19f7d3ee6f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287011119 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.4287011119
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3962101634
Short name T897
Test name
Test status
Simulation time 826077202 ps
CPU time 3.86 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:37 PM PDT 24
Peak memory 200484 kb
Host smart-26292b0f-6994-4072-9ab3-b0d865478d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962101634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.3962101634
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1186872240
Short name T107
Test name
Test status
Simulation time 92440369 ps
CPU time 2.37 seconds
Started Aug 01 06:58:34 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200560 kb
Host smart-fe284a24-d72c-4d44-9c41-9440479efbc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186872240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.1186872240
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3595387
Short name T861
Test name
Test status
Simulation time 41657319 ps
CPU time 1.2 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200416 kb
Host smart-778a3716-bf8d-4a75-b78e-4de01b3232e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595387 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3595387
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.194924821
Short name T862
Test name
Test status
Simulation time 33759510 ps
CPU time 0.86 seconds
Started Aug 01 06:58:45 PM PDT 24
Finished Aug 01 06:58:46 PM PDT 24
Peak memory 200384 kb
Host smart-931bc612-91f5-44ae-8e56-a04dd6404fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194924821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
clkmgr_csr_rw.194924821
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3274668057
Short name T913
Test name
Test status
Simulation time 78287344 ps
CPU time 0.8 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 199048 kb
Host smart-6f249fed-d230-4467-a3bf-f1b6eddd5bf5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274668057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3274668057
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.28369164
Short name T927
Test name
Test status
Simulation time 33294276 ps
CPU time 1.09 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200396 kb
Host smart-d8d6f4ff-94e2-4b54-829e-ba6a330957cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28369164 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 12.clkmgr_same_csr_outstanding.28369164
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.4132430935
Short name T978
Test name
Test status
Simulation time 91992135 ps
CPU time 2.02 seconds
Started Aug 01 06:58:34 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200932 kb
Host smart-054d2e76-4e30-433b-aefc-8538971de587
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132430935 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.4132430935
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3190710199
Short name T859
Test name
Test status
Simulation time 286225669 ps
CPU time 3.91 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200516 kb
Host smart-832366d1-88b1-4d95-855d-a1422fecd4bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190710199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3190710199
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1389224297
Short name T934
Test name
Test status
Simulation time 895444242 ps
CPU time 4.64 seconds
Started Aug 01 06:58:34 PM PDT 24
Finished Aug 01 06:58:39 PM PDT 24
Peak memory 200544 kb
Host smart-d87c16e7-485b-4eff-bfd3-a7a1d8e0f518
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389224297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1389224297
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.3666863120
Short name T151
Test name
Test status
Simulation time 45494250 ps
CPU time 1.07 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200504 kb
Host smart-2262d51d-a021-475c-807b-71f4fbf33bd6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666863120 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.3666863120
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.3305321898
Short name T77
Test name
Test status
Simulation time 66485145 ps
CPU time 0.87 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200368 kb
Host smart-ee9dae12-8eb7-4439-a8a7-b410b41af283
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305321898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.3305321898
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.2647488312
Short name T969
Test name
Test status
Simulation time 17093341 ps
CPU time 0.7 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 199024 kb
Host smart-5e567456-1394-42d5-94d8-51b1e21c8941
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647488312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.2647488312
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.4126640261
Short name T970
Test name
Test status
Simulation time 69138276 ps
CPU time 1.27 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 200548 kb
Host smart-46e3747f-e488-43f5-acc7-a4444e7be7dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126640261 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.4126640261
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.1695206560
Short name T922
Test name
Test status
Simulation time 124085669 ps
CPU time 1.41 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 200644 kb
Host smart-a7626414-84ce-4ba8-b621-997358ad2010
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695206560 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.1695206560
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1168844062
Short name T119
Test name
Test status
Simulation time 89051988 ps
CPU time 1.87 seconds
Started Aug 01 06:58:40 PM PDT 24
Finished Aug 01 06:58:42 PM PDT 24
Peak memory 217152 kb
Host smart-2eb76e91-3ea2-4445-850b-ebf42bb33d6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168844062 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1168844062
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.1338445261
Short name T890
Test name
Test status
Simulation time 41589404 ps
CPU time 2.61 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 200552 kb
Host smart-b28a7074-3299-420d-9d10-778db630fa7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338445261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.1338445261
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.1025099889
Short name T841
Test name
Test status
Simulation time 136540853 ps
CPU time 2.59 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200564 kb
Host smart-bf0d1434-c96f-45c3-9d1a-f3ee7cc269c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025099889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.1025099889
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.960400261
Short name T829
Test name
Test status
Simulation time 24359548 ps
CPU time 1.24 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200468 kb
Host smart-0e4811d7-ee9d-4901-90f3-1434f0fe541d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960400261 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.960400261
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.2095306900
Short name T83
Test name
Test status
Simulation time 22470288 ps
CPU time 0.84 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:42 PM PDT 24
Peak memory 200368 kb
Host smart-a7e1dbbd-c6c5-4b50-ada8-f8a44fd61f7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095306900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.2095306900
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3923803802
Short name T837
Test name
Test status
Simulation time 64858416 ps
CPU time 0.76 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 198520 kb
Host smart-6271663b-e1be-4bce-a157-14f72edc67a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923803802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.3923803802
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.4289911766
Short name T80
Test name
Test status
Simulation time 296312952 ps
CPU time 1.98 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 200588 kb
Host smart-44d02181-afdb-44dc-ac70-d04b9a7ceb30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289911766 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.4289911766
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1894119989
Short name T126
Test name
Test status
Simulation time 50599594 ps
CPU time 1.18 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200184 kb
Host smart-b5437cda-a4d4-44de-a31c-27dc5de5c190
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894119989 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.1894119989
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.1324065716
Short name T121
Test name
Test status
Simulation time 94341898 ps
CPU time 1.88 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 208992 kb
Host smart-19663c11-11c6-444f-841e-e7bf5bbb8d49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324065716 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.1324065716
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.3895747840
Short name T930
Test name
Test status
Simulation time 248539411 ps
CPU time 2.24 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 200388 kb
Host smart-54d62380-a75a-4fa1-9e15-2122eb16a258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895747840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.3895747840
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3913597254
Short name T950
Test name
Test status
Simulation time 169732459 ps
CPU time 2.44 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 200616 kb
Host smart-ec8b4cab-b980-4090-a4ba-15360e34a41e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913597254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3913597254
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.962990111
Short name T926
Test name
Test status
Simulation time 53860613 ps
CPU time 1.15 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200676 kb
Host smart-7688e37d-30b7-4dad-9fdd-4a3a129ee4ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962990111 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.962990111
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.4281984168
Short name T834
Test name
Test status
Simulation time 16649123 ps
CPU time 0.8 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200344 kb
Host smart-18a9cd38-c614-4170-a424-77497cdb42dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281984168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.4281984168
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1725873915
Short name T852
Test name
Test status
Simulation time 32171636 ps
CPU time 0.7 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 198976 kb
Host smart-bf8c2e97-615b-41cc-95cc-4fb71efb54a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725873915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.1725873915
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.856323640
Short name T874
Test name
Test status
Simulation time 56777054 ps
CPU time 1.46 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 200484 kb
Host smart-ad1d95a0-f7fe-4951-875f-c4fefd5cab52
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856323640 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 15.clkmgr_same_csr_outstanding.856323640
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3074486974
Short name T125
Test name
Test status
Simulation time 741734095 ps
CPU time 4.33 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:55 PM PDT 24
Peak memory 209056 kb
Host smart-aec972ee-628d-4059-b421-a7eaaa2d0774
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074486974 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3074486974
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.3694174052
Short name T945
Test name
Test status
Simulation time 125955599 ps
CPU time 2.26 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:53 PM PDT 24
Peak memory 200572 kb
Host smart-f3c49220-5138-4fa3-b65f-a48753ef6b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694174052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.3694174052
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.3923233066
Short name T96
Test name
Test status
Simulation time 86799580 ps
CPU time 1.58 seconds
Started Aug 01 06:58:48 PM PDT 24
Finished Aug 01 06:58:49 PM PDT 24
Peak memory 200572 kb
Host smart-b5c938fd-fd1e-4179-871d-1919e0276b56
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923233066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.3923233066
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3262635238
Short name T860
Test name
Test status
Simulation time 25179148 ps
CPU time 1.28 seconds
Started Aug 01 06:58:45 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 200540 kb
Host smart-365a539b-bbb0-4b98-9f10-2240aa8e2c27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262635238 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3262635238
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.1458056915
Short name T951
Test name
Test status
Simulation time 52574440 ps
CPU time 0.92 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200244 kb
Host smart-a1b56b76-cf3f-4961-b3b8-3bd815eb8460
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458056915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.1458056915
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2971605327
Short name T963
Test name
Test status
Simulation time 13056191 ps
CPU time 0.67 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 198968 kb
Host smart-bee33dd8-8a88-43e2-a7dd-b7f7cfecc1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971605327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2971605327
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.3470510455
Short name T882
Test name
Test status
Simulation time 40134512 ps
CPU time 1.1 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 200380 kb
Host smart-0ec3681c-8c21-43dd-ba5d-1c10c63ce67b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470510455 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.3470510455
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.669228682
Short name T915
Test name
Test status
Simulation time 144721142 ps
CPU time 1.44 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:42 PM PDT 24
Peak memory 200660 kb
Host smart-e243901d-8d65-437b-9319-e1419a006a7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669228682 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.clkmgr_shadow_reg_errors.669228682
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.381944557
Short name T914
Test name
Test status
Simulation time 531504506 ps
CPU time 3.94 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 200892 kb
Host smart-4453f766-ee16-4204-8bdc-e06f62c8eb64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381944557 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.381944557
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3068772952
Short name T976
Test name
Test status
Simulation time 93904114 ps
CPU time 1.41 seconds
Started Aug 01 06:58:44 PM PDT 24
Finished Aug 01 06:58:46 PM PDT 24
Peak memory 200404 kb
Host smart-bd100d0d-1e13-4987-8c95-564b17b3226c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068772952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.3068772952
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3695455594
Short name T102
Test name
Test status
Simulation time 760282410 ps
CPU time 4.11 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 200624 kb
Host smart-927706c5-2ff4-4ffc-ab23-013ce399b0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695455594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.3695455594
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.787218003
Short name T920
Test name
Test status
Simulation time 24975070 ps
CPU time 0.97 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 200452 kb
Host smart-d651f445-b9db-4440-90a6-058f31128988
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787218003 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.787218003
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3523815447
Short name T845
Test name
Test status
Simulation time 21937557 ps
CPU time 0.79 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200340 kb
Host smart-04357a96-2f35-4d54-afc1-dcce99ab91be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523815447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.3523815447
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2493767547
Short name T948
Test name
Test status
Simulation time 15335308 ps
CPU time 0.68 seconds
Started Aug 01 06:58:48 PM PDT 24
Finished Aug 01 06:58:49 PM PDT 24
Peak memory 198972 kb
Host smart-92d02026-0405-4ca6-913f-92251acfcfd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493767547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2493767547
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3083022286
Short name T853
Test name
Test status
Simulation time 138693459 ps
CPU time 1.67 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200540 kb
Host smart-c83f4774-299e-4b1b-a69c-edf20e0f6ec0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083022286 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.3083022286
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3074721264
Short name T127
Test name
Test status
Simulation time 59754373 ps
CPU time 1.18 seconds
Started Aug 01 06:58:44 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 200640 kb
Host smart-fc4aeb33-3ea8-4207-a481-cb47a2887c11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074721264 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3074721264
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.463588504
Short name T120
Test name
Test status
Simulation time 498412454 ps
CPU time 3.79 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 209204 kb
Host smart-9acd8b39-fe2f-48ee-b4f5-8c6ac77fdd01
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463588504 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.463588504
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2083735876
Short name T150
Test name
Test status
Simulation time 60080184 ps
CPU time 1.75 seconds
Started Aug 01 06:58:44 PM PDT 24
Finished Aug 01 06:58:46 PM PDT 24
Peak memory 200576 kb
Host smart-94b0ba5d-bad0-412c-b1ab-451879f2c54e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083735876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2083735876
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.194660845
Short name T103
Test name
Test status
Simulation time 106181460 ps
CPU time 1.68 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200512 kb
Host smart-1e813357-4fc8-48bd-ade2-df0f8cdf31d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194660845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.194660845
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1092262376
Short name T872
Test name
Test status
Simulation time 101012152 ps
CPU time 1.07 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 200384 kb
Host smart-94154a4e-6f66-4db2-bc95-bd15b5e30419
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092262376 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1092262376
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3117304636
Short name T82
Test name
Test status
Simulation time 51466405 ps
CPU time 0.81 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 200344 kb
Host smart-290996df-db94-407e-9833-940a5c9ce3d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117304636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.3117304636
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2266482266
Short name T946
Test name
Test status
Simulation time 22501890 ps
CPU time 0.66 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 199052 kb
Host smart-b700407f-d396-4aaa-9956-69732f40d0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266482266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.2266482266
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.326544660
Short name T898
Test name
Test status
Simulation time 46558031 ps
CPU time 1.02 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 200240 kb
Host smart-aad0746e-188c-498a-9fda-17e7652ae625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326544660 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 18.clkmgr_same_csr_outstanding.326544660
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3278467686
Short name T56
Test name
Test status
Simulation time 86800706 ps
CPU time 1.49 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 200856 kb
Host smart-63cb81e6-eb04-47d2-a9ec-b9e6d321721e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278467686 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.3278467686
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3060080932
Short name T961
Test name
Test status
Simulation time 61396509 ps
CPU time 1.63 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:49 PM PDT 24
Peak memory 200948 kb
Host smart-d4392967-0f42-4211-b18a-b126a37ff294
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060080932 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3060080932
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.4033951320
Short name T847
Test name
Test status
Simulation time 115826053 ps
CPU time 1.93 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 200448 kb
Host smart-ebf8ad79-afe9-4c80-a8a2-f11cf8800f8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033951320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.4033951320
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2965869738
Short name T933
Test name
Test status
Simulation time 71449815 ps
CPU time 1.75 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 200564 kb
Host smart-947ddcec-a12f-4f1e-9dc3-db24311cc14c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965869738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.2965869738
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.2122166339
Short name T982
Test name
Test status
Simulation time 42261470 ps
CPU time 0.93 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 200452 kb
Host smart-7ed8aebb-7a04-492a-8b7d-8ffc39f6de25
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122166339 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.2122166339
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.2627910647
Short name T911
Test name
Test status
Simulation time 19170495 ps
CPU time 0.77 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200340 kb
Host smart-e6b5ba98-fad5-4052-b805-b1340b0a2c9c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627910647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.clkmgr_csr_rw.2627910647
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2828459056
Short name T903
Test name
Test status
Simulation time 76153826 ps
CPU time 0.77 seconds
Started Aug 01 06:58:44 PM PDT 24
Finished Aug 01 06:58:45 PM PDT 24
Peak memory 199016 kb
Host smart-894351c9-b8c1-4189-92b3-70cdb687b2f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828459056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2828459056
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.3540949145
Short name T929
Test name
Test status
Simulation time 144441199 ps
CPU time 1.19 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 200392 kb
Host smart-8b7321c1-d36c-4239-a7db-62479dd0efb5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540949145 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.3540949145
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.4097488826
Short name T57
Test name
Test status
Simulation time 199982190 ps
CPU time 1.82 seconds
Started Aug 01 06:58:41 PM PDT 24
Finished Aug 01 06:58:43 PM PDT 24
Peak memory 200756 kb
Host smart-df25281a-e42f-4a11-a43d-b4ad537279f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097488826 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.4097488826
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.822280678
Short name T55
Test name
Test status
Simulation time 609089009 ps
CPU time 3.92 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:46 PM PDT 24
Peak memory 209036 kb
Host smart-13e742e8-a4b6-48c1-a935-0f33c581e44b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822280678 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.822280678
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1927459166
Short name T865
Test name
Test status
Simulation time 258955142 ps
CPU time 2.6 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 200488 kb
Host smart-0e0095ff-1ede-44bc-b677-e8fcc480c1d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927459166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1927459166
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3654110596
Short name T99
Test name
Test status
Simulation time 186698373 ps
CPU time 1.89 seconds
Started Aug 01 06:58:46 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 200596 kb
Host smart-af356555-3ea3-4cb6-94c0-58e054a712a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654110596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.3654110596
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.4088465358
Short name T902
Test name
Test status
Simulation time 36082354 ps
CPU time 1.12 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200308 kb
Host smart-baac276a-efa2-4af1-8ad2-56d46cd43541
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088465358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.4088465358
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.115773393
Short name T941
Test name
Test status
Simulation time 393588580 ps
CPU time 6.25 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:21 PM PDT 24
Peak memory 200484 kb
Host smart-056cce7f-91a4-4da6-a1bf-bd80f07c111b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115773393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_bit_bash.115773393
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1245009309
Short name T966
Test name
Test status
Simulation time 61328532 ps
CPU time 0.92 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200372 kb
Host smart-31418f0d-4e7e-484a-824d-3cbf182d1e6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245009309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.1245009309
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.2891154278
Short name T906
Test name
Test status
Simulation time 31297924 ps
CPU time 1.1 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200424 kb
Host smart-d629079b-4d1b-4f54-8647-7fa0895d4969
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891154278 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.2891154278
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.37330953
Short name T843
Test name
Test status
Simulation time 104985778 ps
CPU time 0.94 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200304 kb
Host smart-ed0aee16-3d52-4262-a72f-fe891aa7aad0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.cl
kmgr_csr_rw.37330953
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.1038014981
Short name T846
Test name
Test status
Simulation time 14681666 ps
CPU time 0.67 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:13 PM PDT 24
Peak memory 198972 kb
Host smart-0f6cd3e8-9b47-44ff-b6c9-14f7ca13c2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038014981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.1038014981
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.977674458
Short name T81
Test name
Test status
Simulation time 30485994 ps
CPU time 1.01 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200416 kb
Host smart-8a0d4b95-2116-4c02-86a6-1fce551b16d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977674458 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.clkmgr_same_csr_outstanding.977674458
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.3908453363
Short name T129
Test name
Test status
Simulation time 116477624 ps
CPU time 1.9 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200852 kb
Host smart-9f061137-e19c-49dd-ab63-efd1429d5eb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908453363 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.3908453363
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1442882847
Short name T115
Test name
Test status
Simulation time 111999126 ps
CPU time 2.59 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 209004 kb
Host smart-2a336588-7d58-4ccc-80ab-9d2a95e86bf0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442882847 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1442882847
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.2700767002
Short name T956
Test name
Test status
Simulation time 138101800 ps
CPU time 2.57 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:18 PM PDT 24
Peak memory 200284 kb
Host smart-5c7b8db3-8267-48bb-9846-406abc4e856d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700767002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.2700767002
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3089386318
Short name T106
Test name
Test status
Simulation time 341016610 ps
CPU time 2.81 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200584 kb
Host smart-f512db6a-1484-4eae-a95a-e25be1011bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089386318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3089386318
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3454342972
Short name T885
Test name
Test status
Simulation time 29321509 ps
CPU time 0.68 seconds
Started Aug 01 06:58:48 PM PDT 24
Finished Aug 01 06:58:48 PM PDT 24
Peak memory 198972 kb
Host smart-43848ead-07c7-4eec-bf05-fc27608bc4a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454342972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.3454342972
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.4082223663
Short name T868
Test name
Test status
Simulation time 54451692 ps
CPU time 0.75 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198736 kb
Host smart-372cf844-ea19-437b-a1f9-277720375acb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082223663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.4082223663
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.608880765
Short name T943
Test name
Test status
Simulation time 151395301 ps
CPU time 1.07 seconds
Started Aug 01 06:58:43 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 198952 kb
Host smart-a8c05f0c-b8c3-4b7a-b373-9b1f22226838
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608880765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.608880765
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.2091545360
Short name T842
Test name
Test status
Simulation time 18615021 ps
CPU time 0.69 seconds
Started Aug 01 06:58:42 PM PDT 24
Finished Aug 01 06:58:44 PM PDT 24
Peak memory 199056 kb
Host smart-77b5ed5e-2397-487c-8d5a-58db2ac1dc6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091545360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.2091545360
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.193211156
Short name T940
Test name
Test status
Simulation time 21869204 ps
CPU time 0.66 seconds
Started Aug 01 06:58:47 PM PDT 24
Finished Aug 01 06:58:47 PM PDT 24
Peak memory 198944 kb
Host smart-c16a3e0e-f7f0-469b-b1ca-bd2b2ee6ae1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193211156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.193211156
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.156846885
Short name T894
Test name
Test status
Simulation time 12976955 ps
CPU time 0.69 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198972 kb
Host smart-5c098963-6eb6-4342-a3a4-57cc3288b219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156846885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.156846885
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3960528363
Short name T839
Test name
Test status
Simulation time 24123532 ps
CPU time 0.67 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 198952 kb
Host smart-7dc907c3-23fd-4847-9600-8d40ad245f15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960528363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3960528363
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.449294405
Short name T916
Test name
Test status
Simulation time 19423454 ps
CPU time 0.67 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198748 kb
Host smart-648e0a5c-1d1c-41d7-bf5c-8eb7653c1466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449294405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clk
mgr_intr_test.449294405
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.44029224
Short name T857
Test name
Test status
Simulation time 31902972 ps
CPU time 0.69 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198948 kb
Host smart-985a59a1-c828-40f3-b345-f8ff8f1db6a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44029224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkm
gr_intr_test.44029224
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2233979350
Short name T889
Test name
Test status
Simulation time 19160785 ps
CPU time 0.68 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 198696 kb
Host smart-761c2a55-e1d2-464b-8e72-1927e8fcdace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233979350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.2233979350
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1218294400
Short name T832
Test name
Test status
Simulation time 35192107 ps
CPU time 1.19 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200376 kb
Host smart-5b724cea-67f1-4c37-b7cf-f2c6977ddd8f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218294400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.1218294400
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.937434161
Short name T935
Test name
Test status
Simulation time 971345990 ps
CPU time 8.85 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:25 PM PDT 24
Peak memory 200368 kb
Host smart-e5432a19-e3e2-46ae-965e-f4dd5a0bede6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937434161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.937434161
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1694236075
Short name T887
Test name
Test status
Simulation time 97866301 ps
CPU time 0.96 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200280 kb
Host smart-ef2455d3-a058-4c85-8b03-6a9b63d63100
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694236075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1694236075
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3390968436
Short name T871
Test name
Test status
Simulation time 24832279 ps
CPU time 0.91 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200444 kb
Host smart-2290790f-1744-4092-bead-797c753b3238
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390968436 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3390968436
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.23967377
Short name T907
Test name
Test status
Simulation time 27611233 ps
CPU time 0.8 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200228 kb
Host smart-eab77d3a-20fc-4e8b-b319-a5069e6b9698
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23967377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.cl
kmgr_csr_rw.23967377
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3601986893
Short name T952
Test name
Test status
Simulation time 15379561 ps
CPU time 0.66 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 198968 kb
Host smart-963788dc-1aaf-4e22-9421-f66efcb2c8c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601986893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.3601986893
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.838715123
Short name T79
Test name
Test status
Simulation time 50305665 ps
CPU time 1.02 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200368 kb
Host smart-b5917280-71ac-4610-8dfe-f2699bb5a184
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838715123 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.clkmgr_same_csr_outstanding.838715123
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.4235341357
Short name T124
Test name
Test status
Simulation time 114996637 ps
CPU time 1.97 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 217164 kb
Host smart-7c107afc-b0e7-4094-a313-031f33a5c862
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235341357 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.4235341357
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4211484325
Short name T130
Test name
Test status
Simulation time 81732480 ps
CPU time 1.7 seconds
Started Aug 01 06:58:11 PM PDT 24
Finished Aug 01 06:58:13 PM PDT 24
Peak memory 209008 kb
Host smart-4a1f090b-6622-4fad-8236-67be06248c1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211484325 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4211484325
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.3453813694
Short name T888
Test name
Test status
Simulation time 80631911 ps
CPU time 2.07 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200508 kb
Host smart-2559893b-fabc-4e86-9f75-e9bc90a6ab04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453813694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.3453813694
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3362159745
Short name T160
Test name
Test status
Simulation time 244579396 ps
CPU time 1.95 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200580 kb
Host smart-8005089f-2e91-4b83-bbb4-972ea2cc5ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362159745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.3362159745
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1459338656
Short name T869
Test name
Test status
Simulation time 37771201 ps
CPU time 0.74 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198748 kb
Host smart-109d7c1f-3cca-46b4-8b8d-503abe363aec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459338656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.1459338656
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.4089174490
Short name T957
Test name
Test status
Simulation time 24159951 ps
CPU time 0.71 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 198976 kb
Host smart-a0ce1620-4cf8-41b5-a266-5e6b7b8050d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089174490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.4089174490
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3165025385
Short name T910
Test name
Test status
Simulation time 39007514 ps
CPU time 0.71 seconds
Started Aug 01 06:58:49 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 198968 kb
Host smart-84b6e3cd-d86d-467b-b583-f5197893dca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165025385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.3165025385
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2229908358
Short name T904
Test name
Test status
Simulation time 40356829 ps
CPU time 0.74 seconds
Started Aug 01 06:58:49 PM PDT 24
Finished Aug 01 06:58:50 PM PDT 24
Peak memory 199024 kb
Host smart-95c8237c-83f3-450d-908c-17ba94677d0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229908358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.2229908358
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2535014063
Short name T836
Test name
Test status
Simulation time 61256946 ps
CPU time 0.76 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 199040 kb
Host smart-b524d3ca-cd95-4eb9-8304-13c8711fcc45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535014063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.2535014063
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.323593094
Short name T848
Test name
Test status
Simulation time 34099204 ps
CPU time 0.74 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 198960 kb
Host smart-4a512cbc-5d3b-4e2e-88c0-92225ddeb945
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323593094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk
mgr_intr_test.323593094
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4028249481
Short name T938
Test name
Test status
Simulation time 29968706 ps
CPU time 0.68 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:51 PM PDT 24
Peak memory 198968 kb
Host smart-58f48f56-48fe-4990-9376-4ee46812c627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028249481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.4028249481
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.885735719
Short name T831
Test name
Test status
Simulation time 30439180 ps
CPU time 0.7 seconds
Started Aug 01 06:58:50 PM PDT 24
Finished Aug 01 06:58:52 PM PDT 24
Peak memory 198972 kb
Host smart-25344830-6c73-4b25-81f4-6bda5fde8d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885735719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clk
mgr_intr_test.885735719
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.3451061779
Short name T830
Test name
Test status
Simulation time 37233951 ps
CPU time 0.71 seconds
Started Aug 01 06:59:01 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 198948 kb
Host smart-baaa153a-4c67-4693-94e4-49dc4de9cd6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451061779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.3451061779
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.446921774
Short name T840
Test name
Test status
Simulation time 15382632 ps
CPU time 0.67 seconds
Started Aug 01 06:59:02 PM PDT 24
Finished Aug 01 06:59:03 PM PDT 24
Peak memory 198952 kb
Host smart-f7eeb991-0f77-40bb-97b9-3b46ca0e26f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446921774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.446921774
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3238460093
Short name T975
Test name
Test status
Simulation time 117049590 ps
CPU time 1.34 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:15 PM PDT 24
Peak memory 200400 kb
Host smart-9192dcc4-be8c-4ab3-80a3-cc8cfc13c215
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238460093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3238460093
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2632317592
Short name T895
Test name
Test status
Simulation time 261698232 ps
CPU time 6.5 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:19 PM PDT 24
Peak memory 200484 kb
Host smart-686dd4c5-3858-478b-a802-d124b048bc2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632317592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.2632317592
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.2043322652
Short name T891
Test name
Test status
Simulation time 16216633 ps
CPU time 0.84 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200364 kb
Host smart-7752da94-8501-40fc-b640-26353ef1685e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043322652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.2043322652
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3922654227
Short name T876
Test name
Test status
Simulation time 60945376 ps
CPU time 0.99 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 200380 kb
Host smart-0a7cafd4-535f-4a76-80f9-0fe00abe3512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922654227 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3922654227
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.599460004
Short name T912
Test name
Test status
Simulation time 68640759 ps
CPU time 0.91 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200360 kb
Host smart-e0be88e2-c920-41f4-83f7-f08444aad4e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599460004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.c
lkmgr_csr_rw.599460004
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1538111352
Short name T835
Test name
Test status
Simulation time 18811924 ps
CPU time 0.67 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 199032 kb
Host smart-45b4336f-3d95-4f6e-a0ac-27c322cb5ed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538111352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1538111352
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3730958086
Short name T850
Test name
Test status
Simulation time 104113984 ps
CPU time 1.51 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200544 kb
Host smart-7786f8eb-e307-4c38-9297-2a8a3587de2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730958086 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3730958086
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.3687989325
Short name T983
Test name
Test status
Simulation time 83418227 ps
CPU time 1.29 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200596 kb
Host smart-0bd32eea-dc69-4cd5-ba9b-baf92277c22d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687989325 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.3687989325
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.1962858416
Short name T116
Test name
Test status
Simulation time 97514413 ps
CPU time 1.74 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 217172 kb
Host smart-5fcb9473-7ed5-4a6a-9236-ea89b07a01b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962858416 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.1962858416
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.557550987
Short name T959
Test name
Test status
Simulation time 919963478 ps
CPU time 3.86 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:18 PM PDT 24
Peak memory 200532 kb
Host smart-3a1cb9a2-1537-4af4-b12e-17a1447e0bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557550987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_tl_errors.557550987
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.3952653927
Short name T880
Test name
Test status
Simulation time 18006404 ps
CPU time 0.71 seconds
Started Aug 01 06:59:04 PM PDT 24
Finished Aug 01 06:59:05 PM PDT 24
Peak memory 199016 kb
Host smart-bd46e3c7-f85d-4784-a8db-5e6689cc035d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952653927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.3952653927
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2080224275
Short name T937
Test name
Test status
Simulation time 20691598 ps
CPU time 0.67 seconds
Started Aug 01 06:59:01 PM PDT 24
Finished Aug 01 06:59:02 PM PDT 24
Peak memory 198928 kb
Host smart-0886c3b9-a135-4206-adb9-0248834e1ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080224275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2080224275
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1353096878
Short name T878
Test name
Test status
Simulation time 11998585 ps
CPU time 0.66 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:00 PM PDT 24
Peak memory 198860 kb
Host smart-5d3a90b3-5bd0-44d6-889e-e1221e036015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353096878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1353096878
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2844808417
Short name T973
Test name
Test status
Simulation time 17542177 ps
CPU time 0.64 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:00 PM PDT 24
Peak memory 198968 kb
Host smart-be8e4b18-cba4-4349-b411-8d158fdbe3ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844808417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.2844808417
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1664189409
Short name T849
Test name
Test status
Simulation time 19140381 ps
CPU time 0.63 seconds
Started Aug 01 06:59:02 PM PDT 24
Finished Aug 01 06:59:03 PM PDT 24
Peak memory 198972 kb
Host smart-403feaed-2ea1-4d77-afce-9cb7a713ab57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664189409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.1664189409
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.1382560949
Short name T873
Test name
Test status
Simulation time 150996004 ps
CPU time 0.96 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 198968 kb
Host smart-cd37bd81-cfdb-421a-90be-7c6540642d12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382560949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.1382560949
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.882537976
Short name T928
Test name
Test status
Simulation time 12725026 ps
CPU time 0.72 seconds
Started Aug 01 06:58:59 PM PDT 24
Finished Aug 01 06:59:00 PM PDT 24
Peak memory 198976 kb
Host smart-d3ae6808-433c-48ee-a0ea-7fe2f37e7006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882537976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk
mgr_intr_test.882537976
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2097711202
Short name T901
Test name
Test status
Simulation time 35582482 ps
CPU time 0.69 seconds
Started Aug 01 06:59:00 PM PDT 24
Finished Aug 01 06:59:01 PM PDT 24
Peak memory 198916 kb
Host smart-330879a7-ae77-4562-806d-90644c16d40f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097711202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.2097711202
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.1049481181
Short name T870
Test name
Test status
Simulation time 19887706 ps
CPU time 0.69 seconds
Started Aug 01 06:59:04 PM PDT 24
Finished Aug 01 06:59:05 PM PDT 24
Peak memory 198944 kb
Host smart-2d24b733-50b1-40d5-bd0b-9a1a34077466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049481181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.1049481181
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2437261763
Short name T864
Test name
Test status
Simulation time 28167022 ps
CPU time 0.66 seconds
Started Aug 01 06:59:04 PM PDT 24
Finished Aug 01 06:59:05 PM PDT 24
Peak memory 198952 kb
Host smart-0b1b6918-08aa-47be-8993-6222246004b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437261763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2437261763
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2482492675
Short name T905
Test name
Test status
Simulation time 149333575 ps
CPU time 1.53 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200428 kb
Host smart-5c0457c0-45bf-4296-a4fe-d33e0a716507
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482492675 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2482492675
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.3976764295
Short name T909
Test name
Test status
Simulation time 32540090 ps
CPU time 0.86 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200356 kb
Host smart-dda0ffdf-d0c9-45d6-be95-e3ec4417c898
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976764295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.3976764295
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4242548646
Short name T833
Test name
Test status
Simulation time 77613738 ps
CPU time 0.8 seconds
Started Aug 01 06:58:13 PM PDT 24
Finished Aug 01 06:58:14 PM PDT 24
Peak memory 198968 kb
Host smart-bc05bf5b-7760-40e9-901d-e5ad98a7a51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242548646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.4242548646
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.1620968322
Short name T979
Test name
Test status
Simulation time 35640918 ps
CPU time 1.11 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200396 kb
Host smart-1d818553-f3d1-4b50-b4ff-cce9c57c6b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620968322 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.1620968322
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3702737621
Short name T62
Test name
Test status
Simulation time 69122031 ps
CPU time 1.4 seconds
Started Aug 01 06:58:16 PM PDT 24
Finished Aug 01 06:58:18 PM PDT 24
Peak memory 200616 kb
Host smart-157d8ffd-4971-49b8-bc77-0b02f49485c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702737621 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.3702737621
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3587810450
Short name T925
Test name
Test status
Simulation time 784906481 ps
CPU time 4.4 seconds
Started Aug 01 06:58:12 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 209024 kb
Host smart-ccbfaea2-8477-4ade-bb1c-12eb30196534
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587810450 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.3587810450
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4062136239
Short name T893
Test name
Test status
Simulation time 452706369 ps
CPU time 3.93 seconds
Started Aug 01 06:58:17 PM PDT 24
Finished Aug 01 06:58:21 PM PDT 24
Peak memory 200532 kb
Host smart-acd93d23-603b-421a-a6ac-66a0732887ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062136239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.4062136239
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4251183093
Short name T947
Test name
Test status
Simulation time 59526824 ps
CPU time 1.57 seconds
Started Aug 01 06:58:14 PM PDT 24
Finished Aug 01 06:58:16 PM PDT 24
Peak memory 200548 kb
Host smart-3d57faeb-b5ff-4258-8d64-4f2d21c56f15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251183093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.4251183093
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3266393
Short name T932
Test name
Test status
Simulation time 70556279 ps
CPU time 1.06 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 200308 kb
Host smart-72f03682-d584-44dc-bede-d1fd83d643fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266393 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3266393
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.4271805587
Short name T866
Test name
Test status
Simulation time 16116125 ps
CPU time 0.84 seconds
Started Aug 01 06:58:32 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200364 kb
Host smart-9183feb0-fd53-42c2-b489-584abd2fcea5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271805587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.4271805587
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1642820546
Short name T917
Test name
Test status
Simulation time 53672474 ps
CPU time 0.75 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 198908 kb
Host smart-a751a9ae-e30f-4a91-915b-328119e1dd5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642820546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.1642820546
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.978362292
Short name T838
Test name
Test status
Simulation time 34453877 ps
CPU time 1.17 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200352 kb
Host smart-9118f2c9-0d87-46e5-a8fb-05051351ab5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978362292 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.clkmgr_same_csr_outstanding.978362292
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.878447617
Short name T54
Test name
Test status
Simulation time 57964077 ps
CPU time 1.21 seconds
Started Aug 01 06:58:15 PM PDT 24
Finished Aug 01 06:58:17 PM PDT 24
Peak memory 200608 kb
Host smart-359542eb-e7ca-4fdc-861b-2f6b18db548a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878447617 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.878447617
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.2348467698
Short name T59
Test name
Test status
Simulation time 179296442 ps
CPU time 2.58 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 208984 kb
Host smart-d2d5abef-296e-4311-8386-1ee4e384cf65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348467698 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.2348467698
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.528916713
Short name T953
Test name
Test status
Simulation time 32250947 ps
CPU time 1.92 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200536 kb
Host smart-c9bb5645-c558-4f8e-9e82-872a86d50eba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528916713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm
gr_tl_errors.528916713
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.1861335783
Short name T100
Test name
Test status
Simulation time 433955977 ps
CPU time 3.4 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 200552 kb
Host smart-44405252-ef15-4823-80ac-65694d9c9700
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861335783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.1861335783
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.2974160325
Short name T931
Test name
Test status
Simulation time 480626705 ps
CPU time 2.32 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200404 kb
Host smart-a51f3ecd-6a79-493b-826a-09ead70e9ff1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974160325 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.2974160325
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.86754596
Short name T900
Test name
Test status
Simulation time 34526550 ps
CPU time 0.75 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:31 PM PDT 24
Peak memory 200232 kb
Host smart-ce3e0531-f46a-4361-b050-4f2b6e717e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86754596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.cl
kmgr_csr_rw.86754596
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.4041280351
Short name T944
Test name
Test status
Simulation time 37835823 ps
CPU time 0.7 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 199044 kb
Host smart-f2567a9b-a480-4308-bff1-c79ef71976c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041280351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.4041280351
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4156744523
Short name T78
Test name
Test status
Simulation time 115256690 ps
CPU time 1.14 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200388 kb
Host smart-8804b37c-9753-4b63-ba0f-e0b68747ca81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156744523 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.4156744523
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.1357617477
Short name T123
Test name
Test status
Simulation time 330442393 ps
CPU time 2.35 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 208988 kb
Host smart-33ed3a2d-bbbd-4263-8a9e-9c8f2510bc11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357617477 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.1357617477
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3500912652
Short name T955
Test name
Test status
Simulation time 85693059 ps
CPU time 1.82 seconds
Started Aug 01 06:58:29 PM PDT 24
Finished Aug 01 06:58:31 PM PDT 24
Peak memory 210048 kb
Host smart-2feae46a-9c8f-4eac-a862-7ad3a8fb0e85
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500912652 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3500912652
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.888722460
Short name T886
Test name
Test status
Simulation time 49018477 ps
CPU time 2.73 seconds
Started Aug 01 06:58:29 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200504 kb
Host smart-9223d177-77b9-4a6b-9ae9-dc9f4adb43b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888722460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_tl_errors.888722460
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1160112435
Short name T936
Test name
Test status
Simulation time 168883541 ps
CPU time 1.51 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200472 kb
Host smart-573dbf20-a8da-4ba9-87da-d432c6d42055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160112435 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.1160112435
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.3538338431
Short name T883
Test name
Test status
Simulation time 17112193 ps
CPU time 0.8 seconds
Started Aug 01 06:58:29 PM PDT 24
Finished Aug 01 06:58:30 PM PDT 24
Peak memory 200360 kb
Host smart-a36583be-f13e-4722-817b-c74298c8cfa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538338431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.3538338431
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.3313366659
Short name T896
Test name
Test status
Simulation time 29717652 ps
CPU time 0.67 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 198968 kb
Host smart-2b9b8117-af0e-4216-a132-65e3ddda94b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313366659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.3313366659
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.40847029
Short name T981
Test name
Test status
Simulation time 228560638 ps
CPU time 1.87 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200460 kb
Host smart-4e1f0780-1412-4195-86a1-e896f8baf88c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40847029 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 8.clkmgr_same_csr_outstanding.40847029
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4004074352
Short name T962
Test name
Test status
Simulation time 431677165 ps
CPU time 2.51 seconds
Started Aug 01 06:58:34 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 200864 kb
Host smart-62e06238-ed6a-4c3c-be94-336b8a10d536
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004074352 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.4004074352
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.2738641182
Short name T964
Test name
Test status
Simulation time 377579120 ps
CPU time 2.92 seconds
Started Aug 01 06:58:32 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 217200 kb
Host smart-e5e72583-b516-490b-b551-5a371b85b7d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738641182 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2738641182
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.1255740454
Short name T923
Test name
Test status
Simulation time 304407361 ps
CPU time 2.68 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200528 kb
Host smart-b3506c6c-4aa9-4bf7-b2f5-90cefba2bf49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255740454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.1255740454
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3794839113
Short name T161
Test name
Test status
Simulation time 243995725 ps
CPU time 3.01 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200568 kb
Host smart-72562f81-08b0-48d5-81a3-b3e4e6250378
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794839113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.3794839113
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3139360893
Short name T863
Test name
Test status
Simulation time 39282055 ps
CPU time 1.22 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200432 kb
Host smart-6f56af7d-c5f8-4f40-9655-cd2e98dde4af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139360893 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3139360893
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2154163428
Short name T967
Test name
Test status
Simulation time 74988456 ps
CPU time 0.99 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 200368 kb
Host smart-2125e0d5-790e-498a-a501-17e8847b2b03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154163428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.2154163428
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2283623695
Short name T899
Test name
Test status
Simulation time 20666349 ps
CPU time 0.69 seconds
Started Aug 01 06:58:33 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 198920 kb
Host smart-e46fcd82-b17e-4c84-ac3d-c9d8fe9d44cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283623695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2283623695
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.373382870
Short name T867
Test name
Test status
Simulation time 36326653 ps
CPU time 1.1 seconds
Started Aug 01 06:58:31 PM PDT 24
Finished Aug 01 06:58:33 PM PDT 24
Peak memory 200380 kb
Host smart-6ca4ebae-f5d2-4ecb-9e3a-2fcdd207b68d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373382870 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.clkmgr_same_csr_outstanding.373382870
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.961409188
Short name T118
Test name
Test status
Simulation time 253193917 ps
CPU time 2.01 seconds
Started Aug 01 06:58:32 PM PDT 24
Finished Aug 01 06:58:34 PM PDT 24
Peak memory 217396 kb
Host smart-d768be9f-3a72-4d02-bc8e-23e3025e12ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961409188 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.clkmgr_shadow_reg_errors.961409188
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.823184913
Short name T954
Test name
Test status
Simulation time 241627499 ps
CPU time 2.61 seconds
Started Aug 01 06:58:32 PM PDT 24
Finished Aug 01 06:58:35 PM PDT 24
Peak memory 201096 kb
Host smart-3526f178-a449-465c-a502-ecc264ed44c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823184913 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.823184913
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.3833295329
Short name T918
Test name
Test status
Simulation time 27166143 ps
CPU time 1.56 seconds
Started Aug 01 06:58:30 PM PDT 24
Finished Aug 01 06:58:32 PM PDT 24
Peak memory 200504 kb
Host smart-c2da7bc1-4cee-40e0-b523-51d05596c366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833295329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.3833295329
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.1792406901
Short name T498
Test name
Test status
Simulation time 72620852 ps
CPU time 0.98 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 201068 kb
Host smart-60631218-2113-4426-89de-259c20dca12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792406901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.1792406901
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3756464441
Short name T563
Test name
Test status
Simulation time 29510023 ps
CPU time 0.94 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 201088 kb
Host smart-c4fdebd6-5669-44ac-b8ab-678ef04bc6df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756464441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.3756464441
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2890403979
Short name T337
Test name
Test status
Simulation time 24375481 ps
CPU time 0.75 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 201036 kb
Host smart-ef99a9fc-6a74-402a-9fd3-fc1fc699fcdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890403979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2890403979
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1319186294
Short name T764
Test name
Test status
Simulation time 74957086 ps
CPU time 0.89 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 201072 kb
Host smart-e21376ef-3c60-469f-b3fd-061da7c29b19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319186294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1319186294
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.226854896
Short name T167
Test name
Test status
Simulation time 33474979 ps
CPU time 0.77 seconds
Started Aug 01 06:48:55 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 200980 kb
Host smart-94b2165d-622f-44af-b9d0-95290a7bab92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226854896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.226854896
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.236544706
Short name T663
Test name
Test status
Simulation time 2120814287 ps
CPU time 16.69 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201332 kb
Host smart-f5aebaaf-cc43-4869-b809-b111cc8704d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236544706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.236544706
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1034988023
Short name T579
Test name
Test status
Simulation time 1818440341 ps
CPU time 12.49 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201208 kb
Host smart-c5f1d0cc-e322-4407-9593-713edec23069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034988023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1034988023
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.3883645987
Short name T673
Test name
Test status
Simulation time 26541439 ps
CPU time 0.81 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 201076 kb
Host smart-9f828304-5684-42a7-80d9-90e925ade246
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883645987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.3883645987
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3010578302
Short name T139
Test name
Test status
Simulation time 81234860 ps
CPU time 1.08 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201088 kb
Host smart-685c470b-1057-4a52-92b6-b09fcf4478e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010578302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3010578302
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1262080906
Short name T771
Test name
Test status
Simulation time 30078367 ps
CPU time 1.02 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:53 PM PDT 24
Peak memory 201084 kb
Host smart-d6747ea5-308b-4d19-bcbc-1d4c5676262d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262080906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.1262080906
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.895847657
Short name T580
Test name
Test status
Simulation time 30441021 ps
CPU time 0.83 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:54 PM PDT 24
Peak memory 201072 kb
Host smart-40550593-be87-41df-a1b8-75d18ec60999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895847657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.895847657
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3755139833
Short name T141
Test name
Test status
Simulation time 1503981863 ps
CPU time 4.98 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201268 kb
Host smart-65e3fb17-4d8b-4616-a0ec-fc19b9aa80c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755139833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3755139833
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.887334215
Short name T505
Test name
Test status
Simulation time 22334417 ps
CPU time 0.89 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201024 kb
Host smart-86b22d1d-c882-4a02-99c8-dc742919706a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887334215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.887334215
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.1535510865
Short name T401
Test name
Test status
Simulation time 1430374354 ps
CPU time 5.66 seconds
Started Aug 01 06:48:51 PM PDT 24
Finished Aug 01 06:48:57 PM PDT 24
Peak memory 201176 kb
Host smart-4e712eb0-d0ea-4453-bee4-437cf3715c77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535510865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.1535510865
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.1651109185
Short name T414
Test name
Test status
Simulation time 220380706 ps
CPU time 1.44 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201096 kb
Host smart-dbd9facc-cbb6-4555-87d2-918f50a3acf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651109185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.1651109185
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.1692587063
Short name T791
Test name
Test status
Simulation time 26748898 ps
CPU time 0.77 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201052 kb
Host smart-6c3badff-7777-4f59-8419-bd828a3c58e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692587063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.1692587063
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3453330483
Short name T616
Test name
Test status
Simulation time 17350667 ps
CPU time 0.75 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201072 kb
Host smart-39abacaa-0ac6-4744-a715-6a1855bc0c2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453330483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3453330483
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.1922016608
Short name T655
Test name
Test status
Simulation time 11618268 ps
CPU time 0.68 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 200176 kb
Host smart-2ad018f7-e63c-46da-92a8-4383ba45fcff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922016608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1922016608
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2391266442
Short name T817
Test name
Test status
Simulation time 73190274 ps
CPU time 0.97 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201028 kb
Host smart-a2adc38b-7288-4774-9a82-4b82dc160dba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391266442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.2391266442
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.761955417
Short name T405
Test name
Test status
Simulation time 70358025 ps
CPU time 0.94 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:51 PM PDT 24
Peak memory 200944 kb
Host smart-8912cd47-a799-44d8-aaf3-4ac92a0e8026
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761955417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.761955417
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.4005790415
Short name T554
Test name
Test status
Simulation time 2357687114 ps
CPU time 19.2 seconds
Started Aug 01 06:48:53 PM PDT 24
Finished Aug 01 06:49:13 PM PDT 24
Peak memory 201340 kb
Host smart-6bc97325-1e89-4127-a9c2-797fcccf3e16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005790415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.4005790415
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.2561759472
Short name T800
Test name
Test status
Simulation time 1286078666 ps
CPU time 5.39 seconds
Started Aug 01 06:48:50 PM PDT 24
Finished Aug 01 06:48:56 PM PDT 24
Peak memory 201184 kb
Host smart-140b6fb3-770c-4ce8-89a9-98a7c965b05b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561759472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.2561759472
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2313701679
Short name T502
Test name
Test status
Simulation time 54529164 ps
CPU time 1.1 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 200988 kb
Host smart-cda3a91d-e23d-4f1d-b1ce-78d2907a9302
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313701679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2313701679
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.1392974959
Short name T529
Test name
Test status
Simulation time 26401215 ps
CPU time 0.82 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201040 kb
Host smart-49ef63fe-51d2-42c7-bd8e-8c68ac50367c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392974959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.1392974959
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2654302623
Short name T467
Test name
Test status
Simulation time 26928598 ps
CPU time 0.79 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201148 kb
Host smart-5e3a28da-cac7-4a8d-af98-df514d0a6b7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654302623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2654302623
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.3259932423
Short name T546
Test name
Test status
Simulation time 53067390 ps
CPU time 0.85 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201052 kb
Host smart-33687bb2-744d-42ba-b6c3-69f9bd8108e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259932423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.3259932423
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.3341314243
Short name T179
Test name
Test status
Simulation time 1050026968 ps
CPU time 4.77 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201300 kb
Host smart-fcbc4ff1-dce9-4987-8703-77da4706045e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341314243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3341314243
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.106355869
Short name T42
Test name
Test status
Simulation time 487101537 ps
CPU time 3.65 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 221948 kb
Host smart-1fa15473-137e-4157-a15e-72bc605987a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106355869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr
_sec_cm.106355869
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1268444279
Short name T201
Test name
Test status
Simulation time 18179805 ps
CPU time 0.84 seconds
Started Aug 01 06:48:54 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201068 kb
Host smart-73d5f3b7-a32b-4cbe-a071-b55fbd37c340
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268444279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1268444279
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.1672143629
Short name T413
Test name
Test status
Simulation time 2358154449 ps
CPU time 17.31 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:27 PM PDT 24
Peak memory 201340 kb
Host smart-039e5539-f8c8-4e76-bd42-b9ba25ae24c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672143629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.1672143629
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.4084124741
Short name T637
Test name
Test status
Simulation time 467478916 ps
CPU time 2.31 seconds
Started Aug 01 06:48:52 PM PDT 24
Finished Aug 01 06:48:55 PM PDT 24
Peak memory 201124 kb
Host smart-905e96d6-5c09-4b5d-9c73-34c8ff6af016
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084124741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.4084124741
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.747497623
Short name T798
Test name
Test status
Simulation time 46655559 ps
CPU time 0.84 seconds
Started Aug 01 06:49:23 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201080 kb
Host smart-046ab1c9-1278-44b3-abb5-398a772a4d60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747497623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkm
gr_alert_test.747497623
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.2578329085
Short name T311
Test name
Test status
Simulation time 19952493 ps
CPU time 0.73 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 200276 kb
Host smart-026e9f65-6555-405c-b26c-f51aeab4273a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578329085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.2578329085
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.450338081
Short name T468
Test name
Test status
Simulation time 45768626 ps
CPU time 0.84 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201024 kb
Host smart-9a268b9f-f224-4909-a8aa-518acb36502f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450338081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_div_intersig_mubi.450338081
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2323816651
Short name T669
Test name
Test status
Simulation time 133578916 ps
CPU time 1.12 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201036 kb
Host smart-8783417c-b39f-4519-bebe-ce3f6f19e6cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323816651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2323816651
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3127731715
Short name T13
Test name
Test status
Simulation time 1296084302 ps
CPU time 5.82 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:28 PM PDT 24
Peak memory 201132 kb
Host smart-1c24296d-1fda-48fc-820b-5fa408a171a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127731715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3127731715
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.1795691465
Short name T453
Test name
Test status
Simulation time 1031844638 ps
CPU time 4.81 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:27 PM PDT 24
Peak memory 201156 kb
Host smart-fce15105-52df-423a-bb3e-687575bb8cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795691465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.1795691465
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.2246732834
Short name T298
Test name
Test status
Simulation time 28070560 ps
CPU time 0.96 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201084 kb
Host smart-af741f89-2aa5-45f6-b680-045d67d5e48c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246732834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.2246732834
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2699709974
Short name T494
Test name
Test status
Simulation time 33203851 ps
CPU time 0.86 seconds
Started Aug 01 06:49:23 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201064 kb
Host smart-b78126ff-66dc-4a87-9b12-a13eb90029ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699709974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2699709974
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2326079337
Short name T219
Test name
Test status
Simulation time 78418110 ps
CPU time 1.06 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201084 kb
Host smart-e07f59b3-0048-4786-9e95-9f10bbca178f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326079337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.2326079337
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.11094195
Short name T287
Test name
Test status
Simulation time 14148937 ps
CPU time 0.72 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201052 kb
Host smart-b96e476f-cef1-4abd-b633-5e9408dc1037
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11094195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.11094195
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.1897558336
Short name T135
Test name
Test status
Simulation time 23735329 ps
CPU time 0.86 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201124 kb
Host smart-2d986139-0f2e-4553-8f70-6a8e8aeb1c89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897558336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.1897558336
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.1524306685
Short name T572
Test name
Test status
Simulation time 7000548824 ps
CPU time 29.18 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:49 PM PDT 24
Peak memory 201448 kb
Host smart-8604435c-ffa9-49e9-b1d1-54d0dce80d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524306685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.1524306685
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.3613254824
Short name T334
Test name
Test status
Simulation time 20170242 ps
CPU time 0.72 seconds
Started Aug 01 06:49:23 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201076 kb
Host smart-e28cedbc-4b39-4b52-ad55-68badcadcc00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613254824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.3613254824
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.4272311800
Short name T590
Test name
Test status
Simulation time 38446126 ps
CPU time 0.87 seconds
Started Aug 01 06:49:31 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 201148 kb
Host smart-0f382d99-17eb-49e5-94e7-7ffa00e92d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272311800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.4272311800
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.4288247231
Short name T416
Test name
Test status
Simulation time 15169968 ps
CPU time 0.74 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201108 kb
Host smart-fef4c9fd-ab7d-48d0-84ad-2e43f638abe1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288247231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.4288247231
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3500777239
Short name T157
Test name
Test status
Simulation time 13336546 ps
CPU time 0.75 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 200200 kb
Host smart-939e4170-1d41-4596-a957-7f4b98d41ee5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500777239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3500777239
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2856105841
Short name T628
Test name
Test status
Simulation time 25297102 ps
CPU time 0.88 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201088 kb
Host smart-951bf6bd-09b5-4bd0-954b-ade28434bb7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856105841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2856105841
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.3471666894
Short name T510
Test name
Test status
Simulation time 31080739 ps
CPU time 0.83 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201024 kb
Host smart-b27ca2bc-e486-4d9b-8ebb-b2ea95f56de1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471666894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.3471666894
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.3257564311
Short name T618
Test name
Test status
Simulation time 482416014 ps
CPU time 2.59 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201132 kb
Host smart-e4c3fea6-6b54-4ee1-8e59-94114dde5f72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257564311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3257564311
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.560689757
Short name T225
Test name
Test status
Simulation time 1356135833 ps
CPU time 5.73 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:25 PM PDT 24
Peak memory 201204 kb
Host smart-69301f85-87b5-4870-8e79-791e1f473f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560689757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti
meout.560689757
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2887253284
Short name T624
Test name
Test status
Simulation time 26517185 ps
CPU time 0.88 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201084 kb
Host smart-a9e1616f-2763-4d6f-88a0-aab2271d8959
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887253284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2887253284
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.4225526988
Short name T811
Test name
Test status
Simulation time 62629635 ps
CPU time 0.9 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201060 kb
Host smart-72587a3a-ddec-403b-8af2-380201243d08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225526988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.4225526988
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3163522131
Short name T214
Test name
Test status
Simulation time 16828283 ps
CPU time 0.8 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201076 kb
Host smart-b1d4f007-5025-41fe-8f28-9e8ba629f296
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163522131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.3163522131
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.4048328447
Short name T496
Test name
Test status
Simulation time 44363257 ps
CPU time 0.78 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201092 kb
Host smart-bb9f77cd-9601-401a-b2bf-43cb1600e6e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048328447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4048328447
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.1278221497
Short name T826
Test name
Test status
Simulation time 41789926 ps
CPU time 0.97 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201016 kb
Host smart-43e7d2fd-894c-4398-8da0-e3ab5c953443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278221497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1278221497
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.1482600906
Short name T290
Test name
Test status
Simulation time 2330535111 ps
CPU time 19.1 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:48 PM PDT 24
Peak memory 201320 kb
Host smart-e6c2cc7e-803d-47d6-b7a7-c119980d1246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482600906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.1482600906
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.1071564358
Short name T183
Test name
Test status
Simulation time 131064010 ps
CPU time 1.3 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201028 kb
Host smart-2a7c0103-eceb-4452-8eb3-0eaa000f36c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071564358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1071564358
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.3695292743
Short name T36
Test name
Test status
Simulation time 16958051 ps
CPU time 0.76 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201124 kb
Host smart-bff22834-80dc-4c22-9d1b-9b1ccb8f866b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695292743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.3695292743
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2234500328
Short name T333
Test name
Test status
Simulation time 23248324 ps
CPU time 0.89 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201104 kb
Host smart-fa36e3c9-cca8-4360-bdf0-9d272f46b5ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234500328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.2234500328
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.389995569
Short name T377
Test name
Test status
Simulation time 53055238 ps
CPU time 0.81 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 200984 kb
Host smart-44357ac9-2dca-4e99-a3da-1b8c4aed5315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389995569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.389995569
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.4086839665
Short name T29
Test name
Test status
Simulation time 38527183 ps
CPU time 0.87 seconds
Started Aug 01 06:49:31 PM PDT 24
Finished Aug 01 06:49:32 PM PDT 24
Peak memory 201080 kb
Host smart-615a51c1-64ae-4a80-a3b1-e0cbce9d4135
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086839665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.4086839665
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3160921678
Short name T766
Test name
Test status
Simulation time 65413287 ps
CPU time 0.95 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201024 kb
Host smart-1ec5d043-7f61-43f5-bf11-9e380d37c425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160921678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3160921678
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1556672023
Short name T308
Test name
Test status
Simulation time 1547748189 ps
CPU time 6.97 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201160 kb
Host smart-c3f1b7a5-3987-4f75-8158-a3dc31610419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556672023 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1556672023
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2090399390
Short name T365
Test name
Test status
Simulation time 1121639656 ps
CPU time 5.17 seconds
Started Aug 01 06:49:30 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201152 kb
Host smart-850dadd7-a6ee-4c58-a994-bb1da530c027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090399390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2090399390
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.3551966086
Short name T491
Test name
Test status
Simulation time 25240454 ps
CPU time 0.87 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201080 kb
Host smart-4e8695cf-8f42-486b-8cbf-f735068ab4b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551966086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.3551966086
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.2928810761
Short name T744
Test name
Test status
Simulation time 19424002 ps
CPU time 0.78 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201016 kb
Host smart-5cd4bc4a-fa35-4583-8aa9-82b9f7c64273
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928810761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.2928810761
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3408856719
Short name T51
Test name
Test status
Simulation time 65572947 ps
CPU time 1.02 seconds
Started Aug 01 06:49:36 PM PDT 24
Finished Aug 01 06:49:37 PM PDT 24
Peak memory 201028 kb
Host smart-a1840fa9-77e2-40b3-ab37-53cd02a58ea2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408856719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3408856719
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.3242316966
Short name T239
Test name
Test status
Simulation time 40925153 ps
CPU time 0.8 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 201052 kb
Host smart-e9c0fcab-2fd1-4a94-8c28-b0461f11552e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242316966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3242316966
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3454067271
Short name T710
Test name
Test status
Simulation time 962138638 ps
CPU time 5.54 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201224 kb
Host smart-51ca2153-a149-4a78-b701-3226a5aa1f26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454067271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3454067271
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.474055543
Short name T802
Test name
Test status
Simulation time 78258426 ps
CPU time 0.99 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201048 kb
Host smart-9971e045-a637-424c-93c7-361b3b22a54d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474055543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.474055543
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.797029186
Short name T424
Test name
Test status
Simulation time 371616816 ps
CPU time 2.92 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:37 PM PDT 24
Peak memory 201084 kb
Host smart-5320abd3-de17-4752-ba5e-72cbf785eb44
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797029186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.797029186
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.982871606
Short name T594
Test name
Test status
Simulation time 99126336 ps
CPU time 1.16 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201092 kb
Host smart-7f39a8fb-a6ef-4122-900a-e2de520dd678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982871606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.982871606
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.460759871
Short name T44
Test name
Test status
Simulation time 30767491 ps
CPU time 0.79 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201088 kb
Host smart-ec80d699-250d-457d-9745-c0148e433da0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460759871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkm
gr_alert_test.460759871
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.505373249
Short name T630
Test name
Test status
Simulation time 22314648 ps
CPU time 0.82 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 201052 kb
Host smart-282bf7f0-cf5d-4b93-8ce4-b2be499d63c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505373249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.505373249
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3785870991
Short name T356
Test name
Test status
Simulation time 18450986 ps
CPU time 0.72 seconds
Started Aug 01 06:49:30 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 200204 kb
Host smart-5b5477ae-6703-4aed-a86c-a96df2eced90
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785870991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3785870991
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.3282871120
Short name T476
Test name
Test status
Simulation time 37062970 ps
CPU time 0.91 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 201056 kb
Host smart-a4d55d4c-a7d1-4a5d-bc14-aed5c848c24c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282871120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.3282871120
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.2004326914
Short name T786
Test name
Test status
Simulation time 46640397 ps
CPU time 0.98 seconds
Started Aug 01 06:49:36 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201004 kb
Host smart-1028c310-2080-48cb-a53a-edba09009924
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004326914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2004326914
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.4291119796
Short name T617
Test name
Test status
Simulation time 1521670418 ps
CPU time 11.49 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:46 PM PDT 24
Peak memory 201096 kb
Host smart-e3677279-177b-4988-804e-09656831e64e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291119796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4291119796
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.16465610
Short name T49
Test name
Test status
Simulation time 2549718561 ps
CPU time 9.61 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201376 kb
Host smart-228a0e4e-4d9d-403d-8d26-ee6cda9ef2db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16465610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_tim
eout.16465610
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3229136524
Short name T489
Test name
Test status
Simulation time 14514957 ps
CPU time 0.74 seconds
Started Aug 01 06:49:30 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 201076 kb
Host smart-5fec96a6-bed2-4884-9d49-ca913c2c67bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229136524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.3229136524
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1217236364
Short name T215
Test name
Test status
Simulation time 20449989 ps
CPU time 0.85 seconds
Started Aug 01 06:49:37 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201048 kb
Host smart-ed31fbf9-1b1a-4549-9f81-01e3282bc01d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217236364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1217236364
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.3591477960
Short name T206
Test name
Test status
Simulation time 25490534 ps
CPU time 0.76 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201048 kb
Host smart-8b9e1189-81cb-4bb5-a2a8-ad4856b55b71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591477960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.3591477960
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.4156682888
Short name T736
Test name
Test status
Simulation time 35018896 ps
CPU time 0.81 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201024 kb
Host smart-a1c7aea0-daab-4219-9fd1-47d91cbc9c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156682888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.4156682888
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1853274970
Short name T647
Test name
Test status
Simulation time 589022128 ps
CPU time 2.49 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 201008 kb
Host smart-f61c7c7f-bd2c-436d-b0de-cb58925d8fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853274970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1853274970
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.94087564
Short name T306
Test name
Test status
Simulation time 38917728 ps
CPU time 0.9 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201052 kb
Host smart-34df28bf-3a55-470d-a012-83e8f76c854f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94087564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.94087564
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.3237482081
Short name T300
Test name
Test status
Simulation time 10549658146 ps
CPU time 42.09 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:50:20 PM PDT 24
Peak memory 201392 kb
Host smart-3674d589-a4db-4b9d-880f-3bc6bae21498
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237482081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.3237482081
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.1457013888
Short name T753
Test name
Test status
Simulation time 25255305 ps
CPU time 0.85 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201100 kb
Host smart-7ea222e9-4335-4419-8eab-45533373f0be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457013888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.1457013888
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.1426743611
Short name T302
Test name
Test status
Simulation time 16392628 ps
CPU time 0.79 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201104 kb
Host smart-4bf61bb0-ea56-44fc-ba9d-163bf5f0b468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426743611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.1426743611
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.3613933284
Short name T212
Test name
Test status
Simulation time 14235923 ps
CPU time 0.78 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201040 kb
Host smart-9174abd2-6d91-488d-8fee-e78ffe36f717
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613933284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.3613933284
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1921889640
Short name T364
Test name
Test status
Simulation time 13516233 ps
CPU time 0.73 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 200972 kb
Host smart-79ea9d23-8fe9-4bae-b74e-4c9553966fdf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921889640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1921889640
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.1206043489
Short name T442
Test name
Test status
Simulation time 295927216 ps
CPU time 1.72 seconds
Started Aug 01 06:49:36 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201032 kb
Host smart-8b9063e8-a08d-471c-81a0-47980028b077
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206043489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.1206043489
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.1766059921
Short name T728
Test name
Test status
Simulation time 18647492 ps
CPU time 0.78 seconds
Started Aug 01 06:49:28 PM PDT 24
Finished Aug 01 06:49:28 PM PDT 24
Peak memory 201004 kb
Host smart-1aa88291-b7da-441f-86b4-5ed680209643
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766059921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1766059921
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1497825256
Short name T645
Test name
Test status
Simulation time 579369690 ps
CPU time 3.18 seconds
Started Aug 01 06:49:31 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201132 kb
Host smart-f64727de-7a33-4d97-b132-8b5f50e86e67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497825256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1497825256
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.6405956
Short name T446
Test name
Test status
Simulation time 2179486464 ps
CPU time 15.64 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:49 PM PDT 24
Peak memory 201416 kb
Host smart-452dd6fd-6bcc-4be9-9f4f-507c1ff01cb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6405956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_time
out_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_time
out.6405956
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.4123863242
Short name T388
Test name
Test status
Simulation time 68952433 ps
CPU time 1.02 seconds
Started Aug 01 06:49:33 PM PDT 24
Finished Aug 01 06:49:34 PM PDT 24
Peak memory 201088 kb
Host smart-93cde690-a5fb-408d-9833-d976e57a006a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123863242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.4123863242
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.3182047644
Short name T758
Test name
Test status
Simulation time 33106663 ps
CPU time 0.8 seconds
Started Aug 01 06:49:31 PM PDT 24
Finished Aug 01 06:49:32 PM PDT 24
Peak memory 201072 kb
Host smart-2d8ece8d-2c1d-4c32-a30f-a779d86e7546
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182047644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.3182047644
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3110448123
Short name T693
Test name
Test status
Simulation time 55773917 ps
CPU time 0.91 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201088 kb
Host smart-c8ec3e52-360e-4df5-8c4b-13939cf206ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110448123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3110448123
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.4284213337
Short name T668
Test name
Test status
Simulation time 47850740 ps
CPU time 0.85 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201072 kb
Host smart-d13f1a87-c571-4d9d-9170-02898be8ff5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284213337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.4284213337
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3585315357
Short name T609
Test name
Test status
Simulation time 611964702 ps
CPU time 3.76 seconds
Started Aug 01 06:49:31 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 201256 kb
Host smart-b19b931e-0e66-4772-92bb-16a19660a672
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585315357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3585315357
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1266805634
Short name T314
Test name
Test status
Simulation time 35551635 ps
CPU time 0.85 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201116 kb
Host smart-4b531d02-fd7e-44eb-8464-b8845d242547
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266805634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1266805634
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.1839989994
Short name T278
Test name
Test status
Simulation time 7197972785 ps
CPU time 37.16 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 201396 kb
Host smart-c5551b89-a24f-4234-8ac6-97234c4f7251
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839989994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.1839989994
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2777619641
Short name T237
Test name
Test status
Simulation time 50360897 ps
CPU time 0.84 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201044 kb
Host smart-729d5204-8778-4ece-851e-0d0e4e8ddf5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777619641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2777619641
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.3423599705
Short name T202
Test name
Test status
Simulation time 20251199 ps
CPU time 0.74 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:36 PM PDT 24
Peak memory 201100 kb
Host smart-36f5c620-ab62-4b4a-bfad-6dcaffe9c837
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423599705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.3423599705
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.1851959195
Short name T783
Test name
Test status
Simulation time 45379255 ps
CPU time 0.85 seconds
Started Aug 01 06:49:30 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 201068 kb
Host smart-07ceaed0-ce81-4ba9-88b1-d0782c4b9f7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851959195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.1851959195
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.163937340
Short name T595
Test name
Test status
Simulation time 45170915 ps
CPU time 0.79 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 200968 kb
Host smart-785bafc2-5945-4603-9bc1-128327b1eac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163937340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.163937340
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.3500714708
Short name T526
Test name
Test status
Simulation time 16148262 ps
CPU time 0.85 seconds
Started Aug 01 06:49:37 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201020 kb
Host smart-91a5da6a-6e98-43f6-b8a2-556da85e6074
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500714708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.3500714708
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.1118245266
Short name T769
Test name
Test status
Simulation time 25399110 ps
CPU time 0.84 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201076 kb
Host smart-f8c66af3-dc2b-478c-b0f9-3d467f9b17b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118245266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.1118245266
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.1359655136
Short name T654
Test name
Test status
Simulation time 1076176990 ps
CPU time 4.59 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201116 kb
Host smart-17ed23b9-fa05-4a92-888b-92a68e5525f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359655136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.1359655136
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3073490888
Short name T220
Test name
Test status
Simulation time 1343205419 ps
CPU time 9.46 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201164 kb
Host smart-8e073e45-ca74-414e-8239-275898371870
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073490888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3073490888
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.593275381
Short name T354
Test name
Test status
Simulation time 71122575 ps
CPU time 1.07 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 200996 kb
Host smart-50ae214b-aece-4652-a60e-fd13b6287ece
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593275381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.593275381
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2522354961
Short name T164
Test name
Test status
Simulation time 257537833 ps
CPU time 1.63 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:37 PM PDT 24
Peak memory 201088 kb
Host smart-fc20b504-f640-4c8a-9231-1f42c4774f6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522354961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2522354961
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.2637729203
Short name T186
Test name
Test status
Simulation time 33391929 ps
CPU time 0.87 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201036 kb
Host smart-007b7a32-bdf1-43a2-9086-c5a012df0737
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637729203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.2637729203
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.2757262239
Short name T223
Test name
Test status
Simulation time 42973333 ps
CPU time 0.84 seconds
Started Aug 01 06:49:34 PM PDT 24
Finished Aug 01 06:49:35 PM PDT 24
Peak memory 201056 kb
Host smart-7154b599-6283-401e-801c-a7e2b68701b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757262239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2757262239
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.438251312
Short name T428
Test name
Test status
Simulation time 729015895 ps
CPU time 3.37 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201292 kb
Host smart-512a1497-883e-482f-9613-25b0c5afb8fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438251312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.438251312
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1643838050
Short name T213
Test name
Test status
Simulation time 16403030 ps
CPU time 0.81 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 200996 kb
Host smart-44eff9a3-81a2-423e-a28b-b3f4b68099da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643838050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1643838050
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.884401209
Short name T495
Test name
Test status
Simulation time 8923588545 ps
CPU time 65.47 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:50:38 PM PDT 24
Peak memory 201440 kb
Host smart-4a3dfb3d-2f17-472b-bdf2-580fb4d18df5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884401209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.884401209
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.507307863
Short name T805
Test name
Test status
Simulation time 28877981 ps
CPU time 0.91 seconds
Started Aug 01 06:49:29 PM PDT 24
Finished Aug 01 06:49:30 PM PDT 24
Peak memory 201008 kb
Host smart-8db6a5a3-ba42-4db1-a57b-15546c195e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507307863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.507307863
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.2249454478
Short name T756
Test name
Test status
Simulation time 17579865 ps
CPU time 0.81 seconds
Started Aug 01 06:49:37 PM PDT 24
Finished Aug 01 06:49:38 PM PDT 24
Peak memory 201120 kb
Host smart-49b89fbb-bd4b-40fb-a3e2-3c3a5629a437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249454478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.2249454478
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.3443636466
Short name T810
Test name
Test status
Simulation time 18640098 ps
CPU time 0.82 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201060 kb
Host smart-2adbacae-5240-4723-88b2-450dbb7f96ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443636466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.3443636466
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2564427712
Short name T410
Test name
Test status
Simulation time 30086267 ps
CPU time 0.76 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 200292 kb
Host smart-93655ab2-fa97-40fc-808c-77752274ed1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564427712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2564427712
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3647323932
Short name T352
Test name
Test status
Simulation time 20084714 ps
CPU time 0.76 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201084 kb
Host smart-66084e88-58af-486d-a0fe-d2b67d10e533
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647323932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3647323932
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.2753116636
Short name T170
Test name
Test status
Simulation time 30203408 ps
CPU time 0.91 seconds
Started Aug 01 06:49:30 PM PDT 24
Finished Aug 01 06:49:31 PM PDT 24
Peak memory 201032 kb
Host smart-6fa4a5f5-c81b-4625-9368-156dea294db4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753116636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2753116636
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.834440265
Short name T614
Test name
Test status
Simulation time 338206095 ps
CPU time 2.17 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:40 PM PDT 24
Peak memory 201156 kb
Host smart-8dc054ac-2063-4238-9a00-5f6c88b2cab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834440265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.834440265
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.1807778693
Short name T814
Test name
Test status
Simulation time 1539271190 ps
CPU time 6.36 seconds
Started Aug 01 06:49:35 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201192 kb
Host smart-30fda797-3ccf-49cf-bc08-9cad121f3dca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807778693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.1807778693
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3490494380
Short name T688
Test name
Test status
Simulation time 33746108 ps
CPU time 0.91 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:49:40 PM PDT 24
Peak memory 201148 kb
Host smart-588a534e-6cfb-4a23-96fa-8b77cbc852ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490494380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.3490494380
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.512394967
Short name T607
Test name
Test status
Simulation time 16347627 ps
CPU time 0.79 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201076 kb
Host smart-4d1dd324-eb26-4415-bb6a-1ea2964e4965
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512394967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_clk_byp_req_intersig_mubi.512394967
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.611227337
Short name T649
Test name
Test status
Simulation time 46710035 ps
CPU time 0.97 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201072 kb
Host smart-77250ed1-5a3f-4b5d-8c98-7e52c920e309
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611227337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_ctrl_intersig_mubi.611227337
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.2985060483
Short name T407
Test name
Test status
Simulation time 37428320 ps
CPU time 0.78 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201092 kb
Host smart-dc852b18-75d4-4715-ae7b-18bd1e07982a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985060483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2985060483
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.645461423
Short name T721
Test name
Test status
Simulation time 1094601391 ps
CPU time 4.17 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:46 PM PDT 24
Peak memory 201228 kb
Host smart-257b6df1-e575-4d0a-8614-4b90ada7970e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645461423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.645461423
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.3957558284
Short name T598
Test name
Test status
Simulation time 74887703 ps
CPU time 1.07 seconds
Started Aug 01 06:49:32 PM PDT 24
Finished Aug 01 06:49:33 PM PDT 24
Peak memory 201004 kb
Host smart-3078b05e-c33e-4e53-9377-5b5ff2ad236c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957558284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3957558284
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.1046948751
Short name T343
Test name
Test status
Simulation time 726156085 ps
CPU time 4.57 seconds
Started Aug 01 06:49:37 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201184 kb
Host smart-3d3a34ac-b330-433d-8391-7e2e20322281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046948751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.1046948751
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all_with_rand_reset.3821848723
Short name T69
Test name
Test status
Simulation time 92302050979 ps
CPU time 537.18 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:58:36 PM PDT 24
Peak memory 209820 kb
Host smart-d0dcf63b-98e4-4d53-8503-42ad80ffa2cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3821848723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3821848723
Directory /workspace/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3168337509
Short name T795
Test name
Test status
Simulation time 84442636 ps
CPU time 1.14 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201092 kb
Host smart-788ea59d-5c45-4657-91b4-cb1220767550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168337509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3168337509
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2389723550
Short name T506
Test name
Test status
Simulation time 37128414 ps
CPU time 0.82 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201056 kb
Host smart-a1795121-3bea-4f3f-bdd6-155d5891427a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389723550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2389723550
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.3558113948
Short name T497
Test name
Test status
Simulation time 103536479 ps
CPU time 1.18 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201100 kb
Host smart-a32409a5-9463-47c4-bb49-3839d9a58b42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558113948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.3558113948
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.3845108142
Short name T39
Test name
Test status
Simulation time 16298754 ps
CPU time 0.74 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 200244 kb
Host smart-90b597ca-9326-4039-840d-6c8a2f3888bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845108142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3845108142
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.452104179
Short name T392
Test name
Test status
Simulation time 31528745 ps
CPU time 0.79 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201032 kb
Host smart-973eaeee-508a-44c7-b041-9eb0fc5a32c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452104179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_div_intersig_mubi.452104179
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.3712849392
Short name T241
Test name
Test status
Simulation time 50167162 ps
CPU time 0.92 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 200976 kb
Host smart-012c588d-6c2e-427c-b26c-2be3e058cf44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712849392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3712849392
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3920442879
Short name T359
Test name
Test status
Simulation time 1785506476 ps
CPU time 8.31 seconds
Started Aug 01 06:49:48 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 201304 kb
Host smart-a64653d3-9abe-47b6-9bcc-348073c23d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920442879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3920442879
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2397515925
Short name T460
Test name
Test status
Simulation time 2053955837 ps
CPU time 14.94 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201304 kb
Host smart-d1be681c-54de-45d0-9aa8-e9e2d1077922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397515925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2397515925
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2161416188
Short name T643
Test name
Test status
Simulation time 21857838 ps
CPU time 0.92 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201084 kb
Host smart-00e7e8f7-6ddc-45f2-9b5f-04b66a083ab0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161416188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2161416188
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3389038374
Short name T775
Test name
Test status
Simulation time 43559217 ps
CPU time 0.95 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201084 kb
Host smart-c23a7fdf-699f-4a28-ab36-0e95876ea15d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389038374 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.3389038374
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2469734816
Short name T430
Test name
Test status
Simulation time 22095662 ps
CPU time 0.87 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201088 kb
Host smart-9e40d3b2-4afd-4b41-bd4c-1fd038d6ede9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469734816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.2469734816
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.3116945009
Short name T205
Test name
Test status
Simulation time 45458778 ps
CPU time 0.9 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201052 kb
Host smart-b22fcd50-575a-439b-87bd-4ca153e37a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116945009 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.3116945009
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.283538699
Short name T305
Test name
Test status
Simulation time 404858297 ps
CPU time 2.47 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:49:48 PM PDT 24
Peak memory 201080 kb
Host smart-0a452a8e-2d57-4c9e-95d8-6ba0130bbae7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283538699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.283538699
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3662793884
Short name T329
Test name
Test status
Simulation time 52305439 ps
CPU time 0.93 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201080 kb
Host smart-1707e0c5-1b8c-4fdf-afef-63f0a5b28e1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662793884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3662793884
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.1340431580
Short name T267
Test name
Test status
Simulation time 6838223140 ps
CPU time 52.82 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:50:33 PM PDT 24
Peak memory 201412 kb
Host smart-25cc00be-acb7-4cae-b9de-5a320eb67104
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340431580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.1340431580
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2140005686
Short name T192
Test name
Test status
Simulation time 79212454 ps
CPU time 1.02 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:49:40 PM PDT 24
Peak memory 200988 kb
Host smart-741e3265-0acc-4b06-b576-722375b34d10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140005686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2140005686
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2382141545
Short name T245
Test name
Test status
Simulation time 22366975 ps
CPU time 0.76 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:49:40 PM PDT 24
Peak memory 201012 kb
Host smart-3571a8a6-d647-45c0-95db-ae0cfaff856e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382141545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2382141545
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1008108745
Short name T493
Test name
Test status
Simulation time 50188299 ps
CPU time 0.94 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:49:40 PM PDT 24
Peak memory 201052 kb
Host smart-5fab9bce-9bb1-438e-a0b0-b9e3ab6e21b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008108745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1008108745
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.287846555
Short name T325
Test name
Test status
Simulation time 18289424 ps
CPU time 0.72 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:04 PM PDT 24
Peak memory 200996 kb
Host smart-898f895a-c1d9-4a57-8049-145f594be059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287846555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.287846555
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.878766625
Short name T504
Test name
Test status
Simulation time 102775053 ps
CPU time 1.12 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201080 kb
Host smart-3d52b559-5ad1-4161-b709-00ee8eb9f724
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878766625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_div_intersig_mubi.878766625
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.2861221690
Short name T369
Test name
Test status
Simulation time 26700395 ps
CPU time 0.9 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201080 kb
Host smart-8a8a613a-a150-41bf-8a9b-a8c13f2d0b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861221690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2861221690
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.2521227858
Short name T577
Test name
Test status
Simulation time 1051452472 ps
CPU time 6.31 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:45 PM PDT 24
Peak memory 201132 kb
Host smart-d9216885-a024-4293-a666-451ff5a6fa15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521227858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.2521227858
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.3698148577
Short name T316
Test name
Test status
Simulation time 1989906497 ps
CPU time 8.58 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:50 PM PDT 24
Peak memory 201172 kb
Host smart-cf29088c-7aed-4d5b-ac27-437e07d5dd4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698148577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.3698148577
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2265225527
Short name T203
Test name
Test status
Simulation time 64324726 ps
CPU time 1.04 seconds
Started Aug 01 06:49:40 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201124 kb
Host smart-11000f16-c13b-4a25-b7b8-87c6198f6033
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265225527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.2265225527
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.271449512
Short name T360
Test name
Test status
Simulation time 15434908 ps
CPU time 0.76 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201068 kb
Host smart-7ba13e5c-3ef9-4dae-a330-0e107a6cc2d7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271449512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.clkmgr_lc_clk_byp_req_intersig_mubi.271449512
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1607268113
Short name T284
Test name
Test status
Simulation time 23980495 ps
CPU time 0.75 seconds
Started Aug 01 06:49:38 PM PDT 24
Finished Aug 01 06:49:39 PM PDT 24
Peak memory 201056 kb
Host smart-71dba719-0888-498d-958c-52e547b11ef4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607268113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.1607268113
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.1394810163
Short name T246
Test name
Test status
Simulation time 16800988 ps
CPU time 0.75 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201076 kb
Host smart-58f34ff1-b6fe-473a-9616-f850015ea950
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394810163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1394810163
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.4290705169
Short name T653
Test name
Test status
Simulation time 88873403 ps
CPU time 0.99 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201084 kb
Host smart-784641c3-af80-41ad-b8d0-ffed8270d46f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290705169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.4290705169
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.986783968
Short name T622
Test name
Test status
Simulation time 94164263 ps
CPU time 1.06 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:49:47 PM PDT 24
Peak memory 201076 kb
Host smart-20dc0271-4eda-4529-9e89-1a128ee16d2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986783968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.986783968
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1500500871
Short name T733
Test name
Test status
Simulation time 8983842513 ps
CPU time 32.37 seconds
Started Aug 01 06:49:47 PM PDT 24
Finished Aug 01 06:50:20 PM PDT 24
Peak memory 201380 kb
Host smart-e30225a0-dcdf-48cf-822c-e733d86191d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500500871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1500500871
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.2064393339
Short name T739
Test name
Test status
Simulation time 86024944026 ps
CPU time 868.16 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 07:04:08 PM PDT 24
Peak memory 217912 kb
Host smart-bfe6882c-da34-46b8-a33b-5c8d964ea17d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2064393339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.2064393339
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.2227795156
Short name T380
Test name
Test status
Simulation time 35611064 ps
CPU time 0.81 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:49 PM PDT 24
Peak memory 201076 kb
Host smart-abd80195-0c11-435f-b7e5-da29be9bfd7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227795156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.2227795156
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3552118909
Short name T264
Test name
Test status
Simulation time 58075985 ps
CPU time 0.97 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201076 kb
Host smart-2baf7a08-7684-4792-86fa-faf8e46a7e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552118909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3552118909
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3254119146
Short name T88
Test name
Test status
Simulation time 62433490 ps
CPU time 1.06 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:49:48 PM PDT 24
Peak memory 201048 kb
Host smart-6a7b04cf-b777-4350-b03d-4e20d534fec8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254119146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3254119146
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.3003180324
Short name T154
Test name
Test status
Simulation time 28430837 ps
CPU time 0.75 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 200244 kb
Host smart-4a139fcf-f5ee-4ff5-9db9-8fb0bb673cb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003180324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3003180324
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1507703967
Short name T140
Test name
Test status
Simulation time 23346891 ps
CPU time 0.87 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:49:47 PM PDT 24
Peak memory 201084 kb
Host smart-42f53e3a-52cf-4d85-8a75-beaaf1b50426
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507703967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1507703967
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2914560132
Short name T270
Test name
Test status
Simulation time 54056319 ps
CPU time 0.88 seconds
Started Aug 01 06:49:48 PM PDT 24
Finished Aug 01 06:49:49 PM PDT 24
Peak memory 201052 kb
Host smart-25622c6b-b242-43c7-8d2e-bd8be3d66c3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914560132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2914560132
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.914282444
Short name T427
Test name
Test status
Simulation time 322934353 ps
CPU time 2.48 seconds
Started Aug 01 06:49:39 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201132 kb
Host smart-3fbdeed4-4ad1-457a-8a53-d1995a8b9557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914282444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.914282444
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1611677866
Short name T828
Test name
Test status
Simulation time 2296747562 ps
CPU time 16.9 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201304 kb
Host smart-e2c5f1e4-a284-4250-9ccf-20063d74f701
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611677866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1611677866
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1825774777
Short name T433
Test name
Test status
Simulation time 39361360 ps
CPU time 0.79 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:49:47 PM PDT 24
Peak memory 201080 kb
Host smart-847e6dfc-bd89-43d6-bc8f-ead16af0aad5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825774777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.1825774777
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2230312070
Short name T465
Test name
Test status
Simulation time 21233012 ps
CPU time 0.85 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201036 kb
Host smart-c3fa90eb-8da8-4825-96b8-0720193db2cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230312070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2230312070
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.3057269290
Short name T286
Test name
Test status
Simulation time 20699075 ps
CPU time 0.87 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201040 kb
Host smart-27699279-025f-40a8-be28-45967dd0362d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057269290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.3057269290
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.2809250510
Short name T600
Test name
Test status
Simulation time 14879198 ps
CPU time 0.77 seconds
Started Aug 01 06:49:45 PM PDT 24
Finished Aug 01 06:49:46 PM PDT 24
Peak memory 201072 kb
Host smart-951ef148-a31c-46d8-b89e-1d5cec964827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809250510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.2809250510
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2225040754
Short name T672
Test name
Test status
Simulation time 430792722 ps
CPU time 2.85 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:46 PM PDT 24
Peak memory 201052 kb
Host smart-2930ff59-8127-47d0-ad9b-d6abecdc5fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225040754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2225040754
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2314274805
Short name T819
Test name
Test status
Simulation time 41229145 ps
CPU time 0.89 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201040 kb
Host smart-bb190bc5-1f8c-426a-baef-eafb6b47675c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314274805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2314274805
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.3287621265
Short name T15
Test name
Test status
Simulation time 12407519995 ps
CPU time 91.03 seconds
Started Aug 01 06:49:47 PM PDT 24
Finished Aug 01 06:51:18 PM PDT 24
Peak memory 201396 kb
Host smart-e23f9556-6417-440a-9b7b-ad3bd3225134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287621265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.3287621265
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all_with_rand_reset.2806461754
Short name T64
Test name
Test status
Simulation time 14555610010 ps
CPU time 209.14 seconds
Started Aug 01 06:49:46 PM PDT 24
Finished Aug 01 06:53:16 PM PDT 24
Peak memory 209632 kb
Host smart-8ad72add-41f2-4829-b619-360d58e983fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2806461754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.2806461754
Directory /workspace/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.clkmgr_trans.2455234661
Short name T550
Test name
Test status
Simulation time 33597030 ps
CPU time 0.96 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201044 kb
Host smart-e4b8beef-1a8d-4d0f-ad9b-ceee56a0956d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455234661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2455234661
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.90453263
Short name T172
Test name
Test status
Simulation time 113798657 ps
CPU time 1.06 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201068 kb
Host smart-102d8cde-594b-40d7-838c-0f1585aec3ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90453263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_alert_test.90453263
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2200610662
Short name T6
Test name
Test status
Simulation time 31933480 ps
CPU time 0.86 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201112 kb
Host smart-1796b98e-881a-45a7-ab38-7cc71cea6a29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200610662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.2200610662
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.99517079
Short name T153
Test name
Test status
Simulation time 35645917 ps
CPU time 0.78 seconds
Started Aug 01 06:49:14 PM PDT 24
Finished Aug 01 06:49:15 PM PDT 24
Peak memory 200940 kb
Host smart-5b2f2ffc-9a28-4857-82e3-26a6090e01f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99517079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.99517079
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.287092958
Short name T261
Test name
Test status
Simulation time 62042462 ps
CPU time 0.94 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201056 kb
Host smart-3365e23d-fcd4-4f0d-99d1-adb542ed922d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287092958 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.287092958
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1502665063
Short name T671
Test name
Test status
Simulation time 24299448 ps
CPU time 0.86 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201100 kb
Host smart-ee89b6ba-5a2d-4b94-9977-4932c4811418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502665063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1502665063
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2465713670
Short name T228
Test name
Test status
Simulation time 1412070826 ps
CPU time 8.33 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:16 PM PDT 24
Peak memory 201092 kb
Host smart-8a632c07-ca49-4f03-9829-f6acb0870891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465713670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2465713670
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.3357410572
Short name T415
Test name
Test status
Simulation time 500399870 ps
CPU time 4.46 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:11 PM PDT 24
Peak memory 201244 kb
Host smart-e384e6c2-6905-43a1-ba44-678e26ac57a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357410572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.3357410572
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3402217354
Short name T754
Test name
Test status
Simulation time 679961649 ps
CPU time 2.92 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201064 kb
Host smart-a14245e0-50a5-4578-a739-5ed0aed70e96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402217354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.3402217354
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.3024075328
Short name T171
Test name
Test status
Simulation time 23351083 ps
CPU time 0.85 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201052 kb
Host smart-ca6be803-2757-43c7-8099-9cad4823c716
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024075328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.3024075328
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1573594643
Short name T715
Test name
Test status
Simulation time 70086262 ps
CPU time 0.95 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201048 kb
Host smart-64a3d559-8430-42c5-9348-56714de37330
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573594643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.1573594643
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.912566728
Short name T449
Test name
Test status
Simulation time 24285911 ps
CPU time 0.8 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201048 kb
Host smart-5c34cb3c-303f-4df3-8a14-f2e463356f4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912566728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.912566728
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1254711287
Short name T74
Test name
Test status
Simulation time 1592810379 ps
CPU time 4.97 seconds
Started Aug 01 06:49:12 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201236 kb
Host smart-dbe3b9bc-972c-4164-868b-a859d35186d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254711287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1254711287
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.2898782227
Short name T53
Test name
Test status
Simulation time 565400810 ps
CPU time 3.23 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 216540 kb
Host smart-3803c4b3-a5b2-4ccb-a6ab-7494b7b298ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898782227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.2898782227
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3919484931
Short name T260
Test name
Test status
Simulation time 113449027 ps
CPU time 1.11 seconds
Started Aug 01 06:49:10 PM PDT 24
Finished Aug 01 06:49:11 PM PDT 24
Peak memory 200928 kb
Host smart-c8011d42-c10d-4f9f-a56a-af8a3e4a129c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919484931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3919484931
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2960802946
Short name T642
Test name
Test status
Simulation time 1926992569 ps
CPU time 15.84 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:27 PM PDT 24
Peak memory 201188 kb
Host smart-bb60d588-f752-4f9c-b845-bc9f1c78b2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960802946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2960802946
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.1412317830
Short name T687
Test name
Test status
Simulation time 22333355 ps
CPU time 0.73 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201032 kb
Host smart-97828e83-fb75-4da8-9289-715569c08c7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412317830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1412317830
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3617361245
Short name T280
Test name
Test status
Simulation time 20093868 ps
CPU time 0.76 seconds
Started Aug 01 06:49:57 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 201052 kb
Host smart-14800e5e-d4c7-46a3-b4db-728e3840c6a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617361245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3617361245
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3358556482
Short name T759
Test name
Test status
Simulation time 17636719 ps
CPU time 0.82 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:49:52 PM PDT 24
Peak memory 201084 kb
Host smart-95b2d3dc-9696-45f7-a329-63c926c640ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358556482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.3358556482
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.2740348746
Short name T323
Test name
Test status
Simulation time 14379990 ps
CPU time 0.7 seconds
Started Aug 01 06:49:49 PM PDT 24
Finished Aug 01 06:49:50 PM PDT 24
Peak memory 201016 kb
Host smart-d43b141d-d98c-4667-90f4-73439673ca57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740348746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.2740348746
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.1556034522
Short name T709
Test name
Test status
Simulation time 132686025 ps
CPU time 1.16 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201088 kb
Host smart-b0f3f5d0-832a-48e6-b6ce-882adb75696e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556034522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.1556034522
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.273069076
Short name T797
Test name
Test status
Simulation time 24049404 ps
CPU time 0.85 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 200984 kb
Host smart-1b2f9faf-2671-4f06-8b86-2bc9aff9ba08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273069076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.273069076
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1011520606
Short name T355
Test name
Test status
Simulation time 1774574940 ps
CPU time 8.57 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:50:00 PM PDT 24
Peak memory 201096 kb
Host smart-44a5b57f-cc77-4d24-80ae-5b7f429e91a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011520606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1011520606
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.2324575473
Short name T452
Test name
Test status
Simulation time 2060541363 ps
CPU time 15.12 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201340 kb
Host smart-ee859a5d-57fb-4afa-85f4-f244264cc979
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324575473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.2324575473
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.941108179
Short name T403
Test name
Test status
Simulation time 30733902 ps
CPU time 0.94 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201128 kb
Host smart-b64bbbf2-bd05-47fa-b327-d1220279ed9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941108179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.941108179
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2351242256
Short name T174
Test name
Test status
Simulation time 50759443 ps
CPU time 0.89 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:44 PM PDT 24
Peak memory 201092 kb
Host smart-b63ebc32-4a63-460b-84a8-15b6501a5390
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351242256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2351242256
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3010588232
Short name T321
Test name
Test status
Simulation time 14978177 ps
CPU time 0.76 seconds
Started Aug 01 06:49:42 PM PDT 24
Finished Aug 01 06:49:43 PM PDT 24
Peak memory 201080 kb
Host smart-bb57e48b-b697-4b64-a644-96e4bab451c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010588232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3010588232
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.318499921
Short name T657
Test name
Test status
Simulation time 68323801 ps
CPU time 0.92 seconds
Started Aug 01 06:49:44 PM PDT 24
Finished Aug 01 06:49:45 PM PDT 24
Peak memory 201096 kb
Host smart-bdeba84f-35da-4b82-a198-459a34bb36d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318499921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.318499921
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.2021387433
Short name T144
Test name
Test status
Simulation time 1403633712 ps
CPU time 8.16 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:58 PM PDT 24
Peak memory 201280 kb
Host smart-b7ec9866-486d-4e90-8745-0ce6accebacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021387433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2021387433
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.906148655
Short name T133
Test name
Test status
Simulation time 25752366 ps
CPU time 0.86 seconds
Started Aug 01 06:49:41 PM PDT 24
Finished Aug 01 06:49:42 PM PDT 24
Peak memory 201096 kb
Host smart-43258581-9faa-468d-b4bd-b28a26223d5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906148655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.906148655
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1287918367
Short name T549
Test name
Test status
Simulation time 14658113213 ps
CPU time 79.05 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:51:09 PM PDT 24
Peak memory 201456 kb
Host smart-58d42347-12c7-41e5-bf66-502db0a438a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287918367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1287918367
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.678821702
Short name T67
Test name
Test status
Simulation time 262336165873 ps
CPU time 1305.81 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 07:11:36 PM PDT 24
Peak memory 214712 kb
Host smart-fa370b7f-7e31-4962-b612-ce411cadb32d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=678821702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.678821702
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2367857698
Short name T344
Test name
Test status
Simulation time 172001721 ps
CPU time 1.33 seconds
Started Aug 01 06:49:43 PM PDT 24
Finished Aug 01 06:49:45 PM PDT 24
Peak memory 201128 kb
Host smart-2841c65c-8be9-4365-9195-421d7fcd4bed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367857698 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2367857698
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.791722296
Short name T35
Test name
Test status
Simulation time 15366529 ps
CPU time 0.81 seconds
Started Aug 01 06:49:56 PM PDT 24
Finished Aug 01 06:49:57 PM PDT 24
Peak memory 201060 kb
Host smart-a3845233-3686-4110-9b2b-01cfab8a85ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791722296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.791722296
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.3275446647
Short name T444
Test name
Test status
Simulation time 49544854 ps
CPU time 0.99 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 201052 kb
Host smart-c4518963-9830-4851-b6b9-b5e77ca209c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275446647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.3275446647
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.2640799833
Short name T781
Test name
Test status
Simulation time 24965869 ps
CPU time 0.73 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:49:52 PM PDT 24
Peak memory 200316 kb
Host smart-ce43f1b4-1cf3-4cf9-8fc6-af677a223d3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640799833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2640799833
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.2155425228
Short name T259
Test name
Test status
Simulation time 61850565 ps
CPU time 0.91 seconds
Started Aug 01 06:49:57 PM PDT 24
Finished Aug 01 06:49:59 PM PDT 24
Peak memory 201052 kb
Host smart-14dc366f-4b7c-4a64-a1be-8414e5519e0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155425228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.2155425228
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.443742167
Short name T28
Test name
Test status
Simulation time 17547713 ps
CPU time 0.81 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201060 kb
Host smart-0d7ae2da-fd2f-4486-bcca-38b6a0f6ba49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443742167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.443742167
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.1966041695
Short name T606
Test name
Test status
Simulation time 2355291571 ps
CPU time 18.34 seconds
Started Aug 01 06:49:59 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 201388 kb
Host smart-200984e2-3dbf-409a-9d44-830170a9fdfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966041695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.1966041695
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3630591306
Short name T718
Test name
Test status
Simulation time 1224562178 ps
CPU time 6.72 seconds
Started Aug 01 06:49:55 PM PDT 24
Finished Aug 01 06:50:02 PM PDT 24
Peak memory 201152 kb
Host smart-32e89d77-878f-4e42-b55d-c8751cf5786f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630591306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3630591306
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.291149696
Short name T227
Test name
Test status
Simulation time 32686606 ps
CPU time 0.9 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 200984 kb
Host smart-170121d7-6560-41bb-8bbd-da0accecd6d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291149696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.291149696
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2548484164
Short name T779
Test name
Test status
Simulation time 33220660 ps
CPU time 0.91 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 201048 kb
Host smart-fa32c17a-34ec-45cb-9c22-dd1d5835459d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548484164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2548484164
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1608694017
Short name T816
Test name
Test status
Simulation time 72520011 ps
CPU time 0.96 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 201100 kb
Host smart-74465c22-b78e-4b3a-b507-a57442fa58fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608694017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.1608694017
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.4269384633
Short name T454
Test name
Test status
Simulation time 15700554 ps
CPU time 0.7 seconds
Started Aug 01 06:49:48 PM PDT 24
Finished Aug 01 06:49:49 PM PDT 24
Peak memory 201024 kb
Host smart-ea926c71-f9a0-4b0c-9c9f-200624f6247a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269384633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.4269384633
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.4030779185
Short name T827
Test name
Test status
Simulation time 807177729 ps
CPU time 4.92 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:58 PM PDT 24
Peak memory 201288 kb
Host smart-458185d0-44eb-454a-82ab-9bae0e5a0a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030779185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.4030779185
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.2047483350
Short name T31
Test name
Test status
Simulation time 59089602 ps
CPU time 0.97 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:49:52 PM PDT 24
Peak memory 201056 kb
Host smart-d89ff14f-e859-40d9-a102-238c34cc8b08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047483350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2047483350
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.533883507
Short name T750
Test name
Test status
Simulation time 5511852556 ps
CPU time 25.03 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 201456 kb
Host smart-1bbd7ce2-b876-4fdb-8043-bfe5b3eebddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533883507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.533883507
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.3874381400
Short name T11
Test name
Test status
Simulation time 24925926011 ps
CPU time 272.04 seconds
Started Aug 01 06:49:56 PM PDT 24
Finished Aug 01 06:54:29 PM PDT 24
Peak memory 209712 kb
Host smart-5d6c2f1f-daca-4a57-aeec-efa37bdb5820
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3874381400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.3874381400
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.4284556362
Short name T740
Test name
Test status
Simulation time 69812995 ps
CPU time 0.99 seconds
Started Aug 01 06:49:55 PM PDT 24
Finished Aug 01 06:49:56 PM PDT 24
Peak memory 201092 kb
Host smart-b0f62ed0-95b9-4f46-beea-6d2e2d37a162
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284556362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.4284556362
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.2293005858
Short name T724
Test name
Test status
Simulation time 27408022 ps
CPU time 0.77 seconds
Started Aug 01 06:49:54 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201100 kb
Host smart-781e7c54-3bf3-4a72-9b65-9396ef3fef95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293005858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.2293005858
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.92195037
Short name T92
Test name
Test status
Simulation time 66333131 ps
CPU time 1.01 seconds
Started Aug 01 06:49:59 PM PDT 24
Finished Aug 01 06:50:00 PM PDT 24
Peak memory 201036 kb
Host smart-db4560d6-7260-490b-a5dd-1474d111f6ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92195037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_clk_handshake_intersig_mubi.92195037
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.1577562656
Short name T804
Test name
Test status
Simulation time 42895521 ps
CPU time 0.83 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 200932 kb
Host smart-7c6c21b3-4cbc-43d7-8930-07240a76fd8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577562656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.1577562656
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.1485074140
Short name T425
Test name
Test status
Simulation time 17835632 ps
CPU time 0.78 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201108 kb
Host smart-259e7510-2474-418c-9883-97dccbe7589d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485074140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.1485074140
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.2728639136
Short name T785
Test name
Test status
Simulation time 36518640 ps
CPU time 0.86 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 200984 kb
Host smart-8d4fb520-f10d-4dcb-9a5a-bf6b980e3104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728639136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2728639136
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.849633431
Short name T545
Test name
Test status
Simulation time 1755642391 ps
CPU time 14.22 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201316 kb
Host smart-9fa7db42-5ede-4fdc-ba00-5258cdef9e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849633431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.849633431
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.3334659553
Short name T204
Test name
Test status
Simulation time 1099779350 ps
CPU time 8.25 seconds
Started Aug 01 06:49:57 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201148 kb
Host smart-73d49a17-1b0b-4a0d-be28-16cceb35f363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334659553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_t
imeout.3334659553
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2641318790
Short name T166
Test name
Test status
Simulation time 96352694 ps
CPU time 1.09 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 200308 kb
Host smart-c27b4484-bb4d-4825-ac62-493c15ddc9e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641318790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.2641318790
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.3564486631
Short name T557
Test name
Test status
Simulation time 28436917 ps
CPU time 0.9 seconds
Started Aug 01 06:49:54 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201088 kb
Host smart-e705895e-2cfd-48b9-898a-fce9ef1a0294
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564486631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.3564486631
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3614375112
Short name T768
Test name
Test status
Simulation time 15191247 ps
CPU time 0.74 seconds
Started Aug 01 06:49:55 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201072 kb
Host smart-37a70bb9-db0d-41b6-a590-d9c2ff3d0646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614375112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3614375112
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.4262499553
Short name T455
Test name
Test status
Simulation time 43716845 ps
CPU time 0.91 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 201076 kb
Host smart-0627c23a-cb06-44cb-87f1-fe89cc63ae7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262499553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.4262499553
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.4281660463
Short name T742
Test name
Test status
Simulation time 1802268194 ps
CPU time 7.21 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:50:00 PM PDT 24
Peak memory 201192 kb
Host smart-0ec4ebae-e3dd-4803-8ef1-17647661a38a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281660463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.4281660463
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3794947317
Short name T522
Test name
Test status
Simulation time 114046648 ps
CPU time 1.28 seconds
Started Aug 01 06:49:50 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201124 kb
Host smart-841538a9-07b2-4813-851d-421cb9c435bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794947317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3794947317
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.2039466517
Short name T694
Test name
Test status
Simulation time 16672458 ps
CPU time 0.74 seconds
Started Aug 01 06:50:09 PM PDT 24
Finished Aug 01 06:50:10 PM PDT 24
Peak memory 201076 kb
Host smart-b75619ee-63f2-4a8e-bee6-029f573a7ecd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039466517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.2039466517
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1470017323
Short name T216
Test name
Test status
Simulation time 19685676 ps
CPU time 0.8 seconds
Started Aug 01 06:49:53 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 201056 kb
Host smart-c959d3a0-521b-456e-843d-54425af5c4aa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470017323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.1470017323
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3876669495
Short name T570
Test name
Test status
Simulation time 15560645 ps
CPU time 0.73 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 200340 kb
Host smart-f23f651c-ff90-4fd4-9029-09d1ae2d709b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876669495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3876669495
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.3674131514
Short name T659
Test name
Test status
Simulation time 30213481 ps
CPU time 0.91 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:49:52 PM PDT 24
Peak memory 201072 kb
Host smart-fcda964f-89e5-4bd9-818c-32ee13c43181
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674131514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.3674131514
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.495588960
Short name T307
Test name
Test status
Simulation time 26674514 ps
CPU time 0.79 seconds
Started Aug 01 06:49:54 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201108 kb
Host smart-d4e91f69-c0b1-44fe-9c5d-385fd148d0b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495588960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.495588960
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.143801610
Short name T301
Test name
Test status
Simulation time 1160151116 ps
CPU time 9.31 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:50:02 PM PDT 24
Peak memory 201128 kb
Host smart-e921bdcd-0311-4828-9bfe-29be7e21f869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143801610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.143801610
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.4082661467
Short name T575
Test name
Test status
Simulation time 975231537 ps
CPU time 7.52 seconds
Started Aug 01 06:49:59 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201144 kb
Host smart-1c3449e0-4a88-4f43-a073-999a2f438df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082661467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.4082661467
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.4190493150
Short name T574
Test name
Test status
Simulation time 15637579 ps
CPU time 0.78 seconds
Started Aug 01 06:49:58 PM PDT 24
Finished Aug 01 06:49:59 PM PDT 24
Peak memory 201056 kb
Host smart-e3c4e44e-8380-4610-9ad9-6ae615a61e17
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190493150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.4190493150
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1830077180
Short name T619
Test name
Test status
Simulation time 17144506 ps
CPU time 0.8 seconds
Started Aug 01 06:49:55 PM PDT 24
Finished Aug 01 06:49:56 PM PDT 24
Peak memory 201084 kb
Host smart-51df8413-b9c0-4436-8dc4-3801f55dff54
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830077180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1830077180
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.2783544431
Short name T626
Test name
Test status
Simulation time 122808052 ps
CPU time 1.03 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 200260 kb
Host smart-4cc2165a-3e2f-4569-a4cd-c79f8a21b83d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783544431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.2783544431
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.292388618
Short name T581
Test name
Test status
Simulation time 49885691 ps
CPU time 0.9 seconds
Started Aug 01 06:49:49 PM PDT 24
Finished Aug 01 06:49:50 PM PDT 24
Peak memory 201052 kb
Host smart-675b5910-7841-4846-8689-643d8b33a170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292388618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.292388618
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.3042127728
Short name T578
Test name
Test status
Simulation time 775014274 ps
CPU time 3.38 seconds
Started Aug 01 06:49:51 PM PDT 24
Finished Aug 01 06:49:55 PM PDT 24
Peak memory 201252 kb
Host smart-1f54fcb4-bb3a-4caa-b712-3223fe9f44da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042127728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3042127728
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2426281836
Short name T456
Test name
Test status
Simulation time 23079724 ps
CPU time 0.88 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:53 PM PDT 24
Peak memory 200932 kb
Host smart-efa28a7a-b952-4dc2-9bf1-e46ef6275b8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426281836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2426281836
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.1410818273
Short name T625
Test name
Test status
Simulation time 4548995680 ps
CPU time 25.16 seconds
Started Aug 01 06:49:54 PM PDT 24
Finished Aug 01 06:50:19 PM PDT 24
Peak memory 201396 kb
Host smart-91af05e2-012c-4386-bca6-c790d4b68e63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410818273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.1410818273
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all_with_rand_reset.2208748557
Short name T517
Test name
Test status
Simulation time 50402816375 ps
CPU time 507.65 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:58:20 PM PDT 24
Peak memory 217964 kb
Host smart-50575a25-ea05-4058-a518-1102158438cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2208748557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.2208748557
Directory /workspace/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2612404177
Short name T173
Test name
Test status
Simulation time 29148029 ps
CPU time 1.01 seconds
Started Aug 01 06:49:52 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 201032 kb
Host smart-07c3b5a1-3e9c-45ce-93ed-979c54223dad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612404177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2612404177
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.2459092743
Short name T367
Test name
Test status
Simulation time 22075041 ps
CPU time 0.76 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201020 kb
Host smart-644a82f9-e284-4589-a430-61be43bc1e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459092743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.2459092743
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3023291673
Short name T592
Test name
Test status
Simulation time 66247852 ps
CPU time 0.99 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201012 kb
Host smart-a8853b4a-0c5c-4775-bd72-d8fb531c51fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023291673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3023291673
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2668813181
Short name T152
Test name
Test status
Simulation time 16011026 ps
CPU time 0.79 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 200212 kb
Host smart-5cd5e440-9d4e-40b6-b1a5-32e0d3d2f70f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668813181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2668813181
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.2902081337
Short name T178
Test name
Test status
Simulation time 43473788 ps
CPU time 0.93 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201068 kb
Host smart-28f3328d-3681-42f5-a045-a66b948f99ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902081337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.2902081337
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.784835577
Short name T650
Test name
Test status
Simulation time 39707672 ps
CPU time 0.92 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201076 kb
Host smart-33b0349b-85c9-4a06-a756-02295e7bc27e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784835577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.784835577
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3578732232
Short name T432
Test name
Test status
Simulation time 1519742084 ps
CPU time 12.45 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:16 PM PDT 24
Peak memory 201160 kb
Host smart-fb7ef993-01a3-4c2b-86f8-4ff7c54aabb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578732232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3578732232
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.2361107626
Short name T527
Test name
Test status
Simulation time 858073655 ps
CPU time 6.56 seconds
Started Aug 01 06:50:01 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201136 kb
Host smart-e58b749b-9fe6-4503-98b4-745874259d49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361107626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.2361107626
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3937515262
Short name T244
Test name
Test status
Simulation time 71113037 ps
CPU time 1.09 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201156 kb
Host smart-78be3f6f-bcf0-4187-995d-062d25e849d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937515262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3937515262
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1519830847
Short name T45
Test name
Test status
Simulation time 17839423 ps
CPU time 0.83 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201064 kb
Host smart-a0c55471-2b85-4e2b-8f67-0d8bb4be4528
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519830847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1519830847
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.156325450
Short name T255
Test name
Test status
Simulation time 41801184 ps
CPU time 0.85 seconds
Started Aug 01 06:50:00 PM PDT 24
Finished Aug 01 06:50:01 PM PDT 24
Peak memory 201032 kb
Host smart-808c6b70-af88-4ebe-9c81-fe689eefb7d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156325450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 24.clkmgr_lc_ctrl_intersig_mubi.156325450
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.3935551041
Short name T240
Test name
Test status
Simulation time 14974942 ps
CPU time 0.72 seconds
Started Aug 01 06:50:02 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201020 kb
Host smart-31e14739-6027-4498-bb00-a4ef70343f61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935551041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3935551041
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3798101400
Short name T143
Test name
Test status
Simulation time 1449258516 ps
CPU time 6.54 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:10 PM PDT 24
Peak memory 201216 kb
Host smart-b71849af-855c-4f39-ae00-054c0c3e92ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798101400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3798101400
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.3515731210
Short name T512
Test name
Test status
Simulation time 19840249 ps
CPU time 0.84 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201028 kb
Host smart-4612637a-a273-4245-b4f2-bde94d8e46a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515731210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.3515731210
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2744645709
Short name T136
Test name
Test status
Simulation time 5839049183 ps
CPU time 23.5 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 201492 kb
Host smart-bae1b41d-d7f7-4330-9749-e6915b200180
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744645709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2744645709
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.762778357
Short name T480
Test name
Test status
Simulation time 29455680 ps
CPU time 0.8 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:04 PM PDT 24
Peak memory 201080 kb
Host smart-13376e88-0dd0-4c0f-8841-823cba6857a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762778357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.762778357
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.1231739125
Short name T576
Test name
Test status
Simulation time 42499944 ps
CPU time 0.85 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201004 kb
Host smart-8491b433-1723-40c3-b503-d2eb7cb0f245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231739125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.1231739125
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.2770477468
Short name T87
Test name
Test status
Simulation time 16425082 ps
CPU time 0.77 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201080 kb
Host smart-9b42404d-e136-48b5-84c7-16c18c01be6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770477468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.2770477468
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.709511966
Short name T543
Test name
Test status
Simulation time 17465507 ps
CPU time 0.7 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 200272 kb
Host smart-3c83c2db-5a6f-4863-984e-ae793e837de8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709511966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.709511966
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.259002933
Short name T391
Test name
Test status
Simulation time 99452007 ps
CPU time 1.08 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201080 kb
Host smart-d2de30ae-351f-49d1-b7ba-a36962d11cb0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259002933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.259002933
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.1845388510
Short name T741
Test name
Test status
Simulation time 44897216 ps
CPU time 0.83 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:04 PM PDT 24
Peak memory 201040 kb
Host smart-cf0ca49a-b527-4ef5-b2af-9af4c8803e40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845388510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.1845388510
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.856271261
Short name T33
Test name
Test status
Simulation time 568096052 ps
CPU time 3.68 seconds
Started Aug 01 06:50:01 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201112 kb
Host smart-3ae9b2f8-1a1e-49ea-9e0d-d97993af94d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856271261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.856271261
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.3981157416
Short name T793
Test name
Test status
Simulation time 2302470141 ps
CPU time 16.31 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:20 PM PDT 24
Peak memory 201428 kb
Host smart-dd4404ef-d8af-4501-b74f-69153f0e75c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981157416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.3981157416
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.109013184
Short name T399
Test name
Test status
Simulation time 28690833 ps
CPU time 1 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201020 kb
Host smart-2287d0a9-e01d-41b9-94f7-5b9ef0dce6bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109013184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_idle_intersig_mubi.109013184
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.2057447836
Short name T713
Test name
Test status
Simulation time 113370714 ps
CPU time 1.09 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201080 kb
Host smart-2ad5474d-95da-4857-8b82-289411368dcc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057447836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.2057447836
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2187336339
Short name T194
Test name
Test status
Simulation time 33418377 ps
CPU time 0.83 seconds
Started Aug 01 06:50:02 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201084 kb
Host smart-4d75ea68-069b-4355-b84b-b5642af8b5f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187336339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2187336339
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.2643917592
Short name T774
Test name
Test status
Simulation time 17622530 ps
CPU time 0.85 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:04 PM PDT 24
Peak memory 200856 kb
Host smart-8155e6fe-e1c7-4839-9c1c-75c3c3d318a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643917592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.2643917592
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.4145311823
Short name T705
Test name
Test status
Simulation time 440777409 ps
CPU time 2.38 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201060 kb
Host smart-7ae1d32a-ca57-4196-9011-7d3aaa714eb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145311823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.4145311823
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2901354808
Short name T536
Test name
Test status
Simulation time 229757283 ps
CPU time 1.49 seconds
Started Aug 01 06:50:01 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201044 kb
Host smart-0b14a36f-d3bd-4da6-a780-d0df6897271f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901354808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2901354808
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.673918415
Short name T698
Test name
Test status
Simulation time 4963552930 ps
CPU time 38.76 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201652 kb
Host smart-e895c645-cd00-437b-8bf6-eb08c6fd6a14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673918415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.673918415
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.2077784149
Short name T234
Test name
Test status
Simulation time 117966254 ps
CPU time 1.26 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:04 PM PDT 24
Peak memory 201028 kb
Host smart-d3a8155d-4e6e-49a3-89e0-75b9c1416c07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077784149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2077784149
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.2365590707
Short name T184
Test name
Test status
Simulation time 16126238 ps
CPU time 0.78 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 201060 kb
Host smart-32d79f75-d304-4a44-a37b-e1780a986d3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365590707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.2365590707
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.550332134
Short name T737
Test name
Test status
Simulation time 16203168 ps
CPU time 0.79 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201060 kb
Host smart-d9d4a30d-fbed-4356-8560-742904f84d81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550332134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.550332134
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.3015001897
Short name T52
Test name
Test status
Simulation time 148910740 ps
CPU time 1.09 seconds
Started Aug 01 06:50:08 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 200260 kb
Host smart-afa0675d-a66f-43f0-8e24-59bdd048e679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015001897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3015001897
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.1025937064
Short name T680
Test name
Test status
Simulation time 31647743 ps
CPU time 0.87 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201032 kb
Host smart-5a51703c-0a5a-4687-b9fe-10f749939652
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025937064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.1025937064
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.393853049
Short name T690
Test name
Test status
Simulation time 53516220 ps
CPU time 0.93 seconds
Started Aug 01 06:50:02 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201092 kb
Host smart-58362ac0-34a6-4f47-8dcc-f81d87285ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393853049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.393853049
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.2040718681
Short name T279
Test name
Test status
Simulation time 2486595710 ps
CPU time 13.51 seconds
Started Aug 01 06:50:08 PM PDT 24
Finished Aug 01 06:50:22 PM PDT 24
Peak memory 201352 kb
Host smart-06113ee2-09b2-4362-8a3b-c1d720edac4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040718681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.2040718681
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.3753505226
Short name T339
Test name
Test status
Simulation time 1962799671 ps
CPU time 7.96 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201188 kb
Host smart-2d76f3b3-2104-488d-9146-9a64c452ed8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753505226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.3753505226
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.3670993751
Short name T276
Test name
Test status
Simulation time 110038622 ps
CPU time 1.27 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201040 kb
Host smart-f5459e4d-ead4-48f0-8307-52eef8014699
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670993751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.3670993751
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3970737491
Short name T492
Test name
Test status
Simulation time 26579980 ps
CPU time 0.81 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201124 kb
Host smart-e1eac4a8-bd0c-4838-a4ac-c5d40bbbedf9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970737491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3970737491
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1857392535
Short name T801
Test name
Test status
Simulation time 51566138 ps
CPU time 0.87 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201064 kb
Host smart-b69927d1-9964-4774-899e-f57e3c075c63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857392535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1857392535
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.3887707945
Short name T236
Test name
Test status
Simulation time 16580108 ps
CPU time 0.7 seconds
Started Aug 01 06:50:02 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201052 kb
Host smart-0044c68f-c9fe-411c-8c2d-aab9edac013a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887707945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3887707945
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.2039699571
Short name T772
Test name
Test status
Simulation time 79793877 ps
CPU time 0.93 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201024 kb
Host smart-b472b185-fac2-43b2-8147-df0dc7180ce7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039699571 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.2039699571
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.3907175564
Short name T484
Test name
Test status
Simulation time 57027791 ps
CPU time 1.01 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201128 kb
Host smart-c9ddfa0c-ca9c-4290-9faf-4d6ea8a77361
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907175564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3907175564
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.3805859754
Short name T382
Test name
Test status
Simulation time 298814649 ps
CPU time 2.2 seconds
Started Aug 01 06:50:03 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201288 kb
Host smart-ff6b7582-23da-494d-b1ea-d26a65a10024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805859754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.3805859754
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1071158195
Short name T799
Test name
Test status
Simulation time 44014007 ps
CPU time 0.95 seconds
Started Aug 01 06:50:15 PM PDT 24
Finished Aug 01 06:50:16 PM PDT 24
Peak memory 201080 kb
Host smart-2c4f30f6-f4b6-43cc-bfc7-8a949a0519da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071158195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1071158195
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.2548443466
Short name T813
Test name
Test status
Simulation time 49360287 ps
CPU time 0.89 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201068 kb
Host smart-1c5c97b7-d5f1-425a-9049-2102d410e2bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548443466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.2548443466
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.1743908700
Short name T620
Test name
Test status
Simulation time 24135128 ps
CPU time 0.88 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201084 kb
Host smart-afb8aea6-e477-422f-b3d6-610f15c5764d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743908700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.1743908700
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1085567545
Short name T743
Test name
Test status
Simulation time 12820942 ps
CPU time 0.72 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 200888 kb
Host smart-783cba6a-53b8-4db3-a13c-79d906a05890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085567545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1085567545
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3687977341
Short name T72
Test name
Test status
Simulation time 41211344 ps
CPU time 0.86 seconds
Started Aug 01 06:50:10 PM PDT 24
Finished Aug 01 06:50:11 PM PDT 24
Peak memory 201040 kb
Host smart-9a7eda46-75d5-4684-928f-c0872fb64538
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687977341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3687977341
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.1237347993
Short name T257
Test name
Test status
Simulation time 92276650 ps
CPU time 1.02 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201020 kb
Host smart-8cbcca91-68aa-46a2-b591-d00442431796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237347993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1237347993
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1665453622
Short name T776
Test name
Test status
Simulation time 1997791152 ps
CPU time 15.56 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201272 kb
Host smart-8846e1b3-73f1-4320-ba19-33f902f924f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665453622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1665453622
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.2538091331
Short name T582
Test name
Test status
Simulation time 258705764 ps
CPU time 2.33 seconds
Started Aug 01 06:50:09 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201184 kb
Host smart-f8ac4c1e-755f-44b8-9cd2-538e8845a3b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538091331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.2538091331
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.148764387
Short name T667
Test name
Test status
Simulation time 122947387 ps
CPU time 1.32 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201052 kb
Host smart-38c2ab9b-9b76-411d-a4f7-8bebc5e95b84
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148764387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_idle_intersig_mubi.148764387
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.213286911
Short name T726
Test name
Test status
Simulation time 43714865 ps
CPU time 0.98 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201076 kb
Host smart-4aa23d92-61c2-4a87-a404-b23645664b3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213286911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_clk_byp_req_intersig_mubi.213286911
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2145028896
Short name T722
Test name
Test status
Simulation time 36156690 ps
CPU time 0.9 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:05 PM PDT 24
Peak memory 201072 kb
Host smart-6f5dd536-dde5-47fe-a131-0853d3a8146c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145028896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2145028896
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.459553570
Short name T341
Test name
Test status
Simulation time 52289197 ps
CPU time 0.88 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201092 kb
Host smart-bb237ed9-fe7f-47e1-992e-0a290c1930f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459553570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.459553570
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1872282142
Short name T782
Test name
Test status
Simulation time 1156885877 ps
CPU time 4.04 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 201272 kb
Host smart-e98f4921-dfaa-4784-a95c-9583f438deca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872282142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1872282142
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.3759176248
Short name T27
Test name
Test status
Simulation time 43368431 ps
CPU time 0.87 seconds
Started Aug 01 06:50:10 PM PDT 24
Finished Aug 01 06:50:11 PM PDT 24
Peak memory 201076 kb
Host smart-ae317991-bee3-469d-ae10-1adfc79af81c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759176248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.3759176248
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_trans.1806677022
Short name T5
Test name
Test status
Simulation time 45076536 ps
CPU time 1.05 seconds
Started Aug 01 06:50:09 PM PDT 24
Finished Aug 01 06:50:10 PM PDT 24
Peak memory 201064 kb
Host smart-f0d70341-21a8-43cd-9f38-4136249de13a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806677022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1806677022
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.232919169
Short name T770
Test name
Test status
Simulation time 68895966 ps
CPU time 0.98 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:06 PM PDT 24
Peak memory 201032 kb
Host smart-135b0ca0-fce3-4396-8953-a055b1c1649e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232919169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.232919169
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.1595420115
Short name T408
Test name
Test status
Simulation time 61451404 ps
CPU time 1.07 seconds
Started Aug 01 06:50:09 PM PDT 24
Finished Aug 01 06:50:11 PM PDT 24
Peak memory 201068 kb
Host smart-2fb8342e-f6e1-4cee-b372-6e1833728f47
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595420115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.1595420115
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.2804239805
Short name T34
Test name
Test status
Simulation time 58316433 ps
CPU time 0.86 seconds
Started Aug 01 06:50:13 PM PDT 24
Finished Aug 01 06:50:14 PM PDT 24
Peak memory 200308 kb
Host smart-f6e7d29c-38fd-4600-aa0c-2cb9a46c4e46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804239805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2804239805
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.3209640145
Short name T112
Test name
Test status
Simulation time 42726102 ps
CPU time 0.86 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201072 kb
Host smart-e6de7058-d060-4fe5-ad48-f12cfc8ddb42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209640145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.3209640145
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.4171357114
Short name T482
Test name
Test status
Simulation time 88302902 ps
CPU time 1.21 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201008 kb
Host smart-71d14e74-22e0-4704-8d55-a4afb6ce028f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171357114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.4171357114
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.656928833
Short name T12
Test name
Test status
Simulation time 2356579774 ps
CPU time 18.64 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 201424 kb
Host smart-2fc52ab1-5f28-4a24-a2d5-a3ab2f95efa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656928833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.656928833
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.1032280791
Short name T293
Test name
Test status
Simulation time 408261027 ps
CPU time 2.15 seconds
Started Aug 01 06:50:13 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201244 kb
Host smart-3767019c-982f-4127-9635-7e55c0c6a101
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032280791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.1032280791
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.4168725029
Short name T534
Test name
Test status
Simulation time 43871393 ps
CPU time 0.81 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201044 kb
Host smart-31b5d0e2-04f8-4bcc-912f-dac4472d3485
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168725029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.4168725029
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.3319170824
Short name T411
Test name
Test status
Simulation time 17389783 ps
CPU time 0.78 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 200848 kb
Host smart-ca3d80f9-7466-47e4-9849-1bb0c11da7b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319170824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.3319170824
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4006718772
Short name T180
Test name
Test status
Simulation time 39003988 ps
CPU time 0.84 seconds
Started Aug 01 06:50:09 PM PDT 24
Finished Aug 01 06:50:10 PM PDT 24
Peak memory 201068 kb
Host smart-0e2ef28e-058c-4d61-ac50-0eff07143018
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006718772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.4006718772
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.3713372380
Short name T601
Test name
Test status
Simulation time 23411945 ps
CPU time 0.79 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201032 kb
Host smart-eb90f0ce-68ff-4463-8a14-9e022f5fb85e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713372380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.3713372380
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.238829953
Short name T346
Test name
Test status
Simulation time 206424259 ps
CPU time 1.39 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201108 kb
Host smart-d08be989-4f8e-42c8-9ca4-bc201f2ac895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238829953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.238829953
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.1249640616
Short name T806
Test name
Test status
Simulation time 24026449 ps
CPU time 0.92 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201116 kb
Host smart-99f989f4-9adb-46ed-a255-14d3eb88fc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249640616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.1249640616
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.1903124447
Short name T621
Test name
Test status
Simulation time 2853264496 ps
CPU time 15.95 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:23 PM PDT 24
Peak memory 201440 kb
Host smart-4f1464a7-b2c1-48ad-b844-a530cf6c6071
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903124447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.1903124447
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.2221433911
Short name T520
Test name
Test status
Simulation time 70662915 ps
CPU time 1.03 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201008 kb
Host smart-f7b98668-80bb-47bd-81ac-fef1826797b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221433911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.2221433911
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3419758147
Short name T176
Test name
Test status
Simulation time 14200999 ps
CPU time 0.72 seconds
Started Aug 01 06:50:18 PM PDT 24
Finished Aug 01 06:50:18 PM PDT 24
Peak memory 201048 kb
Host smart-8228415e-7cf5-48b4-92b8-71180d886723
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419758147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3419758147
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2202573812
Short name T447
Test name
Test status
Simulation time 54229648 ps
CPU time 0.89 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201072 kb
Host smart-2ede77f8-8ea8-49b1-b3be-077521c7a72e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202573812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.2202573812
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.3241481578
Short name T530
Test name
Test status
Simulation time 12970186 ps
CPU time 0.75 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 200260 kb
Host smart-eeb0c4ae-9394-4196-aba6-0f15d438ebc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241481578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.3241481578
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.415776592
Short name T297
Test name
Test status
Simulation time 21832233 ps
CPU time 0.77 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201064 kb
Host smart-5beee370-abc4-4f22-87b8-58622b0c3390
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415776592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_div_intersig_mubi.415776592
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.3496711308
Short name T208
Test name
Test status
Simulation time 59495966 ps
CPU time 0.95 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:09 PM PDT 24
Peak memory 201068 kb
Host smart-3f83711c-0d7e-4341-ae36-33f93092b4f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496711308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3496711308
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2743005223
Short name T420
Test name
Test status
Simulation time 1040643497 ps
CPU time 8.5 seconds
Started Aug 01 06:50:05 PM PDT 24
Finished Aug 01 06:50:14 PM PDT 24
Peak memory 201132 kb
Host smart-19d52e51-2378-4940-9c21-ca00c516fc05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743005223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2743005223
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3035022489
Short name T825
Test name
Test status
Simulation time 2289008459 ps
CPU time 8.07 seconds
Started Aug 01 06:50:04 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201232 kb
Host smart-4be1eacf-6743-45ea-ad1f-8f5fbc5f0903
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035022489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3035022489
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.1548694544
Short name T812
Test name
Test status
Simulation time 22305020 ps
CPU time 0.85 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201060 kb
Host smart-9de0305e-eb3d-4e2b-ae7a-8ab2403833bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548694544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.1548694544
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.226865741
Short name T187
Test name
Test status
Simulation time 22312297 ps
CPU time 0.85 seconds
Started Aug 01 06:50:10 PM PDT 24
Finished Aug 01 06:50:11 PM PDT 24
Peak memory 201072 kb
Host smart-82f5ffda-9c90-4404-98f2-4a77f405cd04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226865741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_clk_byp_req_intersig_mubi.226865741
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.2705782481
Short name T191
Test name
Test status
Simulation time 16217595 ps
CPU time 0.74 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 201012 kb
Host smart-6d25dc72-7519-4946-9817-d96221d6773f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705782481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.2705782481
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.776367537
Short name T47
Test name
Test status
Simulation time 24680854 ps
CPU time 0.76 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 200996 kb
Host smart-4370c9ea-240b-44cd-8b4d-ac122191358c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776367537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.776367537
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.4015339937
Short name T486
Test name
Test status
Simulation time 128841025 ps
CPU time 1.31 seconds
Started Aug 01 06:50:22 PM PDT 24
Finished Aug 01 06:50:23 PM PDT 24
Peak memory 201008 kb
Host smart-2486fc0a-7953-4984-85df-3104144b1f5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015339937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.4015339937
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1446900719
Short name T353
Test name
Test status
Simulation time 14831742 ps
CPU time 0.82 seconds
Started Aug 01 06:50:07 PM PDT 24
Finished Aug 01 06:50:08 PM PDT 24
Peak memory 201020 kb
Host smart-4f107d2b-d0b0-49cd-9efd-b884b320d514
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446900719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1446900719
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.1981028337
Short name T439
Test name
Test status
Simulation time 1928393683 ps
CPU time 14.93 seconds
Started Aug 01 06:50:16 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 201328 kb
Host smart-03e668bd-e02f-4507-8ea8-ff9eb3f97f60
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981028337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.1981028337
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all_with_rand_reset.508076776
Short name T65
Test name
Test status
Simulation time 115458345296 ps
CPU time 811.05 seconds
Started Aug 01 06:50:22 PM PDT 24
Finished Aug 01 07:03:54 PM PDT 24
Peak memory 217860 kb
Host smart-b6cf11f2-afd9-408f-957c-fdb3cf5fc484
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=508076776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.508076776
Directory /workspace/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.clkmgr_trans.1240596785
Short name T725
Test name
Test status
Simulation time 37140276 ps
CPU time 0.91 seconds
Started Aug 01 06:50:06 PM PDT 24
Finished Aug 01 06:50:07 PM PDT 24
Peak memory 201084 kb
Host smart-b9a1a258-2005-464a-b83e-246687f029ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240596785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1240596785
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1760140263
Short name T196
Test name
Test status
Simulation time 16679700 ps
CPU time 0.79 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 201032 kb
Host smart-487a912b-b3a4-4d72-8fe9-57f4d45f493c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760140263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1760140263
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1041565031
Short name T471
Test name
Test status
Simulation time 109342764 ps
CPU time 1.06 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201088 kb
Host smart-afed55dd-8c29-4cf6-8b01-5128734ec2d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041565031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1041565031
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2479527842
Short name T431
Test name
Test status
Simulation time 17906534 ps
CPU time 0.73 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 200292 kb
Host smart-767b622f-bedf-4cbb-847c-24b1c4b1ef8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479527842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2479527842
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1952256961
Short name T539
Test name
Test status
Simulation time 16639547 ps
CPU time 0.75 seconds
Started Aug 01 06:49:12 PM PDT 24
Finished Aug 01 06:49:13 PM PDT 24
Peak memory 201052 kb
Host smart-a09301a3-1a2f-4e80-a4c5-4cbe61b3e37f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952256961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.1952256961
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.134660914
Short name T528
Test name
Test status
Simulation time 32138154 ps
CPU time 0.91 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 201024 kb
Host smart-43c23fa3-23cf-4a3d-9799-c7885c3f7652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134660914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.134660914
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.766751962
Short name T263
Test name
Test status
Simulation time 231553985 ps
CPU time 1.7 seconds
Started Aug 01 06:49:10 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 200992 kb
Host smart-847e9606-383d-4c4b-ad04-c81a423e37fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766751962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.766751962
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2466099378
Short name T30
Test name
Test status
Simulation time 1030279886 ps
CPU time 4.84 seconds
Started Aug 01 06:49:10 PM PDT 24
Finished Aug 01 06:49:15 PM PDT 24
Peak memory 201272 kb
Host smart-c5470177-585b-4298-84a4-9400f4f32a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466099378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2466099378
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.2472062572
Short name T729
Test name
Test status
Simulation time 19505146 ps
CPU time 0.81 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 200884 kb
Host smart-4f894a98-87ea-4aa1-958b-c67559f16ca1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472062572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.2472062572
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.989384957
Short name T711
Test name
Test status
Simulation time 22317958 ps
CPU time 0.9 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 201108 kb
Host smart-5ce2ede6-5f0a-4b10-89b1-f96ee7b93ffd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989384957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_clk_byp_req_intersig_mubi.989384957
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1691135973
Short name T809
Test name
Test status
Simulation time 49615253 ps
CPU time 0.87 seconds
Started Aug 01 06:49:10 PM PDT 24
Finished Aug 01 06:49:11 PM PDT 24
Peak memory 201000 kb
Host smart-46561994-2cad-4b18-83b9-a16a23a260d6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691135973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.1691135973
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.1766057563
Short name T815
Test name
Test status
Simulation time 45959527 ps
CPU time 0.91 seconds
Started Aug 01 06:49:13 PM PDT 24
Finished Aug 01 06:49:14 PM PDT 24
Peak memory 201036 kb
Host smart-d5521ecb-237f-4221-aa07-49dae9cac982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766057563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1766057563
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.3478976127
Short name T320
Test name
Test status
Simulation time 912844184 ps
CPU time 5.18 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:16 PM PDT 24
Peak memory 201232 kb
Host smart-40c2212e-238a-48f2-ac9b-912f0b0996c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478976127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3478976127
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.803369548
Short name T40
Test name
Test status
Simulation time 318362491 ps
CPU time 2.39 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:11 PM PDT 24
Peak memory 216556 kb
Host smart-6bcb1b07-ec1c-4c0d-b9b2-66cbd7acb85a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803369548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr
_sec_cm.803369548
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.593706770
Short name T499
Test name
Test status
Simulation time 22976448 ps
CPU time 0.85 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201076 kb
Host smart-f714fb55-cf40-477c-bfdf-7a8d597f9fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593706770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.593706770
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.292579858
Short name T310
Test name
Test status
Simulation time 5649039029 ps
CPU time 33.35 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:50 PM PDT 24
Peak memory 201452 kb
Host smart-102f1729-1db3-40ad-affe-e51c9c10e70a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292579858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.292579858
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.2169650737
Short name T749
Test name
Test status
Simulation time 36601484 ps
CPU time 0.9 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 201080 kb
Host smart-72703433-488e-4f63-a69c-4292f97671f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169650737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2169650737
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1810738479
Short name T362
Test name
Test status
Simulation time 36800921 ps
CPU time 0.79 seconds
Started Aug 01 06:50:21 PM PDT 24
Finished Aug 01 06:50:22 PM PDT 24
Peak memory 201048 kb
Host smart-35005059-ea90-479c-b2f0-801ca6d4d4dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810738479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1810738479
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2960422983
Short name T699
Test name
Test status
Simulation time 77864542 ps
CPU time 1.04 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201028 kb
Host smart-ee63129f-f7b8-436e-9492-5b8d58bc9a04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960422983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.2960422983
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.138194236
Short name T434
Test name
Test status
Simulation time 32028236 ps
CPU time 0.73 seconds
Started Aug 01 06:50:15 PM PDT 24
Finished Aug 01 06:50:16 PM PDT 24
Peak memory 200996 kb
Host smart-6609ff58-931b-4c6d-9760-3089e58b3114
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138194236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.138194236
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.2838126342
Short name T479
Test name
Test status
Simulation time 37930031 ps
CPU time 0.78 seconds
Started Aug 01 06:50:16 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 200984 kb
Host smart-08b56de9-f4b2-4b0a-af06-b084e28c1e4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838126342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.2838126342
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.3835155520
Short name T631
Test name
Test status
Simulation time 1160441038 ps
CPU time 9.29 seconds
Started Aug 01 06:50:27 PM PDT 24
Finished Aug 01 06:50:37 PM PDT 24
Peak memory 201064 kb
Host smart-5e5bea25-5805-4ca3-b3bb-7250955566ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835155520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3835155520
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2616324270
Short name T338
Test name
Test status
Simulation time 277639173 ps
CPU time 1.78 seconds
Started Aug 01 06:50:19 PM PDT 24
Finished Aug 01 06:50:21 PM PDT 24
Peak memory 201276 kb
Host smart-d117b20a-0799-4d87-ac17-a735335c841c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616324270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2616324270
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.1951110697
Short name T200
Test name
Test status
Simulation time 28716948 ps
CPU time 0.96 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 201056 kb
Host smart-380bed97-e499-4dcb-a24a-6511e6604a4e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951110697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.1951110697
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.990329509
Short name T608
Test name
Test status
Simulation time 23084001 ps
CPU time 0.87 seconds
Started Aug 01 06:50:20 PM PDT 24
Finished Aug 01 06:50:21 PM PDT 24
Peak memory 201024 kb
Host smart-9f970ed5-c339-454e-ade1-aef339bbc03f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990329509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.990329509
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3077016703
Short name T397
Test name
Test status
Simulation time 123030890 ps
CPU time 1.17 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 201080 kb
Host smart-07eb063d-b40d-46bf-9c59-b9e9e2bc8b18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077016703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3077016703
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.155061156
Short name T712
Test name
Test status
Simulation time 46499398 ps
CPU time 0.83 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 201004 kb
Host smart-979d9ec7-e882-4791-92cd-9e106be2efec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155061156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.155061156
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.223577256
Short name T345
Test name
Test status
Simulation time 968555370 ps
CPU time 3.72 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201260 kb
Host smart-20b5eded-9597-407a-ad57-5d900fa274f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223577256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.223577256
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.3587275580
Short name T670
Test name
Test status
Simulation time 19080029 ps
CPU time 0.83 seconds
Started Aug 01 06:50:18 PM PDT 24
Finished Aug 01 06:50:19 PM PDT 24
Peak memory 201080 kb
Host smart-3d8f8f8b-81e8-4f30-b410-047ff4c059ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587275580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.3587275580
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.4147076548
Short name T821
Test name
Test status
Simulation time 5471834780 ps
CPU time 41.38 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201452 kb
Host smart-a632af0c-52c4-4858-bfa3-48a7bf160697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147076548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.4147076548
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.1650452278
Short name T438
Test name
Test status
Simulation time 91982783 ps
CPU time 1.07 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201048 kb
Host smart-e01e3b57-dd1b-4808-a7ec-bcb33e57d7b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650452278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.1650452278
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1592123008
Short name T763
Test name
Test status
Simulation time 13427379 ps
CPU time 0.79 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201088 kb
Host smart-16ca6111-1b66-4903-bd89-59baa744798a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592123008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1592123008
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3919507961
Short name T90
Test name
Test status
Simulation time 14140783 ps
CPU time 0.75 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:13 PM PDT 24
Peak memory 201052 kb
Host smart-13d9d5b4-e397-458f-bcdb-906f122a2169
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919507961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.3919507961
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.3772288399
Short name T731
Test name
Test status
Simulation time 22058518 ps
CPU time 0.78 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 200292 kb
Host smart-9f4cb0f8-e8ab-4609-b02e-ea767931b46c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772288399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3772288399
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.130062025
Short name T803
Test name
Test status
Simulation time 16724613 ps
CPU time 0.78 seconds
Started Aug 01 06:50:15 PM PDT 24
Finished Aug 01 06:50:16 PM PDT 24
Peak memory 201048 kb
Host smart-61868a6b-f29f-4a1b-846b-a8d8e38a2dcf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130062025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_div_intersig_mubi.130062025
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.2375385153
Short name T169
Test name
Test status
Simulation time 31815615 ps
CPU time 0.92 seconds
Started Aug 01 06:50:13 PM PDT 24
Finished Aug 01 06:50:14 PM PDT 24
Peak memory 201048 kb
Host smart-7e69451b-fd5c-4cb6-8097-9984f0495271
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375385153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.2375385153
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1635394419
Short name T524
Test name
Test status
Simulation time 1938607013 ps
CPU time 7.39 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:33 PM PDT 24
Peak memory 201300 kb
Host smart-26b826f3-832e-40ad-b538-0a4878927958
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635394419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1635394419
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.2898835142
Short name T249
Test name
Test status
Simulation time 1798776141 ps
CPU time 7.73 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:20 PM PDT 24
Peak memory 201100 kb
Host smart-db756808-ab98-416c-8859-4ab5c5d1104d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898835142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.2898835142
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.508957785
Short name T419
Test name
Test status
Simulation time 61868563 ps
CPU time 0.91 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201056 kb
Host smart-a111c45a-1682-4540-9e45-2724fcbfc213
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508957785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_idle_intersig_mubi.508957785
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1152959224
Short name T289
Test name
Test status
Simulation time 24931090 ps
CPU time 0.77 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201056 kb
Host smart-daa27477-ec77-48ce-8976-b1ece1b1aaea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152959224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1152959224
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1925575877
Short name T794
Test name
Test status
Simulation time 17175923 ps
CPU time 0.76 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201036 kb
Host smart-73871565-621b-4a75-ad11-728cc25141ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925575877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1925575877
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.2897627950
Short name T469
Test name
Test status
Simulation time 50784976 ps
CPU time 0.86 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201024 kb
Host smart-51b10061-aa10-49e5-a949-5aa54cc7822d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897627950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2897627950
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.4169013535
Short name T767
Test name
Test status
Simulation time 917632000 ps
CPU time 3.46 seconds
Started Aug 01 06:50:13 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 201240 kb
Host smart-a564ce70-db72-44d9-b719-a6c5c09fd0e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169013535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.4169013535
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.176343864
Short name T350
Test name
Test status
Simulation time 177276642 ps
CPU time 1.36 seconds
Started Aug 01 06:50:16 PM PDT 24
Finished Aug 01 06:50:18 PM PDT 24
Peak memory 201128 kb
Host smart-eb3de9fa-20e2-4ac0-ba6e-2092f81ecf8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176343864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.176343864
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.585032310
Short name T342
Test name
Test status
Simulation time 5514159804 ps
CPU time 23.89 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201480 kb
Host smart-b1b9b3ab-4c53-4639-b7d3-b940b514ef6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585032310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.585032310
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.2238495194
Short name T148
Test name
Test status
Simulation time 120763369223 ps
CPU time 714.1 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 07:02:18 PM PDT 24
Peak memory 217896 kb
Host smart-f6bdfe2c-555a-42a5-a768-bd29e52d8af7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2238495194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.2238495194
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.2723425736
Short name T436
Test name
Test status
Simulation time 14738446 ps
CPU time 0.73 seconds
Started Aug 01 06:50:13 PM PDT 24
Finished Aug 01 06:50:14 PM PDT 24
Peak memory 201064 kb
Host smart-cf872cdb-aefe-48d4-a614-3925eb1dfabd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723425736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2723425736
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.3260124747
Short name T175
Test name
Test status
Simulation time 38430830 ps
CPU time 0.84 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 201008 kb
Host smart-b154356f-d3a7-42e7-9b56-223c9cb0c75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260124747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.3260124747
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1886007872
Short name T697
Test name
Test status
Simulation time 22262683 ps
CPU time 0.9 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201052 kb
Host smart-ff05c6b0-ce72-4ec3-b48b-e20f3cc65d96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886007872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.1886007872
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3895658245
Short name T515
Test name
Test status
Simulation time 22142869 ps
CPU time 0.74 seconds
Started Aug 01 06:50:18 PM PDT 24
Finished Aug 01 06:50:19 PM PDT 24
Peak memory 200336 kb
Host smart-a1427360-ba96-4c72-8e77-da4fccaabd96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895658245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3895658245
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.2596623789
Short name T689
Test name
Test status
Simulation time 118240861 ps
CPU time 1.07 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 201060 kb
Host smart-4ebc1ab2-a452-47e6-9ab7-6f3b1ab04e7d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596623789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.2596623789
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.3864865192
Short name T562
Test name
Test status
Simulation time 30302640 ps
CPU time 0.97 seconds
Started Aug 01 06:50:16 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 201096 kb
Host smart-d35d3495-d65e-4923-90b4-08d35c2e381f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864865192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.3864865192
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.2403384506
Short name T294
Test name
Test status
Simulation time 801027737 ps
CPU time 5.07 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:19 PM PDT 24
Peak memory 201132 kb
Host smart-462c8100-722a-4e20-afd5-7fa23fc54098
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403384506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2403384506
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.3553837070
Short name T723
Test name
Test status
Simulation time 2473611875 ps
CPU time 8.55 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:38 PM PDT 24
Peak memory 201368 kb
Host smart-414bbe01-2ccf-4ad5-a7ef-bb834f817755
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553837070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.3553837070
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1767766935
Short name T242
Test name
Test status
Simulation time 60812003 ps
CPU time 0.99 seconds
Started Aug 01 06:50:14 PM PDT 24
Finished Aug 01 06:50:15 PM PDT 24
Peak memory 201084 kb
Host smart-a8664cb3-8470-494a-b8a0-f5c9f52e8e90
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767766935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1767766935
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2434260662
Short name T760
Test name
Test status
Simulation time 54602902 ps
CPU time 0.91 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201012 kb
Host smart-1ca6cd41-ad48-4ac8-b6d3-e88f6be580d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434260662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.2434260662
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1629396058
Short name T217
Test name
Test status
Simulation time 22879245 ps
CPU time 0.85 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 201012 kb
Host smart-f368d112-f12b-4dd2-a9ce-3309c5fdbc5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629396058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.1629396058
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.2225555845
Short name T720
Test name
Test status
Simulation time 16905024 ps
CPU time 0.77 seconds
Started Aug 01 06:50:16 PM PDT 24
Finished Aug 01 06:50:17 PM PDT 24
Peak memory 200992 kb
Host smart-9cabd5e4-6c54-480f-8ad4-e4af4247b313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225555845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.2225555845
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.3580478218
Short name T423
Test name
Test status
Simulation time 951848039 ps
CPU time 3.42 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201204 kb
Host smart-02f9bdcc-178c-49fe-85e7-7d23fcd8f0d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580478218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.3580478218
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.1329505040
Short name T386
Test name
Test status
Simulation time 15521167 ps
CPU time 0.79 seconds
Started Aug 01 06:50:12 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201068 kb
Host smart-9e03d1cd-5b43-4dfc-839a-87d6d6745845
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329505040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1329505040
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.887193584
Short name T661
Test name
Test status
Simulation time 4306182172 ps
CPU time 24.12 seconds
Started Aug 01 06:50:22 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201416 kb
Host smart-aefdb9fd-526e-4a12-a008-4b8b1d684f0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887193584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.887193584
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.2154554328
Short name T10
Test name
Test status
Simulation time 39447403812 ps
CPU time 670.32 seconds
Started Aug 01 06:50:27 PM PDT 24
Finished Aug 01 07:01:37 PM PDT 24
Peak memory 217924 kb
Host smart-14b388c0-d342-4216-a00b-45e935d269c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2154554328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.2154554328
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.3590072075
Short name T509
Test name
Test status
Simulation time 25119116 ps
CPU time 0.72 seconds
Started Aug 01 06:50:11 PM PDT 24
Finished Aug 01 06:50:12 PM PDT 24
Peak memory 201092 kb
Host smart-9aaae3e6-0bc2-4f4d-91f8-6f0fd700b519
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590072075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3590072075
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2032817226
Short name T398
Test name
Test status
Simulation time 118871671 ps
CPU time 1.05 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201024 kb
Host smart-3f5d5a8c-cab4-4fe5-83b3-f06b8be0d466
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032817226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2032817226
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.4035605894
Short name T511
Test name
Test status
Simulation time 32705788 ps
CPU time 0.75 seconds
Started Aug 01 06:50:37 PM PDT 24
Finished Aug 01 06:50:38 PM PDT 24
Peak memory 200260 kb
Host smart-3a19ab8e-70b9-4eb6-9b7f-6e73b1b8eeb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035605894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.4035605894
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.2871387819
Short name T591
Test name
Test status
Simulation time 44528990 ps
CPU time 0.85 seconds
Started Aug 01 06:50:21 PM PDT 24
Finished Aug 01 06:50:22 PM PDT 24
Peak memory 201056 kb
Host smart-2752afff-1b34-4d87-8b53-78a7a259170e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871387819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.2871387819
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1800761114
Short name T441
Test name
Test status
Simulation time 23737279 ps
CPU time 0.82 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201084 kb
Host smart-cf4c12f6-1e98-481f-9bd8-0c7bc75e05d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800761114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1800761114
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.810218116
Short name T704
Test name
Test status
Simulation time 1716409797 ps
CPU time 7.53 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201124 kb
Host smart-6f8fa5d0-47ac-4e9e-97f8-708a0d2206ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810218116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.810218116
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1337273651
Short name T644
Test name
Test status
Simulation time 640480044 ps
CPU time 2.83 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:37 PM PDT 24
Peak memory 201224 kb
Host smart-8ec28dd8-aa64-4929-bd6e-fd15a99df171
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337273651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1337273651
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.294908027
Short name T459
Test name
Test status
Simulation time 122469606 ps
CPU time 1.25 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201088 kb
Host smart-dd040ce5-a90c-4213-b52d-d5e3835d83a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294908027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.294908027
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3848768376
Short name T596
Test name
Test status
Simulation time 67757640 ps
CPU time 0.92 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 201076 kb
Host smart-45282f01-0748-42e5-955a-bd3726afdaf4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848768376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3848768376
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1331240255
Short name T375
Test name
Test status
Simulation time 57422437 ps
CPU time 0.98 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201116 kb
Host smart-0f88a379-cdf3-47e1-a31f-9535d5e55e87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331240255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1331240255
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.2740574422
Short name T190
Test name
Test status
Simulation time 28282826 ps
CPU time 0.75 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201044 kb
Host smart-bce5343b-a331-4a41-9202-c64d6606cfd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740574422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.2740574422
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1054399990
Short name T145
Test name
Test status
Simulation time 207805384 ps
CPU time 1.67 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 201008 kb
Host smart-9c273c6d-f142-446b-815a-83d62bae9496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054399990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1054399990
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4102848210
Short name T445
Test name
Test status
Simulation time 63690506 ps
CPU time 1.01 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 200960 kb
Host smart-6457b8ee-4d50-4b8d-a044-abc1167d875a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102848210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4102848210
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.3624085340
Short name T358
Test name
Test status
Simulation time 6176824811 ps
CPU time 22.29 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201324 kb
Host smart-6748ea8b-7ab3-4d01-89ea-9e7d289d8906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624085340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.3624085340
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.1949532059
Short name T532
Test name
Test status
Simulation time 65092547550 ps
CPU time 743.14 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 07:02:48 PM PDT 24
Peak memory 213496 kb
Host smart-53c5852f-5975-49dd-94a1-4bca11b89daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1949532059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.1949532059
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.1538308862
Short name T708
Test name
Test status
Simulation time 95201911 ps
CPU time 1.23 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201064 kb
Host smart-c21dd4e7-edd7-4eed-85d2-b5863b762f84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538308862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1538308862
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.3552191696
Short name T181
Test name
Test status
Simulation time 64502448 ps
CPU time 0.99 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201020 kb
Host smart-62f367be-4751-4d4c-a46f-68d3c8ea62e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552191696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.3552191696
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.686975850
Short name T587
Test name
Test status
Simulation time 14564331 ps
CPU time 0.75 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201072 kb
Host smart-3eeebd4f-b167-4a0b-9976-b7723525306a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686975850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.686975850
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.1650258439
Short name T336
Test name
Test status
Simulation time 53848190 ps
CPU time 0.83 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201016 kb
Host smart-e5b47e24-8e24-4170-9023-37e9a0614a8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650258439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1650258439
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.2213861533
Short name T472
Test name
Test status
Simulation time 32290790 ps
CPU time 0.83 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201044 kb
Host smart-3e79f6ef-cd11-4ea9-8eb0-9d1e727a1292
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213861533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.2213861533
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.3638030050
Short name T275
Test name
Test status
Simulation time 89489023 ps
CPU time 1.14 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201028 kb
Host smart-7d8ea9cc-c668-4f0b-b147-58c5543ce560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638030050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3638030050
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.3178206743
Short name T2
Test name
Test status
Simulation time 2114815835 ps
CPU time 16.19 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201256 kb
Host smart-3893feb1-9f6a-4251-a434-6a2fc1b25e4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178206743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.3178206743
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1394298612
Short name T188
Test name
Test status
Simulation time 149808539 ps
CPU time 1.24 seconds
Started Aug 01 06:50:27 PM PDT 24
Finished Aug 01 06:50:28 PM PDT 24
Peak memory 201080 kb
Host smart-beaacc46-7254-4a9a-871d-75e061b67454
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394298612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1394298612
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.597302289
Short name T706
Test name
Test status
Simulation time 45668144 ps
CPU time 0.97 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201076 kb
Host smart-8a789e67-5432-4a47-9e81-3a74b812c9ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597302289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_idle_intersig_mubi.597302289
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.3633539412
Short name T282
Test name
Test status
Simulation time 21287033 ps
CPU time 0.86 seconds
Started Aug 01 06:50:22 PM PDT 24
Finished Aug 01 06:50:23 PM PDT 24
Peak memory 201048 kb
Host smart-afce9424-13e2-46b7-969e-be31ff1769f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633539412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.3633539412
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2758565432
Short name T787
Test name
Test status
Simulation time 37640551 ps
CPU time 0.95 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201032 kb
Host smart-a84ef4ac-9f34-4ed1-88b4-9ae9b7d9f679
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758565432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2758565432
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.43723578
Short name T735
Test name
Test status
Simulation time 12949227 ps
CPU time 0.69 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201052 kb
Host smart-26904e93-67ba-4df6-85b3-ad303cbd8267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43723578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.43723578
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.2165535497
Short name T681
Test name
Test status
Simulation time 1079792364 ps
CPU time 5.23 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201260 kb
Host smart-66d71b1d-f99b-4e1d-a5b2-558396ca7cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165535497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2165535497
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2921815238
Short name T134
Test name
Test status
Simulation time 25720646 ps
CPU time 0.97 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 200996 kb
Host smart-510bef92-196b-4a47-a187-c1a10e3eb5d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921815238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2921815238
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3482334086
Short name T666
Test name
Test status
Simulation time 156074589 ps
CPU time 1.47 seconds
Started Aug 01 06:50:30 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 201052 kb
Host smart-d6c0a910-2fc8-43a5-9276-c82995742bf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482334086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3482334086
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.3215462778
Short name T66
Test name
Test status
Simulation time 27482706747 ps
CPU time 423.83 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:57:33 PM PDT 24
Peak memory 217896 kb
Host smart-adae9eef-44b0-4962-80a3-d7297f663762
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3215462778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3215462778
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.2687061905
Short name T347
Test name
Test status
Simulation time 16132954 ps
CPU time 0.74 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:24 PM PDT 24
Peak memory 201112 kb
Host smart-0436f13a-0099-439e-b8fc-eae01f03aa51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687061905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.2687061905
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.3870651501
Short name T488
Test name
Test status
Simulation time 14379967 ps
CPU time 0.75 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201092 kb
Host smart-6523fdb3-4940-479a-8b69-aa1d0f6d45c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870651501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.3870651501
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.944838381
Short name T94
Test name
Test status
Simulation time 50848961 ps
CPU time 0.88 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201120 kb
Host smart-ce1678ae-2781-4af1-a81f-3cf099d60cda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944838381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.944838381
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.2062379815
Short name T780
Test name
Test status
Simulation time 53088143 ps
CPU time 0.81 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 200280 kb
Host smart-2241d46e-075f-423a-8c0f-a764994a1ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062379815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.2062379815
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2734394465
Short name T389
Test name
Test status
Simulation time 365458273 ps
CPU time 1.87 seconds
Started Aug 01 06:50:23 PM PDT 24
Finished Aug 01 06:50:25 PM PDT 24
Peak memory 201028 kb
Host smart-baad390c-d945-4c60-b093-cf4e1853baae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734394465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2734394465
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.993412288
Short name T218
Test name
Test status
Simulation time 58192271 ps
CPU time 0.91 seconds
Started Aug 01 06:50:27 PM PDT 24
Finished Aug 01 06:50:28 PM PDT 24
Peak memory 201080 kb
Host smart-fe6cb256-194d-45de-8fd5-114a1da6fa40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993412288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.993412288
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2418424628
Short name T727
Test name
Test status
Simulation time 1395027888 ps
CPU time 11.3 seconds
Started Aug 01 06:50:22 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201076 kb
Host smart-eaab59f7-301e-424f-bab7-749a5411a764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418424628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2418424628
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.601386974
Short name T182
Test name
Test status
Simulation time 741312621 ps
CPU time 4.52 seconds
Started Aug 01 06:50:24 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201172 kb
Host smart-29ea302c-23cb-4420-a71b-80295c1b62fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601386974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_ti
meout.601386974
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.371329429
Short name T421
Test name
Test status
Simulation time 85250350 ps
CPU time 1.05 seconds
Started Aug 01 06:50:27 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201084 kb
Host smart-693d767b-1139-4db5-a849-5a1936ffcf9f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371329429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.371329429
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.4101633086
Short name T371
Test name
Test status
Simulation time 37969736 ps
CPU time 0.84 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201088 kb
Host smart-f67d9a7b-7c79-4e76-8895-96c22d4843e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101633086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.4101633086
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.2904879973
Short name T778
Test name
Test status
Simulation time 17830432 ps
CPU time 0.76 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 201068 kb
Host smart-8404e8fe-b79e-43f7-bcc3-603a2e3dfa1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904879973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.2904879973
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.1370874584
Short name T714
Test name
Test status
Simulation time 39039369 ps
CPU time 0.82 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201052 kb
Host smart-2698512d-5a82-48a9-b317-66404dc7e4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370874584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1370874584
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.3355599063
Short name T613
Test name
Test status
Simulation time 757625009 ps
CPU time 3.84 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:33 PM PDT 24
Peak memory 201256 kb
Host smart-18f8c5af-16c7-4313-8007-906d2c4936d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355599063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.3355599063
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.3629380393
Short name T357
Test name
Test status
Simulation time 76283818 ps
CPU time 1.03 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 200848 kb
Host smart-5e0b0f4a-2691-4d05-be7a-4aad4eb1a334
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629380393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.3629380393
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.1527704926
Short name T564
Test name
Test status
Simulation time 8284869169 ps
CPU time 62.4 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:51:31 PM PDT 24
Peak memory 201464 kb
Host smart-cde5bf9f-5990-491d-b6b8-d1e1a9806830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527704926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.1527704926
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1013917119
Short name T437
Test name
Test status
Simulation time 28626264 ps
CPU time 0.93 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201096 kb
Host smart-f29a4b73-6f7c-4543-9687-fe8b10f917bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013917119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1013917119
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3686032604
Short name T586
Test name
Test status
Simulation time 43683459 ps
CPU time 0.86 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201088 kb
Host smart-71f601a5-9ccd-4f95-a434-534ed0b9419c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686032604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3686032604
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.1632543936
Short name T603
Test name
Test status
Simulation time 62844047 ps
CPU time 0.93 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201080 kb
Host smart-f5a5665a-ff76-4625-80bb-0378f829e559
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632543936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.1632543936
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.3653384645
Short name T752
Test name
Test status
Simulation time 17932432 ps
CPU time 0.73 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:50 PM PDT 24
Peak memory 200288 kb
Host smart-e3e030a2-dcd4-44e0-be13-af79277d006d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653384645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.3653384645
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.141938860
Short name T383
Test name
Test status
Simulation time 116588685 ps
CPU time 1.18 seconds
Started Aug 01 06:50:38 PM PDT 24
Finished Aug 01 06:50:40 PM PDT 24
Peak memory 201068 kb
Host smart-056bfb88-5ee1-44b2-b022-ada2a330ee9d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141938860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_div_intersig_mubi.141938860
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.1672901740
Short name T19
Test name
Test status
Simulation time 90480074 ps
CPU time 1.02 seconds
Started Aug 01 06:50:26 PM PDT 24
Finished Aug 01 06:50:27 PM PDT 24
Peak memory 200768 kb
Host smart-c33ebe2b-0049-4ad1-adad-fd1510b7135e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672901740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1672901740
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1427255856
Short name T281
Test name
Test status
Simulation time 1285131280 ps
CPU time 7.5 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:41 PM PDT 24
Peak memory 201128 kb
Host smart-fdd6f7e4-9d12-4171-bc12-e9307ace2fe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427255856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1427255856
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.487075777
Short name T274
Test name
Test status
Simulation time 2197538306 ps
CPU time 9.16 seconds
Started Aug 01 06:50:32 PM PDT 24
Finished Aug 01 06:50:41 PM PDT 24
Peak memory 201388 kb
Host smart-f6da12f3-ffc3-4a62-acfa-3d979a3b71de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487075777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_ti
meout.487075777
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1375467197
Short name T478
Test name
Test status
Simulation time 73316572 ps
CPU time 1.08 seconds
Started Aug 01 06:50:38 PM PDT 24
Finished Aug 01 06:50:39 PM PDT 24
Peak memory 201088 kb
Host smart-613ac47e-1e6b-4d30-88c7-c4d98ba8b3bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375467197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1375467197
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2939463008
Short name T604
Test name
Test status
Simulation time 51080185 ps
CPU time 0.87 seconds
Started Aug 01 06:50:39 PM PDT 24
Finished Aug 01 06:50:40 PM PDT 24
Peak memory 200948 kb
Host smart-c25bc075-4c8d-4057-b635-7485fa6b504b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939463008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.2939463008
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.852771502
Short name T584
Test name
Test status
Simulation time 145782118 ps
CPU time 1.2 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 201072 kb
Host smart-aaaa9016-f42b-4ae3-bdb0-fbfb73172952
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852771502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 36.clkmgr_lc_ctrl_intersig_mubi.852771502
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.874182774
Short name T404
Test name
Test status
Simulation time 13034566 ps
CPU time 0.73 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201040 kb
Host smart-bd2f1c77-40d4-4b25-ad3d-ee8602715f07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874182774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.874182774
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.3445295615
Short name T656
Test name
Test status
Simulation time 1204098401 ps
CPU time 7 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:37 PM PDT 24
Peak memory 201264 kb
Host smart-a2066c1c-f109-4daa-a0f1-995bf3d982e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445295615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3445295615
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.2427806772
Short name T485
Test name
Test status
Simulation time 79543902 ps
CPU time 1.03 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201048 kb
Host smart-d16d8bf8-1c04-439b-85d5-cee8b66507c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427806772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.2427806772
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.477870188
Short name T149
Test name
Test status
Simulation time 36547844190 ps
CPU time 328.48 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:55:53 PM PDT 24
Peak memory 217916 kb
Host smart-44b7832f-bb9b-4ede-aece-895d3802fc1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=477870188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.477870188
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.954470917
Short name T268
Test name
Test status
Simulation time 40618259 ps
CPU time 0.9 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:29 PM PDT 24
Peak memory 201040 kb
Host smart-2375dadd-d542-4f14-aaf1-0a87b44f0cec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954470917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.954470917
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.525120417
Short name T646
Test name
Test status
Simulation time 24283644 ps
CPU time 0.78 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201028 kb
Host smart-1d8c11ee-1e5f-490c-a0ef-a93dff7ce9d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525120417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkm
gr_alert_test.525120417
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.753448927
Short name T560
Test name
Test status
Simulation time 15593445 ps
CPU time 0.75 seconds
Started Aug 01 06:50:31 PM PDT 24
Finished Aug 01 06:50:31 PM PDT 24
Peak memory 201128 kb
Host smart-6c8be7c8-69be-41a3-9756-9492ef3e0b48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753448927 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.753448927
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.3712543996
Short name T685
Test name
Test status
Simulation time 16032100 ps
CPU time 0.73 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 200992 kb
Host smart-245d5705-da66-4c01-8c6f-1180b84cde64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712543996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.3712543996
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.4023922704
Short name T483
Test name
Test status
Simulation time 29723921 ps
CPU time 0.82 seconds
Started Aug 01 06:50:41 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 200976 kb
Host smart-05b7f59f-eb6b-4cbd-92bf-5e1e16f9dd1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023922704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.4023922704
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3696610398
Short name T395
Test name
Test status
Simulation time 215717877 ps
CPU time 1.32 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201072 kb
Host smart-8baa173c-1d26-4833-bfe6-ba4eaa5ea46a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696610398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3696610398
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.8701518
Short name T568
Test name
Test status
Simulation time 1206962041 ps
CPU time 6.02 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:39 PM PDT 24
Peak memory 201184 kb
Host smart-07cd4d95-569c-4666-abe6-1bb38aad01f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8701518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.8701518
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.2100714222
Short name T762
Test name
Test status
Simulation time 1213305167 ps
CPU time 9.02 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:38 PM PDT 24
Peak memory 201188 kb
Host smart-3678c130-e0c8-4808-8a9a-e1fb2eb3deb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100714222 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.2100714222
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2014904526
Short name T378
Test name
Test status
Simulation time 126089930 ps
CPU time 1.34 seconds
Started Aug 01 06:50:37 PM PDT 24
Finished Aug 01 06:50:38 PM PDT 24
Peak memory 201052 kb
Host smart-b17ca465-d896-4f23-bd33-b88f544d0943
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014904526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2014904526
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.4089880036
Short name T288
Test name
Test status
Simulation time 41207730 ps
CPU time 0.83 seconds
Started Aug 01 06:50:25 PM PDT 24
Finished Aug 01 06:50:26 PM PDT 24
Peak memory 201028 kb
Host smart-213b3835-b466-451e-91e3-eb4f3934a739
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089880036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.4089880036
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.1791088499
Short name T692
Test name
Test status
Simulation time 36792232 ps
CPU time 0.83 seconds
Started Aug 01 06:50:39 PM PDT 24
Finished Aug 01 06:50:40 PM PDT 24
Peak memory 200952 kb
Host smart-e07abd2d-b924-4695-b9fd-6ccba53fda8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791088499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.1791088499
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.909877559
Short name T660
Test name
Test status
Simulation time 110467628 ps
CPU time 0.99 seconds
Started Aug 01 06:50:28 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 201096 kb
Host smart-1d6d1251-91aa-4d99-86ad-bbc113340d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909877559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.909877559
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.918526854
Short name T490
Test name
Test status
Simulation time 1392789400 ps
CPU time 5.26 seconds
Started Aug 01 06:50:32 PM PDT 24
Finished Aug 01 06:50:37 PM PDT 24
Peak memory 201248 kb
Host smart-bef612db-14c0-4dbb-adaf-c075534d2d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918526854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.918526854
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.74888251
Short name T247
Test name
Test status
Simulation time 26312505 ps
CPU time 0.84 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 201052 kb
Host smart-7a271723-91c9-490f-9cbe-72828f2ee64a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74888251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.74888251
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.294584988
Short name T551
Test name
Test status
Simulation time 1065790237 ps
CPU time 8.15 seconds
Started Aug 01 06:50:37 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201200 kb
Host smart-f0374342-a64d-42d8-b2e6-9ed5be3d67ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294584988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.294584988
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all_with_rand_reset.1798134673
Short name T38
Test name
Test status
Simulation time 67780545785 ps
CPU time 677.15 seconds
Started Aug 01 06:50:39 PM PDT 24
Finished Aug 01 07:01:56 PM PDT 24
Peak memory 217900 kb
Host smart-e0f63566-4e17-40b5-b9b9-e67d612dd62a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1798134673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.1798134673
Directory /workspace/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.clkmgr_trans.4037504015
Short name T638
Test name
Test status
Simulation time 27408979 ps
CPU time 0.92 seconds
Started Aug 01 06:50:29 PM PDT 24
Finished Aug 01 06:50:30 PM PDT 24
Peak memory 201128 kb
Host smart-c84be48d-dd28-4716-b36c-8dccf653a6d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037504015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.4037504015
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.1060566856
Short name T703
Test name
Test status
Simulation time 36209164 ps
CPU time 0.83 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201124 kb
Host smart-2f773d12-d92d-413d-96a7-ef92db4a9578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060566856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.1060566856
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.927439365
Short name T93
Test name
Test status
Simulation time 24492426 ps
CPU time 0.95 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:52 PM PDT 24
Peak memory 201024 kb
Host smart-90c9559e-5944-48a0-a71e-e2744a2ed54a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927439365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.927439365
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.345852113
Short name T738
Test name
Test status
Simulation time 23924872 ps
CPU time 0.74 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 200292 kb
Host smart-5a38b8b4-9817-4f4d-95a4-3161ce5049f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345852113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.345852113
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.2360368496
Short name T221
Test name
Test status
Simulation time 18971559 ps
CPU time 0.83 seconds
Started Aug 01 06:50:38 PM PDT 24
Finished Aug 01 06:50:39 PM PDT 24
Peak memory 201076 kb
Host smart-6220817d-592d-4b3b-80f6-6ce68d1357f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360368496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.2360368496
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.342215763
Short name T537
Test name
Test status
Simulation time 15756231 ps
CPU time 0.76 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201072 kb
Host smart-3970867c-ee2e-4091-9f0f-1c23733c3d11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342215763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.342215763
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.2972410416
Short name T4
Test name
Test status
Simulation time 197787429 ps
CPU time 2.09 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 201164 kb
Host smart-c5d523b3-4712-4bc7-a013-c235b91718d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972410416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2972410416
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1463624150
Short name T533
Test name
Test status
Simulation time 1336326241 ps
CPU time 10.59 seconds
Started Aug 01 06:50:31 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201228 kb
Host smart-c219a429-418f-4a87-bdad-85f235ab9bf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463624150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1463624150
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1749096677
Short name T755
Test name
Test status
Simulation time 164012201 ps
CPU time 1.33 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201104 kb
Host smart-384f18c7-e9e5-4d86-9a3d-6def9c1652d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749096677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1749096677
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.1833901760
Short name T195
Test name
Test status
Simulation time 20398944 ps
CPU time 0.8 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201136 kb
Host smart-22e82330-8edf-4ec1-b26f-ba6ebfabd562
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833901760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.1833901760
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.1083171565
Short name T198
Test name
Test status
Simulation time 71827410 ps
CPU time 1.04 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201112 kb
Host smart-76a83236-fefd-49e7-87ff-ad3073b16548
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083171565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.1083171565
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.563719734
Short name T531
Test name
Test status
Simulation time 38027294 ps
CPU time 0.81 seconds
Started Aug 01 06:50:32 PM PDT 24
Finished Aug 01 06:50:33 PM PDT 24
Peak memory 201004 kb
Host smart-c8c99824-b492-49e7-a677-0bfece35dbd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563719734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.563719734
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.2826421277
Short name T110
Test name
Test status
Simulation time 1062724352 ps
CPU time 4.68 seconds
Started Aug 01 06:50:31 PM PDT 24
Finished Aug 01 06:50:36 PM PDT 24
Peak memory 201224 kb
Host smart-4128b2aa-aa53-42bf-a2fc-9882c16294e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826421277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.2826421277
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.3679878482
Short name T807
Test name
Test status
Simulation time 30449129 ps
CPU time 0.86 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201000 kb
Host smart-d9cc8fcc-61ef-401e-a345-bcc09b718ad6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679878482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3679878482
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1207601070
Short name T138
Test name
Test status
Simulation time 64108286 ps
CPU time 1.35 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201056 kb
Host smart-e8d637ff-dcd9-4bd4-aa61-02613178882d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207601070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1207601070
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.2931473692
Short name T822
Test name
Test status
Simulation time 57191337696 ps
CPU time 622.75 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 07:01:07 PM PDT 24
Peak memory 217944 kb
Host smart-640aeaed-f949-48c8-b03e-3e0cacc8f77f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2931473692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.2931473692
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.4211018985
Short name T328
Test name
Test status
Simulation time 22440065 ps
CPU time 0.83 seconds
Started Aug 01 06:50:32 PM PDT 24
Finished Aug 01 06:50:33 PM PDT 24
Peak memory 201068 kb
Host smart-4c1c16fd-7371-4568-a872-b44492d61cb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211018985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.4211018985
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.3043063979
Short name T238
Test name
Test status
Simulation time 18095128 ps
CPU time 0.79 seconds
Started Aug 01 06:50:50 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 201020 kb
Host smart-cdaebaae-5585-45a2-9c75-a383f0870640
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043063979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.3043063979
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.337229359
Short name T612
Test name
Test status
Simulation time 20372053 ps
CPU time 0.9 seconds
Started Aug 01 06:50:35 PM PDT 24
Finished Aug 01 06:50:36 PM PDT 24
Peak memory 201080 kb
Host smart-a6732ca8-7fdf-4e2c-b65c-f3f50d270b97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337229359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.337229359
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.1633379758
Short name T683
Test name
Test status
Simulation time 13309146 ps
CPU time 0.7 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 200316 kb
Host smart-8a383df3-c160-46c5-9cc5-9c74cb0f42e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633379758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.1633379758
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.840348930
Short name T473
Test name
Test status
Simulation time 125803652 ps
CPU time 1.18 seconds
Started Aug 01 06:50:50 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 200984 kb
Host smart-8b8daada-9392-4b4b-a9c6-047a6547fd8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840348930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_div_intersig_mubi.840348930
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.821919719
Short name T370
Test name
Test status
Simulation time 26708186 ps
CPU time 0.8 seconds
Started Aug 01 06:50:31 PM PDT 24
Finished Aug 01 06:50:32 PM PDT 24
Peak memory 201040 kb
Host smart-c24f2b1e-5e2d-4893-b44c-31c4ad986c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821919719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.821919719
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3918017792
Short name T235
Test name
Test status
Simulation time 2774708022 ps
CPU time 10.38 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201620 kb
Host smart-610d54d7-ba1d-4863-819b-ea4f38e6383e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918017792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3918017792
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3131995417
Short name T788
Test name
Test status
Simulation time 1341435792 ps
CPU time 10.09 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201192 kb
Host smart-f7187354-d4c9-4620-9035-6b8cedb75ebc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131995417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3131995417
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.761126386
Short name T292
Test name
Test status
Simulation time 105602114 ps
CPU time 1.23 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:52 PM PDT 24
Peak memory 201052 kb
Host smart-23713f79-9426-4831-bc5e-bbfe4d387303
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761126386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.clkmgr_idle_intersig_mubi.761126386
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2761603283
Short name T248
Test name
Test status
Simulation time 36514826 ps
CPU time 0.8 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201080 kb
Host smart-1c652e1e-15be-45fd-a95a-8c8698a57911
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761603283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2761603283
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1284761489
Short name T304
Test name
Test status
Simulation time 14635996 ps
CPU time 0.77 seconds
Started Aug 01 06:50:50 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 201040 kb
Host smart-ddb08939-1c24-4eae-b251-8dcf82110f19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284761489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1284761489
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1399395586
Short name T516
Test name
Test status
Simulation time 19525432 ps
CPU time 0.81 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 200984 kb
Host smart-9b61a3c8-436d-4298-8545-bbde6e17d68e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399395586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1399395586
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1172194271
Short name T8
Test name
Test status
Simulation time 283953514 ps
CPU time 2 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201060 kb
Host smart-4a3f8141-722f-4208-930b-341ff4decbc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172194271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1172194271
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.305357591
Short name T684
Test name
Test status
Simulation time 22173169 ps
CPU time 0.86 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:34 PM PDT 24
Peak memory 201080 kb
Host smart-3abc5c43-3bd4-49e5-b87b-d70568995056
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305357591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.305357591
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.522313440
Short name T514
Test name
Test status
Simulation time 2284950710 ps
CPU time 10.76 seconds
Started Aug 01 06:50:49 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201408 kb
Host smart-0bafa2ad-80e9-48ab-8fa8-26bddc5fcbe1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522313440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.522313440
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3755135639
Short name T513
Test name
Test status
Simulation time 87102365274 ps
CPU time 586.18 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 07:00:19 PM PDT 24
Peak memory 217872 kb
Host smart-1cf15853-621b-49ea-b959-802bf02f295f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3755135639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3755135639
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.1488867278
Short name T541
Test name
Test status
Simulation time 86746517 ps
CPU time 1.16 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201032 kb
Host smart-3e52d526-49bc-4e4f-a828-487375a299ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488867278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1488867278
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.2811603937
Short name T243
Test name
Test status
Simulation time 23932273 ps
CPU time 0.87 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201048 kb
Host smart-df5c00ec-baac-4dbe-ae14-2c0976e3e0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811603937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.2811603937
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.94186144
Short name T177
Test name
Test status
Simulation time 40483581 ps
CPU time 0.86 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201040 kb
Host smart-15ece109-530b-406f-a575-95a104c5759e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94186144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_clk_handshake_intersig_mubi.94186144
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3789180276
Short name T155
Test name
Test status
Simulation time 14873091 ps
CPU time 0.7 seconds
Started Aug 01 06:49:04 PM PDT 24
Finished Aug 01 06:49:05 PM PDT 24
Peak memory 200924 kb
Host smart-a753119e-a47e-465d-86d1-2364f285ca01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789180276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3789180276
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.201527945
Short name T701
Test name
Test status
Simulation time 46734932 ps
CPU time 0.88 seconds
Started Aug 01 06:49:03 PM PDT 24
Finished Aug 01 06:49:04 PM PDT 24
Peak memory 201108 kb
Host smart-120296d7-08d6-4f09-a5c3-e6d9c88f3b43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201527945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_div_intersig_mubi.201527945
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.4172678038
Short name T390
Test name
Test status
Simulation time 15271092 ps
CPU time 0.76 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201108 kb
Host smart-1bf2a1ec-5237-4834-8f7a-2961541ba5c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172678038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.4172678038
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1781997512
Short name T818
Test name
Test status
Simulation time 804870394 ps
CPU time 4.99 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201100 kb
Host smart-1319bc21-540f-422c-b0e8-fdd463c76f58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781997512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1781997512
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.741653316
Short name T466
Test name
Test status
Simulation time 1449172297 ps
CPU time 5.25 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:15 PM PDT 24
Peak memory 201200 kb
Host smart-15a2d1fe-64cc-4659-88b7-c2e726a9e78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741653316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.741653316
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1684247459
Short name T327
Test name
Test status
Simulation time 89635502 ps
CPU time 1.13 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201060 kb
Host smart-625bca8f-2226-43f5-a61f-50c552e76fe4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684247459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1684247459
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1155164112
Short name T503
Test name
Test status
Simulation time 185822023 ps
CPU time 1.32 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201068 kb
Host smart-6a62509d-741d-4cb3-bf66-84e7e0848459
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155164112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1155164112
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.3922564384
Short name T418
Test name
Test status
Simulation time 21395931 ps
CPU time 0.91 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201060 kb
Host smart-6d0e4eb8-1de7-4145-ac4d-80296a13d68a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922564384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.3922564384
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.1174380943
Short name T426
Test name
Test status
Simulation time 15091538 ps
CPU time 0.74 seconds
Started Aug 01 06:49:12 PM PDT 24
Finished Aug 01 06:49:13 PM PDT 24
Peak memory 201028 kb
Host smart-f9eb9b2e-f863-4596-84e4-6fea0cf5cede
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174380943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.1174380943
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.4162821795
Short name T142
Test name
Test status
Simulation time 872947699 ps
CPU time 3.2 seconds
Started Aug 01 06:49:04 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201084 kb
Host smart-00b1a47c-e351-4c19-adf0-b33f3ad59232
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162821795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.4162821795
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.4290963132
Short name T43
Test name
Test status
Simulation time 297644331 ps
CPU time 3.16 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 217948 kb
Host smart-64918d89-2ec5-43fe-9890-63a159a99a93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290963132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.4290963132
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.1455978609
Short name T773
Test name
Test status
Simulation time 22755919 ps
CPU time 0.93 seconds
Started Aug 01 06:49:15 PM PDT 24
Finished Aug 01 06:49:16 PM PDT 24
Peak memory 201052 kb
Host smart-d9d22ea7-cef0-4083-9360-4c6e54034777
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455978609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1455978609
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1753334393
Short name T632
Test name
Test status
Simulation time 4549863597 ps
CPU time 20.5 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:26 PM PDT 24
Peak memory 201468 kb
Host smart-fbde3e6c-b1e2-40c3-92db-631da081a861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753334393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1753334393
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1983768526
Short name T273
Test name
Test status
Simulation time 27561871 ps
CPU time 0.91 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201100 kb
Host smart-d7cdd31b-b766-4b6a-a1b6-49016ea3861d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983768526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1983768526
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1207352522
Short name T636
Test name
Test status
Simulation time 113769079 ps
CPU time 1.05 seconds
Started Aug 01 06:50:34 PM PDT 24
Finished Aug 01 06:50:35 PM PDT 24
Peak memory 201084 kb
Host smart-b37c802c-27fc-4198-b2e7-006e4bb1c1ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207352522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1207352522
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2695079135
Short name T487
Test name
Test status
Simulation time 17535634 ps
CPU time 0.82 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201072 kb
Host smart-e30cad04-e684-448c-a169-9f1292470334
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695079135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.2695079135
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.4028904722
Short name T313
Test name
Test status
Simulation time 17169945 ps
CPU time 0.73 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 200268 kb
Host smart-05a560cf-ce5d-4ea8-9b1a-2d6f1874dd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028904722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.4028904722
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.2019228118
Short name T790
Test name
Test status
Simulation time 14323148 ps
CPU time 0.75 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201076 kb
Host smart-435d5373-ba5f-4d6b-92c2-ad28b2872cdb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019228118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.2019228118
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.161365983
Short name T372
Test name
Test status
Simulation time 43800804 ps
CPU time 0.86 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 201012 kb
Host smart-53313b54-ca90-4782-beb5-f89af39eac75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161365983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.161365983
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.2749363241
Short name T25
Test name
Test status
Simulation time 1336676791 ps
CPU time 5.38 seconds
Started Aug 01 06:50:38 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201092 kb
Host smart-e6fc0067-1cf1-4f7b-8d5a-3d4736c7aeaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749363241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.2749363241
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.423506618
Short name T518
Test name
Test status
Simulation time 1153285760 ps
CPU time 4.1 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201092 kb
Host smart-40eb2fd1-6f06-40e2-a002-8b0f1bb94465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423506618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_ti
meout.423506618
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1721791732
Short name T696
Test name
Test status
Simulation time 109855022 ps
CPU time 1.18 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 201056 kb
Host smart-15ac6f95-c63c-4b93-9397-30d385dbf2fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721791732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1721791732
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3289584306
Short name T443
Test name
Test status
Simulation time 27449438 ps
CPU time 0.82 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201076 kb
Host smart-ecd7490f-1733-4a3b-9a38-2cbf7ffdccfd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289584306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3289584306
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3105891774
Short name T796
Test name
Test status
Simulation time 172482105 ps
CPU time 1.33 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201068 kb
Host smart-79c71525-f12d-44ed-b185-93d7a5ecbb2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105891774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.3105891774
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.64173382
Short name T429
Test name
Test status
Simulation time 14277748 ps
CPU time 0.74 seconds
Started Aug 01 06:50:35 PM PDT 24
Finished Aug 01 06:50:36 PM PDT 24
Peak memory 201044 kb
Host smart-2ebcfb2b-314b-4493-947b-f2e7bbfeadaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64173382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.64173382
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.2493831356
Short name T569
Test name
Test status
Simulation time 147975381 ps
CPU time 1.49 seconds
Started Aug 01 06:50:40 PM PDT 24
Finished Aug 01 06:50:41 PM PDT 24
Peak memory 201076 kb
Host smart-b76c3f79-ad5f-44be-a814-8e1308ffc6f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493831356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.2493831356
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.80976183
Short name T777
Test name
Test status
Simulation time 16689743 ps
CPU time 0.9 seconds
Started Aug 01 06:50:35 PM PDT 24
Finished Aug 01 06:50:36 PM PDT 24
Peak memory 201068 kb
Host smart-aead4d53-0d52-485c-8aed-57a6077e5ab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80976183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.80976183
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.1719505277
Short name T326
Test name
Test status
Simulation time 4061344497 ps
CPU time 30.81 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:51:16 PM PDT 24
Peak memory 201428 kb
Host smart-a64b8768-aacf-451b-bfa6-fc5bed133d8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719505277 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.1719505277
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.988504043
Short name T68
Test name
Test status
Simulation time 49935964009 ps
CPU time 439.7 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:58:05 PM PDT 24
Peak memory 217880 kb
Host smart-0c7f3c05-9e0f-45a2-be16-9631ccceef88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=988504043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.988504043
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2071829753
Short name T676
Test name
Test status
Simulation time 43666753 ps
CPU time 0.87 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201000 kb
Host smart-6ee8b5cd-6382-4435-b20b-12bc6d012542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071829753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2071829753
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1124745168
Short name T250
Test name
Test status
Simulation time 13450341 ps
CPU time 0.74 seconds
Started Aug 01 06:50:41 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201108 kb
Host smart-a7f08236-e910-482f-b9f7-66e931b9c76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124745168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1124745168
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2552654797
Short name T553
Test name
Test status
Simulation time 19795385 ps
CPU time 0.76 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 201104 kb
Host smart-ce3985e8-abca-4242-9b3c-56d039f1c0c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552654797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.2552654797
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.2044508644
Short name T588
Test name
Test status
Simulation time 30789249 ps
CPU time 0.75 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 200972 kb
Host smart-6ec956df-e17d-49ca-84d8-8b757c82781b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044508644 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.2044508644
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.3695673556
Short name T46
Test name
Test status
Simulation time 23472984 ps
CPU time 0.77 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201048 kb
Host smart-845f08ea-d5f3-4f7f-b10f-90a87feeeee8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695673556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.3695673556
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.795718935
Short name T629
Test name
Test status
Simulation time 42037346 ps
CPU time 0.94 seconds
Started Aug 01 06:50:36 PM PDT 24
Finished Aug 01 06:50:37 PM PDT 24
Peak memory 201072 kb
Host smart-1b7e0ba6-3907-47db-8b88-0d250f7479bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795718935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.795718935
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.2860229200
Short name T315
Test name
Test status
Simulation time 2532848020 ps
CPU time 9.2 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 201428 kb
Host smart-6e99b760-fd97-4cbb-838c-450f3e7d8419
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860229200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2860229200
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.18046166
Short name T521
Test name
Test status
Simulation time 2178382872 ps
CPU time 15.41 seconds
Started Aug 01 06:50:33 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 201380 kb
Host smart-2248e8b1-95b1-45dc-802f-2beefb93d6b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18046166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_tim
eout.18046166
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.43185157
Short name T330
Test name
Test status
Simulation time 93754276 ps
CPU time 1.1 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 201088 kb
Host smart-1ace35a4-d61d-45d3-9059-358ce602f392
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43185157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.clkmgr_idle_intersig_mubi.43185157
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.249289763
Short name T675
Test name
Test status
Simulation time 22935467 ps
CPU time 0.86 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201116 kb
Host smart-48f3b485-0c38-433f-9ea3-1d104c264bb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249289763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_clk_byp_req_intersig_mubi.249289763
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3606459019
Short name T634
Test name
Test status
Simulation time 35489751 ps
CPU time 0.79 seconds
Started Aug 01 06:50:41 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201092 kb
Host smart-c2c69595-6374-418c-bc32-4a15fa6a0a2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606459019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.3606459019
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.1422025435
Short name T229
Test name
Test status
Simulation time 51150813 ps
CPU time 0.86 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 201032 kb
Host smart-42aadd07-40b8-42a6-b18a-692ce0da0793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422025435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.1422025435
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.3013454418
Short name T567
Test name
Test status
Simulation time 1120458218 ps
CPU time 5.16 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201288 kb
Host smart-c0d652ee-8e59-4b8b-89ef-01f3c83ad628
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013454418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3013454418
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1118514760
Short name T417
Test name
Test status
Simulation time 103790225 ps
CPU time 1.11 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 200996 kb
Host smart-98447f9e-6199-42d8-9628-84c57c36f1fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118514760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1118514760
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3074314405
Short name T552
Test name
Test status
Simulation time 3530331922 ps
CPU time 18.72 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 201452 kb
Host smart-0065beab-c5b6-4b4f-ade6-cfb184386566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074314405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3074314405
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.150799725
Short name T700
Test name
Test status
Simulation time 21599418 ps
CPU time 0.8 seconds
Started Aug 01 06:50:41 PM PDT 24
Finished Aug 01 06:50:42 PM PDT 24
Peak memory 201100 kb
Host smart-b7f52693-695f-4d8c-872e-8f08c84a2ff4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150799725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.150799725
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.533478607
Short name T440
Test name
Test status
Simulation time 69799322 ps
CPU time 0.86 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201100 kb
Host smart-db91439d-f7b5-4567-9dc1-ef67d0d64bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533478607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkm
gr_alert_test.533478607
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4146533434
Short name T199
Test name
Test status
Simulation time 25472546 ps
CPU time 0.76 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201108 kb
Host smart-35d070dd-dd5c-483d-82b9-1fc4c9a49bdd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146533434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.4146533434
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3675099364
Short name T24
Test name
Test status
Simulation time 11395049 ps
CPU time 0.76 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 200960 kb
Host smart-1a44f1b3-d411-444b-a9c8-9da302f9de8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675099364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3675099364
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1541982707
Short name T373
Test name
Test status
Simulation time 23008627 ps
CPU time 0.74 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:50 PM PDT 24
Peak memory 201080 kb
Host smart-1393c490-55a3-41fc-bdc9-8658b696a4b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541982707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1541982707
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.433143041
Short name T734
Test name
Test status
Simulation time 43782150 ps
CPU time 0.82 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201072 kb
Host smart-32859bec-70d6-4bad-bb96-340f9be29894
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433143041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.433143041
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3572958858
Short name T561
Test name
Test status
Simulation time 1770973433 ps
CPU time 9.72 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201340 kb
Host smart-8ad85701-265e-4c3f-80f7-dcd4b24d47e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572958858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3572958858
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.3716238502
Short name T556
Test name
Test status
Simulation time 2421379324 ps
CPU time 18.13 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 201452 kb
Host smart-50b47936-b7d2-4fff-b314-d32e609b7a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716238502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.3716238502
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3178890237
Short name T461
Test name
Test status
Simulation time 16183485 ps
CPU time 0.73 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 201092 kb
Host smart-bef71dc1-7b06-4b51-8184-f181b5453cc0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178890237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3178890237
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.1994131651
Short name T525
Test name
Test status
Simulation time 43066110 ps
CPU time 0.88 seconds
Started Aug 01 06:50:49 PM PDT 24
Finished Aug 01 06:50:50 PM PDT 24
Peak memory 201080 kb
Host smart-3f49a945-2d11-4201-a119-990875784f63
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994131651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.1994131651
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.4275433534
Short name T168
Test name
Test status
Simulation time 45801354 ps
CPU time 0.81 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:50 PM PDT 24
Peak memory 201096 kb
Host smart-f6bc9b45-c1e8-460f-9513-5f56a07483a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275433534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.4275433534
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2872736918
Short name T648
Test name
Test status
Simulation time 15140328 ps
CPU time 0.78 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201016 kb
Host smart-045d6a30-751f-4734-b801-e6567dd35190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872736918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2872736918
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.1388301825
Short name T108
Test name
Test status
Simulation time 664808704 ps
CPU time 3.17 seconds
Started Aug 01 06:50:56 PM PDT 24
Finished Aug 01 06:50:59 PM PDT 24
Peak memory 201288 kb
Host smart-14e68a75-e1a4-4dcb-ae2b-a9de41cdcc29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388301825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.1388301825
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.543869076
Short name T22
Test name
Test status
Simulation time 207860198 ps
CPU time 1.4 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:50:47 PM PDT 24
Peak memory 200996 kb
Host smart-f0a61b31-9c14-404b-b1ff-666068ef195b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543869076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.543869076
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.696070495
Short name T639
Test name
Test status
Simulation time 3828389467 ps
CPU time 29.82 seconds
Started Aug 01 06:50:40 PM PDT 24
Finished Aug 01 06:51:10 PM PDT 24
Peak memory 201424 kb
Host smart-7b3c9131-9204-410d-ace0-29b357acfa33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696070495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.696070495
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3318145318
Short name T707
Test name
Test status
Simulation time 51106166306 ps
CPU time 527.29 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:59:36 PM PDT 24
Peak memory 217876 kb
Host smart-85e5a9d5-71e4-4293-82f5-ed663a849c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3318145318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3318145318
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1126217128
Short name T615
Test name
Test status
Simulation time 22529094 ps
CPU time 0.87 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:45 PM PDT 24
Peak memory 201048 kb
Host smart-13c71f0c-ceb7-46ae-a707-b319b3b75d65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126217128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1126217128
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.435110253
Short name T599
Test name
Test status
Simulation time 55038625 ps
CPU time 0.87 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201076 kb
Host smart-19a74104-916b-430d-8c1e-ed57dd94788c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435110253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkm
gr_alert_test.435110253
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.581306995
Short name T677
Test name
Test status
Simulation time 70810191 ps
CPU time 1.06 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201104 kb
Host smart-41774fe7-65a3-473d-b6fa-ede540cf4b5c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581306995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.581306995
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.3733603162
Short name T156
Test name
Test status
Simulation time 13716227 ps
CPU time 0.67 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 200268 kb
Host smart-045e6da6-a5f6-425c-8396-d4a92f92a2e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733603162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3733603162
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.4256668380
Short name T385
Test name
Test status
Simulation time 66611977 ps
CPU time 1 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:50 PM PDT 24
Peak memory 201080 kb
Host smart-0f84841b-e20a-41ac-9263-8f2f13738806
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256668380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.4256668380
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.613446647
Short name T463
Test name
Test status
Simulation time 90460796 ps
CPU time 0.97 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 200944 kb
Host smart-66cbd611-ba4f-4dcb-9bbb-f963f8b1a22f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613446647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.613446647
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.3480985842
Short name T519
Test name
Test status
Simulation time 2370690899 ps
CPU time 13.39 seconds
Started Aug 01 06:50:44 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201332 kb
Host smart-393bb14b-e476-4ea3-946b-3ab0dc60390b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480985842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.3480985842
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.675317547
Short name T230
Test name
Test status
Simulation time 1456550633 ps
CPU time 10.65 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201196 kb
Host smart-a2560248-dffb-44b8-a17f-ff1d7bd50724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675317547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_ti
meout.675317547
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3906481554
Short name T331
Test name
Test status
Simulation time 41812072 ps
CPU time 0.95 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:52 PM PDT 24
Peak memory 201036 kb
Host smart-e9d9fc2b-c0fa-421a-90d7-dec32d7818ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906481554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.3906481554
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3603346982
Short name T163
Test name
Test status
Simulation time 26954083 ps
CPU time 0.89 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201108 kb
Host smart-91c973ab-ac9f-487e-bd50-a1f25e57a976
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603346982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3603346982
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3490187862
Short name T540
Test name
Test status
Simulation time 34399023 ps
CPU time 0.86 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201072 kb
Host smart-2cff1d49-d847-4390-95e7-3cd5eaaadf9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490187862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.3490187862
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.106030203
Short name T792
Test name
Test status
Simulation time 11911354 ps
CPU time 0.71 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201064 kb
Host smart-0512c922-0228-4c41-a29e-9e93ed451cc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106030203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.106030203
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.64006940
Short name T555
Test name
Test status
Simulation time 752930241 ps
CPU time 4.62 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:52 PM PDT 24
Peak memory 201280 kb
Host smart-3d5a0d9b-f03a-4971-9ae9-668e4cd9b9bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64006940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.64006940
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.3478402479
Short name T312
Test name
Test status
Simulation time 16146688 ps
CPU time 0.83 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 201052 kb
Host smart-2fb0342a-3390-45ae-9501-364c8653410d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478402479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3478402479
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.2142401950
Short name T37
Test name
Test status
Simulation time 4232500862 ps
CPU time 31.96 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:51:17 PM PDT 24
Peak memory 201436 kb
Host smart-69f25586-68e3-4ab6-8071-7c56875fb22b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142401950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.2142401950
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.3694403339
Short name T784
Test name
Test status
Simulation time 15631061252 ps
CPU time 292.35 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:55:35 PM PDT 24
Peak memory 209728 kb
Host smart-6d75b1ed-48cb-4ba2-804e-1afe53c543ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3694403339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.3694403339
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.1774875754
Short name T547
Test name
Test status
Simulation time 49455534 ps
CPU time 0.86 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201020 kb
Host smart-6cafa2b2-bf6c-40e6-960b-9628bca4cb03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774875754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.1774875754
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.226141263
Short name T462
Test name
Test status
Simulation time 14518968 ps
CPU time 0.78 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 200784 kb
Host smart-a6095ddb-009f-4cee-aacf-4e09961644ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226141263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkm
gr_alert_test.226141263
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1365652964
Short name T474
Test name
Test status
Simulation time 58707002 ps
CPU time 0.98 seconds
Started Aug 01 06:50:50 PM PDT 24
Finished Aug 01 06:50:51 PM PDT 24
Peak memory 201084 kb
Host smart-2270edc7-80a4-4ab5-8d0c-913b3a73440f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365652964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1365652964
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2489325524
Short name T605
Test name
Test status
Simulation time 17652014 ps
CPU time 0.68 seconds
Started Aug 01 06:50:46 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201008 kb
Host smart-f7e6c8f9-9611-4814-9937-2140c54e7da5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489325524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2489325524
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2246347753
Short name T500
Test name
Test status
Simulation time 25307960 ps
CPU time 0.89 seconds
Started Aug 01 06:50:42 PM PDT 24
Finished Aug 01 06:50:43 PM PDT 24
Peak memory 201032 kb
Host smart-469bc9eb-640d-49ca-ac37-3a130d836177
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246347753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.2246347753
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.3518129972
Short name T548
Test name
Test status
Simulation time 18911106 ps
CPU time 0.76 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201044 kb
Host smart-ecdb39bc-60ca-4d7b-b58d-e9f30e2b7b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518129972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3518129972
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.3939804587
Short name T266
Test name
Test status
Simulation time 972774632 ps
CPU time 4.64 seconds
Started Aug 01 06:50:41 PM PDT 24
Finished Aug 01 06:50:46 PM PDT 24
Peak memory 201108 kb
Host smart-09fbfd66-c5e6-4d03-9833-da866702262a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939804587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.3939804587
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2190569887
Short name T789
Test name
Test status
Simulation time 1797893316 ps
CPU time 6.18 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 201236 kb
Host smart-1013b4be-ba39-41ad-8a42-714d00bc8670
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190569887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2190569887
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.4246278658
Short name T363
Test name
Test status
Simulation time 57269631 ps
CPU time 0.93 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201076 kb
Host smart-7a6ff79f-eace-4ad3-82c0-cafe3599f699
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246278658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.4246278658
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2587065107
Short name T507
Test name
Test status
Simulation time 54447310 ps
CPU time 0.89 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201144 kb
Host smart-ea2408b6-e62d-4714-9129-342db002c093
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587065107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.2587065107
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.2440752915
Short name T324
Test name
Test status
Simulation time 14296793 ps
CPU time 0.74 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201080 kb
Host smart-95ac2766-db3d-4211-afc8-a2f2641bd411
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440752915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2440752915
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.4193409770
Short name T348
Test name
Test status
Simulation time 584221085 ps
CPU time 3.67 seconds
Started Aug 01 06:50:45 PM PDT 24
Finished Aug 01 06:50:49 PM PDT 24
Peak memory 201272 kb
Host smart-f3efa49a-8284-4131-b0b6-17572d8ae9c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193409770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.4193409770
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1275847805
Short name T765
Test name
Test status
Simulation time 55870670 ps
CPU time 0.99 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201044 kb
Host smart-0dd96db2-5fb8-45e8-8eec-9bf043b53166
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275847805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1275847805
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.4173945669
Short name T716
Test name
Test status
Simulation time 13105638516 ps
CPU time 90.21 seconds
Started Aug 01 06:50:48 PM PDT 24
Finished Aug 01 06:52:19 PM PDT 24
Peak memory 201412 kb
Host smart-3c154ab4-2fe5-4fce-b58b-0f8492f7f2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173945669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.4173945669
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.2613003304
Short name T508
Test name
Test status
Simulation time 20838321 ps
CPU time 0.78 seconds
Started Aug 01 06:50:43 PM PDT 24
Finished Aug 01 06:50:44 PM PDT 24
Peak memory 201044 kb
Host smart-9d7790fd-22da-468f-9fb5-27b399afb9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613003304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.2613003304
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.4264570373
Short name T224
Test name
Test status
Simulation time 26477311 ps
CPU time 0.76 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201080 kb
Host smart-689debb1-1d06-4ace-a0e4-a0a505dee43d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264570373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.4264570373
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.267537713
Short name T583
Test name
Test status
Simulation time 14846919 ps
CPU time 0.76 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:50:59 PM PDT 24
Peak memory 201084 kb
Host smart-b6a3ffe2-5298-475d-95ed-6ee28418e01b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267537713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.267537713
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3767578081
Short name T262
Test name
Test status
Simulation time 36467628 ps
CPU time 0.74 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 200236 kb
Host smart-2f0d5dab-b628-4b92-b46a-23c3acc3bcd8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767578081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3767578081
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.3335078319
Short name T222
Test name
Test status
Simulation time 21133662 ps
CPU time 0.83 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201064 kb
Host smart-8f154913-5da8-452a-8384-774b85dbb071
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335078319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.3335078319
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.761689296
Short name T272
Test name
Test status
Simulation time 87554246 ps
CPU time 1.04 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201292 kb
Host smart-add9c872-4717-4926-8de0-8a36f6c031dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761689296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.761689296
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.2066645021
Short name T361
Test name
Test status
Simulation time 1879540318 ps
CPU time 14.65 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:51:09 PM PDT 24
Peak memory 201340 kb
Host smart-763e5af9-dd9f-4f63-abd1-e6004cc9f427
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066645021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2066645021
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.1601485101
Short name T730
Test name
Test status
Simulation time 618890351 ps
CPU time 5.31 seconds
Started Aug 01 06:50:50 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201156 kb
Host smart-66b3769d-bee6-43e5-8e8e-86cbf270133d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601485101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.1601485101
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.3756714381
Short name T303
Test name
Test status
Simulation time 284247138 ps
CPU time 1.56 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201112 kb
Host smart-0da94042-8d37-4a74-a131-f14e00654de6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756714381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.3756714381
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.458836613
Short name T623
Test name
Test status
Simulation time 18716493 ps
CPU time 0.8 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201020 kb
Host smart-a2126976-f6d8-49e3-aef5-a921a3811cb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458836613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_clk_byp_req_intersig_mubi.458836613
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.1671443090
Short name T602
Test name
Test status
Simulation time 16957704 ps
CPU time 0.84 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201076 kb
Host smart-9d1b15ae-22e8-4db2-858f-41a26d5577d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671443090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.1671443090
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.767188436
Short name T317
Test name
Test status
Simulation time 29227344 ps
CPU time 0.79 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201052 kb
Host smart-0e03866e-1ddf-417e-819d-da2317828a88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767188436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.767188436
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.1089614200
Short name T9
Test name
Test status
Simulation time 936460282 ps
CPU time 5.55 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:57 PM PDT 24
Peak memory 201288 kb
Host smart-cd4f6ba5-ead3-44b8-8f04-42b0c3c75b77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089614200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1089614200
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2516688098
Short name T113
Test name
Test status
Simulation time 41320803 ps
CPU time 0.87 seconds
Started Aug 01 06:50:47 PM PDT 24
Finished Aug 01 06:50:48 PM PDT 24
Peak memory 201044 kb
Host smart-411ab9a8-d5ea-4ad0-abb4-fd770758fce9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516688098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2516688098
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.2981605557
Short name T627
Test name
Test status
Simulation time 2160870879 ps
CPU time 8.82 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:11 PM PDT 24
Peak memory 201440 kb
Host smart-30832fc1-9152-4e82-a867-4b25e6e6ad51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981605557 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.2981605557
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1116572693
Short name T745
Test name
Test status
Simulation time 53085039 ps
CPU time 0.99 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201044 kb
Host smart-d840798a-6b2f-41fa-b623-28ff5c2ed84a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116572693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1116572693
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.1897987404
Short name T231
Test name
Test status
Simulation time 13495348 ps
CPU time 0.78 seconds
Started Aug 01 06:50:56 PM PDT 24
Finished Aug 01 06:50:57 PM PDT 24
Peak memory 201076 kb
Host smart-8bbafd23-afed-4eb6-925e-7435ef230188
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897987404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.1897987404
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.3120029186
Short name T384
Test name
Test status
Simulation time 106139363 ps
CPU time 1.04 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 201048 kb
Host smart-fb5ed8a3-0ca1-4ef3-9a00-c5b0b9b77043
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120029186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.3120029186
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.3153537170
Short name T573
Test name
Test status
Simulation time 25199495 ps
CPU time 0.73 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 200268 kb
Host smart-4426b377-92f3-48bf-bc97-b9080694beaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153537170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3153537170
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.1205945535
Short name T640
Test name
Test status
Simulation time 20967397 ps
CPU time 0.82 seconds
Started Aug 01 06:50:56 PM PDT 24
Finished Aug 01 06:50:57 PM PDT 24
Peak memory 201060 kb
Host smart-d8194eef-5a93-42f2-af0c-c9802e0fe559
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205945535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.1205945535
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.3435728165
Short name T674
Test name
Test status
Simulation time 74196525 ps
CPU time 0.98 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201076 kb
Host smart-5cecf098-e426-4cf0-aa48-a74d3b00f8d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435728165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3435728165
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.2042074930
Short name T114
Test name
Test status
Simulation time 1237763538 ps
CPU time 5.85 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201152 kb
Host smart-f90c2d16-6ea6-42ea-8290-8f2e93cbaf46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042074930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2042074930
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1814191895
Short name T32
Test name
Test status
Simulation time 300420760 ps
CPU time 1.71 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:59 PM PDT 24
Peak memory 201136 kb
Host smart-1fe4de00-63d2-484a-b4df-9926d70fc3f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814191895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1814191895
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.3118900200
Short name T165
Test name
Test status
Simulation time 89854372 ps
CPU time 1.11 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201084 kb
Host smart-07d94a6c-3ef4-4ea4-94ca-06c4c6324074
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118900200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.3118900200
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.714000677
Short name T678
Test name
Test status
Simulation time 16326245 ps
CPU time 0.75 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201040 kb
Host smart-5108f597-c3f1-425b-9c8d-56788d4d543c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714000677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_clk_byp_req_intersig_mubi.714000677
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.334087087
Short name T719
Test name
Test status
Simulation time 22160101 ps
CPU time 0.84 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 200992 kb
Host smart-8797501e-64d9-44d7-aea5-fa1c5a7a5aad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334087087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_ctrl_intersig_mubi.334087087
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.3787927854
Short name T251
Test name
Test status
Simulation time 15724387 ps
CPU time 0.75 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201052 kb
Host smart-b7b4faff-7d2c-469a-b9c1-1a4d9500e10e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787927854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3787927854
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.2917636987
Short name T211
Test name
Test status
Simulation time 967112748 ps
CPU time 3.64 seconds
Started Aug 01 06:50:56 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201280 kb
Host smart-5b6acb92-2e43-41df-a1bb-e8fa66d2a8f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917636987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.2917636987
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.2178903685
Short name T132
Test name
Test status
Simulation time 72418004 ps
CPU time 0.99 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201028 kb
Host smart-3ee8e08f-fe25-4aa0-9bd7-41bddd5ed2ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178903685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2178903685
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1396959533
Short name T464
Test name
Test status
Simulation time 4648366273 ps
CPU time 20.41 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:51:12 PM PDT 24
Peak memory 201360 kb
Host smart-d2406b2a-c60c-4a83-a2a7-64669c712c4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396959533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1396959533
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_trans.1255265523
Short name T291
Test name
Test status
Simulation time 97371450 ps
CPU time 1.15 seconds
Started Aug 01 06:50:56 PM PDT 24
Finished Aug 01 06:50:57 PM PDT 24
Peak memory 201076 kb
Host smart-83b32a95-14a0-41ab-84bf-54cbc41f085a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255265523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1255265523
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.4070080083
Short name T477
Test name
Test status
Simulation time 45170460 ps
CPU time 0.8 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201016 kb
Host smart-b005b976-1de9-420a-9fda-d4d3ccebcea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070080083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.4070080083
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3921145322
Short name T635
Test name
Test status
Simulation time 22945578 ps
CPU time 0.89 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 200216 kb
Host smart-4e6a73fd-2fc9-46fc-993e-29a9a55c6557
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921145322 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.3921145322
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.4031737189
Short name T682
Test name
Test status
Simulation time 49794626 ps
CPU time 0.79 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 200256 kb
Host smart-acdedecc-0bcb-4921-ac69-9719e03a311b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031737189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.4031737189
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.224467555
Short name T232
Test name
Test status
Simulation time 31766438 ps
CPU time 0.87 seconds
Started Aug 01 06:50:59 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201092 kb
Host smart-e91bc437-8139-465c-bc6d-8f82ccd9467d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224467555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.224467555
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.2938389885
Short name T368
Test name
Test status
Simulation time 41648626 ps
CPU time 0.83 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 200976 kb
Host smart-f844977e-80f7-4247-9dab-a2d1ebe80f53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938389885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.2938389885
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1310706775
Short name T16
Test name
Test status
Simulation time 2002086755 ps
CPU time 16.1 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:51:10 PM PDT 24
Peak memory 201212 kb
Host smart-554cefbc-523b-4921-b6ca-a3225bf2391f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310706775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1310706775
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.4131744186
Short name T271
Test name
Test status
Simulation time 566747562 ps
CPU time 2.61 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201164 kb
Host smart-9f474601-4524-41e0-877b-06aaca708e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131744186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.4131744186
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.1173676283
Short name T189
Test name
Test status
Simulation time 144079375 ps
CPU time 1.38 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 201084 kb
Host smart-c8d2cdb7-afe3-4c53-9710-36e92b4cc8e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173676283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.1173676283
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2745774554
Short name T535
Test name
Test status
Simulation time 24339520 ps
CPU time 0.9 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201040 kb
Host smart-7470fd24-cfe5-4feb-bcc3-869de6a2109c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745774554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2745774554
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1030880764
Short name T322
Test name
Test status
Simulation time 24096991 ps
CPU time 0.86 seconds
Started Aug 01 06:50:54 PM PDT 24
Finished Aug 01 06:50:55 PM PDT 24
Peak memory 201080 kb
Host smart-0a434991-d95f-4dcb-b07e-2e9f33ff4ce8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030880764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.1030880764
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.782687072
Short name T193
Test name
Test status
Simulation time 17242687 ps
CPU time 0.75 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:50:59 PM PDT 24
Peak memory 201040 kb
Host smart-bc0394c5-d571-4d7c-99e9-3a5d848930ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782687072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.782687072
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.92674153
Short name T233
Test name
Test status
Simulation time 1080798257 ps
CPU time 6.1 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 201288 kb
Host smart-de16de4a-e3ff-462a-934e-20d5d1c67fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92674153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.92674153
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.105693899
Short name T256
Test name
Test status
Simulation time 162988384 ps
CPU time 1.31 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 200996 kb
Host smart-99ed0647-a6cd-487e-b0be-1923086dd499
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105693899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.105693899
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.2330027092
Short name T137
Test name
Test status
Simulation time 2460371903 ps
CPU time 13.34 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:15 PM PDT 24
Peak memory 201424 kb
Host smart-e8e42394-26f1-4108-9b00-004a819babfe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330027092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.2330027092
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2043226934
Short name T318
Test name
Test status
Simulation time 24703567 ps
CPU time 0.94 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 201084 kb
Host smart-8a13fe06-ee72-4b67-9eb4-e386df9664c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043226934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2043226934
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.304125606
Short name T340
Test name
Test status
Simulation time 14084072 ps
CPU time 0.74 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:50:58 PM PDT 24
Peak memory 201076 kb
Host smart-edfa6969-5ab1-4a55-ac8b-77daa515b0dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304125606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.304125606
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2328560934
Short name T86
Test name
Test status
Simulation time 106169730 ps
CPU time 1.19 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 200892 kb
Host smart-9b9229e1-6c66-483b-9416-782e76a8bb97
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328560934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.2328560934
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.2282392885
Short name T349
Test name
Test status
Simulation time 26257009 ps
CPU time 0.77 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 200264 kb
Host smart-228d0c7c-03e3-44f0-a5a0-fc6a506bd1ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282392885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2282392885
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.635927326
Short name T732
Test name
Test status
Simulation time 14437498 ps
CPU time 0.78 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201044 kb
Host smart-71211d14-0dfb-465f-8461-94395f8ee3ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635927326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.635927326
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.296579885
Short name T686
Test name
Test status
Simulation time 98461395 ps
CPU time 1.09 seconds
Started Aug 01 06:50:51 PM PDT 24
Finished Aug 01 06:50:53 PM PDT 24
Peak memory 201028 kb
Host smart-de2f5acb-cfd6-49de-b463-5b98eb7312bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296579885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.296579885
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.2276968331
Short name T252
Test name
Test status
Simulation time 2245932764 ps
CPU time 12 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 201352 kb
Host smart-c1ba1731-d329-402a-b164-d8495574c244
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276968331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.2276968331
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3608457408
Short name T394
Test name
Test status
Simulation time 2062573692 ps
CPU time 15.03 seconds
Started Aug 01 06:50:57 PM PDT 24
Finished Aug 01 06:51:12 PM PDT 24
Peak memory 201312 kb
Host smart-41ad3976-fb0d-4910-a02e-2a6b93fa4008
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608457408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3608457408
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2385393985
Short name T633
Test name
Test status
Simulation time 41436627 ps
CPU time 0.84 seconds
Started Aug 01 06:50:53 PM PDT 24
Finished Aug 01 06:50:54 PM PDT 24
Peak memory 201020 kb
Host smart-1a61b914-2ed6-40c2-917a-2470b4cfe46d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385393985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2385393985
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.4169623819
Short name T757
Test name
Test status
Simulation time 69146231 ps
CPU time 0.96 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201068 kb
Host smart-830de6cd-3f63-4d35-9425-40464ab144e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169623819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.4169623819
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.543435699
Short name T366
Test name
Test status
Simulation time 62838683 ps
CPU time 0.91 seconds
Started Aug 01 06:51:00 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201068 kb
Host smart-dffc5744-21c6-461e-83aa-20d4a241a47f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543435699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.clkmgr_lc_ctrl_intersig_mubi.543435699
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.491750308
Short name T481
Test name
Test status
Simulation time 13856584 ps
CPU time 0.75 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 200268 kb
Host smart-1cd438d1-adc9-41b3-9c81-6d6c36ac9c31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491750308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.491750308
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.3455349127
Short name T450
Test name
Test status
Simulation time 1546179304 ps
CPU time 5.41 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 201300 kb
Host smart-3e09b493-76e6-4a01-a724-085d87a50a9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455349127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.3455349127
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.4224893207
Short name T691
Test name
Test status
Simulation time 69267568 ps
CPU time 0.99 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 201024 kb
Host smart-23a48134-3d51-447b-82be-fdb0609d0d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224893207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.4224893207
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.2890302144
Short name T808
Test name
Test status
Simulation time 6274304133 ps
CPU time 26.45 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:51:25 PM PDT 24
Peak memory 201468 kb
Host smart-1956fa5d-bb22-40b3-ab64-1ca95e8b9b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890302144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.2890302144
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all_with_rand_reset.207384719
Short name T63
Test name
Test status
Simulation time 140740222513 ps
CPU time 970.22 seconds
Started Aug 01 06:50:52 PM PDT 24
Finished Aug 01 07:07:03 PM PDT 24
Peak memory 217904 kb
Host smart-02de4389-aacf-4466-8e57-6fb0680073ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=207384719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.207384719
Directory /workspace/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_trans.2195632423
Short name T376
Test name
Test status
Simulation time 119760250 ps
CPU time 1.26 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 201056 kb
Host smart-40cd86c4-cf0d-46d2-82c8-b2668ae9e636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195632423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2195632423
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.2615693287
Short name T309
Test name
Test status
Simulation time 64674831 ps
CPU time 0.89 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201080 kb
Host smart-aa0a5fa7-498f-40bb-8c0c-cb16997d65bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615693287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.2615693287
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.737852153
Short name T451
Test name
Test status
Simulation time 91175148 ps
CPU time 1.16 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201076 kb
Host smart-601b8860-e489-4395-b8ea-92b73adce97f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737852153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.737852153
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.2173483058
Short name T258
Test name
Test status
Simulation time 15075002 ps
CPU time 0.7 seconds
Started Aug 01 06:50:55 PM PDT 24
Finished Aug 01 06:50:56 PM PDT 24
Peak memory 200272 kb
Host smart-ef8e8b6b-ad3b-4465-aac8-53c08a732ac5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173483058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2173483058
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2486411776
Short name T400
Test name
Test status
Simulation time 36014093 ps
CPU time 0.79 seconds
Started Aug 01 06:50:59 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201076 kb
Host smart-c769608a-5e31-4f74-a6d9-779cc4aaa0e4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486411776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2486411776
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.2030718605
Short name T210
Test name
Test status
Simulation time 27911299 ps
CPU time 0.8 seconds
Started Aug 01 06:51:05 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 201012 kb
Host smart-a8c7735b-319f-42b3-a168-7d076846a949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030718605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.2030718605
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.4039573600
Short name T747
Test name
Test status
Simulation time 347968686 ps
CPU time 2.15 seconds
Started Aug 01 06:50:59 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201212 kb
Host smart-9ed03648-114a-4e44-be0f-fbaa073db681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039573600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.4039573600
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2484393405
Short name T761
Test name
Test status
Simulation time 168164363 ps
CPU time 1.31 seconds
Started Aug 01 06:50:59 PM PDT 24
Finished Aug 01 06:51:01 PM PDT 24
Peak memory 201276 kb
Host smart-2f673004-e505-4ece-9764-fc10df01b3bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484393405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2484393405
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.1767724849
Short name T597
Test name
Test status
Simulation time 18917592 ps
CPU time 0.79 seconds
Started Aug 01 06:51:04 PM PDT 24
Finished Aug 01 06:51:05 PM PDT 24
Peak memory 201052 kb
Host smart-4daa8619-4907-4ce7-8693-c795ccc1b867
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767724849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.1767724849
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2191848346
Short name T335
Test name
Test status
Simulation time 18323210 ps
CPU time 0.83 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:03 PM PDT 24
Peak memory 200804 kb
Host smart-891ab2f7-f868-482b-a4a1-5d8c2b3d8ef5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191848346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2191848346
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3686879440
Short name T746
Test name
Test status
Simulation time 216059089 ps
CPU time 1.38 seconds
Started Aug 01 06:51:02 PM PDT 24
Finished Aug 01 06:51:04 PM PDT 24
Peak memory 201056 kb
Host smart-7c1d023b-44d9-4847-a1b8-531d20654d66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686879440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3686879440
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.3623339030
Short name T265
Test name
Test status
Simulation time 38172795 ps
CPU time 0.81 seconds
Started Aug 01 06:51:01 PM PDT 24
Finished Aug 01 06:51:02 PM PDT 24
Peak memory 201080 kb
Host smart-09599a0f-9c8a-4a04-95c7-4f96f9ddc9ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623339030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3623339030
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.3852012663
Short name T226
Test name
Test status
Simulation time 901368680 ps
CPU time 3.13 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:06 PM PDT 24
Peak memory 201260 kb
Host smart-2845b05a-cc7f-4294-888b-a13ea449e48f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852012663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3852012663
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.3550812957
Short name T662
Test name
Test status
Simulation time 17662500 ps
CPU time 0.81 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:50:59 PM PDT 24
Peak memory 201076 kb
Host smart-3e8fc07a-fddb-429f-b7ab-cdc24494a206
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550812957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3550812957
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1675325289
Short name T131
Test name
Test status
Simulation time 2602780228 ps
CPU time 21.88 seconds
Started Aug 01 06:51:03 PM PDT 24
Finished Aug 01 06:51:25 PM PDT 24
Peak memory 201448 kb
Host smart-ca47183a-5d30-4f9f-8371-cb699ad00dbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675325289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1675325289
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.76030567
Short name T824
Test name
Test status
Simulation time 48764955 ps
CPU time 0.96 seconds
Started Aug 01 06:50:58 PM PDT 24
Finished Aug 01 06:51:00 PM PDT 24
Peak memory 201084 kb
Host smart-9a1932d9-c4c3-400e-ae7a-f286a0464ae3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76030567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.76030567
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.254562270
Short name T610
Test name
Test status
Simulation time 25825290 ps
CPU time 0.82 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201068 kb
Host smart-c61b1aa2-b57c-448a-be99-481203150d9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254562270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmg
r_alert_test.254562270
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1208710719
Short name T409
Test name
Test status
Simulation time 23368355 ps
CPU time 0.89 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201084 kb
Host smart-2e6f7cdb-5736-4d89-961a-f6d2acab44f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208710719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.1208710719
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.2705499629
Short name T406
Test name
Test status
Simulation time 20992087 ps
CPU time 0.72 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 200992 kb
Host smart-48983d88-c38d-4cdd-9b02-c455dcc5dade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705499629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2705499629
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3647633992
Short name T50
Test name
Test status
Simulation time 251860375 ps
CPU time 1.62 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:13 PM PDT 24
Peak memory 201068 kb
Host smart-c699b20b-7cb0-4afb-bd05-b1ca26294c52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647633992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.3647633992
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.1857473499
Short name T658
Test name
Test status
Simulation time 24446136 ps
CPU time 0.86 seconds
Started Aug 01 06:49:08 PM PDT 24
Finished Aug 01 06:49:09 PM PDT 24
Peak memory 201080 kb
Host smart-a5cf8dc6-f563-4b28-9235-55fa898e2ef7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857473499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1857473499
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2160128957
Short name T544
Test name
Test status
Simulation time 1876911504 ps
CPU time 13.99 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 201280 kb
Host smart-4a7ddc46-c7e6-4324-9a7c-96ebe9d1df91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160128957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2160128957
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1664777049
Short name T381
Test name
Test status
Simulation time 2072326259 ps
CPU time 8.61 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:15 PM PDT 24
Peak memory 201392 kb
Host smart-b0c46809-3ace-482b-84af-8566d8f2dc60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664777049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1664777049
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3422838123
Short name T283
Test name
Test status
Simulation time 81824033 ps
CPU time 1.1 seconds
Started Aug 01 06:49:06 PM PDT 24
Finished Aug 01 06:49:07 PM PDT 24
Peak memory 201084 kb
Host smart-222a809b-3973-4aa0-b68f-ac5f03df01ae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422838123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3422838123
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3765377556
Short name T458
Test name
Test status
Simulation time 39710434 ps
CPU time 0.92 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201060 kb
Host smart-ad1c20d6-fa07-4181-8e7e-8feb5b72e141
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765377556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.3765377556
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2685865114
Short name T538
Test name
Test status
Simulation time 21657190 ps
CPU time 0.86 seconds
Started Aug 01 06:49:09 PM PDT 24
Finished Aug 01 06:49:10 PM PDT 24
Peak memory 201060 kb
Host smart-4d054c57-5d0e-428a-9948-31e793873ce5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685865114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.2685865114
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.210049133
Short name T254
Test name
Test status
Simulation time 43741865 ps
CPU time 0.78 seconds
Started Aug 01 06:49:07 PM PDT 24
Finished Aug 01 06:49:08 PM PDT 24
Peak memory 201100 kb
Host smart-c710f4ee-9a14-407a-8c17-261772b71d51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210049133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.210049133
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1591687008
Short name T98
Test name
Test status
Simulation time 309464330 ps
CPU time 2.03 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 201124 kb
Host smart-ffa9e8e4-d61d-4d7c-8e7a-54356f52292a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591687008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1591687008
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2048832579
Short name T565
Test name
Test status
Simulation time 27586241 ps
CPU time 0.86 seconds
Started Aug 01 06:49:05 PM PDT 24
Finished Aug 01 06:49:06 PM PDT 24
Peak memory 201024 kb
Host smart-1ed29c00-3d05-45b8-9d8d-22ebce5ad179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048832579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2048832579
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.2071712732
Short name T475
Test name
Test status
Simulation time 10122496982 ps
CPU time 37.72 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:54 PM PDT 24
Peak memory 201656 kb
Host smart-e9b92c40-0edf-4eaf-9eb4-f8cad56dfc03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071712732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.2071712732
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.1043347239
Short name T665
Test name
Test status
Simulation time 46266325 ps
CPU time 0.81 seconds
Started Aug 01 06:49:11 PM PDT 24
Finished Aug 01 06:49:12 PM PDT 24
Peak memory 201008 kb
Host smart-44bffe52-77bb-43e3-8962-e959099b906c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043347239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1043347239
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.236468513
Short name T277
Test name
Test status
Simulation time 17986536 ps
CPU time 0.79 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 201080 kb
Host smart-56d2d19e-b63d-42fa-a9d5-4f10c70eeb98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236468513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.236468513
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.103366527
Short name T457
Test name
Test status
Simulation time 57070466 ps
CPU time 0.93 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201056 kb
Host smart-bfa7e2cd-4416-49b3-b063-0c01f16ab75b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103366527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.103366527
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.3264717757
Short name T158
Test name
Test status
Simulation time 23095430 ps
CPU time 0.76 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 200988 kb
Host smart-c49729d0-f64f-41d5-9914-190edc941394
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264717757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3264717757
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3053230318
Short name T269
Test name
Test status
Simulation time 26526579 ps
CPU time 0.94 seconds
Started Aug 01 06:49:15 PM PDT 24
Finished Aug 01 06:49:16 PM PDT 24
Peak memory 201068 kb
Host smart-1d07d7e2-4a0a-4413-81fe-649f8f6b24d0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053230318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3053230318
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.1262887959
Short name T651
Test name
Test status
Simulation time 15388715 ps
CPU time 0.81 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201016 kb
Host smart-ecfe3fa3-4267-4af5-8059-f43d8be2c351
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262887959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1262887959
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.1113064480
Short name T559
Test name
Test status
Simulation time 1977573769 ps
CPU time 7.66 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:24 PM PDT 24
Peak memory 201316 kb
Host smart-539780f0-07f1-440c-9472-6a990a68ab18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113064480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.1113064480
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.2386399717
Short name T641
Test name
Test status
Simulation time 1099458195 ps
CPU time 6.26 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:28 PM PDT 24
Peak memory 201156 kb
Host smart-7e201ef9-db6b-41bf-96a5-1dae11a082d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386399717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.2386399717
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.1845319569
Short name T566
Test name
Test status
Simulation time 69684496 ps
CPU time 1.01 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201048 kb
Host smart-ca48d3fe-1ff1-4e57-9a3b-df5f7a6cd203
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845319569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.1845319569
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2644200268
Short name T571
Test name
Test status
Simulation time 14428564 ps
CPU time 0.77 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201088 kb
Host smart-146fe19f-3ddf-49e0-9335-c0ec446a6253
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644200268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2644200268
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1053751505
Short name T435
Test name
Test status
Simulation time 25169796 ps
CPU time 0.91 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201076 kb
Host smart-372bb48d-ca3d-4f65-b747-8dd99e419bab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053751505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1053751505
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.3095567246
Short name T748
Test name
Test status
Simulation time 40390354 ps
CPU time 0.81 seconds
Started Aug 01 06:49:15 PM PDT 24
Finished Aug 01 06:49:16 PM PDT 24
Peak memory 201004 kb
Host smart-c4044813-72cd-402f-a79a-f88000ff2677
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095567246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3095567246
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.2287779412
Short name T76
Test name
Test status
Simulation time 916286015 ps
CPU time 3.83 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201252 kb
Host smart-f8b69a47-6ae7-4138-9415-d177dcedfdaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287779412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2287779412
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1077617303
Short name T17
Test name
Test status
Simulation time 69352646 ps
CPU time 1.01 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201300 kb
Host smart-6cc41ea0-36e8-40b3-b785-b843e2fdba0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077617303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1077617303
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2012629319
Short name T396
Test name
Test status
Simulation time 2162600871 ps
CPU time 10.18 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:32 PM PDT 24
Peak memory 201368 kb
Host smart-d06b3b33-1c5c-47bb-9f59-4900c547a39e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012629319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2012629319
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2892509787
Short name T717
Test name
Test status
Simulation time 250956690986 ps
CPU time 1174.35 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 07:08:51 PM PDT 24
Peak memory 209856 kb
Host smart-65fe32ee-99b9-40cd-a305-e1230c4a92ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2892509787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2892509787
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.3658907693
Short name T48
Test name
Test status
Simulation time 28046365 ps
CPU time 0.93 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201080 kb
Host smart-1003f019-d0f1-4265-b03a-5ac410f60ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658907693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3658907693
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.150346298
Short name T185
Test name
Test status
Simulation time 13423953 ps
CPU time 0.79 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201300 kb
Host smart-b39e177c-c168-4445-9cdc-881892e3c6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150346298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.150346298
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1429343604
Short name T75
Test name
Test status
Simulation time 325911281 ps
CPU time 1.81 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201020 kb
Host smart-fcc5fd88-e543-4c17-a67d-f3157a3334f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429343604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1429343604
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.1502644849
Short name T402
Test name
Test status
Simulation time 33621224 ps
CPU time 0.78 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 200116 kb
Host smart-8fe13eb8-e803-498f-b563-6a3e51059ea2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502644849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1502644849
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.3053214089
Short name T470
Test name
Test status
Simulation time 41530223 ps
CPU time 0.95 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201112 kb
Host smart-ab70dbff-2274-43b2-8101-486eafe8f056
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053214089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.3053214089
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3722080642
Short name T501
Test name
Test status
Simulation time 57393028 ps
CPU time 0.91 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201068 kb
Host smart-52b9750e-7e86-44b1-9968-59da28109aee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722080642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3722080642
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3947578843
Short name T387
Test name
Test status
Simulation time 562155260 ps
CPU time 4.78 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 201120 kb
Host smart-eeff1db6-8d22-446e-8c56-e511392578f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947578843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3947578843
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.4072775076
Short name T379
Test name
Test status
Simulation time 2181823881 ps
CPU time 16.13 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:37 PM PDT 24
Peak memory 201484 kb
Host smart-b0981c83-a372-436f-93db-b685572334cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072775076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.4072775076
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1934908003
Short name T585
Test name
Test status
Simulation time 79714321 ps
CPU time 1.09 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201052 kb
Host smart-dcfc54f2-d645-4451-8b0a-a62ab99d42cc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934908003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1934908003
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.2970673128
Short name T695
Test name
Test status
Simulation time 68226961 ps
CPU time 1.03 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201108 kb
Host smart-62081951-a0c5-457e-a81b-74ebdcca77d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970673128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.2970673128
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.2280479811
Short name T448
Test name
Test status
Simulation time 69831329 ps
CPU time 1.02 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201072 kb
Host smart-82aa9fd8-8062-4e19-ad5e-5e988d541d22
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280479811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.2280479811
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.1809156298
Short name T207
Test name
Test status
Simulation time 19287200 ps
CPU time 0.82 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201032 kb
Host smart-7929c75b-8377-4747-9fcc-c697703824f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809156298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1809156298
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.1820095348
Short name T109
Test name
Test status
Simulation time 562890995 ps
CPU time 3.43 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201216 kb
Host smart-8e8b2ed8-e437-4ea0-9b1b-9728545be735
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820095348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1820095348
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.865545766
Short name T295
Test name
Test status
Simulation time 38588153 ps
CPU time 0.91 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 201028 kb
Host smart-ac009200-d913-4ac9-a22e-ccf4f9fc074a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865545766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.865545766
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.4009487197
Short name T589
Test name
Test status
Simulation time 4380671069 ps
CPU time 31.61 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:51 PM PDT 24
Peak memory 201472 kb
Host smart-3b42017a-87dd-4c87-99e0-1b5e834cd371
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009487197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.4009487197
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.2432674932
Short name T253
Test name
Test status
Simulation time 80024361 ps
CPU time 1.2 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 201044 kb
Host smart-e685afd4-d0e2-43ef-b94c-a9e6c347db63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432674932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2432674932
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.487996912
Short name T820
Test name
Test status
Simulation time 38017222 ps
CPU time 0.85 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201024 kb
Host smart-aa4da40e-1bc7-4fa4-a1e6-82f4e729f8de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487996912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.487996912
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.2176885959
Short name T91
Test name
Test status
Simulation time 77575750 ps
CPU time 1.06 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201072 kb
Host smart-463cc7bc-5f72-4f92-8660-d3b58b7662cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176885959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.2176885959
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.4192794615
Short name T285
Test name
Test status
Simulation time 17186737 ps
CPU time 0.73 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:19 PM PDT 24
Peak memory 200272 kb
Host smart-e07923c2-ac08-444d-a9c5-3879e85c833b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192794615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.4192794615
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.3421968231
Short name T20
Test name
Test status
Simulation time 82255202 ps
CPU time 1.06 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201084 kb
Host smart-a9680b97-dc7f-47bf-8f86-05ab335745fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421968231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.3421968231
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.300471848
Short name T412
Test name
Test status
Simulation time 43608605 ps
CPU time 0.84 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201036 kb
Host smart-99fcb00c-2b99-471f-a60e-b6161c5dfeec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300471848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.300471848
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.1088580291
Short name T14
Test name
Test status
Simulation time 2309524842 ps
CPU time 10.35 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:29 PM PDT 24
Peak memory 201392 kb
Host smart-ef807134-a5b9-43fa-a049-2d1a20225746
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088580291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1088580291
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1094374430
Short name T296
Test name
Test status
Simulation time 2538371908 ps
CPU time 10.26 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:29 PM PDT 24
Peak memory 201420 kb
Host smart-7c30a76c-d74a-438e-bd0e-48adbb6131a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094374430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1094374430
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.56929160
Short name T85
Test name
Test status
Simulation time 78174562 ps
CPU time 1.03 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201108 kb
Host smart-ea88b3b8-c140-498b-a51f-8ce79bde772c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56929160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
clkmgr_idle_intersig_mubi.56929160
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3829718909
Short name T542
Test name
Test status
Simulation time 85844382 ps
CPU time 1.1 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 201084 kb
Host smart-a4108334-529c-4355-8de9-e4f8515f68be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829718909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3829718909
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3122187411
Short name T558
Test name
Test status
Simulation time 72673019 ps
CPU time 1.03 seconds
Started Aug 01 06:49:17 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201056 kb
Host smart-c2a5e644-9f63-42df-9c5b-c3eb33c6289d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122187411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3122187411
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.4128253426
Short name T422
Test name
Test status
Simulation time 16325617 ps
CPU time 0.75 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201076 kb
Host smart-333cb462-9aa3-420a-832b-219232e645f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128253426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.4128253426
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.835567979
Short name T679
Test name
Test status
Simulation time 1273268053 ps
CPU time 5.74 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:25 PM PDT 24
Peak memory 201284 kb
Host smart-6d5c4704-8f95-4178-9b2e-c9b929c99c41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835567979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.835567979
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.1231235639
Short name T146
Test name
Test status
Simulation time 43304811 ps
CPU time 0.95 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201100 kb
Host smart-9b08a3b8-184f-4147-b3b5-2ad85667861a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231235639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1231235639
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.2546711247
Short name T26
Test name
Test status
Simulation time 5826899247 ps
CPU time 44.82 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:50:03 PM PDT 24
Peak memory 201388 kb
Host smart-36bca668-24a8-4bff-9575-1a74d341b318
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546711247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.2546711247
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.3325198064
Short name T593
Test name
Test status
Simulation time 154756763 ps
CPU time 1.28 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:20 PM PDT 24
Peak memory 201068 kb
Host smart-feb7bf4d-ad01-4502-a4bb-2ab01b4dfc08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325198064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.3325198064
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.1870476249
Short name T393
Test name
Test status
Simulation time 42834062 ps
CPU time 0.93 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201020 kb
Host smart-a6b2f7b8-400d-4f69-995b-9d118386514a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870476249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.1870476249
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.2070157493
Short name T823
Test name
Test status
Simulation time 26602552 ps
CPU time 0.88 seconds
Started Aug 01 06:49:16 PM PDT 24
Finished Aug 01 06:49:17 PM PDT 24
Peak memory 201080 kb
Host smart-781f3408-b151-43a3-909d-2c9a1702af0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070157493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.2070157493
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.1542781583
Short name T611
Test name
Test status
Simulation time 16594604 ps
CPU time 0.86 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201032 kb
Host smart-f8c7f98c-cb9b-410f-b1cd-e4cc15352acf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542781583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.1542781583
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1394592251
Short name T70
Test name
Test status
Simulation time 20832437 ps
CPU time 0.84 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201080 kb
Host smart-818ca44a-2a8d-4bc6-a312-f9cf6e8c1a92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394592251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1394592251
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.3132966465
Short name T319
Test name
Test status
Simulation time 202306682 ps
CPU time 1.81 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:22 PM PDT 24
Peak memory 201184 kb
Host smart-c1e1632d-0ebb-4926-836f-97d2135c0a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132966465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.3132966465
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.2310671850
Short name T664
Test name
Test status
Simulation time 2328218305 ps
CPU time 9.71 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:28 PM PDT 24
Peak memory 201432 kb
Host smart-79dbab7a-3c8f-48b8-88e6-d0de210b95c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310671850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.2310671850
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3234903867
Short name T351
Test name
Test status
Simulation time 61124480 ps
CPU time 1.09 seconds
Started Aug 01 06:49:21 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 200876 kb
Host smart-277fb0d6-cbae-4346-ac61-6371a208179e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234903867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.3234903867
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.22365072
Short name T523
Test name
Test status
Simulation time 52478796 ps
CPU time 0.9 seconds
Started Aug 01 06:49:22 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201120 kb
Host smart-9f109e83-c9c9-4814-8a70-7868efaf9483
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_lc_clk_byp_req_intersig_mubi.22365072
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1780774391
Short name T374
Test name
Test status
Simulation time 51315724 ps
CPU time 0.95 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201072 kb
Host smart-35f6e41e-2ff9-4a61-b79c-aa8b4c5ed4b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780774391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1780774391
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1780595613
Short name T209
Test name
Test status
Simulation time 12383705 ps
CPU time 0.7 seconds
Started Aug 01 06:49:18 PM PDT 24
Finished Aug 01 06:49:18 PM PDT 24
Peak memory 201020 kb
Host smart-a66d8e33-e1ba-415e-b41e-ecfc13d7e81d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780595613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1780595613
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1261145336
Short name T162
Test name
Test status
Simulation time 1067991227 ps
CPU time 4.17 seconds
Started Aug 01 06:49:19 PM PDT 24
Finished Aug 01 06:49:23 PM PDT 24
Peak memory 201208 kb
Host smart-f0126cf0-6791-44bd-bb92-f1d8c1d46e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261145336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1261145336
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.2517579837
Short name T332
Test name
Test status
Simulation time 21422020 ps
CPU time 0.88 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201088 kb
Host smart-ffdb6975-6c92-43c6-935f-bc9b6069666b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517579837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2517579837
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.2849029679
Short name T702
Test name
Test status
Simulation time 2629609143 ps
CPU time 21.22 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:41 PM PDT 24
Peak memory 201400 kb
Host smart-fe16528f-f2d8-4983-a5e8-635e7cf136b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849029679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.2849029679
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3149112387
Short name T751
Test name
Test status
Simulation time 13547576 ps
CPU time 0.76 seconds
Started Aug 01 06:49:20 PM PDT 24
Finished Aug 01 06:49:21 PM PDT 24
Peak memory 201080 kb
Host smart-7ecbc50c-d032-4fae-984f-c27a614974cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149112387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3149112387
Directory /workspace/9.clkmgr_trans/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%