Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172309532

1

T4

3142

T5

2872

T6

3116

auto[1]

277124

1

T5

956

T22

178

T15

446

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172294532

1

T4

3142

T5

3270

T6

3036

auto[1]

292124

1

T5

558

T6

80

T22

278

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172232084

1

T4

3142

T5

3036

T6

2808

auto[1]

354572

1

T5

792

T6

308

T22

124

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162429416

1

T4

3142

T5

538

T6

692

auto[1]

10157240

1

T5

3290

T6

2424

T22

496

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106750130

1

T4

3122

T5

3184

T6

2966

auto[1]

65836526

1

T4

20

T5

644

T6

150

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

99985528

1

T4

3122

T5

250

T6

516

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

62181686

1

T4

20

T6

22

T23

908

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

21840

1

T5

72

T22

4

T15

46

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4910

1

T15

16

T2

20

T80

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

6340760

1

T5

2186

T6

2154

T22

276

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3576512

1

T5

270

T6

116

T17

1650

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

34244

1

T5

148

T22

30

T17

28

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8278

1

T5

34

T17

60

T80

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

41680

1

T5

12

T22

10

T15

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1106

1

T8

10

T13

70

T14

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7838

1

T5

64

T22

78

T15

64

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2584

1

T8

64

T14

64

T26

210

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7382

1

T22

66

T17

20

T2

38

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2074

1

T8

38

T10

12

T12

20

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12332

1

T17

56

T80

58

T8

820

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3330

1

T8

116

T10

36

T12

170

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

40410

1

T5

2

T6

116

T15

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2686

1

T2

34

T80

2

T117

16

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22276

1

T5

64

T15

90

T17

76

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5302

1

T80

58

T117

44

T8

104

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

19780

1

T5

18

T6

112

T17

108

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4778

1

T5

54

T17

36

T2

68

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36204

1

T5

68

T17

178

T2

176

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9338

1

T5

104

T17

190

T2

66

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

64228

1

T5

2

T6

38

T15

32

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4494

1

T15

10

T2

14

T116

100

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34426

1

T5

72

T15

106

T17

66

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8422

1

T15

124

T2

166

T8

172

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28868

1

T5

46

T6

30

T22

58

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7560

1

T5

32

T6

12

T17

22

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52334

1

T5

180

T22

66

T17

118

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13466

1

T5

150

T17

56

T8

516