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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 983
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T798 /workspace/coverage/default/9.clkmgr_stress_all.1062701144 Aug 03 05:08:19 PM PDT 24 Aug 03 05:08:52 PM PDT 24 6422970690 ps
T799 /workspace/coverage/default/3.clkmgr_frequency.578474144 Aug 03 05:08:05 PM PDT 24 Aug 03 05:08:18 PM PDT 24 1759556496 ps
T800 /workspace/coverage/default/23.clkmgr_stress_all.1788122073 Aug 03 05:08:55 PM PDT 24 Aug 03 05:09:42 PM PDT 24 6718615619 ps
T801 /workspace/coverage/default/17.clkmgr_extclk.2908480656 Aug 03 05:08:37 PM PDT 24 Aug 03 05:08:38 PM PDT 24 28841445 ps
T802 /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.669482949 Aug 03 05:08:24 PM PDT 24 Aug 03 05:08:25 PM PDT 24 39714945 ps
T803 /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2192415699 Aug 03 05:09:20 PM PDT 24 Aug 03 05:09:21 PM PDT 24 21792839 ps
T804 /workspace/coverage/default/5.clkmgr_stress_all.3679502271 Aug 03 05:08:09 PM PDT 24 Aug 03 05:08:16 PM PDT 24 932855568 ps
T805 /workspace/coverage/default/19.clkmgr_frequency_timeout.1320369646 Aug 03 05:08:44 PM PDT 24 Aug 03 05:08:54 PM PDT 24 1342869944 ps
T806 /workspace/coverage/default/37.clkmgr_clk_status.2405033721 Aug 03 05:09:22 PM PDT 24 Aug 03 05:09:23 PM PDT 24 58229424 ps
T807 /workspace/coverage/default/2.clkmgr_regwen.85289328 Aug 03 05:08:01 PM PDT 24 Aug 03 05:08:05 PM PDT 24 567544030 ps
T808 /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2609575566 Aug 03 05:09:37 PM PDT 24 Aug 03 05:09:38 PM PDT 24 69773491 ps
T809 /workspace/coverage/default/35.clkmgr_trans.1800144908 Aug 03 05:09:14 PM PDT 24 Aug 03 05:09:16 PM PDT 24 38476877 ps
T810 /workspace/coverage/default/18.clkmgr_stress_all.715483950 Aug 03 05:08:43 PM PDT 24 Aug 03 05:10:20 PM PDT 24 13001524356 ps
T811 /workspace/coverage/default/22.clkmgr_peri.517785020 Aug 03 05:08:45 PM PDT 24 Aug 03 05:08:46 PM PDT 24 46477646 ps
T157 /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3481381916 Aug 03 05:08:44 PM PDT 24 Aug 03 05:18:01 PM PDT 24 60326365438 ps
T812 /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3475841456 Aug 03 05:08:02 PM PDT 24 Aug 03 05:08:03 PM PDT 24 49017702 ps
T813 /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3467533214 Aug 03 05:07:52 PM PDT 24 Aug 03 05:07:53 PM PDT 24 19371379 ps
T814 /workspace/coverage/default/26.clkmgr_stress_all.701929232 Aug 03 05:08:53 PM PDT 24 Aug 03 05:09:24 PM PDT 24 4160845053 ps
T815 /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2472428602 Aug 03 05:09:20 PM PDT 24 Aug 03 05:09:21 PM PDT 24 22557032 ps
T816 /workspace/coverage/default/29.clkmgr_div_intersig_mubi.2043259001 Aug 03 05:09:02 PM PDT 24 Aug 03 05:09:03 PM PDT 24 53256218 ps
T817 /workspace/coverage/default/46.clkmgr_peri.1317840235 Aug 03 05:09:45 PM PDT 24 Aug 03 05:09:46 PM PDT 24 23965770 ps
T818 /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1220558597 Aug 03 05:08:57 PM PDT 24 Aug 03 05:08:59 PM PDT 24 168058020 ps
T819 /workspace/coverage/default/10.clkmgr_alert_test.862802361 Aug 03 05:08:19 PM PDT 24 Aug 03 05:08:20 PM PDT 24 12414161 ps
T820 /workspace/coverage/default/46.clkmgr_frequency_timeout.4183188853 Aug 03 05:09:52 PM PDT 24 Aug 03 05:10:00 PM PDT 24 1099507833 ps
T821 /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2738347648 Aug 03 05:09:11 PM PDT 24 Aug 03 05:09:12 PM PDT 24 20777751 ps
T822 /workspace/coverage/default/4.clkmgr_smoke.1126092891 Aug 03 05:08:03 PM PDT 24 Aug 03 05:08:04 PM PDT 24 78122514 ps
T823 /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.2256887037 Aug 03 05:08:43 PM PDT 24 Aug 03 05:08:44 PM PDT 24 36165524 ps
T36 /workspace/coverage/default/0.clkmgr_stress_all.3807132366 Aug 03 05:08:00 PM PDT 24 Aug 03 05:08:12 PM PDT 24 2922351973 ps
T106 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3665157489 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:11 PM PDT 24 215682168 ps
T824 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3938726725 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:19 PM PDT 24 545488474 ps
T825 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3965163168 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:32 PM PDT 24 24744812 ps
T86 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.447042100 Aug 03 04:51:32 PM PDT 24 Aug 03 04:51:33 PM PDT 24 60362220 ps
T826 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1227047358 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:30 PM PDT 24 72451676 ps
T827 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.691737309 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 25132899 ps
T54 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4091149287 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:08 PM PDT 24 105393577 ps
T828 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2639687895 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 35993072 ps
T107 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2714734237 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:34 PM PDT 24 129955299 ps
T55 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.157432985 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:21 PM PDT 24 150212657 ps
T158 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2071118929 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:13 PM PDT 24 519652280 ps
T56 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2882788666 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:28 PM PDT 24 200245401 ps
T829 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2673581945 Aug 03 04:51:17 PM PDT 24 Aug 03 04:51:18 PM PDT 24 20538276 ps
T64 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1393720047 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:23 PM PDT 24 89314145 ps
T830 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.429922704 Aug 03 04:51:41 PM PDT 24 Aug 03 04:51:42 PM PDT 24 13247525 ps
T87 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3802325288 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:21 PM PDT 24 39982526 ps
T831 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.536611305 Aug 03 04:51:06 PM PDT 24 Aug 03 04:51:07 PM PDT 24 57950790 ps
T108 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4289176092 Aug 03 04:51:21 PM PDT 24 Aug 03 04:51:23 PM PDT 24 226387688 ps
T832 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.206614909 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 22140229 ps
T60 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.487050339 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:24 PM PDT 24 599743072 ps
T112 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3710008030 Aug 03 04:51:11 PM PDT 24 Aug 03 04:51:13 PM PDT 24 78560723 ps
T833 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2188363658 Aug 03 04:51:44 PM PDT 24 Aug 03 04:51:44 PM PDT 24 12089577 ps
T88 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1556238464 Aug 03 04:51:24 PM PDT 24 Aug 03 04:51:26 PM PDT 24 227452147 ps
T89 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1796375479 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:20 PM PDT 24 46601188 ps
T834 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.683578553 Aug 03 04:51:36 PM PDT 24 Aug 03 04:51:37 PM PDT 24 33427390 ps
T835 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3429400920 Aug 03 04:51:24 PM PDT 24 Aug 03 04:51:25 PM PDT 24 49543291 ps
T836 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.655680569 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:34 PM PDT 24 78577696 ps
T109 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1771487507 Aug 03 04:51:39 PM PDT 24 Aug 03 04:51:41 PM PDT 24 371331434 ps
T837 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3688615295 Aug 03 04:51:27 PM PDT 24 Aug 03 04:51:29 PM PDT 24 81079342 ps
T57 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.920348155 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:11 PM PDT 24 131326648 ps
T90 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1170684226 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:20 PM PDT 24 71483380 ps
T159 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2016001060 Aug 03 04:51:16 PM PDT 24 Aug 03 04:51:16 PM PDT 24 52337552 ps
T58 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4158386379 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:34 PM PDT 24 104390080 ps
T838 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2223217216 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:22 PM PDT 24 122455361 ps
T59 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.779422993 Aug 03 04:51:13 PM PDT 24 Aug 03 04:51:15 PM PDT 24 95459515 ps
T839 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3266610736 Aug 03 04:51:35 PM PDT 24 Aug 03 04:51:37 PM PDT 24 68907353 ps
T63 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1260457488 Aug 03 04:51:16 PM PDT 24 Aug 03 04:51:19 PM PDT 24 660849930 ps
T840 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3899451414 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:36 PM PDT 24 84609469 ps
T841 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3478211863 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:29 PM PDT 24 92295903 ps
T842 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1189681129 Aug 03 04:51:36 PM PDT 24 Aug 03 04:51:37 PM PDT 24 13014426 ps
T61 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1268167290 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:30 PM PDT 24 57055306 ps
T843 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3142549863 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:29 PM PDT 24 24109562 ps
T844 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.284393565 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:20 PM PDT 24 14601171 ps
T845 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.162874367 Aug 03 04:51:42 PM PDT 24 Aug 03 04:51:43 PM PDT 24 35707174 ps
T62 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2566526344 Aug 03 04:51:10 PM PDT 24 Aug 03 04:51:12 PM PDT 24 326909979 ps
T846 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.14476241 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 13840782 ps
T847 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3210207833 Aug 03 04:51:12 PM PDT 24 Aug 03 04:51:14 PM PDT 24 222843911 ps
T113 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1763862731 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:10 PM PDT 24 131064934 ps
T848 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1586136647 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 19774930 ps
T849 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.283636185 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:27 PM PDT 24 35238394 ps
T850 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3970244869 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 14088872 ps
T851 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1335986182 Aug 03 04:51:27 PM PDT 24 Aug 03 04:51:28 PM PDT 24 53136770 ps
T852 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.175962820 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:08 PM PDT 24 19212285 ps
T853 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.787761919 Aug 03 04:51:11 PM PDT 24 Aug 03 04:51:12 PM PDT 24 13477740 ps
T854 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3704379575 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:22 PM PDT 24 18960974 ps
T65 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1604687334 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:30 PM PDT 24 113289493 ps
T855 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2455072995 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:23 PM PDT 24 21691283 ps
T121 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2228671164 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:31 PM PDT 24 390560629 ps
T856 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1889369986 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:27 PM PDT 24 13957407 ps
T857 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1259918332 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:09 PM PDT 24 12677905 ps
T858 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2955679999 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:28 PM PDT 24 51754696 ps
T859 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3567830001 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 35161462 ps
T860 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2413636785 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:15 PM PDT 24 10557296 ps
T168 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.319802044 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:32 PM PDT 24 527254956 ps
T861 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1258161977 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:10 PM PDT 24 40748991 ps
T122 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.422251446 Aug 03 04:51:25 PM PDT 24 Aug 03 04:51:27 PM PDT 24 175939762 ps
T862 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.58206026 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:19 PM PDT 24 43167307 ps
T863 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3893093640 Aug 03 04:51:40 PM PDT 24 Aug 03 04:51:41 PM PDT 24 29320476 ps
T128 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.515902257 Aug 03 04:51:16 PM PDT 24 Aug 03 04:51:18 PM PDT 24 108689688 ps
T864 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.4017435141 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 29017348 ps
T865 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2497186050 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:22 PM PDT 24 78141104 ps
T866 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.4268238849 Aug 03 04:51:40 PM PDT 24 Aug 03 04:51:41 PM PDT 24 29547022 ps
T867 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3644976136 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:17 PM PDT 24 56418338 ps
T868 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3651401654 Aug 03 04:51:35 PM PDT 24 Aug 03 04:51:36 PM PDT 24 54215395 ps
T869 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.553202589 Aug 03 04:51:35 PM PDT 24 Aug 03 04:51:36 PM PDT 24 42822853 ps
T870 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2158150765 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:36 PM PDT 24 101998389 ps
T871 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2778097321 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:15 PM PDT 24 97653525 ps
T110 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3064026720 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:25 PM PDT 24 223959196 ps
T872 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1998536336 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 93363747 ps
T169 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.4234345671 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:17 PM PDT 24 85788661 ps
T873 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3498134259 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:26 PM PDT 24 79287372 ps
T874 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1650907455 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 24004129 ps
T875 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2464622975 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:33 PM PDT 24 127868511 ps
T876 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3371660414 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:18 PM PDT 24 274379803 ps
T877 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2406174860 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:24 PM PDT 24 91970493 ps
T878 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.76993336 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:29 PM PDT 24 275672915 ps
T879 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.870064461 Aug 03 04:51:43 PM PDT 24 Aug 03 04:51:43 PM PDT 24 34304614 ps
T880 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2645951528 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:34 PM PDT 24 35590613 ps
T881 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2606430105 Aug 03 04:51:36 PM PDT 24 Aug 03 04:51:38 PM PDT 24 88576470 ps
T882 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.55319519 Aug 03 04:51:40 PM PDT 24 Aug 03 04:51:41 PM PDT 24 49628305 ps
T883 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.461078890 Aug 03 04:51:39 PM PDT 24 Aug 03 04:51:40 PM PDT 24 29174026 ps
T884 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1710191747 Aug 03 04:51:06 PM PDT 24 Aug 03 04:51:08 PM PDT 24 60634491 ps
T129 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2256894066 Aug 03 04:51:11 PM PDT 24 Aug 03 04:51:14 PM PDT 24 590530680 ps
T885 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1834895270 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 13741266 ps
T127 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1159589513 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:24 PM PDT 24 472523125 ps
T886 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.333384464 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 146052851 ps
T123 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2658276386 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:17 PM PDT 24 249068037 ps
T887 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.740988 Aug 03 04:51:25 PM PDT 24 Aug 03 04:51:26 PM PDT 24 35778535 ps
T133 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2364850217 Aug 03 04:51:05 PM PDT 24 Aug 03 04:51:07 PM PDT 24 235202950 ps
T888 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3695658480 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 22686625 ps
T889 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2075107684 Aug 03 04:51:41 PM PDT 24 Aug 03 04:51:42 PM PDT 24 39297001 ps
T890 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4064634486 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:27 PM PDT 24 18485096 ps
T891 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3916718427 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:29 PM PDT 24 15450988 ps
T124 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1935534490 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:36 PM PDT 24 158104425 ps
T892 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.112842158 Aug 03 04:51:40 PM PDT 24 Aug 03 04:51:41 PM PDT 24 15261875 ps
T893 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1654978972 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:19 PM PDT 24 41938825 ps
T894 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.490466752 Aug 03 04:51:22 PM PDT 24 Aug 03 04:51:23 PM PDT 24 117927434 ps
T130 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.966126409 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:21 PM PDT 24 241303407 ps
T895 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3962846889 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:29 PM PDT 24 39453767 ps
T896 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3167278474 Aug 03 04:51:25 PM PDT 24 Aug 03 04:51:26 PM PDT 24 74112237 ps
T897 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.944575140 Aug 03 04:51:17 PM PDT 24 Aug 03 04:51:18 PM PDT 24 30586061 ps
T898 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3354163671 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:29 PM PDT 24 33107568 ps
T899 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2109934642 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:29 PM PDT 24 223716071 ps
T900 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2087019759 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 33025628 ps
T901 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2823478279 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:35 PM PDT 24 13860853 ps
T902 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3238909446 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 13355082 ps
T903 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.637053652 Aug 03 04:51:44 PM PDT 24 Aug 03 04:51:44 PM PDT 24 35818562 ps
T904 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1534904934 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:10 PM PDT 24 195359244 ps
T905 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1639839937 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:07 PM PDT 24 14537417 ps
T906 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.120528103 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:22 PM PDT 24 311027998 ps
T907 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3800923131 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 35314731 ps
T125 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1265455360 Aug 03 04:51:17 PM PDT 24 Aug 03 04:51:21 PM PDT 24 253333080 ps
T908 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.615573682 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:27 PM PDT 24 38357798 ps
T909 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.723438082 Aug 03 04:51:21 PM PDT 24 Aug 03 04:51:25 PM PDT 24 327582820 ps
T910 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.624174092 Aug 03 04:51:06 PM PDT 24 Aug 03 04:51:07 PM PDT 24 35557974 ps
T911 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2402876445 Aug 03 04:51:19 PM PDT 24 Aug 03 04:51:22 PM PDT 24 226149467 ps
T912 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1768042174 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:27 PM PDT 24 139361452 ps
T913 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.662163709 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:21 PM PDT 24 53424337 ps
T914 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3760498818 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:08 PM PDT 24 90230767 ps
T915 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1605319922 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:17 PM PDT 24 74876946 ps
T134 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.823410631 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:35 PM PDT 24 248276218 ps
T916 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1409976742 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:24 PM PDT 24 28248663 ps
T126 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1381290161 Aug 03 04:51:27 PM PDT 24 Aug 03 04:51:30 PM PDT 24 169684327 ps
T917 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2663204398 Aug 03 04:51:37 PM PDT 24 Aug 03 04:51:38 PM PDT 24 11135165 ps
T918 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1156567635 Aug 03 04:51:16 PM PDT 24 Aug 03 04:51:18 PM PDT 24 234036780 ps
T919 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1231021140 Aug 03 04:51:43 PM PDT 24 Aug 03 04:51:43 PM PDT 24 19428750 ps
T920 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1342175294 Aug 03 04:51:42 PM PDT 24 Aug 03 04:51:43 PM PDT 24 19763682 ps
T921 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.4048060443 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:25 PM PDT 24 27921019 ps
T922 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1161759751 Aug 03 04:51:42 PM PDT 24 Aug 03 04:51:42 PM PDT 24 23399307 ps
T923 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1754100905 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:24 PM PDT 24 25744621 ps
T135 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3792355272 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:18 PM PDT 24 151427720 ps
T924 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3130219643 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 11658347 ps
T925 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2015133019 Aug 03 04:51:37 PM PDT 24 Aug 03 04:51:38 PM PDT 24 24797941 ps
T926 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2464387584 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 70084389 ps
T927 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.258804939 Aug 03 04:51:10 PM PDT 24 Aug 03 04:51:11 PM PDT 24 19088773 ps
T928 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1295460015 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 112555847 ps
T929 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3286460031 Aug 03 04:51:36 PM PDT 24 Aug 03 04:51:38 PM PDT 24 94501145 ps
T930 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1566242519 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:16 PM PDT 24 50210554 ps
T931 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4092702861 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:30 PM PDT 24 42930532 ps
T932 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.736464640 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:21 PM PDT 24 148687104 ps
T933 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1502715260 Aug 03 04:51:39 PM PDT 24 Aug 03 04:51:40 PM PDT 24 22673190 ps
T934 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2200255124 Aug 03 04:51:34 PM PDT 24 Aug 03 04:51:35 PM PDT 24 72156216 ps
T935 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1753149429 Aug 03 04:51:20 PM PDT 24 Aug 03 04:51:21 PM PDT 24 46601049 ps
T936 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3414158730 Aug 03 04:51:24 PM PDT 24 Aug 03 04:51:26 PM PDT 24 121774577 ps
T131 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.301872363 Aug 03 04:51:21 PM PDT 24 Aug 03 04:51:23 PM PDT 24 199003098 ps
T937 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3889142475 Aug 03 04:51:05 PM PDT 24 Aug 03 04:51:07 PM PDT 24 28457873 ps
T938 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1456645531 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:08 PM PDT 24 23655075 ps
T939 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2456014821 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 67282592 ps
T940 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3421998178 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:19 PM PDT 24 21243761 ps
T941 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.76916913 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 81661709 ps
T942 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.4141216741 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:15 PM PDT 24 1358121477 ps
T943 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.908912366 Aug 03 04:51:27 PM PDT 24 Aug 03 04:51:28 PM PDT 24 25366119 ps
T944 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2583727880 Aug 03 04:51:21 PM PDT 24 Aug 03 04:51:23 PM PDT 24 77351054 ps
T945 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2219759888 Aug 03 04:51:26 PM PDT 24 Aug 03 04:51:28 PM PDT 24 119921675 ps
T946 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2627114775 Aug 03 04:51:13 PM PDT 24 Aug 03 04:51:15 PM PDT 24 323298560 ps
T947 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3443219892 Aug 03 04:51:28 PM PDT 24 Aug 03 04:51:30 PM PDT 24 317804557 ps
T111 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1594418166 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:19 PM PDT 24 435973015 ps
T948 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1195642999 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:15 PM PDT 24 41229551 ps
T114 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.101730880 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:35 PM PDT 24 57844621 ps
T949 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1932778482 Aug 03 04:51:06 PM PDT 24 Aug 03 04:51:07 PM PDT 24 57201096 ps
T950 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.764061127 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:16 PM PDT 24 34846648 ps
T951 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3561641776 Aug 03 04:51:21 PM PDT 24 Aug 03 04:51:24 PM PDT 24 107830181 ps
T952 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2227775047 Aug 03 04:51:44 PM PDT 24 Aug 03 04:51:45 PM PDT 24 23426625 ps
T953 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1385893796 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:18 PM PDT 24 305378199 ps
T954 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1375559105 Aug 03 04:51:37 PM PDT 24 Aug 03 04:51:38 PM PDT 24 17796454 ps
T955 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.797476943 Aug 03 04:51:33 PM PDT 24 Aug 03 04:51:34 PM PDT 24 18352291 ps
T956 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2665756049 Aug 03 04:51:41 PM PDT 24 Aug 03 04:51:42 PM PDT 24 32673997 ps
T957 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.4055369540 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:10 PM PDT 24 89573158 ps
T958 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1370284837 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 78934286 ps
T959 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2209923561 Aug 03 04:51:14 PM PDT 24 Aug 03 04:51:15 PM PDT 24 15749497 ps
T960 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2360529693 Aug 03 04:51:13 PM PDT 24 Aug 03 04:51:16 PM PDT 24 425437373 ps
T961 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3181228066 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 84812651 ps
T962 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1597277144 Aug 03 04:51:25 PM PDT 24 Aug 03 04:51:26 PM PDT 24 34761441 ps
T963 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2013874118 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 23688705 ps
T964 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1922974060 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:32 PM PDT 24 78007048 ps
T965 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.806624175 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:10 PM PDT 24 105603576 ps
T966 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4287561608 Aug 03 04:51:31 PM PDT 24 Aug 03 04:51:36 PM PDT 24 584468271 ps
T967 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2184713416 Aug 03 04:51:36 PM PDT 24 Aug 03 04:51:37 PM PDT 24 12211800 ps
T968 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.873910910 Aug 03 04:51:11 PM PDT 24 Aug 03 04:51:14 PM PDT 24 407661832 ps
T969 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1329324914 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:11 PM PDT 24 187855537 ps
T970 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3888271038 Aug 03 04:51:23 PM PDT 24 Aug 03 04:51:25 PM PDT 24 88449742 ps
T971 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1711967670 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:11 PM PDT 24 280030737 ps
T972 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.331948724 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 85818990 ps
T973 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1598096848 Aug 03 04:51:32 PM PDT 24 Aug 03 04:51:33 PM PDT 24 22388154 ps
T132 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.245500195 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 116089222 ps
T974 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3812509898 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:10 PM PDT 24 46497962 ps
T975 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4272293548 Aug 03 04:51:18 PM PDT 24 Aug 03 04:51:20 PM PDT 24 56195211 ps
T976 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3509294636 Aug 03 04:51:29 PM PDT 24 Aug 03 04:51:33 PM PDT 24 126313461 ps
T977 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.356043387 Aug 03 04:51:27 PM PDT 24 Aug 03 04:51:28 PM PDT 24 44684448 ps
T978 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3146729372 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 22506602 ps
T979 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1706091032 Aug 03 04:51:15 PM PDT 24 Aug 03 04:51:16 PM PDT 24 18172333 ps
T980 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.689435938 Aug 03 04:51:07 PM PDT 24 Aug 03 04:51:09 PM PDT 24 72601828 ps
T981 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.345205042 Aug 03 04:51:11 PM PDT 24 Aug 03 04:51:21 PM PDT 24 1373227459 ps
T982 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3375377800 Aug 03 04:51:09 PM PDT 24 Aug 03 04:51:17 PM PDT 24 703291473 ps
T983 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2470562267 Aug 03 04:51:08 PM PDT 24 Aug 03 04:51:09 PM PDT 24 77942048 ps

Test location /workspace/coverage/default/48.clkmgr_frequency.3495440404
Short name T1
Test name
Test status
Simulation time 1521596629 ps
CPU time 11.29 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:10:06 PM PDT 24
Peak memory 201132 kb
Host smart-90697b13-7b09-4dd5-90ac-344d2fce006d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495440404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3495440404
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.4178857824
Short name T2
Test name
Test status
Simulation time 1221424943 ps
CPU time 6.41 seconds
Started Aug 03 05:08:10 PM PDT 24
Finished Aug 03 05:08:16 PM PDT 24
Peak memory 201276 kb
Host smart-fe38664b-eafb-4e1a-91ac-8fcf240d05dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178857824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.4178857824
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.1631937629
Short name T8
Test name
Test status
Simulation time 178962598230 ps
CPU time 1176.62 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:28:08 PM PDT 24
Peak memory 217976 kb
Host smart-0feb9f83-68c4-42c2-8339-745c9cd68abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1631937629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.1631937629
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2882788666
Short name T56
Test name
Test status
Simulation time 200245401 ps
CPU time 2.15 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 200724 kb
Host smart-b183c7c4-54c5-4fdc-bf79-fa43e531f33a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882788666 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.2882788666
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.3575760871
Short name T47
Test name
Test status
Simulation time 968595143 ps
CPU time 5.55 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201420 kb
Host smart-b27521cd-4d24-4138-af94-d971115d170c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575760871 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3575760871
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.458761428
Short name T42
Test name
Test status
Simulation time 296168415 ps
CPU time 3.12 seconds
Started Aug 03 05:07:55 PM PDT 24
Finished Aug 03 05:07:58 PM PDT 24
Peak memory 217792 kb
Host smart-591f54c0-8820-4146-b907-916068d19366
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458761428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.458761428
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.3459194787
Short name T21
Test name
Test status
Simulation time 29980583 ps
CPU time 0.74 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201012 kb
Host smart-8f060c1e-8c73-4260-9f18-56a9a7ff5c03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459194787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.3459194787
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.44248412
Short name T23
Test name
Test status
Simulation time 24777238 ps
CPU time 0.84 seconds
Started Aug 03 05:10:02 PM PDT 24
Finished Aug 03 05:10:03 PM PDT 24
Peak memory 201080 kb
Host smart-685ef62c-71fb-4ad0-84f5-b9d61ff45ac6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44248412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.clkmgr_idle_intersig_mubi.44248412
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.1935534490
Short name T124
Test name
Test status
Simulation time 158104425 ps
CPU time 2.03 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 200776 kb
Host smart-b4e15ae4-825a-4dc6-813a-d74715549aec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935534490 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.1935534490
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3665157489
Short name T106
Test name
Test status
Simulation time 215682168 ps
CPU time 1.94 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 200520 kb
Host smart-5269abbf-629c-4f63-98c6-f31495f67532
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665157489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3665157489
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3824363796
Short name T206
Test name
Test status
Simulation time 27412696 ps
CPU time 0.8 seconds
Started Aug 03 05:08:23 PM PDT 24
Finished Aug 03 05:08:24 PM PDT 24
Peak memory 201060 kb
Host smart-53adb4a4-e8fa-43e3-9f61-ae1a3d1e09ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824363796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3824363796
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3710008030
Short name T112
Test name
Test status
Simulation time 78560723 ps
CPU time 1.64 seconds
Started Aug 03 04:51:11 PM PDT 24
Finished Aug 03 04:51:13 PM PDT 24
Peak memory 200488 kb
Host smart-72825946-852f-44ec-bc4b-669bde4b0048
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710008030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3710008030
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.2825662395
Short name T74
Test name
Test status
Simulation time 40128087 ps
CPU time 0.88 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 200920 kb
Host smart-6289d236-fb09-439a-af0d-80148c07cf27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825662395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.2825662395
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3785598005
Short name T7
Test name
Test status
Simulation time 460918656 ps
CPU time 2.96 seconds
Started Aug 03 05:07:54 PM PDT 24
Finished Aug 03 05:07:57 PM PDT 24
Peak memory 201016 kb
Host smart-ca74e96e-f8a8-4290-be76-9e5c8d7e9d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785598005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3785598005
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.487050339
Short name T60
Test name
Test status
Simulation time 599743072 ps
CPU time 3.76 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 217136 kb
Host smart-bcb567ef-c8da-43ea-8876-31427938fdeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487050339 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.487050339
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.4136542776
Short name T217
Test name
Test status
Simulation time 25797140 ps
CPU time 0.94 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:29 PM PDT 24
Peak memory 201016 kb
Host smart-98decf49-14b3-4c57-a787-9df98e8cee29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136542776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.4136542776
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2219759888
Short name T945
Test name
Test status
Simulation time 119921675 ps
CPU time 2.16 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 217092 kb
Host smart-4c391e94-7f74-4385-8a91-3198ac19b67a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219759888 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2219759888
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2874509616
Short name T91
Test name
Test status
Simulation time 22215564 ps
CPU time 0.84 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201076 kb
Host smart-58d5f02f-8926-49a7-95b1-0a16a507c204
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874509616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2874509616
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.1594418166
Short name T111
Test name
Test status
Simulation time 435973015 ps
CPU time 3.48 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 200532 kb
Host smart-72980a86-6486-4b10-bbaf-fd362333d03b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594418166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.1594418166
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.2714734237
Short name T107
Test name
Test status
Simulation time 129955299 ps
CPU time 2.39 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:34 PM PDT 24
Peak memory 200572 kb
Host smart-57a48f3b-5a35-4b14-9dbf-6293a835ceda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714734237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.2714734237
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.1771487507
Short name T109
Test name
Test status
Simulation time 371331434 ps
CPU time 2.35 seconds
Started Aug 03 04:51:39 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 200524 kb
Host smart-1ef1e70d-ed46-46ae-b92c-3129e9101f0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771487507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.1771487507
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2265649089
Short name T226
Test name
Test status
Simulation time 724645050 ps
CPU time 3.35 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201204 kb
Host smart-84d8396f-34a1-4f61-b875-7e9d748e07b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265649089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2265649089
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.624174092
Short name T910
Test name
Test status
Simulation time 35557974 ps
CPU time 1.25 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 200280 kb
Host smart-42032b1b-847f-417b-aaa8-ebf5b1298688
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624174092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_aliasing.624174092
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3375377800
Short name T982
Test name
Test status
Simulation time 703291473 ps
CPU time 7.22 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 200476 kb
Host smart-c1943f46-7e51-4209-ac79-af44da7044ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375377800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.3375377800
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.536611305
Short name T831
Test name
Test status
Simulation time 57950790 ps
CPU time 0.84 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 200348 kb
Host smart-63c23f8b-81ce-402e-b168-3d5df71df00e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536611305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_hw_reset.536611305
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1998536336
Short name T872
Test name
Test status
Simulation time 93363747 ps
CPU time 1.49 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200348 kb
Host smart-633eff79-d557-4aae-a94d-611c335fe48f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998536336 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.1998536336
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.1456645531
Short name T938
Test name
Test status
Simulation time 23655075 ps
CPU time 0.77 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 200220 kb
Host smart-6fa69d67-9246-450d-bed2-fdb44cf83ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456645531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.1456645531
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1259918332
Short name T857
Test name
Test status
Simulation time 12677905 ps
CPU time 0.67 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 198880 kb
Host smart-ce428a7e-c04a-43bb-b027-154c5e08ffbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259918332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1259918332
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.331948724
Short name T972
Test name
Test status
Simulation time 85818990 ps
CPU time 1.41 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200572 kb
Host smart-102a761c-4dff-42f4-a2e8-d594698d7bd3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331948724 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.331948724
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.245500195
Short name T132
Test name
Test status
Simulation time 116089222 ps
CPU time 1.42 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200580 kb
Host smart-2bb6fb26-01c1-4b6c-b9b5-1286df489301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245500195 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.245500195
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1370284837
Short name T958
Test name
Test status
Simulation time 78934286 ps
CPU time 1.81 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 209032 kb
Host smart-91d8d1f2-d48d-4b1b-88fe-c597cde346d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370284837 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.1370284837
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2456014821
Short name T939
Test name
Test status
Simulation time 67282592 ps
CPU time 2.12 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200448 kb
Host smart-6a0584fb-b451-4fa7-a2ff-8d054ba93ff7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456014821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2456014821
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1763862731
Short name T113
Test name
Test status
Simulation time 131064934 ps
CPU time 1.68 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 200580 kb
Host smart-c4a603c2-3dcf-4de7-a9fa-1e06ccfdbca8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763862731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1763862731
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1295460015
Short name T928
Test name
Test status
Simulation time 112555847 ps
CPU time 1.7 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200480 kb
Host smart-34482528-8fb2-4b8c-8c61-57f6b9a69941
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295460015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.1295460015
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2071118929
Short name T158
Test name
Test status
Simulation time 519652280 ps
CPU time 5.16 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:13 PM PDT 24
Peak memory 200480 kb
Host smart-d980be8c-a7dc-4d5a-90d5-b59b9f58e728
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071118929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.2071118929
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.3695658480
Short name T888
Test name
Test status
Simulation time 22686625 ps
CPU time 0.83 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200296 kb
Host smart-9af9ac0c-299f-4599-a88e-905582f9e45b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695658480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.3695658480
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.3889142475
Short name T937
Test name
Test status
Simulation time 28457873 ps
CPU time 1.4 seconds
Started Aug 03 04:51:05 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 216868 kb
Host smart-25a4bbde-7a04-41ea-90cc-ef86bc822d29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889142475 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.3889142475
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.175962820
Short name T852
Test name
Test status
Simulation time 19212285 ps
CPU time 0.93 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 200372 kb
Host smart-4baa1353-7fd4-490e-943b-47c411172df2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175962820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.175962820
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.787761919
Short name T853
Test name
Test status
Simulation time 13477740 ps
CPU time 0.66 seconds
Started Aug 03 04:51:11 PM PDT 24
Finished Aug 03 04:51:12 PM PDT 24
Peak memory 198936 kb
Host smart-15512b58-be6c-46fe-aa95-b2b2d5d2e744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787761919 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm
gr_intr_test.787761919
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.76916913
Short name T941
Test name
Test status
Simulation time 81661709 ps
CPU time 1.09 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200320 kb
Host smart-60d479ca-a718-485c-9161-322f6b50682e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76916913 -assert nopostproc +UVM_TESTNAME=clkmgr_ba
se_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 1.clkmgr_same_csr_outstanding.76916913
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2256894066
Short name T129
Test name
Test status
Simulation time 590530680 ps
CPU time 2.74 seconds
Started Aug 03 04:51:11 PM PDT 24
Finished Aug 03 04:51:14 PM PDT 24
Peak memory 216764 kb
Host smart-78ff3865-eece-4ae7-bb09-0bcf4e170109
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256894066 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2256894066
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2364850217
Short name T133
Test name
Test status
Simulation time 235202950 ps
CPU time 1.9 seconds
Started Aug 03 04:51:05 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 209028 kb
Host smart-7361908b-b5f2-4566-aa4f-f77e75fd4696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364850217 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.2364850217
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1329324914
Short name T969
Test name
Test status
Simulation time 187855537 ps
CPU time 1.97 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 200544 kb
Host smart-c164a1e9-da53-4542-b8b3-3c86e5e79e0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329324914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.1329324914
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.4048060443
Short name T921
Test name
Test status
Simulation time 27921019 ps
CPU time 1.16 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 200432 kb
Host smart-852dc620-1f09-45eb-b4de-825361916496
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048060443 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.4048060443
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.2455072995
Short name T855
Test name
Test status
Simulation time 21691283 ps
CPU time 0.88 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 200264 kb
Host smart-db7e0475-912d-4cc5-944a-74dbb4e28aa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455072995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.2455072995
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1754100905
Short name T923
Test name
Test status
Simulation time 25744621 ps
CPU time 0.71 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 198932 kb
Host smart-4c82971d-535c-4ee2-9a6a-52388b6a7fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754100905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1754100905
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.1556238464
Short name T88
Test name
Test status
Simulation time 227452147 ps
CPU time 1.59 seconds
Started Aug 03 04:51:24 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200252 kb
Host smart-06974d12-503d-419a-8712-0da6538ea956
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556238464 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.1556238464
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2583727880
Short name T944
Test name
Test status
Simulation time 77351054 ps
CPU time 1.45 seconds
Started Aug 03 04:51:21 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 200620 kb
Host smart-90cb1969-a360-49dc-8826-72fde0a8d2a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583727880 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.2583727880
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1393720047
Short name T64
Test name
Test status
Simulation time 89314145 ps
CPU time 2.1 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 208988 kb
Host smart-10bf539f-c12b-42ad-b767-e499adbce137
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393720047 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.1393720047
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.1768042174
Short name T912
Test name
Test status
Simulation time 139361452 ps
CPU time 3.35 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 200472 kb
Host smart-4c488550-f604-47c2-acfc-52d5da2dc29a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768042174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.1768042174
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.2497186050
Short name T865
Test name
Test status
Simulation time 78141104 ps
CPU time 1.61 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 200452 kb
Host smart-5dad77db-25a5-4a6c-8671-385983303a47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497186050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.2497186050
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3688615295
Short name T837
Test name
Test status
Simulation time 81079342 ps
CPU time 1.58 seconds
Started Aug 03 04:51:27 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200484 kb
Host smart-6a5e5e40-7e03-469b-ad0e-30d122a008d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688615295 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3688615295
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.283636185
Short name T849
Test name
Test status
Simulation time 35238394 ps
CPU time 0.81 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 200352 kb
Host smart-d71f1bf2-bab0-4747-8571-983a25269e0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283636185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
clkmgr_csr_rw.283636185
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1409976742
Short name T916
Test name
Test status
Simulation time 28248663 ps
CPU time 0.71 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 198912 kb
Host smart-d097f450-ce69-4277-9090-05d70b1ab7cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409976742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1409976742
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3802325288
Short name T87
Test name
Test status
Simulation time 39982526 ps
CPU time 1.2 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200320 kb
Host smart-5d904213-a5bf-44bf-805e-0d852d8d63c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802325288 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3802325288
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.966126409
Short name T130
Test name
Test status
Simulation time 241303407 ps
CPU time 1.68 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200548 kb
Host smart-e71db324-75bb-4a25-94f5-ecdd69a29923
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966126409 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.clkmgr_shadow_reg_errors.966126409
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.1159589513
Short name T127
Test name
Test status
Simulation time 472523125 ps
CPU time 3.78 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 201004 kb
Host smart-80d8735f-d6a0-46ce-9f4c-b642efe45dd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159589513 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.1159589513
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.723438082
Short name T909
Test name
Test status
Simulation time 327582820 ps
CPU time 3.77 seconds
Started Aug 03 04:51:21 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 200544 kb
Host smart-00cc0f6e-c37a-482f-b754-86f2a5fb2175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723438082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk
mgr_tl_errors.723438082
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4289176092
Short name T108
Test name
Test status
Simulation time 226387688 ps
CPU time 1.96 seconds
Started Aug 03 04:51:21 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 200572 kb
Host smart-981e7887-4c95-4258-b04e-b8016a5152c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289176092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.4289176092
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.3429400920
Short name T835
Test name
Test status
Simulation time 49543291 ps
CPU time 1.16 seconds
Started Aug 03 04:51:24 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 200432 kb
Host smart-04b8002b-dff8-4501-8582-9c08e563ba8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429400920 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.3429400920
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1796375479
Short name T89
Test name
Test status
Simulation time 46601188 ps
CPU time 0.91 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:20 PM PDT 24
Peak memory 200376 kb
Host smart-06ad5c08-9b79-491a-94a7-501e5e779416
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796375479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.1796375479
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.284393565
Short name T844
Test name
Test status
Simulation time 14601171 ps
CPU time 0.77 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:20 PM PDT 24
Peak memory 198912 kb
Host smart-ed044bfc-93cd-47a7-a36c-6393efaf49bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284393565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clk
mgr_intr_test.284393565
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.1170684226
Short name T90
Test name
Test status
Simulation time 71483380 ps
CPU time 1.02 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:20 PM PDT 24
Peak memory 200288 kb
Host smart-91cd39c8-dadd-4e66-9fba-a02ef454e9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170684226 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.1170684226
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.422251446
Short name T122
Test name
Test status
Simulation time 175939762 ps
CPU time 1.97 seconds
Started Aug 03 04:51:25 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 209136 kb
Host smart-9cfcdd69-6706-4b79-9d27-600ed806db9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422251446 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.422251446
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3498134259
Short name T873
Test name
Test status
Simulation time 79287372 ps
CPU time 2.02 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200468 kb
Host smart-9ccafe34-72fd-4614-bb0c-d5a4e7d6e91b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498134259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3498134259
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2402876445
Short name T911
Test name
Test status
Simulation time 226149467 ps
CPU time 2.11 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 200508 kb
Host smart-d8a372ae-5721-48c3-8c89-518e0871d7e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402876445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.2402876445
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.356043387
Short name T977
Test name
Test status
Simulation time 44684448 ps
CPU time 1.36 seconds
Started Aug 03 04:51:27 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 200420 kb
Host smart-f27281bc-a25d-4420-8e32-d056729df69d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356043387 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.356043387
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.662163709
Short name T913
Test name
Test status
Simulation time 53424337 ps
CPU time 0.98 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200296 kb
Host smart-2f3a4e93-0f74-4bc3-a7f5-ff37a9c972d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662163709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
clkmgr_csr_rw.662163709
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.1889369986
Short name T856
Test name
Test status
Simulation time 13957407 ps
CPU time 0.71 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 198944 kb
Host smart-48e0f9c9-1124-4e0b-9f2a-1f8ddd1e7fdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889369986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.1889369986
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.1753149429
Short name T935
Test name
Test status
Simulation time 46601049 ps
CPU time 1.3 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200536 kb
Host smart-7a0528da-7d05-4574-9991-314f5e07150a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753149429 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.1753149429
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.301872363
Short name T131
Test name
Test status
Simulation time 199003098 ps
CPU time 1.69 seconds
Started Aug 03 04:51:21 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 200588 kb
Host smart-24bf1556-a0fc-4aec-8c23-9556070732a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301872363 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.clkmgr_shadow_reg_errors.301872363
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.2223217216
Short name T838
Test name
Test status
Simulation time 122455361 ps
CPU time 2.06 seconds
Started Aug 03 04:51:20 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 200476 kb
Host smart-ce48cd12-0ce9-4212-b2c2-3cf476e6bd22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223217216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.2223217216
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.120528103
Short name T906
Test name
Test status
Simulation time 311027998 ps
CPU time 2.61 seconds
Started Aug 03 04:51:19 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 200444 kb
Host smart-1a801485-94b9-4259-b971-01fb5be94ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120528103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.120528103
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.615573682
Short name T908
Test name
Test status
Simulation time 38357798 ps
CPU time 1.27 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 200388 kb
Host smart-20c48ee3-7431-445b-9efa-fdea2901505a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615573682 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.615573682
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3962846889
Short name T895
Test name
Test status
Simulation time 39453767 ps
CPU time 0.82 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200340 kb
Host smart-466ceb85-7f5e-4d2b-adc8-1eecc75d24b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962846889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.3962846889
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.4064634486
Short name T890
Test name
Test status
Simulation time 18485096 ps
CPU time 0.7 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:27 PM PDT 24
Peak memory 199020 kb
Host smart-2d021564-c298-43ac-b553-c70fa4faa381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064634486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.4064634486
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2464622975
Short name T875
Test name
Test status
Simulation time 127868511 ps
CPU time 1.4 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:33 PM PDT 24
Peak memory 200352 kb
Host smart-e6dd62c0-3b0a-42c9-924e-7ca170d74ae7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464622975 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.2464622975
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3443219892
Short name T947
Test name
Test status
Simulation time 317804557 ps
CPU time 1.88 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 200568 kb
Host smart-4c7338a3-7d40-4b9e-a7c9-1caadce40092
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443219892 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.3443219892
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4158386379
Short name T58
Test name
Test status
Simulation time 104390080 ps
CPU time 2.57 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:34 PM PDT 24
Peak memory 217036 kb
Host smart-fe3bd1c7-1489-4bc6-9196-f81e4497b48a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158386379 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.4158386379
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2109934642
Short name T899
Test name
Test status
Simulation time 223716071 ps
CPU time 3.02 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200528 kb
Host smart-f4b85e3a-e364-425f-8a47-eb819d5b66f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109934642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.2109934642
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.1335986182
Short name T851
Test name
Test status
Simulation time 53136770 ps
CPU time 1.52 seconds
Started Aug 03 04:51:27 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 200544 kb
Host smart-4747ece7-4247-40e2-b3a5-2ba252da03e9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335986182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.1335986182
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3478211863
Short name T841
Test name
Test status
Simulation time 92295903 ps
CPU time 1.31 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200376 kb
Host smart-29340c0a-8b4a-43c4-ac89-2c7c95b5c282
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478211863 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3478211863
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.908912366
Short name T943
Test name
Test status
Simulation time 25366119 ps
CPU time 0.83 seconds
Started Aug 03 04:51:27 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 200268 kb
Host smart-c3199cfb-80b3-49d3-a9c8-fbcd51f0f88b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908912366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
clkmgr_csr_rw.908912366
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.3354163671
Short name T898
Test name
Test status
Simulation time 33107568 ps
CPU time 0.73 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 198936 kb
Host smart-8b0f5095-ee9b-4dcb-a975-6fac3a89ebb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354163671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.3354163671
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1597277144
Short name T962
Test name
Test status
Simulation time 34761441 ps
CPU time 0.95 seconds
Started Aug 03 04:51:25 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200336 kb
Host smart-c0f0536e-2706-454b-849f-62413336f03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597277144 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.1597277144
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.2228671164
Short name T121
Test name
Test status
Simulation time 390560629 ps
CPU time 3.2 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:31 PM PDT 24
Peak memory 217024 kb
Host smart-6b627c02-e804-42c5-94c6-6dc91fe41842
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228671164 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.2228671164
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.4287561608
Short name T966
Test name
Test status
Simulation time 584468271 ps
CPU time 4.66 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 200500 kb
Host smart-5291d28f-9837-4eb3-a4aa-2dd87723951d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287561608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.4287561608
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.319802044
Short name T168
Test name
Test status
Simulation time 527254956 ps
CPU time 3.43 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:32 PM PDT 24
Peak memory 200524 kb
Host smart-76eddc99-3754-43a5-8c81-492ae31b9b2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319802044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_tl_intg_err.319802044
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.4092702861
Short name T931
Test name
Test status
Simulation time 42930532 ps
CPU time 1.36 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 200436 kb
Host smart-5adb74d1-20f2-4b22-894a-91a4c526a1eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092702861 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.4092702861
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3142549863
Short name T843
Test name
Test status
Simulation time 24109562 ps
CPU time 0.81 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200336 kb
Host smart-d85f6107-1797-4e65-b698-f480610a8518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142549863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3142549863
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2823478279
Short name T901
Test name
Test status
Simulation time 13860853 ps
CPU time 0.7 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198932 kb
Host smart-aa623a56-2e44-40ad-adc1-b5fdf884955c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823478279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2823478279
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.2955679999
Short name T858
Test name
Test status
Simulation time 51754696 ps
CPU time 1.23 seconds
Started Aug 03 04:51:26 PM PDT 24
Finished Aug 03 04:51:28 PM PDT 24
Peak memory 200500 kb
Host smart-6c48fa09-ccf0-4d8b-a6f0-d2c460a134f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955679999 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.2955679999
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1604687334
Short name T65
Test name
Test status
Simulation time 113289493 ps
CPU time 1.77 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 200612 kb
Host smart-9b903e11-8f38-4a80-847a-1da17bbf32a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604687334 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.1604687334
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1381290161
Short name T126
Test name
Test status
Simulation time 169684327 ps
CPU time 2.97 seconds
Started Aug 03 04:51:27 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 216896 kb
Host smart-e1c407f8-9c5a-4e57-b92f-634f9d709185
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381290161 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.1381290161
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.1227047358
Short name T826
Test name
Test status
Simulation time 72451676 ps
CPU time 2.28 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 200568 kb
Host smart-921ae760-70a8-4f8e-a8e5-93d806ceb411
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227047358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.1227047358
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3899451414
Short name T840
Test name
Test status
Simulation time 84609469 ps
CPU time 1.44 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 200432 kb
Host smart-e0f099ef-fb5c-4f46-b2af-a595487c444e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899451414 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3899451414
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3916718427
Short name T891
Test name
Test status
Simulation time 15450988 ps
CPU time 0.75 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200368 kb
Host smart-4b7bf85a-cc98-4577-9022-6c8861f04602
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916718427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.3916718427
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3965163168
Short name T825
Test name
Test status
Simulation time 24744812 ps
CPU time 0.7 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:32 PM PDT 24
Peak memory 198936 kb
Host smart-0b55a22f-e352-4314-8016-51df6e5d97cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965163168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3965163168
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.447042100
Short name T86
Test name
Test status
Simulation time 60362220 ps
CPU time 1.3 seconds
Started Aug 03 04:51:32 PM PDT 24
Finished Aug 03 04:51:33 PM PDT 24
Peak memory 200568 kb
Host smart-727eea3c-c061-44d4-92f0-12fa3a7ddf92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447042100 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 17.clkmgr_same_csr_outstanding.447042100
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.1268167290
Short name T61
Test name
Test status
Simulation time 57055306 ps
CPU time 1.26 seconds
Started Aug 03 04:51:28 PM PDT 24
Finished Aug 03 04:51:30 PM PDT 24
Peak memory 200616 kb
Host smart-34eb0516-2e68-4a9a-acc2-cb76195057a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268167290 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.1268167290
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.1922974060
Short name T964
Test name
Test status
Simulation time 78007048 ps
CPU time 1.83 seconds
Started Aug 03 04:51:31 PM PDT 24
Finished Aug 03 04:51:32 PM PDT 24
Peak memory 210048 kb
Host smart-7fc1ae77-a274-4a1d-b8c0-718c214bbf30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922974060 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1922974060
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3509294636
Short name T976
Test name
Test status
Simulation time 126313461 ps
CPU time 3.34 seconds
Started Aug 03 04:51:29 PM PDT 24
Finished Aug 03 04:51:33 PM PDT 24
Peak memory 200448 kb
Host smart-75352f1c-17a4-496c-80f0-9e0790ecfbf8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509294636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3509294636
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.2200255124
Short name T934
Test name
Test status
Simulation time 72156216 ps
CPU time 1.51 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 200588 kb
Host smart-f5cef220-4850-43eb-a553-71912b7c369e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200255124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.2200255124
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.2015133019
Short name T925
Test name
Test status
Simulation time 24797941 ps
CPU time 0.98 seconds
Started Aug 03 04:51:37 PM PDT 24
Finished Aug 03 04:51:38 PM PDT 24
Peak memory 200272 kb
Host smart-576a13a1-a482-4fe0-9e1c-fe4c5a0cb1dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015133019 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.2015133019
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.461078890
Short name T883
Test name
Test status
Simulation time 29174026 ps
CPU time 0.85 seconds
Started Aug 03 04:51:39 PM PDT 24
Finished Aug 03 04:51:40 PM PDT 24
Peak memory 200332 kb
Host smart-a69a10e8-8731-4bb3-81d6-a4a593ac6a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461078890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
clkmgr_csr_rw.461078890
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.2663204398
Short name T917
Test name
Test status
Simulation time 11135165 ps
CPU time 0.67 seconds
Started Aug 03 04:51:37 PM PDT 24
Finished Aug 03 04:51:38 PM PDT 24
Peak memory 198932 kb
Host smart-ee333c91-0b26-473b-9397-353043b4def3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663204398 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.2663204398
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.2087019759
Short name T900
Test name
Test status
Simulation time 33025628 ps
CPU time 0.97 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 200364 kb
Host smart-baf46fdf-6ae8-4a51-9946-bff37eafdf7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087019759 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.2087019759
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2464387584
Short name T926
Test name
Test status
Simulation time 70084389 ps
CPU time 1.43 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 200484 kb
Host smart-acc79be1-9bb0-4aee-9f40-b5213c803327
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464387584 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2464387584
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.823410631
Short name T134
Test name
Test status
Simulation time 248276218 ps
CPU time 2.02 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 200772 kb
Host smart-eb2d5a7f-43a0-46c4-b82b-f95799fea519
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823410631 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.823410631
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3266610736
Short name T839
Test name
Test status
Simulation time 68907353 ps
CPU time 1.39 seconds
Started Aug 03 04:51:35 PM PDT 24
Finished Aug 03 04:51:37 PM PDT 24
Peak memory 200336 kb
Host smart-12051148-a2cc-456e-bffa-7ea24a92aaa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266610736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3266610736
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.101730880
Short name T114
Test name
Test status
Simulation time 57844621 ps
CPU time 1.59 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 200524 kb
Host smart-38821903-1cbf-426a-890b-3edf2295d0c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101730880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_tl_intg_err.101730880
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3651401654
Short name T868
Test name
Test status
Simulation time 54215395 ps
CPU time 1.11 seconds
Started Aug 03 04:51:35 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 200380 kb
Host smart-1d0e86ed-406a-49b8-b28a-d281ed1e84a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651401654 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3651401654
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.797476943
Short name T955
Test name
Test status
Simulation time 18352291 ps
CPU time 0.83 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:34 PM PDT 24
Peak memory 200300 kb
Host smart-4208b2d9-e671-4ca8-8bb9-a2daa3fc550d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797476943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.797476943
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2645951528
Short name T880
Test name
Test status
Simulation time 35590613 ps
CPU time 0.72 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:34 PM PDT 24
Peak memory 198924 kb
Host smart-99232668-6b3f-4ec3-8d1c-de6a95387980
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645951528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2645951528
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2606430105
Short name T881
Test name
Test status
Simulation time 88576470 ps
CPU time 1.5 seconds
Started Aug 03 04:51:36 PM PDT 24
Finished Aug 03 04:51:38 PM PDT 24
Peak memory 200504 kb
Host smart-9dd53b75-185c-4dfb-845c-ef77922c58de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606430105 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.2606430105
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.3286460031
Short name T929
Test name
Test status
Simulation time 94501145 ps
CPU time 1.82 seconds
Started Aug 03 04:51:36 PM PDT 24
Finished Aug 03 04:51:38 PM PDT 24
Peak memory 200788 kb
Host smart-9003a531-997e-45cd-81b0-4861c8fa5794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286460031 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.3286460031
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2158150765
Short name T870
Test name
Test status
Simulation time 101998389 ps
CPU time 2.05 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 200520 kb
Host smart-88580881-29b9-4bd5-9855-014087c6e6c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158150765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.2158150765
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3812509898
Short name T974
Test name
Test status
Simulation time 46497962 ps
CPU time 1.26 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 200340 kb
Host smart-c94f5e4e-b02f-47c6-9e8c-ced99641d642
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812509898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.3812509898
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.4141216741
Short name T942
Test name
Test status
Simulation time 1358121477 ps
CPU time 8.52 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 200516 kb
Host smart-f486afe7-a6c4-429a-8686-002b49fbd558
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141216741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.4141216741
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.1639839937
Short name T905
Test name
Test status
Simulation time 14537417 ps
CPU time 0.76 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 200308 kb
Host smart-ff6789f5-ca8a-4e3a-a83a-bb3596a7819b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639839937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.1639839937
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1710191747
Short name T884
Test name
Test status
Simulation time 60634491 ps
CPU time 1.79 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 208724 kb
Host smart-fbade719-8376-44be-bb56-c23d400ea65a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710191747 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1710191747
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1834895270
Short name T885
Test name
Test status
Simulation time 13741266 ps
CPU time 0.81 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200352 kb
Host smart-b30fe536-6458-4e92-b9c2-d068524f6c4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834895270 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.1834895270
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.2470562267
Short name T983
Test name
Test status
Simulation time 77942048 ps
CPU time 0.84 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 199008 kb
Host smart-e0a92ceb-d211-4a6b-a29d-08669f0144c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470562267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.2470562267
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3146729372
Short name T978
Test name
Test status
Simulation time 22506602 ps
CPU time 0.93 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200344 kb
Host smart-116fb586-6668-47b0-92d8-bb1fa19b30ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146729372 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.3146729372
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.806624175
Short name T965
Test name
Test status
Simulation time 105603576 ps
CPU time 1.96 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 208928 kb
Host smart-4cf6fe69-2c32-4b83-ac97-8ed78009f42f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806624175 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.clkmgr_shadow_reg_errors.806624175
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.1711967670
Short name T971
Test name
Test status
Simulation time 280030737 ps
CPU time 2.26 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 208968 kb
Host smart-36949b62-1f0d-4cda-a2a4-10bccddcaa0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711967670 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.1711967670
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.3181228066
Short name T961
Test name
Test status
Simulation time 84812651 ps
CPU time 2.61 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200540 kb
Host smart-a59384f1-44b3-4e8a-9688-a7e88219c381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181228066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_tl_errors.3181228066
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2639687895
Short name T828
Test name
Test status
Simulation time 35993072 ps
CPU time 0.69 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198952 kb
Host smart-fae021f2-2ee1-4937-83ba-16ad600856e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639687895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2639687895
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1598096848
Short name T973
Test name
Test status
Simulation time 22388154 ps
CPU time 0.67 seconds
Started Aug 03 04:51:32 PM PDT 24
Finished Aug 03 04:51:33 PM PDT 24
Peak memory 198876 kb
Host smart-a27c6315-be61-4bb9-a000-26ab00ae965d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598096848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.1598096848
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.655680569
Short name T836
Test name
Test status
Simulation time 78577696 ps
CPU time 0.88 seconds
Started Aug 03 04:51:33 PM PDT 24
Finished Aug 03 04:51:34 PM PDT 24
Peak memory 198920 kb
Host smart-fb329fb3-017e-4991-bd44-78f36a8c08e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655680569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.655680569
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.4017435141
Short name T864
Test name
Test status
Simulation time 29017348 ps
CPU time 0.71 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198880 kb
Host smart-cef2b728-9697-4022-8d0d-d3cca3db3d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017435141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.4017435141
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.691737309
Short name T827
Test name
Test status
Simulation time 25132899 ps
CPU time 0.76 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198916 kb
Host smart-7558243b-c913-4b7b-a1c1-23beedf94908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691737309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clk
mgr_intr_test.691737309
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.55319519
Short name T882
Test name
Test status
Simulation time 49628305 ps
CPU time 0.74 seconds
Started Aug 03 04:51:40 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 198916 kb
Host smart-9dc88609-cb09-48b4-8c6d-906955f29b3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55319519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkm
gr_intr_test.55319519
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3893093640
Short name T863
Test name
Test status
Simulation time 29320476 ps
CPU time 0.7 seconds
Started Aug 03 04:51:40 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 198920 kb
Host smart-45e64529-229f-4342-8d26-4b011dfefb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893093640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3893093640
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1586136647
Short name T848
Test name
Test status
Simulation time 19774930 ps
CPU time 0.69 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 199008 kb
Host smart-a9f2ac9d-b22a-49b7-af75-5549beed78d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586136647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1586136647
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.206614909
Short name T832
Test name
Test status
Simulation time 22140229 ps
CPU time 0.7 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 199028 kb
Host smart-d3dcb9f4-4832-4d6f-bcfa-4969c544920e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206614909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clk
mgr_intr_test.206614909
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.683578553
Short name T834
Test name
Test status
Simulation time 33427390 ps
CPU time 0.7 seconds
Started Aug 03 04:51:36 PM PDT 24
Finished Aug 03 04:51:37 PM PDT 24
Peak memory 198912 kb
Host smart-e490ec79-d87f-4cb9-a685-964e8f6517cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683578553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clk
mgr_intr_test.683578553
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.689435938
Short name T980
Test name
Test status
Simulation time 72601828 ps
CPU time 1.33 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 200292 kb
Host smart-642101ed-9dc4-4e35-bca1-d78977447aa8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689435938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_aliasing.689435938
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.345205042
Short name T981
Test name
Test status
Simulation time 1373227459 ps
CPU time 9.53 seconds
Started Aug 03 04:51:11 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200600 kb
Host smart-df076e6f-9316-4cad-833e-2e1fb38ee546
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345205042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.345205042
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.258804939
Short name T927
Test name
Test status
Simulation time 19088773 ps
CPU time 0.83 seconds
Started Aug 03 04:51:10 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 200384 kb
Host smart-055af783-12e2-4f03-9677-8237d9019f6a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258804939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.258804939
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3760498818
Short name T914
Test name
Test status
Simulation time 90230767 ps
CPU time 1.48 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 200376 kb
Host smart-69054e57-e416-4b8d-beb9-60fe637c3672
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760498818 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3760498818
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1932778482
Short name T949
Test name
Test status
Simulation time 57201096 ps
CPU time 0.92 seconds
Started Aug 03 04:51:06 PM PDT 24
Finished Aug 03 04:51:07 PM PDT 24
Peak memory 200340 kb
Host smart-f7e2010f-6304-4c5a-8af6-9f3a96b79e6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932778482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1932778482
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.3238909446
Short name T902
Test name
Test status
Simulation time 13355082 ps
CPU time 0.65 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:09 PM PDT 24
Peak memory 199012 kb
Host smart-64f6aa61-bb8f-473f-9026-2c81a5a5bf16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238909446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.3238909446
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.4055369540
Short name T957
Test name
Test status
Simulation time 89573158 ps
CPU time 1.56 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 200684 kb
Host smart-171210cc-b46f-4168-848c-edabefd4f965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055369540 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.4055369540
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.2566526344
Short name T62
Test name
Test status
Simulation time 326909979 ps
CPU time 2.3 seconds
Started Aug 03 04:51:10 PM PDT 24
Finished Aug 03 04:51:12 PM PDT 24
Peak memory 200760 kb
Host smart-8471fbbd-b3cd-43cb-956a-29b54a8f1854
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566526344 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.2566526344
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.4091149287
Short name T54
Test name
Test status
Simulation time 105393577 ps
CPU time 1.57 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:08 PM PDT 24
Peak memory 200780 kb
Host smart-85157d4b-51f6-4bd1-bd97-ce8099c2fc9c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091149287 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4091149287
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.1258161977
Short name T861
Test name
Test status
Simulation time 40748991 ps
CPU time 2.33 seconds
Started Aug 03 04:51:08 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 200476 kb
Host smart-73c81918-8daf-41c6-bc1a-c6a0bab6c0f5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258161977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.1258161977
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1534904934
Short name T904
Test name
Test status
Simulation time 195359244 ps
CPU time 2.71 seconds
Started Aug 03 04:51:07 PM PDT 24
Finished Aug 03 04:51:10 PM PDT 24
Peak memory 200460 kb
Host smart-2f653280-8d50-45d6-ad78-9fbcb1d1fd23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534904934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.1534904934
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.14476241
Short name T846
Test name
Test status
Simulation time 13840782 ps
CPU time 0.7 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198932 kb
Host smart-076db580-4cdb-46e8-9f28-5e4caca5276b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14476241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkm
gr_intr_test.14476241
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1375559105
Short name T954
Test name
Test status
Simulation time 17796454 ps
CPU time 0.68 seconds
Started Aug 03 04:51:37 PM PDT 24
Finished Aug 03 04:51:38 PM PDT 24
Peak memory 199008 kb
Host smart-d3d383fa-8756-4c51-a60f-37c4c65c3aa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375559105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1375559105
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.3800923131
Short name T907
Test name
Test status
Simulation time 35314731 ps
CPU time 0.71 seconds
Started Aug 03 04:51:34 PM PDT 24
Finished Aug 03 04:51:35 PM PDT 24
Peak memory 198880 kb
Host smart-71d242a0-12f5-4ea8-83b5-f91de5064e5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800923131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.3800923131
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.1189681129
Short name T842
Test name
Test status
Simulation time 13014426 ps
CPU time 0.72 seconds
Started Aug 03 04:51:36 PM PDT 24
Finished Aug 03 04:51:37 PM PDT 24
Peak memory 199004 kb
Host smart-c61cdc34-fb51-47bd-949c-d7d75e478a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189681129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.1189681129
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.2184713416
Short name T967
Test name
Test status
Simulation time 12211800 ps
CPU time 0.66 seconds
Started Aug 03 04:51:36 PM PDT 24
Finished Aug 03 04:51:37 PM PDT 24
Peak memory 199016 kb
Host smart-08ed3766-47ab-4390-bae2-2f1091d870c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184713416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.2184713416
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.1502715260
Short name T933
Test name
Test status
Simulation time 22673190 ps
CPU time 0.69 seconds
Started Aug 03 04:51:39 PM PDT 24
Finished Aug 03 04:51:40 PM PDT 24
Peak memory 198932 kb
Host smart-73ef270a-b8d0-4910-9541-9a3c41034ecd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502715260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.1502715260
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.553202589
Short name T869
Test name
Test status
Simulation time 42822853 ps
CPU time 0.72 seconds
Started Aug 03 04:51:35 PM PDT 24
Finished Aug 03 04:51:36 PM PDT 24
Peak memory 198940 kb
Host smart-3e4d44f2-d564-4c12-850a-1d7f89b023db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553202589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clk
mgr_intr_test.553202589
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.4268238849
Short name T866
Test name
Test status
Simulation time 29547022 ps
CPU time 0.7 seconds
Started Aug 03 04:51:40 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 198848 kb
Host smart-2d25a1f4-3bcf-4166-815d-88a8d05d0149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268238849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.4268238849
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.1342175294
Short name T920
Test name
Test status
Simulation time 19763682 ps
CPU time 0.65 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 198884 kb
Host smart-97bfb8e6-56e2-482f-a4cf-9dbfb6825f77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342175294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.1342175294
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.1161759751
Short name T922
Test name
Test status
Simulation time 23399307 ps
CPU time 0.69 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 04:51:42 PM PDT 24
Peak memory 198956 kb
Host smart-c80f672e-2283-467c-bf0e-d78f72221518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161759751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.1161759751
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3644976136
Short name T867
Test name
Test status
Simulation time 56418338 ps
CPU time 1.66 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 200544 kb
Host smart-6ebba67a-9ea1-4803-9549-b985c1a2ef8a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644976136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3644976136
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.76993336
Short name T878
Test name
Test status
Simulation time 275672915 ps
CPU time 6.94 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:29 PM PDT 24
Peak memory 200504 kb
Host smart-84b39667-e5b1-496b-b202-d5842fb09a12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76993336 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_csr_bit_bash.76993336
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1650907455
Short name T874
Test name
Test status
Simulation time 24004129 ps
CPU time 0.87 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200304 kb
Host smart-3cca5251-7136-4ea6-a625-73e762cda057
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650907455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1650907455
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.2013874118
Short name T963
Test name
Test status
Simulation time 23688705 ps
CPU time 1.26 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200352 kb
Host smart-78483abc-35f7-417c-ba1d-648ea346de51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013874118 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2013874118
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3421998178
Short name T940
Test name
Test status
Simulation time 21243761 ps
CPU time 0.86 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 200340 kb
Host smart-893e3478-986d-4af2-87c4-546871ecccf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421998178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3421998178
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2209923561
Short name T959
Test name
Test status
Simulation time 15749497 ps
CPU time 0.67 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 198880 kb
Host smart-4b661aef-5941-4f34-9f32-d60de8f91d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209923561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2209923561
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1195642999
Short name T948
Test name
Test status
Simulation time 41229551 ps
CPU time 1.12 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 200340 kb
Host smart-1588da2a-e264-4c5b-b85c-53519ab39cd5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195642999 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.1195642999
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.873910910
Short name T968
Test name
Test status
Simulation time 407661832 ps
CPU time 2.07 seconds
Started Aug 03 04:51:11 PM PDT 24
Finished Aug 03 04:51:14 PM PDT 24
Peak memory 200584 kb
Host smart-decd1c0a-479a-44c8-8bfb-2a7032a24bbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873910910 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.873910910
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.920348155
Short name T57
Test name
Test status
Simulation time 131326648 ps
CPU time 1.68 seconds
Started Aug 03 04:51:09 PM PDT 24
Finished Aug 03 04:51:11 PM PDT 24
Peak memory 208904 kb
Host smart-c1d1d026-ff12-4883-aba7-9e030e362632
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920348155 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.920348155
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.3371660414
Short name T876
Test name
Test status
Simulation time 274379803 ps
CPU time 2.5 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 200528 kb
Host smart-b3b5d116-6694-4af4-a47e-c682c45d1744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371660414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.3371660414
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.4234345671
Short name T169
Test name
Test status
Simulation time 85788661 ps
CPU time 1.63 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 200580 kb
Host smart-cec87d9e-5596-4827-8100-eeb3a39b962b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234345671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.4234345671
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.429922704
Short name T830
Test name
Test status
Simulation time 13247525 ps
CPU time 0.7 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:51:42 PM PDT 24
Peak memory 198920 kb
Host smart-dc1a7134-719c-45a3-b0c0-b5c6b932452d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429922704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.429922704
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2665756049
Short name T956
Test name
Test status
Simulation time 32673997 ps
CPU time 0.69 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:51:42 PM PDT 24
Peak memory 198888 kb
Host smart-de958b58-2504-49f7-9ee1-63046a1bdf1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665756049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2665756049
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1231021140
Short name T919
Test name
Test status
Simulation time 19428750 ps
CPU time 0.7 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 198836 kb
Host smart-1bbdfab5-a18f-4b2a-a6ab-db586ab49a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231021140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1231021140
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.162874367
Short name T845
Test name
Test status
Simulation time 35707174 ps
CPU time 0.69 seconds
Started Aug 03 04:51:42 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 198892 kb
Host smart-5c9f20f1-085d-401a-a8b5-9e2f089fcea4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162874367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clk
mgr_intr_test.162874367
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2075107684
Short name T889
Test name
Test status
Simulation time 39297001 ps
CPU time 0.74 seconds
Started Aug 03 04:51:41 PM PDT 24
Finished Aug 03 04:51:42 PM PDT 24
Peak memory 199088 kb
Host smart-4bb26beb-974c-4c19-9523-60b726685249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075107684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.2075107684
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.637053652
Short name T903
Test name
Test status
Simulation time 35818562 ps
CPU time 0.74 seconds
Started Aug 03 04:51:44 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 198872 kb
Host smart-00a42bbd-61bc-4f4c-9308-457054a1b572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637053652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clk
mgr_intr_test.637053652
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.870064461
Short name T879
Test name
Test status
Simulation time 34304614 ps
CPU time 0.71 seconds
Started Aug 03 04:51:43 PM PDT 24
Finished Aug 03 04:51:43 PM PDT 24
Peak memory 198948 kb
Host smart-8f7394d0-a47c-4b79-8437-bfafa488e460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870064461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk
mgr_intr_test.870064461
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.112842158
Short name T892
Test name
Test status
Simulation time 15261875 ps
CPU time 0.71 seconds
Started Aug 03 04:51:40 PM PDT 24
Finished Aug 03 04:51:41 PM PDT 24
Peak memory 198948 kb
Host smart-b63d418a-9aa6-47e6-898e-fc30b348877b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112842158 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.112842158
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2188363658
Short name T833
Test name
Test status
Simulation time 12089577 ps
CPU time 0.72 seconds
Started Aug 03 04:51:44 PM PDT 24
Finished Aug 03 04:51:44 PM PDT 24
Peak memory 198868 kb
Host smart-e0c3dbbb-73d2-4371-ba50-5cb79494da68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188363658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.2188363658
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2227775047
Short name T952
Test name
Test status
Simulation time 23426625 ps
CPU time 0.71 seconds
Started Aug 03 04:51:44 PM PDT 24
Finished Aug 03 04:51:45 PM PDT 24
Peak memory 198864 kb
Host smart-8fb838e8-c379-4e41-9667-dfb6fe41aac4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227775047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2227775047
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.2627114775
Short name T946
Test name
Test status
Simulation time 323298560 ps
CPU time 2.31 seconds
Started Aug 03 04:51:13 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 200552 kb
Host smart-eb2e1024-e377-40b8-90ff-3e89757735ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627114775 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.2627114775
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.58206026
Short name T862
Test name
Test status
Simulation time 43167307 ps
CPU time 0.86 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 200312 kb
Host smart-057cbfbe-807c-4fd1-afa5-e242702fedad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58206026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.cl
kmgr_csr_rw.58206026
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3970244869
Short name T850
Test name
Test status
Simulation time 14088872 ps
CPU time 0.67 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 199012 kb
Host smart-f56517fb-58f6-4975-845b-41a7615c7ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970244869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.3970244869
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.3567830001
Short name T859
Test name
Test status
Simulation time 35161462 ps
CPU time 1.11 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200332 kb
Host smart-6f37da81-3a0d-4351-9551-bbed81b6bd24
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567830001 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.3567830001
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1260457488
Short name T63
Test name
Test status
Simulation time 660849930 ps
CPU time 2.76 seconds
Started Aug 03 04:51:16 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 200564 kb
Host smart-fec2c732-09e9-4492-b5cd-6ec94f9d855a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260457488 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1260457488
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2658276386
Short name T123
Test name
Test status
Simulation time 249068037 ps
CPU time 2.75 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 200976 kb
Host smart-cfd22d52-4456-494b-8c6d-3720d56ff62c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658276386 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2658276386
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2360529693
Short name T960
Test name
Test status
Simulation time 425437373 ps
CPU time 3.48 seconds
Started Aug 03 04:51:13 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200496 kb
Host smart-c0fdecfd-c733-4597-8d96-ec25cc725076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360529693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.2360529693
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1605319922
Short name T915
Test name
Test status
Simulation time 74876946 ps
CPU time 1.8 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:17 PM PDT 24
Peak memory 200516 kb
Host smart-64408426-b674-4d89-a20f-59e83fd2ed0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605319922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1605319922
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2778097321
Short name T871
Test name
Test status
Simulation time 97653525 ps
CPU time 1.71 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 200624 kb
Host smart-afa6547f-043f-42ad-ab1b-16fa902a3780
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778097321 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2778097321
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2016001060
Short name T159
Test name
Test status
Simulation time 52337552 ps
CPU time 0.87 seconds
Started Aug 03 04:51:16 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200316 kb
Host smart-7d76f5cc-536b-4cce-8754-9f7f4b2d4046
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016001060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.2016001060
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3130219643
Short name T924
Test name
Test status
Simulation time 11658347 ps
CPU time 0.66 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 198888 kb
Host smart-f2a06fdb-fa86-4c1e-b203-fe68bd74db0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130219643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3130219643
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.4272293548
Short name T975
Test name
Test status
Simulation time 56195211 ps
CPU time 1.47 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:20 PM PDT 24
Peak memory 200420 kb
Host smart-7076518d-336b-4517-ae3a-9a1e9c12e6b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272293548 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.4272293548
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1156567635
Short name T918
Test name
Test status
Simulation time 234036780 ps
CPU time 1.77 seconds
Started Aug 03 04:51:16 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 200588 kb
Host smart-8b2b62e1-6cce-4b27-9271-a7d0ab9e2c99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156567635 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.1156567635
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1385893796
Short name T953
Test name
Test status
Simulation time 305378199 ps
CPU time 2.5 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 208948 kb
Host smart-8ddbd23a-ec63-48e3-b71c-ef7bb17a9029
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385893796 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1385893796
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.736464640
Short name T932
Test name
Test status
Simulation time 148687104 ps
CPU time 2.72 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 200492 kb
Host smart-d391c36a-8ebc-4dfa-97e0-09a404a09342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736464640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkm
gr_tl_errors.736464640
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3064026720
Short name T110
Test name
Test status
Simulation time 223959196 ps
CPU time 3.17 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 200500 kb
Host smart-b711401c-729c-466f-a497-744407950d96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064026720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3064026720
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.490466752
Short name T894
Test name
Test status
Simulation time 117927434 ps
CPU time 1.39 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:23 PM PDT 24
Peak memory 200344 kb
Host smart-27ac4def-75e1-4b7b-abe7-dbd5961f46c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490466752 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.490466752
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.3704379575
Short name T854
Test name
Test status
Simulation time 18960974 ps
CPU time 0.79 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:22 PM PDT 24
Peak memory 200248 kb
Host smart-b4bd9ec0-5c3b-4a16-98dc-860699969ec3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704379575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.3704379575
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2673581945
Short name T829
Test name
Test status
Simulation time 20538276 ps
CPU time 0.7 seconds
Started Aug 03 04:51:17 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 198940 kb
Host smart-d1f0cd87-2192-4d78-9fc5-ac740c0ea6ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673581945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.2673581945
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.944575140
Short name T897
Test name
Test status
Simulation time 30586061 ps
CPU time 1.19 seconds
Started Aug 03 04:51:17 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 200352 kb
Host smart-2704d83e-40d5-4ed5-a45c-a832306af7ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944575140 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.clkmgr_same_csr_outstanding.944575140
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.3561641776
Short name T951
Test name
Test status
Simulation time 107830181 ps
CPU time 2.08 seconds
Started Aug 03 04:51:21 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 200744 kb
Host smart-0dce7256-3cf3-4e72-9ff5-1faec9b8f312
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561641776 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.3561641776
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1265455360
Short name T125
Test name
Test status
Simulation time 253333080 ps
CPU time 3 seconds
Started Aug 03 04:51:17 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 201008 kb
Host smart-3bd3572e-2f0b-48f4-937b-d56c1a4f2afb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265455360 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.1265455360
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.3938726725
Short name T824
Test name
Test status
Simulation time 545488474 ps
CPU time 3.73 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 200512 kb
Host smart-71a82af7-e034-4fb0-8b0d-14b0f1ee65f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938726725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.3938726725
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3210207833
Short name T847
Test name
Test status
Simulation time 222843911 ps
CPU time 2.04 seconds
Started Aug 03 04:51:12 PM PDT 24
Finished Aug 03 04:51:14 PM PDT 24
Peak memory 200488 kb
Host smart-d5e39836-a01f-448d-918b-dcacfc7f078f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210207833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3210207833
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.333384464
Short name T886
Test name
Test status
Simulation time 146052851 ps
CPU time 1.29 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200392 kb
Host smart-af6537fc-a283-48de-83ab-818394e4ac29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333384464 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.333384464
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.1706091032
Short name T979
Test name
Test status
Simulation time 18172333 ps
CPU time 0.8 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200304 kb
Host smart-db5447ae-3db2-4021-8735-14261dbbac3f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706091032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.1706091032
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2413636785
Short name T860
Test name
Test status
Simulation time 10557296 ps
CPU time 0.67 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 198940 kb
Host smart-336b5c89-8970-4b78-9b51-3c5edaf53b29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413636785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.2413636785
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2406174860
Short name T877
Test name
Test status
Simulation time 91970493 ps
CPU time 1.46 seconds
Started Aug 03 04:51:22 PM PDT 24
Finished Aug 03 04:51:24 PM PDT 24
Peak memory 200548 kb
Host smart-d4c4d5cb-a14f-42ca-a218-6df2f12a3c15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406174860 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.2406174860
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.779422993
Short name T59
Test name
Test status
Simulation time 95459515 ps
CPU time 1.25 seconds
Started Aug 03 04:51:13 PM PDT 24
Finished Aug 03 04:51:15 PM PDT 24
Peak memory 200544 kb
Host smart-88aabf89-3321-43c1-9af1-ad2132f94a9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779422993 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.clkmgr_shadow_reg_errors.779422993
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3792355272
Short name T135
Test name
Test status
Simulation time 151427720 ps
CPU time 2.91 seconds
Started Aug 03 04:51:15 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 208976 kb
Host smart-ee4d65bc-29db-4a36-b357-9125f28fca86
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792355272 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3792355272
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.764061127
Short name T950
Test name
Test status
Simulation time 34846648 ps
CPU time 2.1 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200500 kb
Host smart-39eb43db-aaa3-4e2b-8de4-c0527ea612ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764061127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.764061127
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.740988
Short name T887
Test name
Test status
Simulation time 35778535 ps
CPU time 1.13 seconds
Started Aug 03 04:51:25 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200480 kb
Host smart-27338560-8500-49f2-a6b5-169fa3588575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740988 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.740988
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3167278474
Short name T896
Test name
Test status
Simulation time 74112237 ps
CPU time 0.96 seconds
Started Aug 03 04:51:25 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200488 kb
Host smart-a64d6018-7fa0-45c2-bfb3-93b986da94a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167278474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3167278474
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.1654978972
Short name T893
Test name
Test status
Simulation time 41938825 ps
CPU time 0.72 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:19 PM PDT 24
Peak memory 198900 kb
Host smart-7120f520-ec92-43d0-9abc-f4c7b302feed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654978972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.1654978972
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3888271038
Short name T970
Test name
Test status
Simulation time 88449742 ps
CPU time 1.45 seconds
Started Aug 03 04:51:23 PM PDT 24
Finished Aug 03 04:51:25 PM PDT 24
Peak memory 200580 kb
Host smart-56c6dd88-9654-499e-842c-b1913efcff43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888271038 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.3888271038
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.515902257
Short name T128
Test name
Test status
Simulation time 108689688 ps
CPU time 1.4 seconds
Started Aug 03 04:51:16 PM PDT 24
Finished Aug 03 04:51:18 PM PDT 24
Peak memory 200620 kb
Host smart-f9abc5bf-3be6-44c1-8c77-65504b55cc0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515902257 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.clkmgr_shadow_reg_errors.515902257
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.157432985
Short name T55
Test name
Test status
Simulation time 150212657 ps
CPU time 2.64 seconds
Started Aug 03 04:51:18 PM PDT 24
Finished Aug 03 04:51:21 PM PDT 24
Peak memory 217096 kb
Host smart-4fbf3c04-5b89-49bc-9c06-d21d71a2a2f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157432985 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.157432985
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.1566242519
Short name T930
Test name
Test status
Simulation time 50210554 ps
CPU time 1.6 seconds
Started Aug 03 04:51:14 PM PDT 24
Finished Aug 03 04:51:16 PM PDT 24
Peak memory 200500 kb
Host smart-de3ce12f-89d7-432b-abed-d12ddc22f3b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566242519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.1566242519
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.3414158730
Short name T936
Test name
Test status
Simulation time 121774577 ps
CPU time 2.57 seconds
Started Aug 03 04:51:24 PM PDT 24
Finished Aug 03 04:51:26 PM PDT 24
Peak memory 200584 kb
Host smart-9dcb86a8-3899-4ab8-8de9-78eed78aceb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414158730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.3414158730
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.879827312
Short name T580
Test name
Test status
Simulation time 53493945 ps
CPU time 0.87 seconds
Started Aug 03 05:07:55 PM PDT 24
Finished Aug 03 05:07:56 PM PDT 24
Peak memory 201052 kb
Host smart-ed8be23c-ad63-410b-af5d-bb56d33892af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879827312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_alert_test.879827312
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1323973545
Short name T478
Test name
Test status
Simulation time 44595467 ps
CPU time 0.84 seconds
Started Aug 03 05:08:04 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 201096 kb
Host smart-e600f1c9-6b5d-4a7a-9062-675f30886739
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323973545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1323973545
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.1673976783
Short name T771
Test name
Test status
Simulation time 17790508 ps
CPU time 0.74 seconds
Started Aug 03 05:07:49 PM PDT 24
Finished Aug 03 05:07:50 PM PDT 24
Peak memory 200292 kb
Host smart-c8eab96c-0b15-4e9c-a5d7-56a721ba8a7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673976783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.1673976783
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.714162108
Short name T533
Test name
Test status
Simulation time 27970872 ps
CPU time 0.75 seconds
Started Aug 03 05:07:59 PM PDT 24
Finished Aug 03 05:08:00 PM PDT 24
Peak memory 200992 kb
Host smart-24ae7899-0a6d-46c5-be7f-9dee70a5f3af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714162108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.714162108
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2526727330
Short name T538
Test name
Test status
Simulation time 16188566 ps
CPU time 0.77 seconds
Started Aug 03 05:07:54 PM PDT 24
Finished Aug 03 05:07:55 PM PDT 24
Peak memory 201000 kb
Host smart-cd061766-26e5-4327-8032-d1720c1c4b30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526727330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2526727330
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.4257212745
Short name T25
Test name
Test status
Simulation time 808815332 ps
CPU time 4.81 seconds
Started Aug 03 05:07:47 PM PDT 24
Finished Aug 03 05:07:52 PM PDT 24
Peak memory 201156 kb
Host smart-7148f8d9-71eb-47e4-8a1f-395eb214ed50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257212745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.4257212745
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.1799925885
Short name T198
Test name
Test status
Simulation time 155277114 ps
CPU time 1.24 seconds
Started Aug 03 05:07:46 PM PDT 24
Finished Aug 03 05:07:47 PM PDT 24
Peak memory 201152 kb
Host smart-9a2495ce-6c4e-45d6-9374-b26e8050e0f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799925885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.1799925885
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.554826634
Short name T327
Test name
Test status
Simulation time 27714800 ps
CPU time 0.91 seconds
Started Aug 03 05:07:53 PM PDT 24
Finished Aug 03 05:07:54 PM PDT 24
Peak memory 201084 kb
Host smart-ceaf72bd-8ff0-4cea-a715-a34bb15f92d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554826634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_idle_intersig_mubi.554826634
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.2402834183
Short name T303
Test name
Test status
Simulation time 58538799 ps
CPU time 0.96 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201108 kb
Host smart-63a2fa38-1372-4958-b8dd-9b1435cfee5a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402834183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.2402834183
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.619054899
Short name T645
Test name
Test status
Simulation time 43926036 ps
CPU time 0.99 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201096 kb
Host smart-b58d9615-585c-4d90-8db2-79e1323ca2da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619054899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.619054899
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.542430707
Short name T197
Test name
Test status
Simulation time 20048083 ps
CPU time 0.81 seconds
Started Aug 03 05:07:58 PM PDT 24
Finished Aug 03 05:07:59 PM PDT 24
Peak memory 201044 kb
Host smart-59160a8b-56f6-4420-ba0e-25398398746a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542430707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.542430707
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.2324198814
Short name T174
Test name
Test status
Simulation time 15620193 ps
CPU time 0.79 seconds
Started Aug 03 05:07:45 PM PDT 24
Finished Aug 03 05:07:46 PM PDT 24
Peak memory 201016 kb
Host smart-65667300-cdeb-4f38-95d8-d556d4b3380a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324198814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2324198814
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.3807132366
Short name T36
Test name
Test status
Simulation time 2922351973 ps
CPU time 12.27 seconds
Started Aug 03 05:08:00 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 201392 kb
Host smart-a5944450-dcd6-4eed-801c-ad4d38a9dc64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807132366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.3807132366
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.78349135
Short name T452
Test name
Test status
Simulation time 121477994 ps
CPU time 1.31 seconds
Started Aug 03 05:07:46 PM PDT 24
Finished Aug 03 05:07:48 PM PDT 24
Peak memory 200956 kb
Host smart-8cbe8d88-130d-48c8-9794-d3058459da5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78349135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.78349135
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.3689404415
Short name T647
Test name
Test status
Simulation time 34043865 ps
CPU time 0.82 seconds
Started Aug 03 05:07:54 PM PDT 24
Finished Aug 03 05:07:55 PM PDT 24
Peak memory 201076 kb
Host smart-d21cc642-156a-4da6-8885-655302a324c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689404415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.3689404415
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1822431245
Short name T629
Test name
Test status
Simulation time 94382377 ps
CPU time 1.18 seconds
Started Aug 03 05:08:00 PM PDT 24
Finished Aug 03 05:08:01 PM PDT 24
Peak memory 201116 kb
Host smart-ec641318-876e-41a6-8765-1aaed143236c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822431245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.1822431245
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3569159469
Short name T505
Test name
Test status
Simulation time 56606599 ps
CPU time 0.91 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201084 kb
Host smart-67653879-6dc7-4720-a0f2-ed394a99c7d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569159469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3569159469
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.1136808643
Short name T761
Test name
Test status
Simulation time 92279050 ps
CPU time 1.1 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201056 kb
Host smart-17c30650-0098-48c5-9540-d6e15871f432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136808643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1136808643
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3937029480
Short name T676
Test name
Test status
Simulation time 676917365 ps
CPU time 5.59 seconds
Started Aug 03 05:07:59 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201160 kb
Host smart-ee2f7364-18e1-41c0-b1a3-e58976e5a034
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937029480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3937029480
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.1861672242
Short name T614
Test name
Test status
Simulation time 1343721306 ps
CPU time 7.49 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201164 kb
Host smart-22e3ad3f-d082-4f02-be6b-0e3f001cb906
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861672242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.1861672242
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2403570104
Short name T768
Test name
Test status
Simulation time 72430605 ps
CPU time 1.06 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201048 kb
Host smart-5181c2d8-4196-4aa0-8237-585d47d2d3e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403570104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2403570104
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3884682828
Short name T270
Test name
Test status
Simulation time 21731382 ps
CPU time 0.87 seconds
Started Aug 03 05:07:57 PM PDT 24
Finished Aug 03 05:07:58 PM PDT 24
Peak memory 201024 kb
Host smart-c91829f3-7926-49e3-a46a-ea7b46b4db14
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884682828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3884682828
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3475841456
Short name T812
Test name
Test status
Simulation time 49017702 ps
CPU time 0.98 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 200984 kb
Host smart-aad9875b-8f50-48a0-8711-94b713328d34
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475841456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.3475841456
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.57053529
Short name T273
Test name
Test status
Simulation time 38040253 ps
CPU time 0.87 seconds
Started Aug 03 05:07:58 PM PDT 24
Finished Aug 03 05:07:59 PM PDT 24
Peak memory 201232 kb
Host smart-b823182d-d8d1-4b2d-a07a-1768eabc9d9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57053529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.57053529
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.998110490
Short name T415
Test name
Test status
Simulation time 194728292 ps
CPU time 1.61 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 201052 kb
Host smart-ff3a6231-e446-47b6-85f3-0d378a0aae74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998110490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.998110490
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.307490996
Short name T44
Test name
Test status
Simulation time 783079693 ps
CPU time 4.39 seconds
Started Aug 03 05:08:00 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 221872 kb
Host smart-9a3e8cf1-e848-41ba-a106-de50ef42323c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307490996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr
_sec_cm.307490996
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1250014389
Short name T576
Test name
Test status
Simulation time 15822619 ps
CPU time 0.81 seconds
Started Aug 03 05:08:00 PM PDT 24
Finished Aug 03 05:08:01 PM PDT 24
Peak memory 200884 kb
Host smart-c778ee24-fa05-4e04-a81f-15a3071b6bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250014389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1250014389
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.3644817521
Short name T242
Test name
Test status
Simulation time 778334957 ps
CPU time 5.9 seconds
Started Aug 03 05:07:56 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201188 kb
Host smart-13a8a4f0-6135-491c-92a9-1bdf91ac7c7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644817521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.3644817521
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.1036628129
Short name T71
Test name
Test status
Simulation time 120622579956 ps
CPU time 854.13 seconds
Started Aug 03 05:07:54 PM PDT 24
Finished Aug 03 05:22:08 PM PDT 24
Peak memory 217936 kb
Host smart-c52ad8cc-2c31-4f71-a293-2b74cf7c04c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1036628129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1036628129
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.1229482144
Short name T418
Test name
Test status
Simulation time 17278382 ps
CPU time 0.79 seconds
Started Aug 03 05:07:59 PM PDT 24
Finished Aug 03 05:08:00 PM PDT 24
Peak memory 200936 kb
Host smart-b4789abf-d4c7-4fcf-b08a-4377944f690a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229482144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1229482144
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.862802361
Short name T819
Test name
Test status
Simulation time 12414161 ps
CPU time 0.75 seconds
Started Aug 03 05:08:19 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201104 kb
Host smart-908e471c-a133-4502-bc77-257d90fd51ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862802361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkm
gr_alert_test.862802361
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1903834760
Short name T589
Test name
Test status
Simulation time 39823093 ps
CPU time 0.91 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201032 kb
Host smart-84aea643-ebd3-44d9-8b5a-298aefc7d281
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903834760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1903834760
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.3486620473
Short name T658
Test name
Test status
Simulation time 12590194 ps
CPU time 0.69 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 200220 kb
Host smart-703cb259-48f3-4f3e-9a31-e41106fba2fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486620473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.3486620473
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1933471953
Short name T568
Test name
Test status
Simulation time 12930340 ps
CPU time 0.7 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 200916 kb
Host smart-820c7171-5e91-4b66-bc83-e236e5a28db5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933471953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1933471953
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2946594229
Short name T51
Test name
Test status
Simulation time 22827073 ps
CPU time 0.88 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201008 kb
Host smart-19a610ab-426d-4a3c-a1cf-48e2168f110e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946594229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2946594229
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.2259217171
Short name T758
Test name
Test status
Simulation time 1612194419 ps
CPU time 7.15 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201104 kb
Host smart-1a041651-5ee2-49bd-9c4e-988af832acca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259217171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2259217171
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.103606318
Short name T762
Test name
Test status
Simulation time 625487899 ps
CPU time 4.04 seconds
Started Aug 03 05:08:16 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201192 kb
Host smart-46bf3ca8-3eb9-4c9e-b308-3aed582f539f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103606318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_ti
meout.103606318
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.4054905554
Short name T182
Test name
Test status
Simulation time 88849013 ps
CPU time 1.05 seconds
Started Aug 03 05:08:19 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201096 kb
Host smart-657dba9e-6bb7-4e2e-b872-57f76abfe6c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054905554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.4054905554
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.4164720273
Short name T116
Test name
Test status
Simulation time 84149284 ps
CPU time 0.99 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 200396 kb
Host smart-d214b217-f872-453d-8b24-e96d132920e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164720273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.4164720273
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.749887666
Short name T266
Test name
Test status
Simulation time 15939206 ps
CPU time 0.71 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201048 kb
Host smart-0fc56677-e415-4b48-9722-a91ba204b8b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749887666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.clkmgr_lc_ctrl_intersig_mubi.749887666
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3309006857
Short name T479
Test name
Test status
Simulation time 83619937 ps
CPU time 0.94 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201072 kb
Host smart-845bc42b-e103-4b4c-977d-bebfffc1c5a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309006857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3309006857
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.756660118
Short name T214
Test name
Test status
Simulation time 704724025 ps
CPU time 3.81 seconds
Started Aug 03 05:08:16 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201280 kb
Host smart-9f062764-27ab-44a1-9ff7-3f277df959d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756660118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.756660118
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.984632386
Short name T154
Test name
Test status
Simulation time 70467504 ps
CPU time 1.02 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 200936 kb
Host smart-ac926ff6-7cc1-4b81-a3ad-f02bdf9125a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984632386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.984632386
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.3622870969
Short name T575
Test name
Test status
Simulation time 9030493893 ps
CPU time 66.28 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201416 kb
Host smart-8b47dd89-888f-4235-8dff-f9656827d0ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622870969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.3622870969
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.2711615135
Short name T639
Test name
Test status
Simulation time 106132037247 ps
CPU time 675.25 seconds
Started Aug 03 05:08:15 PM PDT 24
Finished Aug 03 05:19:31 PM PDT 24
Peak memory 209756 kb
Host smart-b2f459d2-cf2e-4246-b30d-b51b019c4e46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2711615135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.2711615135
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2429012706
Short name T740
Test name
Test status
Simulation time 27829076 ps
CPU time 1.06 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201096 kb
Host smart-aef5f98d-8cc4-48ba-9276-01b82ba7a443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429012706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2429012706
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3900442018
Short name T165
Test name
Test status
Simulation time 40048101 ps
CPU time 0.78 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:24 PM PDT 24
Peak memory 200248 kb
Host smart-98226928-a54a-49e3-9b86-c66d7603ea6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900442018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3900442018
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.1484788035
Short name T196
Test name
Test status
Simulation time 24759537 ps
CPU time 0.88 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 200992 kb
Host smart-395c2bc4-19de-4de9-863c-447f46fc7e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484788035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.1484788035
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1239035846
Short name T773
Test name
Test status
Simulation time 341153059 ps
CPU time 2.03 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 200992 kb
Host smart-29742fdb-72b5-4ac0-a3ab-da0828b2ef10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239035846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1239035846
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.2632920469
Short name T29
Test name
Test status
Simulation time 1821462532 ps
CPU time 13.23 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201036 kb
Host smart-31610218-4098-4c07-8806-559d40b2321a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632920469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.2632920469
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.4157998840
Short name T437
Test name
Test status
Simulation time 97794836 ps
CPU time 1.18 seconds
Started Aug 03 05:08:23 PM PDT 24
Finished Aug 03 05:08:24 PM PDT 24
Peak memory 200996 kb
Host smart-e91c1025-cab5-49e1-9bc5-fa803477a2bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157998840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.4157998840
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1639268525
Short name T257
Test name
Test status
Simulation time 50094647 ps
CPU time 0.83 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:28 PM PDT 24
Peak memory 201220 kb
Host smart-8f49a843-117f-4444-8d4e-20d5cb1e8a8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639268525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1639268525
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.886361367
Short name T784
Test name
Test status
Simulation time 40168656 ps
CPU time 0.86 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201008 kb
Host smart-2a374bc0-1c28-4fb5-a6b7-df58ea476fcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886361367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.886361367
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.962980118
Short name T136
Test name
Test status
Simulation time 21676010 ps
CPU time 0.82 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201028 kb
Host smart-3f5f5bf5-b0b6-452a-87aa-8de0b6fd326a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962980118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.962980118
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.818634404
Short name T574
Test name
Test status
Simulation time 10443176501 ps
CPU time 43 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 201456 kb
Host smart-997eabe1-b761-4078-a79d-b6c3f320db3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818634404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.818634404
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.1092555128
Short name T510
Test name
Test status
Simulation time 44620294 ps
CPU time 0.81 seconds
Started Aug 03 05:08:19 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201116 kb
Host smart-b5bdab75-e432-46cc-98e9-e03703cc5762
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092555128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1092555128
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.1455238658
Short name T449
Test name
Test status
Simulation time 22470052 ps
CPU time 0.86 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:25 PM PDT 24
Peak memory 201072 kb
Host smart-67236ad4-8bef-49ef-8d5a-f56339b707ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455238658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.1455238658
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3617654334
Short name T618
Test name
Test status
Simulation time 27503763 ps
CPU time 0.77 seconds
Started Aug 03 05:08:32 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 200940 kb
Host smart-4b779472-33f0-4823-acb7-943d40ff5cb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617654334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3617654334
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1512647562
Short name T237
Test name
Test status
Simulation time 50055352 ps
CPU time 0.8 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:27 PM PDT 24
Peak memory 200260 kb
Host smart-d8ead16b-4cb1-46ee-a388-689720d972aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512647562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1512647562
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.3517712924
Short name T456
Test name
Test status
Simulation time 85098669 ps
CPU time 1.06 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:25 PM PDT 24
Peak memory 201004 kb
Host smart-67118ce3-b5eb-4f26-8bde-f05a73cd0ea1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517712924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.3517712924
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.1400295704
Short name T436
Test name
Test status
Simulation time 309388519 ps
CPU time 1.72 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:28 PM PDT 24
Peak memory 201000 kb
Host smart-50d8aebc-88ca-4020-af89-9fe93828c215
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400295704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1400295704
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.970528539
Short name T261
Test name
Test status
Simulation time 917788542 ps
CPU time 7.35 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 201172 kb
Host smart-b04c28ff-462e-4fba-9be8-07aa84826591
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970528539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.970528539
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.47595862
Short name T598
Test name
Test status
Simulation time 1460259084 ps
CPU time 11.13 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201176 kb
Host smart-536c6b07-38de-402b-8f1f-2d79fa08b543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47595862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_tim
eout.47595862
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.4255866256
Short name T79
Test name
Test status
Simulation time 27977907 ps
CPU time 0.94 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:34 PM PDT 24
Peak memory 200876 kb
Host smart-9408ff10-3608-44c4-ab88-540e4232c326
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255866256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.4255866256
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.413236572
Short name T602
Test name
Test status
Simulation time 61150417 ps
CPU time 0.94 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201064 kb
Host smart-a074b7d7-75ab-48cd-9095-541591b5bd4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413236572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.413236572
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.669482949
Short name T802
Test name
Test status
Simulation time 39714945 ps
CPU time 0.85 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:25 PM PDT 24
Peak memory 201076 kb
Host smart-6c06e8a2-c54d-4e3f-96df-718da575ce4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669482949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_ctrl_intersig_mubi.669482949
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.3160743943
Short name T287
Test name
Test status
Simulation time 18855368 ps
CPU time 0.71 seconds
Started Aug 03 05:08:34 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 200912 kb
Host smart-029c9f51-24ba-4bda-881c-5f38791d09d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160743943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3160743943
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.1745898514
Short name T346
Test name
Test status
Simulation time 110416049 ps
CPU time 1.05 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:27 PM PDT 24
Peak memory 201008 kb
Host smart-2bb4b31b-d4a7-43ab-ad88-513377d6a155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745898514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.1745898514
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.1076287793
Short name T615
Test name
Test status
Simulation time 17271777 ps
CPU time 0.83 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201032 kb
Host smart-63c9b029-8cde-406b-967e-9f8c2365a34a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076287793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1076287793
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.590254935
Short name T516
Test name
Test status
Simulation time 979831772 ps
CPU time 5.02 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:29 PM PDT 24
Peak memory 201076 kb
Host smart-c857912a-3f18-4557-a2a1-08c775bfb363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590254935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.590254935
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all_with_rand_reset.3958347500
Short name T68
Test name
Test status
Simulation time 149921709313 ps
CPU time 955.85 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:24:21 PM PDT 24
Peak memory 217896 kb
Host smart-57e6417b-b71c-42aa-a797-16aeb93c5370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3958347500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.3958347500
Directory /workspace/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1493304162
Short name T419
Test name
Test status
Simulation time 26410111 ps
CPU time 0.85 seconds
Started Aug 03 05:08:34 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 200936 kb
Host smart-b82a30b8-76db-46bf-ad4c-df462b49e9b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493304162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1493304162
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.1287916691
Short name T612
Test name
Test status
Simulation time 23275754 ps
CPU time 0.8 seconds
Started Aug 03 05:08:32 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 201028 kb
Host smart-abacf1aa-9159-4193-9a07-b9ef1d64efa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287916691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.1287916691
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.3354101936
Short name T540
Test name
Test status
Simulation time 78629719 ps
CPU time 1.03 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:29 PM PDT 24
Peak memory 201088 kb
Host smart-ec953d20-4182-4b49-b296-20dd8e022ade
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354101936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.3354101936
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.1689314391
Short name T405
Test name
Test status
Simulation time 31173049 ps
CPU time 0.75 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 200224 kb
Host smart-a3a84438-cf30-4436-a900-2cacb13ca888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689314391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1689314391
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.2713422576
Short name T344
Test name
Test status
Simulation time 69521040 ps
CPU time 1.02 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 201072 kb
Host smart-e1bc600a-56aa-4b15-a63b-e445972e8f08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713422576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.2713422576
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.22039045
Short name T297
Test name
Test status
Simulation time 29075620 ps
CPU time 0.93 seconds
Started Aug 03 05:08:25 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201036 kb
Host smart-71b285e9-314b-43bb-a600-f937becc6e2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22039045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.22039045
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.394706078
Short name T11
Test name
Test status
Simulation time 2485465519 ps
CPU time 14.45 seconds
Started Aug 03 05:08:24 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 201376 kb
Host smart-c98d9c66-b0b8-4dd7-81de-cb38886018e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394706078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.394706078
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3203881139
Short name T731
Test name
Test status
Simulation time 644481325 ps
CPU time 3.22 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201120 kb
Host smart-98ab48bb-5547-486c-bf73-9ef317a478be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203881139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3203881139
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3351956943
Short name T711
Test name
Test status
Simulation time 19403760 ps
CPU time 0.76 seconds
Started Aug 03 05:08:32 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 201104 kb
Host smart-2698865f-5c6e-4f64-94e4-0cf828709986
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351956943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.3351956943
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1712749574
Short name T331
Test name
Test status
Simulation time 72596459 ps
CPU time 0.98 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 201064 kb
Host smart-55324f40-b5c5-477d-8d73-ee0a42ba36dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712749574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1712749574
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1281052501
Short name T15
Test name
Test status
Simulation time 36797025 ps
CPU time 0.81 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 200924 kb
Host smart-06906e36-ee6b-4879-97d7-eebfb08f74c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281052501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1281052501
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1881609349
Short name T389
Test name
Test status
Simulation time 19137245 ps
CPU time 0.74 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 200992 kb
Host smart-9040effd-a2c8-4136-be13-b39359ceb6e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881609349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1881609349
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1060643403
Short name T531
Test name
Test status
Simulation time 947860899 ps
CPU time 3.71 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 201200 kb
Host smart-2bdbad51-48e4-48a1-8350-4ff69b090598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060643403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1060643403
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2492649431
Short name T382
Test name
Test status
Simulation time 19944742 ps
CPU time 0.87 seconds
Started Aug 03 05:08:26 PM PDT 24
Finished Aug 03 05:08:27 PM PDT 24
Peak memory 201020 kb
Host smart-778ce962-593c-461d-8621-1cebec9a14b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492649431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2492649431
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1946864018
Short name T764
Test name
Test status
Simulation time 10055110433 ps
CPU time 42.83 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201492 kb
Host smart-8840cedb-1e31-435e-8ef3-39e5bb764ec6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946864018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1946864018
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3911606543
Short name T772
Test name
Test status
Simulation time 147000133 ps
CPU time 1.54 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201072 kb
Host smart-22e76cd8-3801-4955-86e3-f5419e9d6985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911606543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3911606543
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.2362874012
Short name T252
Test name
Test status
Simulation time 25426962 ps
CPU time 0.89 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201012 kb
Host smart-4f9b6070-2c0e-47f2-97ca-4c95b36b24ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362874012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.2362874012
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1992101297
Short name T596
Test name
Test status
Simulation time 85688689 ps
CPU time 1.07 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 201064 kb
Host smart-d5980a00-e93f-445e-994c-8e6880b27ed2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992101297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.1992101297
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1781271846
Short name T279
Test name
Test status
Simulation time 23995058 ps
CPU time 0.82 seconds
Started Aug 03 05:08:27 PM PDT 24
Finished Aug 03 05:08:28 PM PDT 24
Peak memory 200996 kb
Host smart-13b7bca2-db52-4ce0-a1e1-90ae29b791f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781271846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1781271846
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.2821964606
Short name T754
Test name
Test status
Simulation time 44057742 ps
CPU time 0.87 seconds
Started Aug 03 05:08:34 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 201036 kb
Host smart-eae3361d-0b9e-431b-a48b-2eefa02e7294
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821964606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_div_intersig_mubi.2821964606
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3165770900
Short name T705
Test name
Test status
Simulation time 23876652 ps
CPU time 0.88 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201056 kb
Host smart-2e92dc0a-1720-40a6-adeb-087f69400874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165770900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3165770900
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.178694897
Short name T481
Test name
Test status
Simulation time 1397288008 ps
CPU time 10.69 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201100 kb
Host smart-883ba514-ec5f-4602-a37a-6461f9d2765a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178694897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.178694897
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.2177929529
Short name T552
Test name
Test status
Simulation time 1239238223 ps
CPU time 5.63 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 201152 kb
Host smart-0bf7b205-ef66-4ccf-8a07-d735207c62e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177929529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.2177929529
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2651554565
Short name T296
Test name
Test status
Simulation time 38257619 ps
CPU time 1.09 seconds
Started Aug 03 05:08:34 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 201016 kb
Host smart-76a4b2a5-0480-4637-9cfa-518b36fcc32c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651554565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.2651554565
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.3417700007
Short name T153
Test name
Test status
Simulation time 27401992 ps
CPU time 0.84 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:34 PM PDT 24
Peak memory 201048 kb
Host smart-0ab81979-a3f2-4edb-a5e5-a37a7c240a9a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417700007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.3417700007
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3048924572
Short name T564
Test name
Test status
Simulation time 76121326 ps
CPU time 1.03 seconds
Started Aug 03 05:08:32 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 201028 kb
Host smart-538f23df-c3a4-4c80-8a94-5b269a780fd6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048924572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3048924572
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.1845077843
Short name T379
Test name
Test status
Simulation time 26382773 ps
CPU time 0.74 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 201036 kb
Host smart-e19a459e-1b67-421e-b628-014491f05371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845077843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.1845077843
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.1726424659
Short name T85
Test name
Test status
Simulation time 1162039108 ps
CPU time 4.28 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 201204 kb
Host smart-a08d3a39-689f-4b44-a32e-09b21650cd65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726424659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.1726424659
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1613341994
Short name T20
Test name
Test status
Simulation time 21056339 ps
CPU time 0.85 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 201028 kb
Host smart-06982b36-806c-4b11-b7bd-a9a9ff2824e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613341994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1613341994
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2553266729
Short name T35
Test name
Test status
Simulation time 5294615692 ps
CPU time 28.05 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201428 kb
Host smart-30705dda-7495-4b5a-8fd2-d43cd4abaad7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553266729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2553266729
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2371151916
Short name T265
Test name
Test status
Simulation time 34752521 ps
CPU time 1.07 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 200968 kb
Host smart-088664b7-92b4-4301-90e2-e60d5d0a836e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371151916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2371151916
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1807708900
Short name T609
Test name
Test status
Simulation time 25830369 ps
CPU time 0.84 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:34 PM PDT 24
Peak memory 201024 kb
Host smart-0e441aa3-ec34-4ee7-8864-7edcde3f0a07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807708900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1807708900
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2642913546
Short name T46
Test name
Test status
Simulation time 66198191 ps
CPU time 0.96 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 201064 kb
Host smart-e6a37a85-a6a8-4022-96ed-a5f8da9ef05c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642913546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2642913546
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.886509869
Short name T571
Test name
Test status
Simulation time 52616151 ps
CPU time 0.83 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 200296 kb
Host smart-5176f054-79f1-4135-8e66-3751e9aef4aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886509869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.886509869
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.4227213466
Short name T224
Test name
Test status
Simulation time 16179046 ps
CPU time 0.79 seconds
Started Aug 03 05:08:28 PM PDT 24
Finished Aug 03 05:08:29 PM PDT 24
Peak memory 201032 kb
Host smart-1822efd1-872b-4617-86c7-57263e4596d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227213466 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.4227213466
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.32728898
Short name T467
Test name
Test status
Simulation time 51870333 ps
CPU time 0.95 seconds
Started Aug 03 05:08:34 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 200960 kb
Host smart-9b67baa7-895c-4b7e-85b0-a0417dcb5fe9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32728898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.32728898
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.3262655242
Short name T791
Test name
Test status
Simulation time 681705371 ps
CPU time 5.64 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 201112 kb
Host smart-207f0bbe-d9d1-42e0-aed7-9ea68b971c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262655242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.3262655242
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.1163318424
Short name T610
Test name
Test status
Simulation time 262171653 ps
CPU time 2.47 seconds
Started Aug 03 05:08:33 PM PDT 24
Finished Aug 03 05:08:35 PM PDT 24
Peak memory 201172 kb
Host smart-e803666d-2aef-40ae-b775-b8cbef725690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163318424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.1163318424
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1207906134
Short name T52
Test name
Test status
Simulation time 31324967 ps
CPU time 0.87 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 201052 kb
Host smart-707f19e2-7233-4cce-9bc7-4fb86c39f74b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207906134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1207906134
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.2695966813
Short name T699
Test name
Test status
Simulation time 194106510 ps
CPU time 1.3 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:32 PM PDT 24
Peak memory 201056 kb
Host smart-5f356982-f506-4eeb-8dbf-e05b4a6d47b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695966813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.2695966813
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1726532056
Short name T288
Test name
Test status
Simulation time 50473466 ps
CPU time 0.99 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201060 kb
Host smart-37c70649-a17f-4140-8160-5dcdb8c2ca76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726532056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1726532056
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.1734854685
Short name T304
Test name
Test status
Simulation time 17786951 ps
CPU time 0.76 seconds
Started Aug 03 05:08:32 PM PDT 24
Finished Aug 03 05:08:33 PM PDT 24
Peak memory 201068 kb
Host smart-79fe80c9-7a41-414e-8fac-3d1d71fd4cde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734854685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1734854685
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.2563162990
Short name T439
Test name
Test status
Simulation time 695228777 ps
CPU time 3 seconds
Started Aug 03 05:08:31 PM PDT 24
Finished Aug 03 05:08:34 PM PDT 24
Peak memory 201244 kb
Host smart-bedfab51-723e-4fc0-b36f-6c7c8d39381d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563162990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.2563162990
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.2416895351
Short name T4
Test name
Test status
Simulation time 67340593 ps
CPU time 0.96 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 200936 kb
Host smart-149cc57d-65f5-4196-8e4e-0120985cc313
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416895351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.2416895351
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.3437032042
Short name T649
Test name
Test status
Simulation time 4644578510 ps
CPU time 14.84 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201512 kb
Host smart-89e5b1d9-3d3c-4557-bdeb-1366912c5067
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437032042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.3437032042
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.1775327965
Short name T457
Test name
Test status
Simulation time 73163545 ps
CPU time 1.17 seconds
Started Aug 03 05:08:29 PM PDT 24
Finished Aug 03 05:08:30 PM PDT 24
Peak memory 201096 kb
Host smart-327d7f32-4a75-4b39-b2b4-c7e638b6f328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775327965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.1775327965
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.3950972611
Short name T604
Test name
Test status
Simulation time 35753418 ps
CPU time 0.86 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201040 kb
Host smart-31df0d0e-8780-4a05-96eb-b90578b485e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950972611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.3950972611
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.712333726
Short name T101
Test name
Test status
Simulation time 250332255 ps
CPU time 1.54 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201064 kb
Host smart-b50d6e3c-962d-4a96-bc94-f8422c582d1f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712333726 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.712333726
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2271117930
Short name T272
Test name
Test status
Simulation time 24140714 ps
CPU time 0.72 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 200276 kb
Host smart-38e69400-8025-4ba3-b662-cc0b7d81422f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271117930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2271117930
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.3594569528
Short name T366
Test name
Test status
Simulation time 47888928 ps
CPU time 0.89 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 200968 kb
Host smart-a1926d88-91f7-44e0-8abc-eccabd5d8804
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594569528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.3594569528
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.2469967511
Short name T664
Test name
Test status
Simulation time 53678407 ps
CPU time 0.86 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 201068 kb
Host smart-d57a3c3f-f841-467a-b8ba-31adf4b55456
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469967511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2469967511
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.2171396548
Short name T483
Test name
Test status
Simulation time 557319053 ps
CPU time 4.79 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:42 PM PDT 24
Peak memory 201132 kb
Host smart-265fdad0-f8bb-4bcc-bc21-0c5e355a0636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171396548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.2171396548
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2602248318
Short name T655
Test name
Test status
Simulation time 2303769698 ps
CPU time 12.69 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201448 kb
Host smart-ef54d7d8-5352-459a-9c0b-1ce36b50d8c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602248318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2602248318
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3673611893
Short name T365
Test name
Test status
Simulation time 15253249 ps
CPU time 0.81 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 201024 kb
Host smart-84d2c9c8-1b66-47a3-bba3-c6f3d3d1fb2b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673611893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.3673611893
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1953058846
Short name T670
Test name
Test status
Simulation time 190210178 ps
CPU time 1.42 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 201020 kb
Host smart-94437cfc-f4ae-4c6a-9178-a5f907209e0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953058846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1953058846
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.3568032972
Short name T616
Test name
Test status
Simulation time 25629789 ps
CPU time 0.9 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201028 kb
Host smart-747b0366-50ef-4d7f-9a3d-8b6192234b3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568032972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.3568032972
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.3972489914
Short name T400
Test name
Test status
Simulation time 17017040 ps
CPU time 0.77 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201052 kb
Host smart-8fab6b9e-6eab-4d83-b0d2-623a45eff165
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972489914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3972489914
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.3844973021
Short name T306
Test name
Test status
Simulation time 55424577 ps
CPU time 0.96 seconds
Started Aug 03 05:08:30 PM PDT 24
Finished Aug 03 05:08:31 PM PDT 24
Peak memory 201020 kb
Host smart-a0520e21-f6e3-4310-8b76-06e86222e04a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844973021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3844973021
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.1094729131
Short name T424
Test name
Test status
Simulation time 186255456 ps
CPU time 1.56 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 201016 kb
Host smart-d197e394-a71c-4eac-a827-0e9de16ab6a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094729131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.1094729131
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3655770181
Short name T220
Test name
Test status
Simulation time 16089383 ps
CPU time 0.79 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201044 kb
Host smart-fef898c5-21d3-424f-8455-8894d6b56ad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655770181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3655770181
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.4215074818
Short name T760
Test name
Test status
Simulation time 23452928 ps
CPU time 0.81 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201064 kb
Host smart-d5023c88-ec95-4751-b3c3-17ad2659ad2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215074818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.4215074818
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1311413749
Short name T104
Test name
Test status
Simulation time 86135107 ps
CPU time 1 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201064 kb
Host smart-283b5418-8fd6-4597-a2d7-8e24f1dd41d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311413749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1311413749
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.4041217441
Short name T317
Test name
Test status
Simulation time 47003313 ps
CPU time 0.76 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 200700 kb
Host smart-6b8f85e1-82f3-46cb-913c-011ff7ff903e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041217441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.4041217441
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1985284933
Short name T340
Test name
Test status
Simulation time 54949463 ps
CPU time 0.84 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 201032 kb
Host smart-021834e1-088f-427f-9430-39fbc0e16b44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985284933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1985284933
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.2908480656
Short name T801
Test name
Test status
Simulation time 28841445 ps
CPU time 1.12 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 201016 kb
Host smart-e2a4b929-aa94-4db5-8868-cfb403058b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908480656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2908480656
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.4244596049
Short name T726
Test name
Test status
Simulation time 331796979 ps
CPU time 1.83 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 201148 kb
Host smart-26345029-4246-4f66-a511-193814ec1e30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244596049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.4244596049
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.4253977945
Short name T367
Test name
Test status
Simulation time 617013306 ps
CPU time 4.99 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201136 kb
Host smart-352265a9-6c45-4e8b-9a3d-9fd35397f4f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253977945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.4253977945
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.3940493604
Short name T177
Test name
Test status
Simulation time 22346279 ps
CPU time 0.9 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 201028 kb
Host smart-030e8d9b-5bfe-4da0-8751-abc4edab4bf7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940493604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.3940493604
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.166037711
Short name T636
Test name
Test status
Simulation time 63179430 ps
CPU time 0.99 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 200932 kb
Host smart-6722e684-7e65-4d5e-8c85-095d44dc41b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166037711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.166037711
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1842793879
Short name T499
Test name
Test status
Simulation time 25859423 ps
CPU time 0.76 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 201036 kb
Host smart-c9f9ff98-2195-4847-9e35-326c531875cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842793879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.1842793879
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1852688967
Short name T504
Test name
Test status
Simulation time 18038090 ps
CPU time 0.77 seconds
Started Aug 03 05:08:40 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 200912 kb
Host smart-6c1d5f5b-d238-4b87-9079-2a14f91ecacf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852688967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1852688967
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.4294474352
Short name T585
Test name
Test status
Simulation time 1263528017 ps
CPU time 5.3 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 201260 kb
Host smart-d3fa142a-c8e0-4da4-83bb-ffb08c98876e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294474352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.4294474352
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.2476903362
Short name T534
Test name
Test status
Simulation time 41978076 ps
CPU time 1.04 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 201052 kb
Host smart-7f738e0e-06f7-4db2-a54d-e0c7d9bc1b9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476903362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.2476903362
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.3833835274
Short name T433
Test name
Test status
Simulation time 1313459172 ps
CPU time 8.41 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201304 kb
Host smart-7128df6b-1a81-4530-af4a-b4fa4361af62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833835274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.3833835274
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1915956308
Short name T603
Test name
Test status
Simulation time 64237482482 ps
CPU time 604.49 seconds
Started Aug 03 05:08:40 PM PDT 24
Finished Aug 03 05:18:45 PM PDT 24
Peak memory 209748 kb
Host smart-fd7ee5e5-6d2a-4260-b794-79d54377a413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1915956308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1915956308
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2530714939
Short name T19
Test name
Test status
Simulation time 17740158 ps
CPU time 0.77 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 201040 kb
Host smart-a81fba71-e448-4596-a79b-91451cdec155
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530714939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2530714939
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.4013222888
Short name T290
Test name
Test status
Simulation time 58769132 ps
CPU time 0.89 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:49 PM PDT 24
Peak memory 200996 kb
Host smart-7673b5e8-8650-47fc-b228-627334d3ec31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013222888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.4013222888
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.767274961
Short name T142
Test name
Test status
Simulation time 46814428 ps
CPU time 0.96 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201064 kb
Host smart-303508f8-6604-4695-948e-94040969eec7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767274961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.767274961
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.1926789593
Short name T555
Test name
Test status
Simulation time 37512126 ps
CPU time 0.79 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 200220 kb
Host smart-f50e3647-ee70-4a2d-9a36-e2f77f9c778a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926789593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1926789593
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.4021447493
Short name T351
Test name
Test status
Simulation time 21969720 ps
CPU time 0.88 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 200996 kb
Host smart-b84d43c4-d461-431f-a7ca-b7bf61b9ec6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021447493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.4021447493
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.832521365
Short name T414
Test name
Test status
Simulation time 35052019 ps
CPU time 0.78 seconds
Started Aug 03 05:08:37 PM PDT 24
Finished Aug 03 05:08:38 PM PDT 24
Peak memory 200636 kb
Host smart-f2a5fa29-3634-4f1b-b487-d4522dc006ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832521365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.832521365
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.4242682250
Short name T30
Test name
Test status
Simulation time 329226519 ps
CPU time 2.39 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201088 kb
Host smart-a95b1b7f-1e25-4d2b-8f43-5cceee40f2a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242682250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.4242682250
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.1092611226
Short name T28
Test name
Test status
Simulation time 623634547 ps
CPU time 3.53 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201132 kb
Host smart-e292d401-cb89-46fa-adb7-68249b1edfdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092611226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.1092611226
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1046260707
Short name T330
Test name
Test status
Simulation time 31924708 ps
CPU time 0.96 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 200968 kb
Host smart-41232dd4-22d4-4459-9c9f-479e2b2a048c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046260707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1046260707
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.1507671165
Short name T205
Test name
Test status
Simulation time 62577717 ps
CPU time 0.93 seconds
Started Aug 03 05:08:40 PM PDT 24
Finished Aug 03 05:08:41 PM PDT 24
Peak memory 201052 kb
Host smart-f901ba2a-3959-4f6a-8f6c-e84caf28918c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507671165 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.1507671165
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.1618546125
Short name T421
Test name
Test status
Simulation time 130471991 ps
CPU time 1.06 seconds
Started Aug 03 05:08:38 PM PDT 24
Finished Aug 03 05:08:39 PM PDT 24
Peak memory 201008 kb
Host smart-ceb4eb1d-e554-4a3a-b63b-c2cee7eea621
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618546125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.1618546125
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.2573489980
Short name T381
Test name
Test status
Simulation time 21382223 ps
CPU time 0.79 seconds
Started Aug 03 05:08:35 PM PDT 24
Finished Aug 03 05:08:36 PM PDT 24
Peak memory 200992 kb
Host smart-2154e204-c8cf-4780-9dec-76a078a90ca2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573489980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.2573489980
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3510389599
Short name T146
Test name
Test status
Simulation time 859480879 ps
CPU time 4.97 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:49 PM PDT 24
Peak memory 201260 kb
Host smart-a81013b7-e11e-4f3d-8341-03259502f8cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510389599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3510389599
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.1867754599
Short name T494
Test name
Test status
Simulation time 46412475 ps
CPU time 0.89 seconds
Started Aug 03 05:08:36 PM PDT 24
Finished Aug 03 05:08:37 PM PDT 24
Peak memory 201056 kb
Host smart-71e09e1f-4766-47ca-b511-3a66ec895a18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867754599 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.1867754599
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.715483950
Short name T810
Test name
Test status
Simulation time 13001524356 ps
CPU time 96.98 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:10:20 PM PDT 24
Peak memory 201380 kb
Host smart-540e9010-da9b-479d-a3b3-d15f94ad79ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715483950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.715483950
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.3481381916
Short name T157
Test name
Test status
Simulation time 60326365438 ps
CPU time 557.28 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:18:01 PM PDT 24
Peak memory 217952 kb
Host smart-0a33b3c4-267f-458e-9d6a-e3c4fc3cea7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3481381916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.3481381916
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3376409809
Short name T172
Test name
Test status
Simulation time 217559404 ps
CPU time 1.43 seconds
Started Aug 03 05:08:39 PM PDT 24
Finished Aug 03 05:08:40 PM PDT 24
Peak memory 201240 kb
Host smart-f808ca37-55dc-4666-b5c5-49cf37accc25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376409809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3376409809
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.2429290893
Short name T689
Test name
Test status
Simulation time 27476518 ps
CPU time 0.79 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 200940 kb
Host smart-a5ce4492-41fe-4596-b655-ee36dd585f9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429290893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.2429290893
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3413821893
Short name T765
Test name
Test status
Simulation time 74470391 ps
CPU time 1 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201236 kb
Host smart-0eb53547-7496-44d1-9f74-6fbb7ebd38d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413821893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3413821893
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.2617114600
Short name T361
Test name
Test status
Simulation time 15198483 ps
CPU time 0.75 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 200248 kb
Host smart-f192dd8a-7fcf-4e3a-a22d-0b544cd7e5e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617114600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.2617114600
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.2457243846
Short name T339
Test name
Test status
Simulation time 110660193 ps
CPU time 1.1 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201040 kb
Host smart-7dda5b5c-5c65-419b-a89c-4364aa5c9d2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457243846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.2457243846
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.1768691239
Short name T721
Test name
Test status
Simulation time 22387693 ps
CPU time 0.85 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201056 kb
Host smart-8eb051fd-54ec-40d7-8577-8698ee4cdf92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768691239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1768691239
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.1916031634
Short name T539
Test name
Test status
Simulation time 2230179793 ps
CPU time 10.06 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201328 kb
Host smart-9aaf26f0-193d-4489-9bf0-672b74a5f16f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916031634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1916031634
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.1320369646
Short name T805
Test name
Test status
Simulation time 1342869944 ps
CPU time 10.07 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:54 PM PDT 24
Peak memory 201172 kb
Host smart-de507107-e53a-4c44-b9e3-76382de0b504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320369646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.1320369646
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.1651567864
Short name T470
Test name
Test status
Simulation time 44721732 ps
CPU time 0.83 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201068 kb
Host smart-37ed9f3f-ca8c-4b57-95be-757c45969af6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651567864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.1651567864
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.3035650366
Short name T200
Test name
Test status
Simulation time 59305823 ps
CPU time 0.91 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201084 kb
Host smart-5b8c447c-caf2-41a5-9fc4-71b1e6118ab7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035650366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.3035650366
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2521598817
Short name T681
Test name
Test status
Simulation time 22914210 ps
CPU time 0.84 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201072 kb
Host smart-0751cb8d-0d82-4518-b13f-7266ec98fdae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521598817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.2521598817
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1451148166
Short name T428
Test name
Test status
Simulation time 53214567 ps
CPU time 0.86 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201000 kb
Host smart-67f3713f-832e-44ad-8321-57a65c92bb9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451148166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1451148166
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.3419902077
Short name T229
Test name
Test status
Simulation time 933038650 ps
CPU time 3.19 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201264 kb
Host smart-33284ff6-758f-444b-8ff4-43903319bb80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419902077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.3419902077
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.2538230085
Short name T441
Test name
Test status
Simulation time 27403485 ps
CPU time 0.84 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201068 kb
Host smart-f23c4330-d8a5-4d51-a955-956f9814cfc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538230085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.2538230085
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.4187155720
Short name T137
Test name
Test status
Simulation time 2784475720 ps
CPU time 13.68 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:56 PM PDT 24
Peak memory 201508 kb
Host smart-ba727e4c-033f-4489-aebf-3f1b604d58dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187155720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.4187155720
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.2297887185
Short name T73
Test name
Test status
Simulation time 15771903 ps
CPU time 0.73 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201060 kb
Host smart-f0bf6002-80b1-4d80-a81c-ffbd6aae46a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297887185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.2297887185
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.225659512
Short name T509
Test name
Test status
Simulation time 11310115 ps
CPU time 0.7 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201052 kb
Host smart-29c8cff5-7b33-480c-ac4b-62a7ebec1d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225659512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_alert_test.225659512
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.3467533214
Short name T813
Test name
Test status
Simulation time 19371379 ps
CPU time 0.82 seconds
Started Aug 03 05:07:52 PM PDT 24
Finished Aug 03 05:07:53 PM PDT 24
Peak memory 201048 kb
Host smart-130c828a-4ac0-4243-8797-fbbbc84c6cc7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467533214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.3467533214
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1163932831
Short name T659
Test name
Test status
Simulation time 22167595 ps
CPU time 0.77 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 200256 kb
Host smart-328070a4-efe4-4f1b-9317-3be90c49fd54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163932831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1163932831
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2181547194
Short name T396
Test name
Test status
Simulation time 34256555 ps
CPU time 0.85 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201044 kb
Host smart-99a54667-caa3-49a3-b862-41f2026fb703
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181547194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2181547194
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.2889199772
Short name T507
Test name
Test status
Simulation time 22745358 ps
CPU time 0.83 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201016 kb
Host smart-87e1b1bb-6dd5-4ce2-b2db-cbb0883d4489
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889199772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.2889199772
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.2447788963
Short name T566
Test name
Test status
Simulation time 2356251888 ps
CPU time 19 seconds
Started Aug 03 05:07:58 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201356 kb
Host smart-181dc176-3b88-491d-8bec-6be7ce4cc8d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447788963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.2447788963
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.3358734910
Short name T212
Test name
Test status
Simulation time 1473547152 ps
CPU time 6.88 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 201072 kb
Host smart-39ec27c2-35f6-48dd-af5b-dc35a056bbd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358734910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.3358734910
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.3470528000
Short name T48
Test name
Test status
Simulation time 25760203 ps
CPU time 0.83 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201088 kb
Host smart-3ee62086-f3f8-4cef-ba80-df6203c23f7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470528000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.3470528000
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2076138206
Short name T702
Test name
Test status
Simulation time 45270520 ps
CPU time 1.04 seconds
Started Aug 03 05:07:59 PM PDT 24
Finished Aug 03 05:08:01 PM PDT 24
Peak memory 201028 kb
Host smart-94defc6a-7af4-4d7e-b9ab-d188405ab7c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076138206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2076138206
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1558868180
Short name T665
Test name
Test status
Simulation time 23335258 ps
CPU time 0.88 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201064 kb
Host smart-85c30e4a-afc2-442f-ab17-01c1e73f6119
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558868180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.1558868180
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.743377997
Short name T537
Test name
Test status
Simulation time 13840710 ps
CPU time 0.69 seconds
Started Aug 03 05:07:56 PM PDT 24
Finished Aug 03 05:07:57 PM PDT 24
Peak memory 201048 kb
Host smart-9e238e7f-9f5c-4f67-8ad9-8bf09dda7f6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743377997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.743377997
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.85289328
Short name T807
Test name
Test status
Simulation time 567544030 ps
CPU time 3.09 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 201276 kb
Host smart-763f7cc3-d0d2-411a-afd6-2237a0cc352d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85289328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.85289328
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.4038483833
Short name T45
Test name
Test status
Simulation time 303389953 ps
CPU time 3.25 seconds
Started Aug 03 05:07:55 PM PDT 24
Finished Aug 03 05:07:58 PM PDT 24
Peak memory 218144 kb
Host smart-9b601928-bc1c-4931-a6c4-beedc7c54edf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038483833 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.4038483833
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.721272348
Short name T573
Test name
Test status
Simulation time 69945585 ps
CPU time 1.03 seconds
Started Aug 03 05:07:57 PM PDT 24
Finished Aug 03 05:07:58 PM PDT 24
Peak memory 201016 kb
Host smart-b61624d4-e588-40c8-b8fd-c8274696f469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721272348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.721272348
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2095648755
Short name T140
Test name
Test status
Simulation time 189956745 ps
CPU time 1.63 seconds
Started Aug 03 05:07:55 PM PDT 24
Finished Aug 03 05:07:57 PM PDT 24
Peak memory 201096 kb
Host smart-6120e011-3c2b-4cb4-b154-1d5542c1456c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095648755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2095648755
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.2876336047
Short name T489
Test name
Test status
Simulation time 34000750 ps
CPU time 1.03 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:02 PM PDT 24
Peak memory 201052 kb
Host smart-d1279e05-896d-400a-9a16-6fe131979315
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876336047 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.2876336047
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.2257371163
Short name T155
Test name
Test status
Simulation time 44623072 ps
CPU time 0.84 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201068 kb
Host smart-4fa75242-7e51-491b-a583-9cc03cec39b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257371163 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.2257371163
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.898854710
Short name T105
Test name
Test status
Simulation time 18826506 ps
CPU time 0.84 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 201096 kb
Host smart-bfbf1e01-cf6d-49f1-a88b-732fbe3e5368
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898854710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.898854710
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.735315717
Short name T775
Test name
Test status
Simulation time 39383841 ps
CPU time 0.75 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 200248 kb
Host smart-cb001fdb-0b19-4cc0-b32f-78cec87c1234
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735315717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.735315717
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.2668340652
Short name T778
Test name
Test status
Simulation time 32213171 ps
CPU time 0.85 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201096 kb
Host smart-f981baa2-9727-4110-a320-d3cc99301c4b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668340652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.2668340652
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3837085418
Short name T194
Test name
Test status
Simulation time 40286413 ps
CPU time 0.84 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201068 kb
Host smart-b70e2080-54cf-44bb-9c8d-64679a266e74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837085418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3837085418
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.3134041308
Short name T271
Test name
Test status
Simulation time 1882567516 ps
CPU time 14.8 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:57 PM PDT 24
Peak memory 201280 kb
Host smart-c1ac7f92-3632-4772-b687-222158f0ea9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134041308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.3134041308
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.1348659441
Short name T310
Test name
Test status
Simulation time 1231186402 ps
CPU time 5.65 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:49 PM PDT 24
Peak memory 201124 kb
Host smart-6c1c29eb-1ddb-4fed-bf71-982a6f3d7a4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348659441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.1348659441
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.2082125275
Short name T301
Test name
Test status
Simulation time 39256380 ps
CPU time 1.04 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201080 kb
Host smart-e4e8b1f2-304b-455b-bede-43b6d98d9da2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082125275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.2082125275
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.223313259
Short name T642
Test name
Test status
Simulation time 143464171 ps
CPU time 1.18 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 200980 kb
Host smart-098875d7-7abb-4ae9-a226-ce2e207218d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223313259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_clk_byp_req_intersig_mubi.223313259
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.4001247831
Short name T763
Test name
Test status
Simulation time 21117270 ps
CPU time 0.79 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201080 kb
Host smart-2da9123b-1d76-42ea-9301-196fd5d766c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001247831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.4001247831
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.1709224587
Short name T213
Test name
Test status
Simulation time 35866748 ps
CPU time 0.79 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 200204 kb
Host smart-3be6f1ea-d4c2-4af6-8bc6-e11197f135f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709224587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.1709224587
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.2471527067
Short name T115
Test name
Test status
Simulation time 786634372 ps
CPU time 3.66 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201272 kb
Host smart-6cb34e6c-1595-4b7d-9151-b57119c2e59d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471527067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.2471527067
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.664191901
Short name T383
Test name
Test status
Simulation time 37819145 ps
CPU time 0.89 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201024 kb
Host smart-2f58938d-0ef8-4917-8db0-73798fb85407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664191901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.664191901
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.1658000448
Short name T594
Test name
Test status
Simulation time 766200762 ps
CPU time 4 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201176 kb
Host smart-63b5d778-14f6-4794-8ab1-b1822d3adca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658000448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.1658000448
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.2856202676
Short name T26
Test name
Test status
Simulation time 224860391640 ps
CPU time 978.79 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:25:04 PM PDT 24
Peak memory 209616 kb
Host smart-b06d71a8-f165-4dd0-8ecb-85e8f7ccdec0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2856202676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.2856202676
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2030655497
Short name T668
Test name
Test status
Simulation time 45340902 ps
CPU time 0.93 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201072 kb
Host smart-08f0e8ce-d281-4925-9cfd-e0defa0b3c0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030655497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2030655497
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.411414147
Short name T532
Test name
Test status
Simulation time 77603304 ps
CPU time 0.92 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 200728 kb
Host smart-78e6d3f0-eee7-4008-a5cf-513434157326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411414147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.411414147
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2381060785
Short name T98
Test name
Test status
Simulation time 44336209 ps
CPU time 0.98 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201080 kb
Host smart-4f5d35d2-2d3e-49d8-a1b6-5c4d974cfe18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381060785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.2381060785
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.17606265
Short name T646
Test name
Test status
Simulation time 25413930 ps
CPU time 0.72 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 200936 kb
Host smart-31502046-4df6-465a-97ef-8150da012eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.17606265
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.3351561959
Short name T377
Test name
Test status
Simulation time 41784760 ps
CPU time 0.81 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201052 kb
Host smart-e503148e-23b2-49d9-8430-7c1f56dc1169
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351561959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.3351561959
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.1547822742
Short name T542
Test name
Test status
Simulation time 30487631 ps
CPU time 0.81 seconds
Started Aug 03 05:08:42 PM PDT 24
Finished Aug 03 05:08:43 PM PDT 24
Peak memory 201068 kb
Host smart-a5012ff3-7fd5-4def-b3e9-65bd64eae2c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547822742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1547822742
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.744025629
Short name T371
Test name
Test status
Simulation time 436765559 ps
CPU time 3.83 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 201128 kb
Host smart-b0212c93-4851-4e67-ac97-28707051611f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744025629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.744025629
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.2283469346
Short name T152
Test name
Test status
Simulation time 1818802668 ps
CPU time 9.66 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201132 kb
Host smart-80a18281-2473-4ce3-84f4-d28af7518c85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283469346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.2283469346
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.2256887037
Short name T823
Test name
Test status
Simulation time 36165524 ps
CPU time 0.75 seconds
Started Aug 03 05:08:43 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201088 kb
Host smart-b509c9d4-bb55-4791-a210-0542a855bd8a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256887037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.2256887037
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1023407415
Short name T353
Test name
Test status
Simulation time 37829013 ps
CPU time 0.88 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 200024 kb
Host smart-fa0bd1ba-b08d-4f92-97f1-669f3b472186
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023407415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.1023407415
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3874468564
Short name T643
Test name
Test status
Simulation time 69376268 ps
CPU time 0.99 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:45 PM PDT 24
Peak memory 201012 kb
Host smart-01b23508-3c32-47fa-a4b1-7cd37818ed5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874468564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3874468564
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.530583951
Short name T216
Test name
Test status
Simulation time 39355069 ps
CPU time 0.82 seconds
Started Aug 03 05:08:49 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201040 kb
Host smart-2c0739d2-94e0-4e56-8b89-e58e13bff7e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530583951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.530583951
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.1685661454
Short name T621
Test name
Test status
Simulation time 451528491 ps
CPU time 2.99 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201220 kb
Host smart-bd0a9696-013d-4d78-8571-9873497b580f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685661454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.1685661454
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.1825615202
Short name T370
Test name
Test status
Simulation time 44855550 ps
CPU time 0.94 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:49 PM PDT 24
Peak memory 201052 kb
Host smart-432333c1-9c5f-4784-9789-89f67d93df7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825615202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.1825615202
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1999722974
Short name T276
Test name
Test status
Simulation time 6467960054 ps
CPU time 24.39 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 201460 kb
Host smart-87aa519d-5f1a-484f-acb1-da9423479126
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999722974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1999722974
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.421793718
Short name T578
Test name
Test status
Simulation time 13916981 ps
CPU time 0.77 seconds
Started Aug 03 05:08:44 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201020 kb
Host smart-013fafbd-1a97-4149-990c-d282214a4cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421793718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.421793718
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.3843587351
Short name T495
Test name
Test status
Simulation time 21467098 ps
CPU time 0.77 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201060 kb
Host smart-35e01ead-3607-46f0-8d61-4a67c49b95ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843587351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.3843587351
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1162768061
Short name T488
Test name
Test status
Simulation time 33980980 ps
CPU time 0.79 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201064 kb
Host smart-b3869d7f-8caf-4212-9201-f3e1c3be52a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162768061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1162768061
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.2621362996
Short name T695
Test name
Test status
Simulation time 37229746 ps
CPU time 0.78 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 200288 kb
Host smart-7fe6d018-2e72-4729-92d2-c38367c6da52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621362996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2621362996
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.1715898258
Short name T151
Test name
Test status
Simulation time 36421916 ps
CPU time 0.77 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201064 kb
Host smart-9b9ccd8a-d231-4c95-aa11-be624434238c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715898258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_div_intersig_mubi.1715898258
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1130351537
Short name T742
Test name
Test status
Simulation time 93983241 ps
CPU time 1.04 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:49 PM PDT 24
Peak memory 201064 kb
Host smart-23447465-c6dd-414e-9bdd-10e9fbfd4216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130351537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1130351537
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.1924015379
Short name T543
Test name
Test status
Simulation time 489708955 ps
CPU time 2.66 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201148 kb
Host smart-58efc5da-2c95-488e-8c79-fe26d6d53388
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924015379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.1924015379
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.96528187
Short name T630
Test name
Test status
Simulation time 1215414820 ps
CPU time 8.5 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201124 kb
Host smart-afbaa3a4-e48c-406c-a8ea-acb10e934a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96528187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_tim
eout.96528187
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.3028755724
Short name T92
Test name
Test status
Simulation time 101810954 ps
CPU time 1.3 seconds
Started Aug 03 05:08:49 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201032 kb
Host smart-33d6bd03-cfbe-41ea-b1fa-7c4a438a5242
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028755724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.3028755724
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2488006868
Short name T464
Test name
Test status
Simulation time 62040604 ps
CPU time 0.85 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201068 kb
Host smart-20fb7075-07da-4fa1-b691-a981acac2232
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488006868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2488006868
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1600878078
Short name T663
Test name
Test status
Simulation time 43671647 ps
CPU time 0.95 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201080 kb
Host smart-8300942d-3235-4698-a3b1-a4a41f93b8af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600878078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.1600878078
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.517785020
Short name T811
Test name
Test status
Simulation time 46477646 ps
CPU time 0.92 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 200988 kb
Host smart-18d9ccee-0bd0-4ee1-8969-8d6b564a2b99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517785020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.517785020
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2645024155
Short name T490
Test name
Test status
Simulation time 1535928784 ps
CPU time 4.99 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201260 kb
Host smart-1e0aa710-c949-4ce0-b0b8-fd24e14751d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645024155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2645024155
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.1321257421
Short name T556
Test name
Test status
Simulation time 23906145 ps
CPU time 0.89 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201012 kb
Host smart-90af4327-63e6-4a1b-989c-b3e3bb837326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321257421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1321257421
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3409844303
Short name T387
Test name
Test status
Simulation time 9164210819 ps
CPU time 66.12 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201440 kb
Host smart-1030b595-f413-4cb6-9581-d3dcccf12813
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409844303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3409844303
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.762760473
Short name T185
Test name
Test status
Simulation time 24142219 ps
CPU time 0.87 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201076 kb
Host smart-24b1e5b4-62f3-48ed-a926-7f3aa662bdfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762760473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.762760473
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.7951980
Short name T474
Test name
Test status
Simulation time 16396989 ps
CPU time 0.77 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201040 kb
Host smart-7e961f3a-0420-4711-a90c-7610928f9ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7951980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr
_alert_test.7951980
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3518193356
Short name T720
Test name
Test status
Simulation time 26924091 ps
CPU time 0.95 seconds
Started Aug 03 05:09:00 PM PDT 24
Finished Aug 03 05:09:01 PM PDT 24
Peak memory 201036 kb
Host smart-87bbe8ce-7ec9-4d50-949c-12e548e5aaef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518193356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.3518193356
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3925345286
Short name T181
Test name
Test status
Simulation time 33525232 ps
CPU time 0.73 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201008 kb
Host smart-7a374cc7-3cab-4c59-a7d9-22c935e62f24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925345286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3925345286
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.3113083964
Short name T319
Test name
Test status
Simulation time 17545698 ps
CPU time 0.78 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201088 kb
Host smart-60bf8b4d-a273-4fa7-b99f-d1a57af67857
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113083964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.3113083964
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.2288458017
Short name T359
Test name
Test status
Simulation time 29264358 ps
CPU time 0.82 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 200968 kb
Host smart-dba14c42-60a3-4054-b3a2-7117b33689ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288458017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2288458017
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.849436964
Short name T119
Test name
Test status
Simulation time 1738108528 ps
CPU time 7.83 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:53 PM PDT 24
Peak memory 201100 kb
Host smart-64d336fe-1b75-4434-a0b9-653e0919436d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849436964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.849436964
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.3974189528
Short name T53
Test name
Test status
Simulation time 503884789 ps
CPU time 2.95 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201116 kb
Host smart-cae04225-0c45-4c51-940c-a36dffe1ca76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974189528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.3974189528
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1751821824
Short name T608
Test name
Test status
Simulation time 106952518 ps
CPU time 1.13 seconds
Started Aug 03 05:08:47 PM PDT 24
Finished Aug 03 05:08:48 PM PDT 24
Peak memory 201240 kb
Host smart-9041e019-e791-498f-a4d7-a0f735ffd58f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751821824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.1751821824
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.3242072123
Short name T240
Test name
Test status
Simulation time 136799140 ps
CPU time 1.16 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201080 kb
Host smart-deca6e5e-99e4-4362-a9d7-77d947fb43a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242072123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.3242072123
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.3100389583
Short name T417
Test name
Test status
Simulation time 56653625 ps
CPU time 0.95 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201088 kb
Host smart-eda02f22-551c-48aa-b1dc-6dbddf51bb50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100389583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.3100389583
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.2777556147
Short name T406
Test name
Test status
Simulation time 20135065 ps
CPU time 0.75 seconds
Started Aug 03 05:08:46 PM PDT 24
Finished Aug 03 05:08:47 PM PDT 24
Peak memory 201064 kb
Host smart-5e1e7b95-7e1d-429d-9c45-5c4f08c90619
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777556147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2777556147
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.3860398795
Short name T148
Test name
Test status
Simulation time 2421331787 ps
CPU time 8.08 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 201340 kb
Host smart-f252f496-5e08-48f4-80c6-4aab978e692d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860398795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.3860398795
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2473723087
Short name T769
Test name
Test status
Simulation time 47837947 ps
CPU time 0.9 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201008 kb
Host smart-4639a022-a3b4-4155-a463-e4ae42ce49e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473723087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2473723087
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.1788122073
Short name T800
Test name
Test status
Simulation time 6718615619 ps
CPU time 47.36 seconds
Started Aug 03 05:08:55 PM PDT 24
Finished Aug 03 05:09:42 PM PDT 24
Peak memory 201376 kb
Host smart-13259bd9-7e86-4539-a6bf-286b6f4746c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788122073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.1788122073
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2488535106
Short name T485
Test name
Test status
Simulation time 50816303 ps
CPU time 1 seconds
Started Aug 03 05:08:45 PM PDT 24
Finished Aug 03 05:08:46 PM PDT 24
Peak memory 201068 kb
Host smart-addcc90e-2615-4e3d-84e6-d982fdaa5023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488535106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2488535106
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.986867310
Short name T677
Test name
Test status
Simulation time 47350516 ps
CPU time 0.89 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201052 kb
Host smart-0f04221e-b028-4ad1-a56c-1e55af21cb5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986867310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkm
gr_alert_test.986867310
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3650596198
Short name T244
Test name
Test status
Simulation time 84621961 ps
CPU time 1.01 seconds
Started Aug 03 05:08:56 PM PDT 24
Finished Aug 03 05:08:57 PM PDT 24
Peak memory 201060 kb
Host smart-e9376983-69f4-4ab4-8daa-38b4ab3a21db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650596198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3650596198
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.3206654820
Short name T560
Test name
Test status
Simulation time 46761084 ps
CPU time 0.77 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 200252 kb
Host smart-7f06d2fa-24ca-4ed6-997a-ec0ca06c7ea6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206654820 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.3206654820
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3406158861
Short name T22
Test name
Test status
Simulation time 17087115 ps
CPU time 0.78 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201084 kb
Host smart-91e353ae-dcab-4714-ba27-12bfd7660753
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406158861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3406158861
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.279397971
Short name T487
Test name
Test status
Simulation time 60684726 ps
CPU time 1.05 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 200968 kb
Host smart-4eb33aa5-91d9-41d9-b6f7-a3cd4dbf2c97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279397971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.279397971
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.2037138588
Short name T707
Test name
Test status
Simulation time 2240248929 ps
CPU time 16.61 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 201368 kb
Host smart-5ab004c6-d564-44e7-a8a0-9352d543c247
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037138588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2037138588
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.1235470853
Short name T215
Test name
Test status
Simulation time 2080400637 ps
CPU time 9.14 seconds
Started Aug 03 05:08:59 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 201312 kb
Host smart-72811bcb-0174-487d-9d70-55eb2b4e3e35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235470853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.1235470853
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3316408846
Short name T72
Test name
Test status
Simulation time 104632851 ps
CPU time 1.21 seconds
Started Aug 03 05:09:05 PM PDT 24
Finished Aug 03 05:09:06 PM PDT 24
Peak memory 201024 kb
Host smart-c8b950c0-8121-4876-a76a-cc2e35323929
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316408846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3316408846
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2864113879
Short name T280
Test name
Test status
Simulation time 17564259 ps
CPU time 0.83 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201060 kb
Host smart-d9db6ed5-eadb-4ab9-9653-ca0a8de5e5ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864113879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2864113879
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.1399945018
Short name T357
Test name
Test status
Simulation time 87212438 ps
CPU time 1.09 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201032 kb
Host smart-1a77b7dc-4198-43a1-8c24-cdad656d51a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399945018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.1399945018
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.1973365542
Short name T167
Test name
Test status
Simulation time 43914430 ps
CPU time 0.84 seconds
Started Aug 03 05:09:14 PM PDT 24
Finished Aug 03 05:09:15 PM PDT 24
Peak memory 201024 kb
Host smart-4eb3b45e-1e1a-4c92-be27-4db1d8779407
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973365542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1973365542
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.2988083101
Short name T656
Test name
Test status
Simulation time 165693823 ps
CPU time 1.48 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201100 kb
Host smart-0df041f2-1cc2-4fa6-a273-df74ee782eba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988083101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.2988083101
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.1422672108
Short name T292
Test name
Test status
Simulation time 19524731 ps
CPU time 0.84 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201120 kb
Host smart-5aefdb01-8c05-4230-8066-c2ebf22348de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422672108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.1422672108
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.3226802409
Short name T423
Test name
Test status
Simulation time 8043361119 ps
CPU time 59.47 seconds
Started Aug 03 05:08:49 PM PDT 24
Finished Aug 03 05:09:49 PM PDT 24
Peak memory 201440 kb
Host smart-1e3f50f8-6640-410c-906a-c8b44ecf2484
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226802409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.3226802409
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all_with_rand_reset.767861861
Short name T409
Test name
Test status
Simulation time 17828849012 ps
CPU time 256.09 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:13:10 PM PDT 24
Peak memory 216560 kb
Host smart-526ca04a-3d6e-4b66-ad9d-7894da23c408
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=767861861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.767861861
Directory /workspace/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2272515735
Short name T631
Test name
Test status
Simulation time 39294785 ps
CPU time 1.04 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201004 kb
Host smart-81d9debd-af1d-441c-97f9-56e2e1e04280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272515735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2272515735
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3455402063
Short name T386
Test name
Test status
Simulation time 56020670 ps
CPU time 0.92 seconds
Started Aug 03 05:08:53 PM PDT 24
Finished Aug 03 05:08:54 PM PDT 24
Peak memory 201056 kb
Host smart-85a20c9a-e631-4412-96df-be7c784e9ee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455402063 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3455402063
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1006635069
Short name T103
Test name
Test status
Simulation time 42591792 ps
CPU time 0.96 seconds
Started Aug 03 05:09:14 PM PDT 24
Finished Aug 03 05:09:15 PM PDT 24
Peak memory 201088 kb
Host smart-2506dd25-255d-4b0d-aa8e-7a593eb0995d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006635069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1006635069
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.2155793008
Short name T680
Test name
Test status
Simulation time 40102669 ps
CPU time 0.79 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 200244 kb
Host smart-becd5833-77d3-4959-a555-44420e30cf06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155793008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.2155793008
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.994672867
Short name T569
Test name
Test status
Simulation time 19682178 ps
CPU time 0.78 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201044 kb
Host smart-cd65af7d-a89c-4b97-888d-d129a346792c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994672867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.994672867
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3991051439
Short name T189
Test name
Test status
Simulation time 13457079 ps
CPU time 0.75 seconds
Started Aug 03 05:08:55 PM PDT 24
Finished Aug 03 05:08:56 PM PDT 24
Peak memory 200996 kb
Host smart-b35d5afd-8dc3-47c7-91fc-00e1b55f3c7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991051439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3991051439
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.4129666620
Short name T601
Test name
Test status
Simulation time 803242853 ps
CPU time 4.67 seconds
Started Aug 03 05:09:04 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200984 kb
Host smart-5bbe7403-299f-4896-abce-2f28578c72f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129666620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.4129666620
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.4086037934
Short name T587
Test name
Test status
Simulation time 2055507530 ps
CPU time 14.36 seconds
Started Aug 03 05:08:59 PM PDT 24
Finished Aug 03 05:09:13 PM PDT 24
Peak memory 201368 kb
Host smart-e52e5e2f-a318-4e91-8722-996ecc98fe04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086037934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.4086037934
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.2082948310
Short name T432
Test name
Test status
Simulation time 21608617 ps
CPU time 0.82 seconds
Started Aug 03 05:08:49 PM PDT 24
Finished Aug 03 05:08:50 PM PDT 24
Peak memory 201036 kb
Host smart-00b8c997-a543-48ea-8f31-f306e5faa6d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082948310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.2082948310
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.313695876
Short name T572
Test name
Test status
Simulation time 39814346 ps
CPU time 0.81 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201048 kb
Host smart-86f33032-da6a-462e-b1c1-c8b2b0fd62c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313695876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_clk_byp_req_intersig_mubi.313695876
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2866225283
Short name T117
Test name
Test status
Simulation time 79821602 ps
CPU time 1.01 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201036 kb
Host smart-49d3e636-b8ed-4e9e-97c5-cb1c1d51702c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866225283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2866225283
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.1316402297
Short name T796
Test name
Test status
Simulation time 61216729 ps
CPU time 0.85 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201048 kb
Host smart-13767fb4-a806-4fc6-b8b6-5bdc35381c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316402297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1316402297
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.2252834536
Short name T245
Test name
Test status
Simulation time 1149861376 ps
CPU time 6.48 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:09:01 PM PDT 24
Peak memory 201268 kb
Host smart-6369233b-9659-44f6-ba4a-2053e4337006
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252834536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.2252834536
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2215933414
Short name T318
Test name
Test status
Simulation time 175565376 ps
CPU time 1.24 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:08:58 PM PDT 24
Peak memory 201060 kb
Host smart-356f2397-a07f-420e-a1c4-c5134ff0228c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215933414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2215933414
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.3612625598
Short name T232
Test name
Test status
Simulation time 2046832572 ps
CPU time 10.09 seconds
Started Aug 03 05:09:13 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201320 kb
Host smart-6a43091a-4b98-414e-979f-729b79e8fdfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612625598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.3612625598
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.1842472228
Short name T70
Test name
Test status
Simulation time 82450824328 ps
CPU time 476.46 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:16:47 PM PDT 24
Peak memory 209760 kb
Host smart-c64adf7d-68f0-4adc-b614-b60c83e8975d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1842472228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.1842472228
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.804740949
Short name T173
Test name
Test status
Simulation time 20207032 ps
CPU time 0.79 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:08:58 PM PDT 24
Peak memory 201000 kb
Host smart-a82609cd-2beb-4efc-a13c-b0234ee3996b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804740949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.804740949
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.654372383
Short name T32
Test name
Test status
Simulation time 19070997 ps
CPU time 0.78 seconds
Started Aug 03 05:08:59 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201036 kb
Host smart-6e46e38e-c128-4bed-bc65-99ebbbc28a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654372383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkm
gr_alert_test.654372383
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3959052784
Short name T401
Test name
Test status
Simulation time 15162693 ps
CPU time 0.76 seconds
Started Aug 03 05:08:59 PM PDT 24
Finished Aug 03 05:09:00 PM PDT 24
Peak memory 201096 kb
Host smart-d5fe5875-f20f-4699-8c9e-05b5ee37ed1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959052784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3959052784
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.3431010470
Short name T514
Test name
Test status
Simulation time 110999857 ps
CPU time 0.97 seconds
Started Aug 03 05:09:05 PM PDT 24
Finished Aug 03 05:09:06 PM PDT 24
Peak memory 200240 kb
Host smart-0061ad74-b90d-44a4-8455-60a6751ec637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431010470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.3431010470
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.4236583022
Short name T80
Test name
Test status
Simulation time 23757940 ps
CPU time 0.9 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201060 kb
Host smart-1c9b770b-05b0-41c2-959e-b49e3731ff50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236583022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.4236583022
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.196321381
Short name T191
Test name
Test status
Simulation time 85680983 ps
CPU time 1.06 seconds
Started Aug 03 05:08:59 PM PDT 24
Finished Aug 03 05:09:00 PM PDT 24
Peak memory 201024 kb
Host smart-a47b2999-28b2-4b05-8d26-8b63a840c0cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196321381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.196321381
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3473455911
Short name T260
Test name
Test status
Simulation time 607073498 ps
CPU time 3.49 seconds
Started Aug 03 05:09:09 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201148 kb
Host smart-097ff253-cb8e-4b9a-b8ac-3e760a990caf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473455911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3473455911
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.3931222488
Short name T246
Test name
Test status
Simulation time 161727876 ps
CPU time 1.35 seconds
Started Aug 03 05:09:04 PM PDT 24
Finished Aug 03 05:09:06 PM PDT 24
Peak memory 201192 kb
Host smart-1040fd1c-2356-47c0-9a71-e71f575c1544
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931222488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.3931222488
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.354103006
Short name T637
Test name
Test status
Simulation time 84815660 ps
CPU time 1.07 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201040 kb
Host smart-35a8539b-02fe-4a9e-9166-7448794f12bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354103006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.clkmgr_idle_intersig_mubi.354103006
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3285999362
Short name T741
Test name
Test status
Simulation time 43290252 ps
CPU time 0.83 seconds
Started Aug 03 05:08:53 PM PDT 24
Finished Aug 03 05:08:54 PM PDT 24
Peak memory 201036 kb
Host smart-8e92bf14-49bd-4a03-95ab-41ab823fb03e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3285999362 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3285999362
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.1220558597
Short name T818
Test name
Test status
Simulation time 168058020 ps
CPU time 1.36 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201040 kb
Host smart-dbbb40a0-b3b2-4994-a8de-decfe5a8d395
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220558597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.1220558597
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.68634872
Short name T496
Test name
Test status
Simulation time 41921910 ps
CPU time 0.81 seconds
Started Aug 03 05:08:53 PM PDT 24
Finished Aug 03 05:08:53 PM PDT 24
Peak memory 201016 kb
Host smart-dedc2038-d496-4bdd-aecb-5df094ceab27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68634872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.68634872
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.3485195262
Short name T208
Test name
Test status
Simulation time 1065805040 ps
CPU time 6.07 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:57 PM PDT 24
Peak memory 201228 kb
Host smart-6b375c13-512b-473e-88ce-ec2ae175da21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485195262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.3485195262
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.2019090674
Short name T254
Test name
Test status
Simulation time 95717150 ps
CPU time 1.09 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 200936 kb
Host smart-dbe517ae-9f67-4f86-b49f-d118b96e5449
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019090674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2019090674
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.701929232
Short name T814
Test name
Test status
Simulation time 4160845053 ps
CPU time 31.64 seconds
Started Aug 03 05:08:53 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201364 kb
Host smart-0c998086-124b-440f-95ef-d31919f3efd4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701929232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.701929232
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all_with_rand_reset.3547186669
Short name T147
Test name
Test status
Simulation time 66741787725 ps
CPU time 609.61 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:19:18 PM PDT 24
Peak memory 211700 kb
Host smart-428fa346-830f-4ee6-8816-965e95a8c5e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3547186669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.3547186669
Directory /workspace/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1608515889
Short name T207
Test name
Test status
Simulation time 110409419 ps
CPU time 1.18 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201000 kb
Host smart-a5374208-eb62-470f-a15e-2b0871d801cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608515889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1608515889
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.458004772
Short name T669
Test name
Test status
Simulation time 56339701 ps
CPU time 0.85 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201076 kb
Host smart-3eb86882-132d-4574-9ed6-776964f7f2a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458004772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkm
gr_alert_test.458004772
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3660090783
Short name T781
Test name
Test status
Simulation time 14360059 ps
CPU time 0.73 seconds
Started Aug 03 05:09:09 PM PDT 24
Finished Aug 03 05:09:10 PM PDT 24
Peak memory 201084 kb
Host smart-cf60b3c1-48cb-411f-923d-31be3e85f4be
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660090783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.3660090783
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.640069610
Short name T164
Test name
Test status
Simulation time 14719671 ps
CPU time 0.73 seconds
Started Aug 03 05:08:52 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 200240 kb
Host smart-b7ab98e5-32ad-4c21-a6da-b1e5549ebcc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640069610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.640069610
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3231319260
Short name T554
Test name
Test status
Simulation time 81431517 ps
CPU time 0.93 seconds
Started Aug 03 05:08:52 PM PDT 24
Finished Aug 03 05:08:53 PM PDT 24
Peak memory 201040 kb
Host smart-572c7db4-36f9-49b9-b5ef-64f7bc246e6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231319260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3231319260
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.394066832
Short name T221
Test name
Test status
Simulation time 23018514 ps
CPU time 0.84 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201012 kb
Host smart-4a8a6dcc-2c2e-4e6a-8e5f-6a3c4089ba4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394066832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.394066832
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.4105766653
Short name T250
Test name
Test status
Simulation time 1162958054 ps
CPU time 9.62 seconds
Started Aug 03 05:08:57 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 201080 kb
Host smart-b3b1cea6-24a6-4889-a09d-48a77e9acf81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105766653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.4105766653
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3839945142
Short name T438
Test name
Test status
Simulation time 1631095780 ps
CPU time 5.86 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201196 kb
Host smart-d4195bdd-bbc1-4c22-8b1d-879d82b07410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839945142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3839945142
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.3973219454
Short name T795
Test name
Test status
Simulation time 59473116 ps
CPU time 0.83 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 200900 kb
Host smart-04901bed-3f26-45aa-976b-d8a697ca7b9c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973219454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_idle_intersig_mubi.3973219454
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.3777131605
Short name T219
Test name
Test status
Simulation time 23418554 ps
CPU time 0.89 seconds
Started Aug 03 05:08:50 PM PDT 24
Finished Aug 03 05:08:51 PM PDT 24
Peak memory 201072 kb
Host smart-47cfeb10-0d42-43d2-a94d-799319f677a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777131605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.3777131605
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.3936926126
Short name T562
Test name
Test status
Simulation time 29930068 ps
CPU time 0.93 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201044 kb
Host smart-4e487d10-ee35-4a85-885c-cd661bcc8a70
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936926126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.3936926126
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.549022524
Short name T293
Test name
Test status
Simulation time 45176282 ps
CPU time 0.82 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 200988 kb
Host smart-4f5f6e89-2264-4478-9384-64423554a485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549022524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.549022524
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.288967967
Short name T316
Test name
Test status
Simulation time 304939384 ps
CPU time 2.32 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:03 PM PDT 24
Peak memory 201052 kb
Host smart-9024bc54-8944-4feb-aac5-5289541cf90e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288967967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.288967967
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1258138664
Short name T392
Test name
Test status
Simulation time 20175659 ps
CPU time 0.83 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 201032 kb
Host smart-3bf4f7eb-5d9e-4d35-b317-e55fdc5ecb02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258138664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1258138664
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.1882334841
Short name T10
Test name
Test status
Simulation time 18509406869 ps
CPU time 92.66 seconds
Started Aug 03 05:08:48 PM PDT 24
Finished Aug 03 05:10:21 PM PDT 24
Peak memory 200784 kb
Host smart-98c33233-9d94-4f18-9434-c66d4ee73f09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882334841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.1882334841
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.664480792
Short name T69
Test name
Test status
Simulation time 14649860046 ps
CPU time 231.47 seconds
Started Aug 03 05:09:09 PM PDT 24
Finished Aug 03 05:13:00 PM PDT 24
Peak memory 217916 kb
Host smart-4647d02c-f8a5-4768-b9c6-c37323979ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=664480792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.664480792
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.1087176012
Short name T709
Test name
Test status
Simulation time 55392069 ps
CPU time 0.94 seconds
Started Aug 03 05:08:51 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 200972 kb
Host smart-b266feb4-da8d-43bd-962d-658a20dfa848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087176012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.1087176012
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.313764975
Short name T281
Test name
Test status
Simulation time 12856667 ps
CPU time 0.76 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 201024 kb
Host smart-5b4df564-0c88-49c9-b4ef-8d3a21c19558
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313764975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkm
gr_alert_test.313764975
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.2875270848
Short name T99
Test name
Test status
Simulation time 89513337 ps
CPU time 1.12 seconds
Started Aug 03 05:09:05 PM PDT 24
Finished Aug 03 05:09:06 PM PDT 24
Peak memory 201096 kb
Host smart-1eb3e0fc-e124-4d46-bf5d-74c32bf7387d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875270848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.2875270848
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.1191399284
Short name T512
Test name
Test status
Simulation time 17066113 ps
CPU time 0.75 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 200268 kb
Host smart-86815784-46dc-4b28-8393-e459052871dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191399284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1191399284
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.3330734054
Short name T624
Test name
Test status
Simulation time 15540511 ps
CPU time 0.78 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201056 kb
Host smart-22a85d95-dcff-4f76-8c78-9434260efdcb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330734054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.3330734054
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.2185240763
Short name T550
Test name
Test status
Simulation time 203988414 ps
CPU time 1.34 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 200880 kb
Host smart-a3bd4db1-ff08-485a-aea7-cb16352b1608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185240763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2185240763
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.1500200275
Short name T326
Test name
Test status
Simulation time 1279253806 ps
CPU time 9.34 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:32 PM PDT 24
Peak memory 200984 kb
Host smart-50a2b938-9a99-4db5-862a-2027be03e497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500200275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1500200275
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.4292833844
Short name T683
Test name
Test status
Simulation time 384893200 ps
CPU time 2.69 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201128 kb
Host smart-a9a15794-6304-434b-af99-ca7fae49ee7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292833844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.4292833844
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.2463635502
Short name T461
Test name
Test status
Simulation time 43004469 ps
CPU time 0.85 seconds
Started Aug 03 05:09:04 PM PDT 24
Finished Aug 03 05:09:05 PM PDT 24
Peak memory 201040 kb
Host smart-0172b0df-9ec4-4c5a-a0c0-b5a08f498606
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463635502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.2463635502
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1602634672
Short name T203
Test name
Test status
Simulation time 100625020 ps
CPU time 1.13 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201040 kb
Host smart-6cb79640-ac18-4a26-9f07-e754ed5637d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602634672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1602634672
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.2738347648
Short name T821
Test name
Test status
Simulation time 20777751 ps
CPU time 0.79 seconds
Started Aug 03 05:09:11 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201036 kb
Host smart-055b686f-deb4-44e7-a937-91f573194d45
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738347648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.2738347648
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.974703575
Short name T591
Test name
Test status
Simulation time 20889027 ps
CPU time 0.78 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 201044 kb
Host smart-97f564be-6409-40dc-ab98-99f6b44b88e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974703575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.974703575
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2126441189
Short name T448
Test name
Test status
Simulation time 569765276 ps
CPU time 2.6 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201176 kb
Host smart-134710e2-da6b-4674-9655-28eaea821690
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126441189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2126441189
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.897880476
Short name T607
Test name
Test status
Simulation time 27493226 ps
CPU time 0.83 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 200052 kb
Host smart-f9625989-4bd8-4c3e-90b9-c2ab88c4b952
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897880476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.897880476
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2741732581
Short name T687
Test name
Test status
Simulation time 8636208577 ps
CPU time 34.47 seconds
Started Aug 03 05:08:55 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201452 kb
Host smart-0de1c77d-9079-4a77-a5b4-7460b2288128
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741732581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2741732581
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.101994798
Short name T97
Test name
Test status
Simulation time 79241074 ps
CPU time 1.04 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201184 kb
Host smart-dcd14b2a-ac18-4be6-9ce4-23fe66386c06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101994798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.101994798
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.1659525087
Short name T186
Test name
Test status
Simulation time 15074567 ps
CPU time 0.73 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201016 kb
Host smart-6a8cc95d-8054-43a2-8181-0f65d8ce541a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659525087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.1659525087
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.921191200
Short name T446
Test name
Test status
Simulation time 32424622 ps
CPU time 0.78 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 201008 kb
Host smart-29ce1701-afbe-4957-a2be-5e365e89f05d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921191200 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.921191200
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2820593671
Short name T384
Test name
Test status
Simulation time 26593459 ps
CPU time 0.82 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200972 kb
Host smart-d9268c1e-af69-41d9-a285-acc364bd4a14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820593671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2820593671
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.2043259001
Short name T816
Test name
Test status
Simulation time 53256218 ps
CPU time 0.9 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:03 PM PDT 24
Peak memory 201068 kb
Host smart-ff7cc98c-d329-4ebe-b2de-3a6f6f2cb3f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043259001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.2043259001
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.1520263438
Short name T302
Test name
Test status
Simulation time 38199315 ps
CPU time 0.93 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 201028 kb
Host smart-4982758a-3d28-4392-a4ac-8dbd66b6801f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520263438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1520263438
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.3138212330
Short name T653
Test name
Test status
Simulation time 1770909440 ps
CPU time 9.92 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201288 kb
Host smart-ccc7b330-9ee9-42cb-bd76-8948d37b0219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138212330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3138212330
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.1916667332
Short name T654
Test name
Test status
Simulation time 2058287809 ps
CPU time 15.2 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201296 kb
Host smart-7caff7fc-3ced-4011-a76a-3d7c1e84958a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916667332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.1916667332
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3003912367
Short name T291
Test name
Test status
Simulation time 36162452 ps
CPU time 1.09 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 200984 kb
Host smart-a3c3573e-85bd-4555-92ac-34c47ae5e913
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003912367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.3003912367
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2653173112
Short name T231
Test name
Test status
Simulation time 99304816 ps
CPU time 1.09 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 201008 kb
Host smart-4199bd08-1c30-4ae1-9e85-cdbff03f5e8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653173112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2653173112
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.3587211870
Short name T690
Test name
Test status
Simulation time 87595668 ps
CPU time 1.13 seconds
Started Aug 03 05:09:14 PM PDT 24
Finished Aug 03 05:09:15 PM PDT 24
Peak memory 201068 kb
Host smart-ad183d5d-7641-41c6-9636-525b461cde55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587211870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.3587211870
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.39563128
Short name T50
Test name
Test status
Simulation time 62094497 ps
CPU time 0.88 seconds
Started Aug 03 05:09:04 PM PDT 24
Finished Aug 03 05:09:05 PM PDT 24
Peak memory 201052 kb
Host smart-058bde55-6aea-4f0c-8b7b-8fc78a1b46d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39563128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.39563128
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.1904647143
Short name T31
Test name
Test status
Simulation time 1872600445 ps
CPU time 6.08 seconds
Started Aug 03 05:09:05 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201220 kb
Host smart-a22ddcb1-0214-468c-a337-9e3156be5c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904647143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.1904647143
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.4142119856
Short name T713
Test name
Test status
Simulation time 19305578 ps
CPU time 0.85 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:03 PM PDT 24
Peak memory 201048 kb
Host smart-e4b26087-e0d5-4255-8136-aa88fa75208c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142119856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.4142119856
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.1564518906
Short name T356
Test name
Test status
Simulation time 7482483906 ps
CPU time 56.09 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:10:02 PM PDT 24
Peak memory 201376 kb
Host smart-25e3d2bf-0a8e-4d3a-837a-d2025c490df9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564518906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.1564518906
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.1204053267
Short name T454
Test name
Test status
Simulation time 35573952 ps
CPU time 0.9 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 200988 kb
Host smart-ef34f9f3-b6df-4093-b09e-1d0cdb9ddb84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204053267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1204053267
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.3444075308
Short name T786
Test name
Test status
Simulation time 22475315 ps
CPU time 0.82 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201060 kb
Host smart-3ce06192-ea0a-45a5-b9de-2b3515b863b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444075308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.3444075308
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3328995345
Short name T171
Test name
Test status
Simulation time 35994199 ps
CPU time 0.76 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201088 kb
Host smart-08b3df95-493d-4508-a744-4f8228af0517
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328995345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3328995345
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.3502547946
Short name T732
Test name
Test status
Simulation time 13456633 ps
CPU time 0.75 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 200992 kb
Host smart-82449484-6464-4e4f-9ed4-c157c8c97f67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502547946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3502547946
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.3164410195
Short name T393
Test name
Test status
Simulation time 35218141 ps
CPU time 0.88 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201088 kb
Host smart-fb5bf819-b212-42d3-bc04-4720f460feb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164410195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.3164410195
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.292833825
Short name T718
Test name
Test status
Simulation time 24617259 ps
CPU time 0.96 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201000 kb
Host smart-f658cb99-d614-45eb-9a3b-1370d046d652
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292833825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.292833825
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.578474144
Short name T799
Test name
Test status
Simulation time 1759556496 ps
CPU time 13.31 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201344 kb
Host smart-f293ef63-796b-456f-be1a-3c87848ed7d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578474144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.578474144
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.2638082875
Short name T27
Test name
Test status
Simulation time 1937102242 ps
CPU time 14.05 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201056 kb
Host smart-6941246b-5d53-495a-8e6d-ba4538c414dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638082875 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.2638082875
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3018600268
Short name T527
Test name
Test status
Simulation time 27048855 ps
CPU time 0.98 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201040 kb
Host smart-88f6d32e-3585-4dbd-bb0c-b85170c69206
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018600268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3018600268
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1701894746
Short name T93
Test name
Test status
Simulation time 29541586 ps
CPU time 0.77 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201080 kb
Host smart-ccf80be6-9282-4677-84b6-e61acd9f404d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701894746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1701894746
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.1707179075
Short name T328
Test name
Test status
Simulation time 47964884 ps
CPU time 0.79 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201080 kb
Host smart-28825854-e714-43ae-9945-48409ca8bd2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707179075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.1707179075
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.2049569171
Short name T620
Test name
Test status
Simulation time 19714517 ps
CPU time 0.72 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201068 kb
Host smart-4f8f6ab1-cd0d-4a7e-aa2a-2212018720e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049569171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2049569171
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.1733161542
Short name T144
Test name
Test status
Simulation time 1254291036 ps
CPU time 4.83 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 201200 kb
Host smart-442e42e6-c9d3-4be1-8b4e-6cfcce73dc06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733161542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1733161542
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3841721371
Short name T43
Test name
Test status
Simulation time 202058368 ps
CPU time 1.95 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 216424 kb
Host smart-0509f581-8049-4ce0-81d4-5555f50008d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841721371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3841721371
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2460785463
Short name T176
Test name
Test status
Simulation time 34527460 ps
CPU time 0.98 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201036 kb
Host smart-9745791f-17b0-4dc6-8a94-47889ca93536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460785463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2460785463
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3981805598
Short name T321
Test name
Test status
Simulation time 214111087 ps
CPU time 1.67 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 200976 kb
Host smart-c467e3d7-9cc5-46ee-86f1-9846ff3a330e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981805598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3981805598
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3511631279
Short name T635
Test name
Test status
Simulation time 102945562 ps
CPU time 1.19 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201088 kb
Host smart-b78d386e-ed78-4dfc-a887-61c5a7e3c4bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511631279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3511631279
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1523575564
Short name T33
Test name
Test status
Simulation time 122370579 ps
CPU time 1.1 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:04 PM PDT 24
Peak memory 201096 kb
Host smart-1c504aea-aa3a-4358-a74a-b12dfc2ed3ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523575564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1523575564
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.2152008459
Short name T391
Test name
Test status
Simulation time 18932878 ps
CPU time 0.85 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 201080 kb
Host smart-17da361e-9e25-4061-b3be-6f158d5ba8e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152008459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.2152008459
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.2920520450
Short name T332
Test name
Test status
Simulation time 24406662 ps
CPU time 0.74 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200236 kb
Host smart-52a040df-768b-47a7-986f-e193a2ce99de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920520450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.2920520450
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.793347154
Short name T256
Test name
Test status
Simulation time 59156255 ps
CPU time 0.84 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 201044 kb
Host smart-13b116f8-2168-4306-bea1-ec1a5688dbe2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793347154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_div_intersig_mubi.793347154
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.3664073993
Short name T201
Test name
Test status
Simulation time 17050814 ps
CPU time 0.79 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200964 kb
Host smart-542e7c50-902a-489d-ac11-f29df8234eef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664073993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.3664073993
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.10408310
Short name T529
Test name
Test status
Simulation time 2004115916 ps
CPU time 11.56 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201248 kb
Host smart-74cd575a-1877-485a-b349-d7c5e0d9372b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.10408310
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.1087191486
Short name T342
Test name
Test status
Simulation time 1221963703 ps
CPU time 9.64 seconds
Started Aug 03 05:09:03 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201340 kb
Host smart-4e0dc675-7516-48e0-8994-469d1b91b705
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087191486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.1087191486
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.2175000747
Short name T81
Test name
Test status
Simulation time 74669685 ps
CPU time 1.16 seconds
Started Aug 03 05:09:00 PM PDT 24
Finished Aug 03 05:09:01 PM PDT 24
Peak memory 200988 kb
Host smart-56326929-296b-4be3-91ee-5d97bd07fa2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175000747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.2175000747
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.2665247862
Short name T648
Test name
Test status
Simulation time 84003479 ps
CPU time 1.04 seconds
Started Aug 03 05:08:58 PM PDT 24
Finished Aug 03 05:08:59 PM PDT 24
Peak memory 201076 kb
Host smart-da575cf3-7139-4521-ad4c-b3a4dfa79980
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665247862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.2665247862
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.723937512
Short name T227
Test name
Test status
Simulation time 45949449 ps
CPU time 0.93 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 201056 kb
Host smart-7a72b277-c1ca-48e5-8be0-3dc3522a72d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723937512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_ctrl_intersig_mubi.723937512
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.3042732567
Short name T493
Test name
Test status
Simulation time 12620351 ps
CPU time 0.73 seconds
Started Aug 03 05:09:13 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 201060 kb
Host smart-34d1a253-8a23-48ba-bc93-a44e1ee4588b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042732567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.3042732567
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.4005073050
Short name T255
Test name
Test status
Simulation time 650043857 ps
CPU time 3.06 seconds
Started Aug 03 05:09:11 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 201220 kb
Host smart-60a80e51-2323-47ac-bc24-b5e779f8115d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005073050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.4005073050
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.2894910160
Short name T138
Test name
Test status
Simulation time 26866037 ps
CPU time 0.9 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 201060 kb
Host smart-cabcbae9-b98d-44d1-9800-440546c343b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894910160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.2894910160
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.115854937
Short name T228
Test name
Test status
Simulation time 90736491 ps
CPU time 1.09 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201100 kb
Host smart-790a61a8-4e95-4c11-a9e7-92bc5314f75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115854937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.115854937
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.2018875757
Short name T352
Test name
Test status
Simulation time 33795906 ps
CPU time 0.85 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:09:11 PM PDT 24
Peak memory 201020 kb
Host smart-64861ac3-4141-4528-8bcd-3ae6bb0c869d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018875757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.2018875757
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1062051680
Short name T644
Test name
Test status
Simulation time 58347299 ps
CPU time 0.91 seconds
Started Aug 03 05:09:18 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 201112 kb
Host smart-171663fa-fbf0-4ac5-815c-63e043c7a52e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062051680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1062051680
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3484742209
Short name T774
Test name
Test status
Simulation time 18075608 ps
CPU time 0.78 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 201076 kb
Host smart-1f3e94a9-dc5f-4307-90bc-360dac61157d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484742209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.3484742209
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.905889512
Short name T431
Test name
Test status
Simulation time 15579355 ps
CPU time 0.74 seconds
Started Aug 03 05:08:54 PM PDT 24
Finished Aug 03 05:08:55 PM PDT 24
Peak memory 200252 kb
Host smart-364b204b-a87f-4c3b-9ef8-0a913be0a70b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905889512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.905889512
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.150967257
Short name T581
Test name
Test status
Simulation time 23312913 ps
CPU time 0.88 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 200996 kb
Host smart-a0163769-3bca-4ece-8b42-9e085854936b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150967257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_div_intersig_mubi.150967257
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.539882131
Short name T345
Test name
Test status
Simulation time 18989103 ps
CPU time 0.86 seconds
Started Aug 03 05:09:02 PM PDT 24
Finished Aug 03 05:09:03 PM PDT 24
Peak memory 201048 kb
Host smart-da626985-e5f9-4387-ba03-563d7a3fbfe1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539882131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.539882131
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.129084319
Short name T600
Test name
Test status
Simulation time 474274416 ps
CPU time 2.58 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:09:13 PM PDT 24
Peak memory 201128 kb
Host smart-7c2d282d-69a5-4ab0-bbe0-79246eaa619e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129084319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.129084319
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.4179420125
Short name T222
Test name
Test status
Simulation time 650361642 ps
CPU time 3.29 seconds
Started Aug 03 05:09:00 PM PDT 24
Finished Aug 03 05:09:03 PM PDT 24
Peak memory 201152 kb
Host smart-6e5734da-81ce-48e5-a20b-39235be34666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179420125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.4179420125
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.3771415038
Short name T500
Test name
Test status
Simulation time 36281397 ps
CPU time 0.78 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:09:11 PM PDT 24
Peak memory 201012 kb
Host smart-20e37810-4bb9-4375-a323-c83619492185
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771415038 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.3771415038
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.3823444221
Short name T729
Test name
Test status
Simulation time 22240751 ps
CPU time 0.82 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 201076 kb
Host smart-5ed594ee-78ef-436b-b7c5-4e554426be3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823444221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.3823444221
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2472428602
Short name T815
Test name
Test status
Simulation time 22557032 ps
CPU time 0.85 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201080 kb
Host smart-432a1bde-f322-4fa1-b9fc-00a7e3b14e69
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472428602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.2472428602
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.4158292440
Short name T77
Test name
Test status
Simulation time 28894622 ps
CPU time 0.73 seconds
Started Aug 03 05:08:56 PM PDT 24
Finished Aug 03 05:08:57 PM PDT 24
Peak memory 201032 kb
Host smart-7bad92b1-94b0-4854-aa2a-c53245ae927b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158292440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.4158292440
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.3932846660
Short name T535
Test name
Test status
Simulation time 1415336768 ps
CPU time 5.1 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201280 kb
Host smart-46f64021-711c-4712-b155-2120ca47bdb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932846660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3932846660
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.487462463
Short name T238
Test name
Test status
Simulation time 39019099 ps
CPU time 0.98 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200936 kb
Host smart-d9aa0a59-8924-435f-92b1-2505078779bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487462463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.487462463
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1750447697
Short name T553
Test name
Test status
Simulation time 2834519878 ps
CPU time 21.23 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201408 kb
Host smart-a6437802-284a-4395-a340-10c472bb558d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750447697 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1750447697
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.975823550
Short name T66
Test name
Test status
Simulation time 97993164167 ps
CPU time 603.49 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:19:14 PM PDT 24
Peak memory 212488 kb
Host smart-7a093f72-a114-462c-9fa7-1ea24e0549e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=975823550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.975823550
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.2760562675
Short name T561
Test name
Test status
Simulation time 55832096 ps
CPU time 0.87 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:09 PM PDT 24
Peak memory 200988 kb
Host smart-81b209da-4fc3-4ead-b8ee-b8079858af7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760562675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2760562675
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.625811572
Short name T744
Test name
Test status
Simulation time 16471252 ps
CPU time 0.74 seconds
Started Aug 03 05:09:18 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 200956 kb
Host smart-742f7af4-451b-4dec-b2e2-fb6cb171564b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625811572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkm
gr_alert_test.625811572
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.909377689
Short name T715
Test name
Test status
Simulation time 69310496 ps
CPU time 1.02 seconds
Started Aug 03 05:09:11 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 200940 kb
Host smart-0153807a-b890-4a76-9339-1592873254eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909377689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.909377689
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.693530016
Short name T710
Test name
Test status
Simulation time 16020654 ps
CPU time 0.71 seconds
Started Aug 03 05:09:01 PM PDT 24
Finished Aug 03 05:09:02 PM PDT 24
Peak memory 200988 kb
Host smart-363e1596-29bb-4ac4-9ff1-931bd2e5a9ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693530016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.693530016
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.877350127
Short name T314
Test name
Test status
Simulation time 139728286 ps
CPU time 1.33 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:07 PM PDT 24
Peak memory 201100 kb
Host smart-427a41ec-89c7-4e18-ab65-9e28278bb3ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877350127 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_div_intersig_mubi.877350127
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.3350480614
Short name T673
Test name
Test status
Simulation time 26179834 ps
CPU time 0.91 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201016 kb
Host smart-419a9949-382a-4acf-910f-2575b2964c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350480614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.3350480614
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.3588053998
Short name T324
Test name
Test status
Simulation time 1757518062 ps
CPU time 13.95 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:31 PM PDT 24
Peak memory 201368 kb
Host smart-2d6f77cf-598c-41e7-acf5-84ac05150828
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588053998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.3588053998
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.1686993364
Short name T84
Test name
Test status
Simulation time 1855271691 ps
CPU time 7.57 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201076 kb
Host smart-f8306b5f-7c56-44bc-ba90-c1763b6f7f5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686993364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.1686993364
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3028444565
Short name T743
Test name
Test status
Simulation time 36807019 ps
CPU time 0.86 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201104 kb
Host smart-7cc253f3-10d2-4a7d-bb37-9a72b858273c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028444565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.3028444565
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.1963626917
Short name T412
Test name
Test status
Simulation time 77922222 ps
CPU time 1 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201072 kb
Host smart-2a7606b2-7e14-4648-a523-521bfa5cc8eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963626917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.1963626917
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.673498034
Short name T341
Test name
Test status
Simulation time 33875779 ps
CPU time 0.87 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201104 kb
Host smart-93853172-c386-485a-912f-73525551e96f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673498034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.673498034
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.3041779178
Short name T175
Test name
Test status
Simulation time 21248538 ps
CPU time 0.8 seconds
Started Aug 03 05:09:12 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201028 kb
Host smart-a29a5f03-f076-46a8-8d94-7036ce4bf113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041779178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.3041779178
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.1170425796
Short name T634
Test name
Test status
Simulation time 1274910148 ps
CPU time 4.81 seconds
Started Aug 03 05:09:14 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 201252 kb
Host smart-456f9f0a-5a97-4111-8bae-fe37932496b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170425796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.1170425796
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.3986991113
Short name T753
Test name
Test status
Simulation time 22863575 ps
CPU time 0.86 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201064 kb
Host smart-e9e16c59-9d8b-4d7d-91d1-fc089eb14b62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986991113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3986991113
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.203428311
Short name T450
Test name
Test status
Simulation time 9784225968 ps
CPU time 38.39 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:58 PM PDT 24
Peak memory 201428 kb
Host smart-c143ee61-91ac-4649-aca3-cf33fb79d2c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203428311 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.203428311
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.2044198810
Short name T312
Test name
Test status
Simulation time 22590440 ps
CPU time 0.83 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 201096 kb
Host smart-7eb7b5e0-4a29-4a19-b889-b0b93fcc92f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044198810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.2044198810
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1561984430
Short name T734
Test name
Test status
Simulation time 22640328 ps
CPU time 0.86 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201100 kb
Host smart-62254329-d409-48e0-89ce-004c4a4c39e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561984430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1561984430
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3234892767
Short name T268
Test name
Test status
Simulation time 36203167 ps
CPU time 0.79 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 200988 kb
Host smart-243cb766-47f4-4429-ab67-ece25b6f03c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234892767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3234892767
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.1731398262
Short name T162
Test name
Test status
Simulation time 41339395 ps
CPU time 0.75 seconds
Started Aug 03 05:09:07 PM PDT 24
Finished Aug 03 05:09:08 PM PDT 24
Peak memory 200212 kb
Host smart-e3afa974-11cd-4c11-b7e1-ffd85abec992
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731398262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1731398262
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.2638562083
Short name T355
Test name
Test status
Simulation time 112885735 ps
CPU time 1.06 seconds
Started Aug 03 05:09:13 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 200924 kb
Host smart-246960b9-f207-486b-b5d2-29a9367912a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638562083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.2638562083
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.2567457737
Short name T427
Test name
Test status
Simulation time 43847846 ps
CPU time 0.89 seconds
Started Aug 03 05:09:08 PM PDT 24
Finished Aug 03 05:09:10 PM PDT 24
Peak memory 201024 kb
Host smart-6cfb04fc-e7bd-466c-bc38-b3b6d0af98d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567457737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.2567457737
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.2311904645
Short name T248
Test name
Test status
Simulation time 2438823422 ps
CPU time 11.17 seconds
Started Aug 03 05:09:06 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201392 kb
Host smart-8c401d6d-9367-4189-ac43-ceb11ac4348e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311904645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.2311904645
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.2683925177
Short name T323
Test name
Test status
Simulation time 854823318 ps
CPU time 6.33 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201160 kb
Host smart-037100e6-d89c-4336-8f71-ba277559d6b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683925177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.2683925177
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2855769225
Short name T626
Test name
Test status
Simulation time 32881872 ps
CPU time 0.82 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:20 PM PDT 24
Peak memory 200988 kb
Host smart-c611fcb6-7f3a-4e42-8197-bdd0c39f2af4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855769225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.2855769225
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.4001635098
Short name T195
Test name
Test status
Simulation time 102785356 ps
CPU time 1.02 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 200988 kb
Host smart-9ef09b87-3a33-4712-b5fe-fcd09be4e627
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001635098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.4001635098
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3891403973
Short name T202
Test name
Test status
Simulation time 16793283 ps
CPU time 0.76 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:09:10 PM PDT 24
Peak memory 201068 kb
Host smart-53e5f617-376e-4fb8-9539-979b59b1e831
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891403973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.3891403973
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.4156768335
Short name T471
Test name
Test status
Simulation time 34233556 ps
CPU time 0.74 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 200984 kb
Host smart-fc6a30a8-198c-4e43-827a-5e8ef9deb310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156768335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.4156768335
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.1571581462
Short name T747
Test name
Test status
Simulation time 431100121 ps
CPU time 2.95 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201028 kb
Host smart-37009e61-0be9-4a45-8a14-42edb017f178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571581462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.1571581462
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.2731546936
Short name T592
Test name
Test status
Simulation time 21616847 ps
CPU time 0.95 seconds
Started Aug 03 05:09:11 PM PDT 24
Finished Aug 03 05:09:12 PM PDT 24
Peak memory 201032 kb
Host smart-e566cc45-c4d9-4abd-9dbc-6947df264c49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731546936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.2731546936
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.3048308125
Short name T522
Test name
Test status
Simulation time 214781488 ps
CPU time 2.13 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201088 kb
Host smart-6991601d-9c31-4c77-9ed2-095ca9591f30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048308125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.3048308125
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.3992265906
Short name T752
Test name
Test status
Simulation time 115053830722 ps
CPU time 1051.57 seconds
Started Aug 03 05:09:10 PM PDT 24
Finished Aug 03 05:26:42 PM PDT 24
Peak memory 217880 kb
Host smart-e2cd8530-8cc9-422c-822c-2318e5099acf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3992265906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3992265906
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2366161026
Short name T606
Test name
Test status
Simulation time 67000844 ps
CPU time 1.11 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201020 kb
Host smart-65b3c43a-bf79-4cb2-afa7-13311d384837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366161026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2366161026
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.4176711291
Short name T247
Test name
Test status
Simulation time 50834974 ps
CPU time 0.87 seconds
Started Aug 03 05:09:12 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201072 kb
Host smart-1d4cc1bb-84f2-459d-a712-ac6b2fcda026
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176711291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.4176711291
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.283248836
Short name T625
Test name
Test status
Simulation time 49494756 ps
CPU time 0.94 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201068 kb
Host smart-855e0cb1-d512-4787-84ec-cfb5dfd0be89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283248836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.283248836
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.4045091745
Short name T523
Test name
Test status
Simulation time 44716760 ps
CPU time 0.84 seconds
Started Aug 03 05:09:18 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 200248 kb
Host smart-87bb59f3-9177-4976-9309-29a92c94c916
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045091745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.4045091745
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.435331554
Short name T277
Test name
Test status
Simulation time 26787634 ps
CPU time 0.89 seconds
Started Aug 03 05:09:18 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 201048 kb
Host smart-ac8a6369-975f-4aa3-aa05-5b27eafd8bd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435331554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_div_intersig_mubi.435331554
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.3250580282
Short name T785
Test name
Test status
Simulation time 38432509 ps
CPU time 0.9 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201028 kb
Host smart-961fae3d-5874-4924-ae5b-cc4399efd982
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250580282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3250580282
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.694464600
Short name T498
Test name
Test status
Simulation time 1998759800 ps
CPU time 15.9 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:35 PM PDT 24
Peak memory 201388 kb
Host smart-0f8d901b-7c94-413d-a356-7153bb487b29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694464600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.694464600
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.2690150807
Short name T672
Test name
Test status
Simulation time 2054573676 ps
CPU time 14.73 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201416 kb
Host smart-3650d734-a9b7-42a4-9684-9cdf08f0558e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690150807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.2690150807
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.3316463932
Short name T259
Test name
Test status
Simulation time 106317509 ps
CPU time 1.2 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201020 kb
Host smart-6d8c1cf9-0309-436d-ac3d-563c8619cafd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316463932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.3316463932
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.530347001
Short name T337
Test name
Test status
Simulation time 34713653 ps
CPU time 0.78 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:20 PM PDT 24
Peak memory 201120 kb
Host smart-bbf96890-4fd5-4add-98b5-ebe329f1070d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530347001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.530347001
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2161286550
Short name T402
Test name
Test status
Simulation time 33530735 ps
CPU time 0.83 seconds
Started Aug 03 05:09:19 PM PDT 24
Finished Aug 03 05:09:20 PM PDT 24
Peak memory 201076 kb
Host smart-e7601ab8-e024-48e6-8a69-6d300c67026b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161286550 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2161286550
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.1697119400
Short name T451
Test name
Test status
Simulation time 14991653 ps
CPU time 0.78 seconds
Started Aug 03 05:09:41 PM PDT 24
Finished Aug 03 05:09:42 PM PDT 24
Peak memory 200980 kb
Host smart-eb5c0f7c-aac8-454b-852c-6378ece10983
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697119400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1697119400
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.617143514
Short name T725
Test name
Test status
Simulation time 162631011 ps
CPU time 1.48 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201068 kb
Host smart-4a305885-12db-4b82-adda-267647c6cdeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617143514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.617143514
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2843311895
Short name T179
Test name
Test status
Simulation time 73520809 ps
CPU time 0.96 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201028 kb
Host smart-62646ea8-3bbd-4c54-8c02-d795ed758020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843311895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2843311895
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.3188851572
Short name T582
Test name
Test status
Simulation time 36537690 ps
CPU time 0.84 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 201036 kb
Host smart-afafad46-2a4e-4419-832b-ae3d8c55dbe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188851572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.3188851572
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.24255868
Short name T790
Test name
Test status
Simulation time 71973108728 ps
CPU time 451.15 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:17:03 PM PDT 24
Peak memory 209708 kb
Host smart-1aba19e0-670a-49b6-be5b-185d9c64d431
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=24255868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.24255868
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.clkmgr_trans.961599124
Short name T590
Test name
Test status
Simulation time 125465370 ps
CPU time 1.28 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201072 kb
Host smart-08375f01-f838-42ec-a7a4-d669fbf8cf49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961599124 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.961599124
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.2995910227
Short name T199
Test name
Test status
Simulation time 49031937 ps
CPU time 0.9 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201100 kb
Host smart-f2fd4213-2dd3-4c98-b1b9-a2454e920806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995910227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.2995910227
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.4093395553
Short name T567
Test name
Test status
Simulation time 46481279 ps
CPU time 0.9 seconds
Started Aug 03 05:09:18 PM PDT 24
Finished Aug 03 05:09:19 PM PDT 24
Peak memory 201036 kb
Host smart-6d7b9b16-2f75-49d6-9d24-7069f27a05ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093395553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.4093395553
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.3982031252
Short name T311
Test name
Test status
Simulation time 90349010 ps
CPU time 0.89 seconds
Started Aug 03 05:09:13 PM PDT 24
Finished Aug 03 05:09:15 PM PDT 24
Peak memory 200200 kb
Host smart-51ac7a06-2268-454c-9c23-47733dc73827
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982031252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3982031252
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.3199322318
Short name T524
Test name
Test status
Simulation time 18980828 ps
CPU time 0.9 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 201036 kb
Host smart-477dd980-b2c0-47de-afe3-e355e9c4ebc9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199322318 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.3199322318
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.1121748659
Short name T700
Test name
Test status
Simulation time 134167453 ps
CPU time 1.12 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 200984 kb
Host smart-c986dccb-9c59-4ce3-b07a-c5aeeea16724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121748659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1121748659
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2220643211
Short name T536
Test name
Test status
Simulation time 1522776271 ps
CPU time 8.79 seconds
Started Aug 03 05:09:05 PM PDT 24
Finished Aug 03 05:09:14 PM PDT 24
Peak memory 201124 kb
Host smart-24b7a342-6665-4720-a60e-4e949a22e599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220643211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2220643211
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.2906494224
Short name T559
Test name
Test status
Simulation time 1939748492 ps
CPU time 9.68 seconds
Started Aug 03 05:09:09 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201168 kb
Host smart-8d0cca12-04a9-4457-8e7b-0da10beb7409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906494224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.2906494224
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3528877533
Short name T385
Test name
Test status
Simulation time 42100090 ps
CPU time 0.96 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201024 kb
Host smart-72a265b5-6a80-4928-817a-7fed93ca8b4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528877533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3528877533
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2794746364
Short name T766
Test name
Test status
Simulation time 36475709 ps
CPU time 0.84 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201032 kb
Host smart-d02223b8-fbb8-4604-aef0-d18dbbd1e611
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794746364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2794746364
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.4243464139
Short name T218
Test name
Test status
Simulation time 50189366 ps
CPU time 0.81 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201004 kb
Host smart-20d2499a-e6fb-4211-abe6-975db4a3f7e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243464139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.4243464139
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.1120075045
Short name T511
Test name
Test status
Simulation time 46192626 ps
CPU time 0.8 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 200960 kb
Host smart-e8a0e19c-afc4-4a02-9567-9ca52b3ac329
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120075045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.1120075045
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.2239125081
Short name T513
Test name
Test status
Simulation time 1016443961 ps
CPU time 4.05 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201272 kb
Host smart-6ff06f1d-19c7-424a-bc2e-7c8904c0aba6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239125081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2239125081
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.1165017513
Short name T78
Test name
Test status
Simulation time 57823510 ps
CPU time 0.97 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 200940 kb
Host smart-de70bad7-5c7a-4a43-b248-dbc8da449efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165017513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.1165017513
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.702357720
Short name T285
Test name
Test status
Simulation time 3423819468 ps
CPU time 18.6 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201324 kb
Host smart-dd664350-1559-4abb-acff-9f83e21e3774
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702357720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.702357720
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.379600857
Short name T13
Test name
Test status
Simulation time 158779367835 ps
CPU time 924.03 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:24:47 PM PDT 24
Peak memory 217936 kb
Host smart-8c943d48-ab6b-47f2-8b26-b2614c1bd472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=379600857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.379600857
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1800144908
Short name T809
Test name
Test status
Simulation time 38476877 ps
CPU time 1.02 seconds
Started Aug 03 05:09:14 PM PDT 24
Finished Aug 03 05:09:16 PM PDT 24
Peak memory 201060 kb
Host smart-073ea5ae-0115-4375-b59c-91c2a67e78a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800144908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1800144908
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.2577796452
Short name T779
Test name
Test status
Simulation time 115553425 ps
CPU time 1.04 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201224 kb
Host smart-c439388d-82a4-4fe3-b6ce-04b32e5d168f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577796452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.2577796452
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.654127937
Short name T75
Test name
Test status
Simulation time 19365546 ps
CPU time 0.83 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:09:31 PM PDT 24
Peak memory 201020 kb
Host smart-04956220-54c3-4ca8-abd5-ad5b0ba69e03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654127937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.654127937
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.3167473642
Short name T163
Test name
Test status
Simulation time 37119744 ps
CPU time 0.75 seconds
Started Aug 03 05:09:12 PM PDT 24
Finished Aug 03 05:09:13 PM PDT 24
Peak memory 200272 kb
Host smart-b557e91e-7f3e-4107-96a0-e25bf6bf7608
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167473642 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.3167473642
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2406066026
Short name T300
Test name
Test status
Simulation time 40188815 ps
CPU time 0.8 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201004 kb
Host smart-d3defac3-d3da-48be-ab5c-3799758df6fc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406066026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2406066026
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.322019665
Short name T373
Test name
Test status
Simulation time 94095331 ps
CPU time 1.07 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201068 kb
Host smart-50b643ad-7f2d-43cf-bdcc-dbc09d6e0335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322019665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.322019665
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.115730334
Short name T477
Test name
Test status
Simulation time 321084147 ps
CPU time 3.07 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201104 kb
Host smart-a602d4bb-ddc9-41bb-8211-f941eecb96a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115730334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.115730334
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.1239076913
Short name T429
Test name
Test status
Simulation time 1360855703 ps
CPU time 5.91 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201164 kb
Host smart-9b28ecab-4b26-47c9-ab6f-1f529cdda005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239076913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.1239076913
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1807149786
Short name T719
Test name
Test status
Simulation time 53879987 ps
CPU time 1.01 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201028 kb
Host smart-c3260924-c3d7-4aff-a808-b1c7d4534e1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807149786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1807149786
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3195674177
Short name T315
Test name
Test status
Simulation time 107578913 ps
CPU time 1.02 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201048 kb
Host smart-8926b813-26e8-43a9-abce-235108e65ba2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195674177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3195674177
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.2192415699
Short name T803
Test name
Test status
Simulation time 21792839 ps
CPU time 0.84 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201016 kb
Host smart-7bacfd7c-330e-49ba-9f57-172311406a87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192415699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.2192415699
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.3569898126
Short name T770
Test name
Test status
Simulation time 33659396 ps
CPU time 0.76 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201012 kb
Host smart-7aa02e24-89f9-4908-b622-04a2174383c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569898126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.3569898126
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.2297881100
Short name T209
Test name
Test status
Simulation time 938810039 ps
CPU time 5.22 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 201236 kb
Host smart-123acd53-9678-47b8-9384-9a4a427b9147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297881100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2297881100
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3433991039
Short name T588
Test name
Test status
Simulation time 129373425 ps
CPU time 1.18 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201028 kb
Host smart-89369d49-ba24-4073-a0d7-f663b146b3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433991039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3433991039
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.511219234
Short name T577
Test name
Test status
Simulation time 7406477550 ps
CPU time 52.25 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:10:12 PM PDT 24
Peak memory 201472 kb
Host smart-740debb7-6d72-45dc-b839-b21fea82dece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511219234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.511219234
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.3706546164
Short name T82
Test name
Test status
Simulation time 27944513 ps
CPU time 0.91 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:18 PM PDT 24
Peak memory 201060 kb
Host smart-902bccde-0089-4cc2-96ac-e5a895484f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706546164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.3706546164
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.2834429558
Short name T49
Test name
Test status
Simulation time 50975278 ps
CPU time 0.9 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201064 kb
Host smart-346fd20c-c868-4334-9722-1575d814df27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834429558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.2834429558
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.3591951977
Short name T662
Test name
Test status
Simulation time 28767829 ps
CPU time 0.78 seconds
Started Aug 03 05:09:16 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201036 kb
Host smart-61573700-c92c-48a4-9e81-6976c9bd6add
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591951977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.3591951977
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2405033721
Short name T806
Test name
Test status
Simulation time 58229424 ps
CPU time 0.8 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 200280 kb
Host smart-45d8c639-b476-4bb5-a62b-9ffb32d46b64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405033721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2405033721
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.1413865787
Short name T525
Test name
Test status
Simulation time 24793647 ps
CPU time 0.86 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201044 kb
Host smart-5a713fa8-cbda-4189-a87d-5d275cfe36f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413865787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.1413865787
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.3478228782
Short name T225
Test name
Test status
Simulation time 21922354 ps
CPU time 0.88 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201032 kb
Host smart-902628aa-1902-45d7-8f23-6a8c2ebb6515
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478228782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.3478228782
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2038476615
Short name T364
Test name
Test status
Simulation time 379538164 ps
CPU time 2.03 seconds
Started Aug 03 05:09:38 PM PDT 24
Finished Aug 03 05:09:40 PM PDT 24
Peak memory 201072 kb
Host smart-44fce746-969d-4393-875e-fd44274ddb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038476615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2038476615
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.372420893
Short name T792
Test name
Test status
Simulation time 2060190773 ps
CPU time 14.19 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 201420 kb
Host smart-9f4a0ea8-d4e8-447f-b6f9-4bc3156499cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372420893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_ti
meout.372420893
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.1181446338
Short name T651
Test name
Test status
Simulation time 70937867 ps
CPU time 1.06 seconds
Started Aug 03 05:09:46 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201032 kb
Host smart-22ea8a6b-e0d5-466a-97cb-19fd447a0a26
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181446338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.1181446338
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2579308460
Short name T549
Test name
Test status
Simulation time 13287659 ps
CPU time 0.74 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201016 kb
Host smart-7ec72af9-6baf-4dd3-b394-0e23e6b096e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579308460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.2579308460
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.240507721
Short name T350
Test name
Test status
Simulation time 40438019 ps
CPU time 0.9 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201024 kb
Host smart-38308f4e-faa6-4e23-8697-d33ce7d95bf9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240507721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_ctrl_intersig_mubi.240507721
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.4228309955
Short name T388
Test name
Test status
Simulation time 15210869 ps
CPU time 0.78 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201000 kb
Host smart-3032780b-56d8-4554-b9e2-e110d0ce2d22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228309955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4228309955
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.3157390072
Short name T347
Test name
Test status
Simulation time 585979071 ps
CPU time 2.55 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201240 kb
Host smart-db4f36b7-eac5-4e43-9855-06e7a1d4f905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157390072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.3157390072
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.3552772819
Short name T605
Test name
Test status
Simulation time 68453615 ps
CPU time 1 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201096 kb
Host smart-e59c80ca-5263-4b35-bafd-09f18774321f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552772819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.3552772819
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.1592840410
Short name T508
Test name
Test status
Simulation time 650984912 ps
CPU time 2.86 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 201080 kb
Host smart-0a10f464-f85c-4d3a-96bd-cd6215327a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592840410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.1592840410
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.90709769
Short name T674
Test name
Test status
Simulation time 24512140 ps
CPU time 0.85 seconds
Started Aug 03 05:09:26 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201088 kb
Host smart-c7e8041c-afc9-4eff-8a9e-91bfb41f6fe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90709769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.90709769
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.1550427935
Short name T251
Test name
Test status
Simulation time 20124888 ps
CPU time 0.71 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 200916 kb
Host smart-e8a9cb32-69d6-4835-ac65-2a2f44106df0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550427935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.1550427935
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1503668013
Short name T102
Test name
Test status
Simulation time 80403483 ps
CPU time 1.03 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201072 kb
Host smart-dc084b93-7bce-4817-a55f-b7549e18a9dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503668013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.1503668013
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.2656211713
Short name T394
Test name
Test status
Simulation time 19335113 ps
CPU time 0.75 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 201020 kb
Host smart-fa8a3589-12a6-451e-8519-4e73a494f887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656211713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2656211713
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.1512240265
Short name T210
Test name
Test status
Simulation time 17712567 ps
CPU time 0.73 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201016 kb
Host smart-1983272a-d948-4886-8c82-1faaff9b5896
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512240265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.1512240265
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.4034295360
Short name T425
Test name
Test status
Simulation time 30272072 ps
CPU time 0.73 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201028 kb
Host smart-24917daa-80ec-4584-8b35-511de3f78840
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034295360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.4034295360
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.454295530
Short name T586
Test name
Test status
Simulation time 682236829 ps
CPU time 5.64 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201172 kb
Host smart-de793055-2ae3-47d5-b4e0-22bf33555496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454295530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.454295530
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.401863288
Short name T278
Test name
Test status
Simulation time 1107554685 ps
CPU time 5.13 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:09:40 PM PDT 24
Peak memory 201104 kb
Host smart-448b5925-d4d9-4791-8405-2cba2911711b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401863288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti
meout.401863288
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1518213123
Short name T178
Test name
Test status
Simulation time 24137696 ps
CPU time 0.87 seconds
Started Aug 03 05:09:26 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201048 kb
Host smart-57f7cf90-c42e-4557-ad41-d25dc3c7ed7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518213123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1518213123
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2888742717
Short name T767
Test name
Test status
Simulation time 16651668 ps
CPU time 0.76 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 200908 kb
Host smart-7005601b-a0f6-4c65-9461-7cb3acc1d5ed
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888742717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2888742717
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.975641785
Short name T703
Test name
Test status
Simulation time 70382493 ps
CPU time 1 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 200916 kb
Host smart-a39b5e64-d345-44e1-bc76-c9515d2e4962
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975641785 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.975641785
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.2721271711
Short name T462
Test name
Test status
Simulation time 22543870 ps
CPU time 0.75 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:37 PM PDT 24
Peak memory 201060 kb
Host smart-48d6e6a8-62fa-4b72-8a57-d12c1d8e7eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721271711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2721271711
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1075420409
Short name T305
Test name
Test status
Simulation time 999887607 ps
CPU time 5.78 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201204 kb
Host smart-e2270001-7606-45df-bce8-19c372bf3e15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075420409 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1075420409
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.3541790971
Short name T283
Test name
Test status
Simulation time 29945883 ps
CPU time 0.82 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 200980 kb
Host smart-891fc699-e6c0-43bc-a088-df3cb57f7678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541790971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3541790971
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.2306647131
Short name T40
Test name
Test status
Simulation time 117037063 ps
CPU time 1.61 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201056 kb
Host smart-13dbd2d3-f5b7-412a-83e0-098299b7f8b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306647131 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.2306647131
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.692475733
Short name T14
Test name
Test status
Simulation time 93922071743 ps
CPU time 646.52 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:20:12 PM PDT 24
Peak memory 217900 kb
Host smart-12652af2-8e60-4019-af5d-ff5975da8823
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=692475733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.692475733
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3740936750
Short name T782
Test name
Test status
Simulation time 142905901 ps
CPU time 1.33 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201056 kb
Host smart-409b40c8-8d69-4618-a78a-c1fe0041f80e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740936750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3740936750
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.1553692230
Short name T685
Test name
Test status
Simulation time 16819623 ps
CPU time 0.76 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201076 kb
Host smart-00a95ee6-75fa-4187-b89e-6f69212c71a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553692230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.1553692230
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.3376607283
Short name T5
Test name
Test status
Simulation time 44178716 ps
CPU time 0.93 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:22 PM PDT 24
Peak memory 200984 kb
Host smart-5a04890b-9df1-4a04-bf51-dcb962f7a273
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376607283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.3376607283
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.584352214
Short name T38
Test name
Test status
Simulation time 17646912 ps
CPU time 0.71 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:09:48 PM PDT 24
Peak memory 200980 kb
Host smart-fb2aa3a2-ced6-48e7-8e03-5052f6bc0f55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584352214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.584352214
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.4167784004
Short name T335
Test name
Test status
Simulation time 213878278 ps
CPU time 1.46 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:09:48 PM PDT 24
Peak memory 201032 kb
Host smart-f05d9ea4-e5a7-4442-aa82-d2b5cbabd57a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167784004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.4167784004
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.395900497
Short name T358
Test name
Test status
Simulation time 40199599 ps
CPU time 0.77 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:09:26 PM PDT 24
Peak memory 201044 kb
Host smart-36064e5c-b351-4f21-9776-8d44d88b2955
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395900497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.395900497
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.2609217213
Short name T24
Test name
Test status
Simulation time 1422603386 ps
CPU time 6.71 seconds
Started Aug 03 05:09:40 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201076 kb
Host smart-20b55676-03a6-4b4f-ab96-46f4fff4b988
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609217213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2609217213
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3148640896
Short name T623
Test name
Test status
Simulation time 220544013 ps
CPU time 1.43 seconds
Started Aug 03 05:09:42 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201192 kb
Host smart-d748e23e-f68b-4f53-9143-7244b950da66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148640896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3148640896
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1059501458
Short name T698
Test name
Test status
Simulation time 24687923 ps
CPU time 0.89 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:09:31 PM PDT 24
Peak memory 201032 kb
Host smart-e8afc37a-708d-4c42-8215-ff3ef0270646
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059501458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1059501458
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.2568064964
Short name T466
Test name
Test status
Simulation time 17567313 ps
CPU time 0.76 seconds
Started Aug 03 05:09:38 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 201032 kb
Host smart-c3ef3f62-8c6f-48b1-894a-607823f48808
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568064964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.2568064964
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3014258872
Short name T547
Test name
Test status
Simulation time 89668968 ps
CPU time 1.09 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201036 kb
Host smart-5a36678a-b5f7-49fe-a7de-12014bd2b082
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014258872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.3014258872
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.1550762289
Short name T599
Test name
Test status
Simulation time 33362068 ps
CPU time 0.78 seconds
Started Aug 03 05:09:17 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 201068 kb
Host smart-bc292638-ce46-4486-8616-029c9f464af9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550762289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1550762289
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1352144474
Short name T794
Test name
Test status
Simulation time 1461560321 ps
CPU time 5.51 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201284 kb
Host smart-a22833d9-e558-440b-b08c-7844e9a08d7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352144474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1352144474
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.4033586898
Short name T368
Test name
Test status
Simulation time 27233566 ps
CPU time 0.84 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201044 kb
Host smart-1e20d8ba-8c4b-4a7e-808a-da7a2c285246
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033586898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.4033586898
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.3652435754
Short name T413
Test name
Test status
Simulation time 6877063764 ps
CPU time 51.31 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:10:19 PM PDT 24
Peak memory 201484 kb
Host smart-3f0b68c9-936c-4521-9e5b-b1029a5bd1b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652435754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3652435754
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.1742399789
Short name T735
Test name
Test status
Simulation time 371708637 ps
CPU time 1.89 seconds
Started Aug 03 05:09:15 PM PDT 24
Finished Aug 03 05:09:17 PM PDT 24
Peak memory 200984 kb
Host smart-610da73b-64e5-4a57-8e2a-31219d647717
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742399789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1742399789
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.3246547757
Short name T416
Test name
Test status
Simulation time 89584538 ps
CPU time 0.97 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201052 kb
Host smart-a259055d-a31d-439f-bee8-645b4fd5c35e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246547757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.3246547757
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2385660648
Short name T338
Test name
Test status
Simulation time 63713323 ps
CPU time 0.94 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201080 kb
Host smart-61222f6a-df2e-47e7-a1ce-2f12c9091354
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385660648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.2385660648
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.966041815
Short name T434
Test name
Test status
Simulation time 38076438 ps
CPU time 0.75 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:01 PM PDT 24
Peak memory 200264 kb
Host smart-67963bcf-8b85-4456-8ced-efc4073514e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966041815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.966041815
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.2332143073
Short name T515
Test name
Test status
Simulation time 27735039 ps
CPU time 0.91 seconds
Started Aug 03 05:08:04 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 201016 kb
Host smart-eca4fa26-17e5-4d19-82b7-9717c2cd2975
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332143073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.2332143073
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3338607220
Short name T751
Test name
Test status
Simulation time 16884353 ps
CPU time 0.79 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201044 kb
Host smart-2d47186f-9728-4bf4-954b-549b2cb1a92a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338607220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3338607220
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.2577935639
Short name T235
Test name
Test status
Simulation time 2372078890 ps
CPU time 13.27 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201384 kb
Host smart-b6de1bba-5392-462a-a07d-51f1ce7fcc28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577935639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2577935639
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.1441504954
Short name T408
Test name
Test status
Simulation time 1574855835 ps
CPU time 11.39 seconds
Started Aug 03 05:08:04 PM PDT 24
Finished Aug 03 05:08:15 PM PDT 24
Peak memory 201144 kb
Host smart-fa4a7494-4789-4a54-9dbb-e0a7a6229e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441504954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.1441504954
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.1978580241
Short name T267
Test name
Test status
Simulation time 69767731 ps
CPU time 0.98 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201072 kb
Host smart-9a2af22a-866a-4d9c-b788-b3020768cb66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978580241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.1978580241
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.782773097
Short name T399
Test name
Test status
Simulation time 31053891 ps
CPU time 0.77 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201224 kb
Host smart-24273a92-3ac7-4c8b-bd85-1e7486021ea5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782773097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_lc_clk_byp_req_intersig_mubi.782773097
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2014057157
Short name T264
Test name
Test status
Simulation time 51512002 ps
CPU time 0.97 seconds
Started Aug 03 05:08:01 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 201080 kb
Host smart-fdee71a8-bd77-43e3-b0c1-33694fb5ce37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014057157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2014057157
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.44165388
Short name T733
Test name
Test status
Simulation time 45136747 ps
CPU time 0.82 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201028 kb
Host smart-84e5bafd-936f-4d52-a304-321804792ca0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44165388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.44165388
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.478511344
Short name T308
Test name
Test status
Simulation time 1126255014 ps
CPU time 4.47 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:11 PM PDT 24
Peak memory 201260 kb
Host smart-a1ac12d3-7a94-4f96-9d7e-ad4eb0af8325
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478511344 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.478511344
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.3755470015
Short name T41
Test name
Test status
Simulation time 227664858 ps
CPU time 2.1 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 216480 kb
Host smart-f9149bd5-bac9-49f0-850b-01ace9e1ac95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755470015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.3755470015
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.1126092891
Short name T822
Test name
Test status
Simulation time 78122514 ps
CPU time 1.12 seconds
Started Aug 03 05:08:03 PM PDT 24
Finished Aug 03 05:08:04 PM PDT 24
Peak memory 201196 kb
Host smart-5d9ad3aa-92dc-4e22-888d-db05af198778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126092891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.1126092891
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2575000095
Short name T675
Test name
Test status
Simulation time 3895778205 ps
CPU time 22.18 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:28 PM PDT 24
Peak memory 201436 kb
Host smart-fdaf60af-1b80-480e-b690-31eaf30e9264
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575000095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2575000095
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1855249399
Short name T313
Test name
Test status
Simulation time 61657583 ps
CPU time 1.01 seconds
Started Aug 03 05:08:02 PM PDT 24
Finished Aug 03 05:08:03 PM PDT 24
Peak memory 200996 kb
Host smart-68dde3f9-b706-4315-ab00-ab3989e064c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855249399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1855249399
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.757602168
Short name T473
Test name
Test status
Simulation time 45873942 ps
CPU time 0.88 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201020 kb
Host smart-7b3a4cf4-9d12-437a-8765-f38242322a04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757602168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkm
gr_alert_test.757602168
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.3081774435
Short name T299
Test name
Test status
Simulation time 27605296 ps
CPU time 0.82 seconds
Started Aug 03 05:09:20 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201052 kb
Host smart-21a552a6-9591-48bb-a5ba-8ce0d00aac3f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081774435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.3081774435
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.3274962633
Short name T584
Test name
Test status
Simulation time 12781213 ps
CPU time 0.72 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 200220 kb
Host smart-30353d66-a62e-4057-b142-137318a42d01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274962633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.3274962633
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.1640784487
Short name T678
Test name
Test status
Simulation time 26051106 ps
CPU time 0.87 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201244 kb
Host smart-21ec0106-1360-479d-958e-1f701d1f791b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640784487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.1640784487
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.3372917001
Short name T551
Test name
Test status
Simulation time 33434411 ps
CPU time 0.85 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201076 kb
Host smart-0cab3d4b-5514-41cc-b8a1-cdea6f855b10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372917001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3372917001
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.3225978892
Short name T492
Test name
Test status
Simulation time 2131749140 ps
CPU time 12.11 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:55 PM PDT 24
Peak memory 201260 kb
Host smart-d93efbff-4206-4029-b939-25272c76aa83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225978892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.3225978892
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1736730005
Short name T521
Test name
Test status
Simulation time 739780252 ps
CPU time 5.52 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:27 PM PDT 24
Peak memory 201192 kb
Host smart-572f1e46-32ad-4e1d-887a-6e5da17978cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736730005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1736730005
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.80676266
Short name T723
Test name
Test status
Simulation time 49318346 ps
CPU time 0.86 seconds
Started Aug 03 05:09:46 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201028 kb
Host smart-765f0188-c7cc-4b26-b42f-6e6c6a1764df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80676266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.clkmgr_idle_intersig_mubi.80676266
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3028000580
Short name T704
Test name
Test status
Simulation time 104530334 ps
CPU time 1.1 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201032 kb
Host smart-8745ad40-9f60-4338-abed-9f24f9817bef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028000580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3028000580
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.3729753949
Short name T141
Test name
Test status
Simulation time 41881226 ps
CPU time 0.91 seconds
Started Aug 03 05:09:40 PM PDT 24
Finished Aug 03 05:09:41 PM PDT 24
Peak memory 201028 kb
Host smart-b6a8a2ed-d90e-4054-9b6b-775bf1b6d7c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729753949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.3729753949
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.63309366
Short name T541
Test name
Test status
Simulation time 22366042 ps
CPU time 0.84 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201048 kb
Host smart-6254cb4b-d609-4063-927a-bdb5cfbb1424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63309366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.63309366
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3417262918
Short name T613
Test name
Test status
Simulation time 753615588 ps
CPU time 3.16 seconds
Started Aug 03 05:09:40 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201272 kb
Host smart-1654b00f-a842-44f0-a00b-586af1059094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417262918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3417262918
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.2021511584
Short name T679
Test name
Test status
Simulation time 70261295 ps
CPU time 0.98 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201008 kb
Host smart-c240901f-d33f-46dc-b8fd-09caf599a659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021511584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2021511584
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.2668445395
Short name T671
Test name
Test status
Simulation time 2154343805 ps
CPU time 10.98 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:10:03 PM PDT 24
Peak memory 201388 kb
Host smart-5109df2b-38b3-4866-9d98-d80e477cdcfc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668445395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.2668445395
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2665445310
Short name T544
Test name
Test status
Simulation time 62096347 ps
CPU time 0.95 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201072 kb
Host smart-04b228ef-d1aa-41e5-b7b9-e5f1ea88a8d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665445310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2665445310
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1766217832
Short name T736
Test name
Test status
Simulation time 76989410 ps
CPU time 0.96 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201100 kb
Host smart-4f5d9187-82b8-48a1-be82-31ce2d8be21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766217832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1766217832
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.861192205
Short name T150
Test name
Test status
Simulation time 85244615 ps
CPU time 1.08 seconds
Started Aug 03 05:09:41 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201092 kb
Host smart-c3a3d304-217b-4696-b4c8-411a361f7c5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861192205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.861192205
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.4122070817
Short name T161
Test name
Test status
Simulation time 69034159 ps
CPU time 0.85 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 200240 kb
Host smart-01b76bfd-ef1f-440e-a839-1b267dfa8b9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122070817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.4122070817
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.848511680
Short name T472
Test name
Test status
Simulation time 41273834 ps
CPU time 0.86 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201092 kb
Host smart-4bf85ed4-0c24-4f91-acaf-78e91a61f167
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848511680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_div_intersig_mubi.848511680
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.2022892781
Short name T716
Test name
Test status
Simulation time 21286059 ps
CPU time 0.82 seconds
Started Aug 03 05:09:34 PM PDT 24
Finished Aug 03 05:09:35 PM PDT 24
Peak memory 200988 kb
Host smart-ab5b8e99-57ca-446c-b771-45bd0402f8aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022892781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.2022892781
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1451950151
Short name T517
Test name
Test status
Simulation time 1530953886 ps
CPU time 8.84 seconds
Started Aug 03 05:09:42 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201112 kb
Host smart-50ed3b10-fe22-4632-baa4-f2b61220bd48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451950151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1451950151
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1094258482
Short name T750
Test name
Test status
Simulation time 1712185637 ps
CPU time 5.53 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201132 kb
Host smart-edab19c5-e670-4e95-8cd7-1628b7bbdedc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094258482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1094258482
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.2303817688
Short name T187
Test name
Test status
Simulation time 115850851 ps
CPU time 1.25 seconds
Started Aug 03 05:09:49 PM PDT 24
Finished Aug 03 05:09:50 PM PDT 24
Peak memory 201084 kb
Host smart-f19f178c-9dfa-4690-90df-020e4217de8e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303817688 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.2303817688
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.396164350
Short name T696
Test name
Test status
Simulation time 37748081 ps
CPU time 0.92 seconds
Started Aug 03 05:09:26 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 200996 kb
Host smart-a36e41fb-c6a9-4092-b821-ef216cbebeae
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396164350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_clk_byp_req_intersig_mubi.396164350
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.453674982
Short name T360
Test name
Test status
Simulation time 19786975 ps
CPU time 0.79 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 201076 kb
Host smart-f4dadc6b-bbd5-4439-adc3-54694fdfb031
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453674982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_ctrl_intersig_mubi.453674982
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.2006291942
Short name T183
Test name
Test status
Simulation time 23702473 ps
CPU time 0.68 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201068 kb
Host smart-d3837a36-b19c-4148-827b-588a45457936
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006291942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2006291942
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.3505388247
Short name T708
Test name
Test status
Simulation time 647528995 ps
CPU time 2.86 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201276 kb
Host smart-fb1b7c46-31fc-4a20-ab0d-1ac965585722
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505388247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3505388247
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2960071476
Short name T362
Test name
Test status
Simulation time 24555874 ps
CPU time 0.82 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 200968 kb
Host smart-84195545-1099-47e4-927b-0e0373a7ced8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960071476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2960071476
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.1538294766
Short name T497
Test name
Test status
Simulation time 2035301659 ps
CPU time 9.58 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 201304 kb
Host smart-88465f6a-e94d-42d0-832f-698475186549
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538294766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.1538294766
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all_with_rand_reset.3415483395
Short name T170
Test name
Test status
Simulation time 48223894812 ps
CPU time 535.39 seconds
Started Aug 03 05:09:26 PM PDT 24
Finished Aug 03 05:18:22 PM PDT 24
Peak memory 209616 kb
Host smart-a606a830-2dad-4d56-bd37-eefcd86161e6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3415483395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.3415483395
Directory /workspace/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1145094672
Short name T746
Test name
Test status
Simulation time 65182612 ps
CPU time 1.08 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201024 kb
Host smart-f538359a-4e64-439f-bd8e-966e38c580b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145094672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1145094672
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.1581682264
Short name T239
Test name
Test status
Simulation time 25181400 ps
CPU time 0.83 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 201052 kb
Host smart-b5ddbd7d-a321-498e-80ee-eed3f7b5317a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581682264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.1581682264
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.3597386221
Short name T724
Test name
Test status
Simulation time 36633641 ps
CPU time 0.78 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 201044 kb
Host smart-ba20e95d-8748-427f-b8d5-bcdc5b4b7fce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597386221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.3597386221
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.3893553564
Short name T336
Test name
Test status
Simulation time 23667412 ps
CPU time 0.72 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 200968 kb
Host smart-136e86e7-0db6-4441-ae2c-0ed0c2ce5472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893553564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.3893553564
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.38275031
Short name T738
Test name
Test status
Simulation time 31144047 ps
CPU time 0.83 seconds
Started Aug 03 05:09:55 PM PDT 24
Finished Aug 03 05:09:56 PM PDT 24
Peak memory 201072 kb
Host smart-472452cb-330f-4858-8605-33ce8c9fdb03
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38275031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.clkmgr_div_intersig_mubi.38275031
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.1413110795
Short name T787
Test name
Test status
Simulation time 35221877 ps
CPU time 0.84 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201052 kb
Host smart-fda60eba-5124-46e0-ab73-2e15fb2629a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413110795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1413110795
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3740260710
Short name T756
Test name
Test status
Simulation time 2116301148 ps
CPU time 9.02 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 201308 kb
Host smart-76b19622-99f6-453f-9c07-d0a7a9816d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740260710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3740260710
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2498675748
Short name T526
Test name
Test status
Simulation time 260947976 ps
CPU time 2.28 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:40 PM PDT 24
Peak memory 201184 kb
Host smart-23324357-84af-4b5c-9808-0d03d074106b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498675748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2498675748
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3024938438
Short name T520
Test name
Test status
Simulation time 17162495 ps
CPU time 0.76 seconds
Started Aug 03 05:09:21 PM PDT 24
Finished Aug 03 05:09:21 PM PDT 24
Peak memory 201016 kb
Host smart-d273b338-4140-4a7b-80c2-5cf232d38744
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024938438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3024938438
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3819998656
Short name T545
Test name
Test status
Simulation time 22815101 ps
CPU time 0.85 seconds
Started Aug 03 05:09:25 PM PDT 24
Finished Aug 03 05:09:26 PM PDT 24
Peak memory 201032 kb
Host smart-9272078d-f642-4932-93ff-1d3be28c38b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819998656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3819998656
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3492964350
Short name T426
Test name
Test status
Simulation time 107715385 ps
CPU time 1.17 seconds
Started Aug 03 05:09:33 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201008 kb
Host smart-c1998e66-5873-4063-b2dd-6b8598c3ca55
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492964350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.3492964350
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.2215011069
Short name T193
Test name
Test status
Simulation time 50811337 ps
CPU time 0.86 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201012 kb
Host smart-37d4ca33-4534-4699-bb52-c20c114f32f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215011069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.2215011069
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.44287188
Short name T309
Test name
Test status
Simulation time 1594523079 ps
CPU time 5.11 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:09:56 PM PDT 24
Peak memory 201260 kb
Host smart-8f58c02e-24e0-489e-81b5-9ce5e0d025e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44287188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.44287188
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.3946620808
Short name T491
Test name
Test status
Simulation time 19807201 ps
CPU time 0.85 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:53 PM PDT 24
Peak memory 201028 kb
Host smart-7ca57472-3a29-4914-b497-9703606b4f87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946620808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.3946620808
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.589722637
Short name T686
Test name
Test status
Simulation time 2784230386 ps
CPU time 14.58 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:41 PM PDT 24
Peak memory 201444 kb
Host smart-40e84b80-face-46d5-9c31-6cd29aaa0a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589722637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.589722637
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.3968783712
Short name T67
Test name
Test status
Simulation time 174022496977 ps
CPU time 1215.5 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:29:51 PM PDT 24
Peak memory 217964 kb
Host smart-87b69e71-d1e9-4f96-8444-858e82f95bdc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3968783712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.3968783712
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.479153545
Short name T528
Test name
Test status
Simulation time 26311682 ps
CPU time 0.78 seconds
Started Aug 03 05:09:39 PM PDT 24
Finished Aug 03 05:09:40 PM PDT 24
Peak memory 201052 kb
Host smart-8d48f863-b658-478a-b010-46a8a47a93d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479153545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.479153545
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.3770518818
Short name T298
Test name
Test status
Simulation time 45188359 ps
CPU time 0.91 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201064 kb
Host smart-703f40ad-6018-4dbe-987d-4d6d5b20429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770518818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.3770518818
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.2043860244
Short name T143
Test name
Test status
Simulation time 23082212 ps
CPU time 0.84 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201076 kb
Host smart-cf15df72-4d6c-43cd-b041-2a48ea2b96b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043860244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.2043860244
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.732897539
Short name T459
Test name
Test status
Simulation time 36083684 ps
CPU time 0.76 seconds
Started Aug 03 05:09:42 PM PDT 24
Finished Aug 03 05:09:43 PM PDT 24
Peak memory 200208 kb
Host smart-a764d51e-125b-42bf-81f6-2c8ebc7ad5a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732897539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.732897539
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2118742953
Short name T737
Test name
Test status
Simulation time 14051688 ps
CPU time 0.71 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:28 PM PDT 24
Peak memory 201048 kb
Host smart-e60248ef-8a02-4c4f-b9e2-aa982ebf88de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118742953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2118742953
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.2434466808
Short name T286
Test name
Test status
Simulation time 39148841 ps
CPU time 0.94 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201076 kb
Host smart-9b3f1aae-baf3-43eb-b56a-e78328ef1487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434466808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2434466808
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.216913185
Short name T694
Test name
Test status
Simulation time 1174817608 ps
CPU time 6.33 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:37 PM PDT 24
Peak memory 201148 kb
Host smart-ad05ae39-57a2-40fe-98f7-97967fe80526
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216913185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.216913185
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3480100070
Short name T661
Test name
Test status
Simulation time 854182085 ps
CPU time 6.22 seconds
Started Aug 03 05:09:27 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201148 kb
Host smart-5bd9fbfe-f25e-4de7-9a7d-f532a19971f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480100070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3480100070
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.2501337361
Short name T595
Test name
Test status
Simulation time 25685706 ps
CPU time 0.92 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 200992 kb
Host smart-453c3a0a-391b-42ad-8051-48b762c4cb5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501337361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.2501337361
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.3189774768
Short name T745
Test name
Test status
Simulation time 46290510 ps
CPU time 0.86 seconds
Started Aug 03 05:09:36 PM PDT 24
Finished Aug 03 05:09:37 PM PDT 24
Peak memory 201072 kb
Host smart-2f52fc18-baf0-47b5-9720-2a077dc95339
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189774768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.3189774768
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.4015456381
Short name T453
Test name
Test status
Simulation time 27319757 ps
CPU time 0.86 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:09:31 PM PDT 24
Peak memory 201084 kb
Host smart-b55e4368-bf9d-4bc2-a34f-c406fee2aac9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015456381 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_ctrl_intersig_mubi.4015456381
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.2067851528
Short name T188
Test name
Test status
Simulation time 17226550 ps
CPU time 0.78 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 200984 kb
Host smart-47c40d28-4603-4836-8b3a-bc5f553e0f79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067851528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.2067851528
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.4104837514
Short name T145
Test name
Test status
Simulation time 282791791 ps
CPU time 1.78 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201028 kb
Host smart-65d8f419-38ec-4f5b-9102-b94edf409ab4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104837514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.4104837514
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.2457091325
Short name T76
Test name
Test status
Simulation time 63991377 ps
CPU time 0.95 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201072 kb
Host smart-e3d8c1dc-83d8-4b2a-9776-1a8c3cf0c136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457091325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.2457091325
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.3095310653
Short name T95
Test name
Test status
Simulation time 6094812677 ps
CPU time 25.1 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:50 PM PDT 24
Peak memory 201432 kb
Host smart-fb8c32cf-0d4e-4626-ae8a-5197a4b4f669
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095310653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.3095310653
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.3005839211
Short name T506
Test name
Test status
Simulation time 49891658 ps
CPU time 0.92 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201100 kb
Host smart-c769329e-db57-40c3-b3fb-0ec260c36532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005839211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3005839211
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.2416992805
Short name T211
Test name
Test status
Simulation time 21942592 ps
CPU time 0.78 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201108 kb
Host smart-0cc99a39-0354-413f-872a-34d622553a89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416992805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.2416992805
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.3917571540
Short name T757
Test name
Test status
Simulation time 20370279 ps
CPU time 0.89 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201104 kb
Host smart-585b12b6-6958-4f0b-8a4a-7e836e71535f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917571540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.3917571540
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.685217792
Short name T463
Test name
Test status
Simulation time 28891654 ps
CPU time 0.73 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 200256 kb
Host smart-4e4507eb-3ef2-473e-bf39-cacb6e296eb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685217792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.685217792
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.2200450449
Short name T583
Test name
Test status
Simulation time 20650260 ps
CPU time 0.81 seconds
Started Aug 03 05:09:24 PM PDT 24
Finished Aug 03 05:09:25 PM PDT 24
Peak memory 201028 kb
Host smart-230d5f9f-00e9-4523-913c-84f770938583
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200450449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.2200450449
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.1543561082
Short name T17
Test name
Test status
Simulation time 80806855 ps
CPU time 1.05 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 200948 kb
Host smart-f685e8f8-b989-40a2-9154-9b42dcacb72a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543561082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.1543561082
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1784591880
Short name T3
Test name
Test status
Simulation time 811457821 ps
CPU time 4.69 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:09:35 PM PDT 24
Peak memory 201136 kb
Host smart-bc85a054-cc2f-4f40-a4e3-ba4c8289fcbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784591880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1784591880
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.2769082731
Short name T469
Test name
Test status
Simulation time 618852688 ps
CPU time 4.64 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:42 PM PDT 24
Peak memory 201184 kb
Host smart-cb7e254a-0a4d-45a6-ae9b-34bbf4194e66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769082731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.2769082731
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.3928026645
Short name T354
Test name
Test status
Simulation time 26424469 ps
CPU time 0.89 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201028 kb
Host smart-b4150ddd-8bfb-4109-a9b2-c335cb047c6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928026645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_idle_intersig_mubi.3928026645
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3426277826
Short name T548
Test name
Test status
Simulation time 32132951 ps
CPU time 0.8 seconds
Started Aug 03 05:09:23 PM PDT 24
Finished Aug 03 05:09:24 PM PDT 24
Peak memory 201012 kb
Host smart-d8115d40-516b-49fc-b6b3-7e2a384836d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426277826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3426277826
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3299607986
Short name T777
Test name
Test status
Simulation time 33438405 ps
CPU time 0.86 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 201048 kb
Host smart-c5a665da-9d56-4aab-8f39-b4a52b7250c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299607986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.3299607986
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.433230645
Short name T333
Test name
Test status
Simulation time 17423448 ps
CPU time 0.75 seconds
Started Aug 03 05:09:40 PM PDT 24
Finished Aug 03 05:09:41 PM PDT 24
Peak memory 201052 kb
Host smart-ee5c8024-e49f-43e0-af4e-401e8ca1af89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433230645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.433230645
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.2902222227
Short name T458
Test name
Test status
Simulation time 346753972 ps
CPU time 1.78 seconds
Started Aug 03 05:09:42 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201004 kb
Host smart-056b5216-e62f-466a-bbd0-e5b739168cc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902222227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.2902222227
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.371193771
Short name T295
Test name
Test status
Simulation time 61264787 ps
CPU time 0.95 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201076 kb
Host smart-2a1d7ee2-a3d2-4ed7-ac10-448fc99471a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371193771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.371193771
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.4217469827
Short name T797
Test name
Test status
Simulation time 63730923 ps
CPU time 0.92 seconds
Started Aug 03 05:09:28 PM PDT 24
Finished Aug 03 05:09:29 PM PDT 24
Peak memory 201052 kb
Host smart-fb565eee-d9fd-4777-be8d-dc233b3a1235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217469827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.4217469827
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.2853059005
Short name T16
Test name
Test status
Simulation time 24893479 ps
CPU time 0.89 seconds
Started Aug 03 05:09:22 PM PDT 24
Finished Aug 03 05:09:23 PM PDT 24
Peak memory 201060 kb
Host smart-1081116b-b419-4f31-aebf-ce8490ee8bd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853059005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.2853059005
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.2583526783
Short name T325
Test name
Test status
Simulation time 16853492 ps
CPU time 0.8 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201040 kb
Host smart-6bb6d7bd-dedd-48b7-9ee3-8ef1c50a9b85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583526783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.2583526783
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1168413862
Short name T100
Test name
Test status
Simulation time 67345706 ps
CPU time 1 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201124 kb
Host smart-ac796ef3-9757-4bd2-b9e6-de431466e289
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168413862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.1168413862
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3825976287
Short name T363
Test name
Test status
Simulation time 18631826 ps
CPU time 0.74 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:09:48 PM PDT 24
Peak memory 200252 kb
Host smart-8cefa684-a660-4aee-9b87-5ad517b24890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825976287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3825976287
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2245939095
Short name T693
Test name
Test status
Simulation time 25275401 ps
CPU time 0.81 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201056 kb
Host smart-dad65ae7-cd8e-43d2-b542-d6c0b29dcb2e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245939095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2245939095
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.519109634
Short name T793
Test name
Test status
Simulation time 26967195 ps
CPU time 0.89 seconds
Started Aug 03 05:09:46 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201044 kb
Host smart-269870dd-dfc0-40ef-9525-cdce27c7698a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519109634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.519109634
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.1029418515
Short name T243
Test name
Test status
Simulation time 2119474710 ps
CPU time 17.17 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201328 kb
Host smart-8478165e-4ec4-4f47-a7c7-39136bd9f261
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029418515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1029418515
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.1461534248
Short name T627
Test name
Test status
Simulation time 1098942728 ps
CPU time 8.22 seconds
Started Aug 03 05:09:38 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201100 kb
Host smart-adbf6e93-ee40-4600-9510-4129d11dcbb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461534248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.1461534248
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.490610476
Short name T682
Test name
Test status
Simulation time 62753161 ps
CPU time 0.92 seconds
Started Aug 03 05:09:30 PM PDT 24
Finished Aug 03 05:09:32 PM PDT 24
Peak memory 201092 kb
Host smart-41dda908-4c41-4490-a35b-8c69279a02ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490610476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_idle_intersig_mubi.490610476
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1356601677
Short name T480
Test name
Test status
Simulation time 36557426 ps
CPU time 0.84 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 200996 kb
Host smart-ff5d36b6-1046-471e-945f-683ce41c3be5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356601677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1356601677
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.2487258172
Short name T563
Test name
Test status
Simulation time 32099909 ps
CPU time 0.79 seconds
Started Aug 03 05:09:46 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201076 kb
Host smart-596c074d-5602-451e-b726-f1cf727a416e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487258172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.2487258172
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.351968482
Short name T349
Test name
Test status
Simulation time 18777752 ps
CPU time 0.76 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 201024 kb
Host smart-7a0b4d80-a79c-4bc6-91db-0b0775141e6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351968482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.351968482
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2569834128
Short name T657
Test name
Test status
Simulation time 269445112 ps
CPU time 1.41 seconds
Started Aug 03 05:09:33 PM PDT 24
Finished Aug 03 05:09:34 PM PDT 24
Peak memory 201044 kb
Host smart-875430fe-d4a5-4ca5-bfea-e52826fefa32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569834128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2569834128
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.729136808
Short name T190
Test name
Test status
Simulation time 53115387 ps
CPU time 0.91 seconds
Started Aug 03 05:09:29 PM PDT 24
Finished Aug 03 05:09:30 PM PDT 24
Peak memory 201068 kb
Host smart-51a96376-cef9-43f0-b7c1-da2f748986a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729136808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.729136808
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.3198179306
Short name T783
Test name
Test status
Simulation time 19332718955 ps
CPU time 84.94 seconds
Started Aug 03 05:09:35 PM PDT 24
Finished Aug 03 05:11:00 PM PDT 24
Peak memory 201464 kb
Host smart-11e09fb1-c1aa-40d9-8bca-8475e1b974fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198179306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.3198179306
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all_with_rand_reset.1697497689
Short name T476
Test name
Test status
Simulation time 62755081583 ps
CPU time 672.32 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:20:58 PM PDT 24
Peak memory 217888 kb
Host smart-8fb5a8ca-d055-4726-a221-581e21f60156
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1697497689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.1697497689
Directory /workspace/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1138953367
Short name T263
Test name
Test status
Simulation time 38351781 ps
CPU time 0.82 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201072 kb
Host smart-53723314-9c0b-4dd4-829b-d1375899c1be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138953367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1138953367
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.274298414
Short name T34
Test name
Test status
Simulation time 79818255 ps
CPU time 1.03 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201080 kb
Host smart-47ab0979-3e4d-4a42-ad32-ccac7c33cd39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274298414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.274298414
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.1322447937
Short name T369
Test name
Test status
Simulation time 73950736 ps
CPU time 1 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:09:57 PM PDT 24
Peak memory 201036 kb
Host smart-df4a7091-5b5c-422f-945e-464adcb78b82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322447937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.1322447937
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1729018061
Short name T249
Test name
Test status
Simulation time 31589489 ps
CPU time 0.74 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:10:04 PM PDT 24
Peak memory 200992 kb
Host smart-fd36415b-d701-43a9-9337-06fdbdf1864a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729018061 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1729018061
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.1871775781
Short name T788
Test name
Test status
Simulation time 95992963 ps
CPU time 1.15 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201028 kb
Host smart-1b403a82-1437-44fe-9504-5dd1579de950
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871775781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.1871775781
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.33405839
Short name T444
Test name
Test status
Simulation time 72959472 ps
CPU time 1.04 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:33 PM PDT 24
Peak memory 201012 kb
Host smart-d605a42b-7e26-422d-9ec1-87cb41f0459a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.33405839
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.2800716482
Short name T322
Test name
Test status
Simulation time 1396961745 ps
CPU time 10.11 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:42 PM PDT 24
Peak memory 201128 kb
Host smart-0111891a-a812-44c3-a2fb-9ce905f44f81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800716482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.2800716482
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.4183188853
Short name T820
Test name
Test status
Simulation time 1099507833 ps
CPU time 8.56 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:10:00 PM PDT 24
Peak memory 201148 kb
Host smart-68b2ec3a-3936-41e1-b06e-4e27042a2251
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183188853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.4183188853
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1828365750
Short name T376
Test name
Test status
Simulation time 50894990 ps
CPU time 0.89 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201080 kb
Host smart-d136ea80-bf9b-4b65-9667-8de0ceb40ca5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828365750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1828365750
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.2813524256
Short name T241
Test name
Test status
Simulation time 26944089 ps
CPU time 0.89 seconds
Started Aug 03 05:09:48 PM PDT 24
Finished Aug 03 05:09:49 PM PDT 24
Peak memory 201076 kb
Host smart-4ea6e2ee-8a47-4d8c-ba2b-51bf0b72afce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813524256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.2813524256
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2609575566
Short name T808
Test name
Test status
Simulation time 69773491 ps
CPU time 0.92 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 200980 kb
Host smart-c72affa8-0d09-40a0-8032-50d7524bdab0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609575566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2609575566
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.1317840235
Short name T817
Test name
Test status
Simulation time 23965770 ps
CPU time 0.79 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201084 kb
Host smart-4810bc80-6f20-4ede-b1fe-a66934d26053
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317840235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.1317840235
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.692218180
Short name T565
Test name
Test status
Simulation time 909128523 ps
CPU time 3.91 seconds
Started Aug 03 05:09:53 PM PDT 24
Finished Aug 03 05:09:57 PM PDT 24
Peak memory 201424 kb
Host smart-451c9718-69cf-4c5f-97c2-3524fe935eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692218180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.692218180
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.442366422
Short name T118
Test name
Test status
Simulation time 47362112 ps
CPU time 0.85 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:46 PM PDT 24
Peak memory 201032 kb
Host smart-e866959e-c9db-41e0-b94d-9794567a665a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442366422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.442366422
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.3995595179
Short name T482
Test name
Test status
Simulation time 3546667859 ps
CPU time 22.38 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:22 PM PDT 24
Peak memory 201424 kb
Host smart-8c9f425d-238f-48d4-83f9-3a437560a7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995595179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.3995595179
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.4015346780
Short name T37
Test name
Test status
Simulation time 33282520144 ps
CPU time 306.47 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:14:38 PM PDT 24
Peak memory 209752 kb
Host smart-170a3b37-f8a8-479c-9b5c-288a5824687f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4015346780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.4015346780
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2815671085
Short name T640
Test name
Test status
Simulation time 54265385 ps
CPU time 1.04 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201028 kb
Host smart-3219a573-a3ea-4623-8a4d-2ca18fa7c4b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815671085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2815671085
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2729651134
Short name T558
Test name
Test status
Simulation time 35541683 ps
CPU time 0.85 seconds
Started Aug 03 05:09:42 PM PDT 24
Finished Aug 03 05:09:43 PM PDT 24
Peak memory 201056 kb
Host smart-f8881c40-f84e-4e4a-8f12-72c6090f3045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729651134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2729651134
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2275261965
Short name T691
Test name
Test status
Simulation time 56589533 ps
CPU time 0.91 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201084 kb
Host smart-08a15ef9-1c48-4579-8126-20645ec9db2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275261965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2275261965
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.3851519985
Short name T755
Test name
Test status
Simulation time 46831402 ps
CPU time 0.78 seconds
Started Aug 03 05:09:37 PM PDT 24
Finished Aug 03 05:09:38 PM PDT 24
Peak memory 200308 kb
Host smart-a3e1bd94-4903-4a4f-9a9d-7ec794836533
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851519985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.3851519985
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.3007851757
Short name T650
Test name
Test status
Simulation time 17505058 ps
CPU time 0.81 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 201052 kb
Host smart-ba75f8d3-1349-4dc1-a7d4-55dfe527d803
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007851757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.3007851757
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1513941169
Short name T149
Test name
Test status
Simulation time 62343674 ps
CPU time 0.92 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:32 PM PDT 24
Peak memory 201016 kb
Host smart-007a5f8f-c578-4a96-bbd5-0e082b80492e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513941169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1513941169
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.1623063257
Short name T9
Test name
Test status
Simulation time 1156832829 ps
CPU time 7.74 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:09:55 PM PDT 24
Peak memory 201072 kb
Host smart-0c569468-4c23-49c3-b0d6-5f419fc79655
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623063257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.1623063257
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.554833578
Short name T475
Test name
Test status
Simulation time 1336043509 ps
CPU time 8.67 seconds
Started Aug 03 05:09:41 PM PDT 24
Finished Aug 03 05:09:49 PM PDT 24
Peak memory 201192 kb
Host smart-01390a8c-9090-4ccb-b213-28f9889e2e73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554833578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.554833578
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.612527539
Short name T688
Test name
Test status
Simulation time 80039258 ps
CPU time 1.04 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 201012 kb
Host smart-e7efcdd0-505f-42ca-8b12-0f673960128f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612527539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_idle_intersig_mubi.612527539
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3034089757
Short name T284
Test name
Test status
Simulation time 28139878 ps
CPU time 0.79 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 201036 kb
Host smart-ff015145-3526-4b33-ae34-b8d8a0a078b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034089757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3034089757
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.672773717
Short name T712
Test name
Test status
Simulation time 22486661 ps
CPU time 0.87 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:09:57 PM PDT 24
Peak memory 201020 kb
Host smart-fdd3e857-490a-46e3-b125-3ebce2d7808e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672773717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_ctrl_intersig_mubi.672773717
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2359748057
Short name T455
Test name
Test status
Simulation time 26972356 ps
CPU time 0.75 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201096 kb
Host smart-79c48464-4514-438b-8357-104390f50985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359748057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2359748057
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2969732257
Short name T776
Test name
Test status
Simulation time 322376306 ps
CPU time 2.3 seconds
Started Aug 03 05:09:45 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201004 kb
Host smart-36d3613c-7a94-43fa-ae31-617a718bb932
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969732257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2969732257
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.1556997598
Short name T307
Test name
Test status
Simulation time 54354785 ps
CPU time 0.89 seconds
Started Aug 03 05:09:57 PM PDT 24
Finished Aug 03 05:09:58 PM PDT 24
Peak memory 201020 kb
Host smart-af4359b0-a91b-4552-afdf-bb935c32ef9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556997598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1556997598
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.3152546259
Short name T789
Test name
Test status
Simulation time 6762398690 ps
CPU time 28.37 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:10:18 PM PDT 24
Peak memory 201388 kb
Host smart-ef06404e-b768-41c1-8115-1c51fe5ec83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152546259 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.3152546259
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.666163984
Short name T518
Test name
Test status
Simulation time 36259605 ps
CPU time 1.01 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:45 PM PDT 24
Peak memory 201092 kb
Host smart-b4bd19dc-6129-4417-9a9f-724e7697692a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666163984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.666163984
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.552170042
Short name T530
Test name
Test status
Simulation time 46669111 ps
CPU time 0.83 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:58 PM PDT 24
Peak memory 201064 kb
Host smart-24c96e18-e778-4ea7-a92e-bf2400ace1cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552170042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.552170042
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.354651574
Short name T404
Test name
Test status
Simulation time 13604807 ps
CPU time 0.76 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201064 kb
Host smart-c3eb3013-0976-44ca-9be1-e74e06cbb299
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354651574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.354651574
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.3711942416
Short name T39
Test name
Test status
Simulation time 121906994 ps
CPU time 0.95 seconds
Started Aug 03 05:09:49 PM PDT 24
Finished Aug 03 05:09:50 PM PDT 24
Peak memory 200260 kb
Host smart-726c6097-c10b-4166-a8bb-1c666da12d4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711942416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.3711942416
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.390670792
Short name T372
Test name
Test status
Simulation time 68084247 ps
CPU time 0.91 seconds
Started Aug 03 05:09:43 PM PDT 24
Finished Aug 03 05:09:44 PM PDT 24
Peak memory 201076 kb
Host smart-afe777b6-f0d4-4abf-bc4c-aa0dc1e34663
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390670792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
8.clkmgr_div_intersig_mubi.390670792
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.3866668211
Short name T253
Test name
Test status
Simulation time 24979474 ps
CPU time 0.86 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:09:56 PM PDT 24
Peak memory 201052 kb
Host smart-02697262-2b94-40e3-99b4-48b395b5c6b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866668211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.3866668211
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.3296023832
Short name T289
Test name
Test status
Simulation time 883204338 ps
CPU time 3.82 seconds
Started Aug 03 05:09:32 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201152 kb
Host smart-a68d4990-c789-471a-8192-04b06130c0c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296023832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.3296023832
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1234259620
Short name T638
Test name
Test status
Simulation time 69523132 ps
CPU time 0.98 seconds
Started Aug 03 05:09:38 PM PDT 24
Finished Aug 03 05:09:39 PM PDT 24
Peak memory 201000 kb
Host smart-58e53322-6bed-4ff4-9abc-cb82e1aa7fa5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234259620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1234259620
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2808527681
Short name T204
Test name
Test status
Simulation time 56191933 ps
CPU time 0.91 seconds
Started Aug 03 05:09:52 PM PDT 24
Finished Aug 03 05:09:54 PM PDT 24
Peak memory 201072 kb
Host smart-7603282e-327f-4633-bb2c-fe4cbdb4dead
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808527681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2808527681
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.2493701348
Short name T557
Test name
Test status
Simulation time 19127278 ps
CPU time 0.79 seconds
Started Aug 03 05:09:47 PM PDT 24
Finished Aug 03 05:09:48 PM PDT 24
Peak memory 201052 kb
Host smart-80d469dd-504e-40d7-9339-d9541d25ca66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493701348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.2493701348
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.4024646030
Short name T329
Test name
Test status
Simulation time 1271908719 ps
CPU time 4.98 seconds
Started Aug 03 05:09:31 PM PDT 24
Finished Aug 03 05:09:36 PM PDT 24
Peak memory 201196 kb
Host smart-55497877-2a17-46f5-ba8f-c6ebdc028e68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024646030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.4024646030
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2130434004
Short name T390
Test name
Test status
Simulation time 80711788 ps
CPU time 1.05 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 201024 kb
Host smart-cba5a58b-c471-4f4b-994e-2f424fb2d002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130434004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2130434004
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.999029219
Short name T12
Test name
Test status
Simulation time 8412676831 ps
CPU time 54.05 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:54 PM PDT 24
Peak memory 201496 kb
Host smart-a0b9df21-12ba-4c0d-a367-3dc1132c8d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999029219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.999029219
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3061916231
Short name T697
Test name
Test status
Simulation time 43204880 ps
CPU time 0.94 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 201016 kb
Host smart-863b6415-68d5-4223-b80d-8afa9a9288ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061916231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3061916231
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1748881347
Short name T728
Test name
Test status
Simulation time 28142573 ps
CPU time 0.72 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:00 PM PDT 24
Peak memory 201084 kb
Host smart-c38cb12f-369d-42ed-bbc4-4ad5d20ecae5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748881347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1748881347
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.4062927265
Short name T519
Test name
Test status
Simulation time 25451497 ps
CPU time 0.89 seconds
Started Aug 03 05:10:00 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201072 kb
Host smart-b9fb25ae-67a6-4169-a5b3-14202101fca3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062927265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.4062927265
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.977997205
Short name T166
Test name
Test status
Simulation time 20094035 ps
CPU time 0.75 seconds
Started Aug 03 05:09:51 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 200296 kb
Host smart-21bae92c-149e-4108-ad7b-79aa08f3a4bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977997205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.977997205
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.1291271183
Short name T375
Test name
Test status
Simulation time 47538099 ps
CPU time 0.87 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 201068 kb
Host smart-e0d5c0ab-5400-48a6-8b99-413e8b2a8804
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291271183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.1291271183
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.1073430461
Short name T722
Test name
Test status
Simulation time 158522796 ps
CPU time 1.25 seconds
Started Aug 03 05:10:01 PM PDT 24
Finished Aug 03 05:10:02 PM PDT 24
Peak memory 201040 kb
Host smart-db9e6b80-86df-4de7-9731-1d3aac140c05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073430461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.1073430461
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.2194937452
Short name T234
Test name
Test status
Simulation time 447614546 ps
CPU time 2.9 seconds
Started Aug 03 05:09:44 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201132 kb
Host smart-887c62bb-bd02-4500-9f7d-b796eae1c4c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194937452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.2194937452
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.4061441552
Short name T570
Test name
Test status
Simulation time 748454066 ps
CPU time 4.55 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:10:00 PM PDT 24
Peak memory 201076 kb
Host smart-a9c7d9be-ac2a-4221-998e-cecaba1a0469
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061441552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.4061441552
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.215254529
Short name T641
Test name
Test status
Simulation time 81197390 ps
CPU time 0.98 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:09:59 PM PDT 24
Peak memory 201048 kb
Host smart-c006c1ed-97ed-4224-a19a-a3c85e70c32c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215254529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.clkmgr_idle_intersig_mubi.215254529
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.3528906702
Short name T440
Test name
Test status
Simulation time 58452808 ps
CPU time 1.07 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:52 PM PDT 24
Peak memory 201076 kb
Host smart-0c2c60dd-45dc-4e1f-a5b1-c6cc8021b92c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528906702 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.3528906702
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3658625053
Short name T18
Test name
Test status
Simulation time 20330231 ps
CPU time 0.74 seconds
Started Aug 03 05:09:56 PM PDT 24
Finished Aug 03 05:09:57 PM PDT 24
Peak memory 201080 kb
Host smart-f1f13923-f41f-450f-a7bd-234340bfc50b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658625053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3658625053
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.2169731048
Short name T465
Test name
Test status
Simulation time 19511805 ps
CPU time 0.79 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:51 PM PDT 24
Peak memory 201220 kb
Host smart-2a32d007-6104-45bf-b414-301627cf3ca7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169731048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.2169731048
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.4203164010
Short name T706
Test name
Test status
Simulation time 380668213 ps
CPU time 2.58 seconds
Started Aug 03 05:09:58 PM PDT 24
Finished Aug 03 05:10:01 PM PDT 24
Peak memory 201072 kb
Host smart-91541afb-bd15-4352-a860-2da1711f96d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203164010 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.4203164010
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.3978009823
Short name T484
Test name
Test status
Simulation time 53679852 ps
CPU time 0.91 seconds
Started Aug 03 05:09:46 PM PDT 24
Finished Aug 03 05:09:47 PM PDT 24
Peak memory 201024 kb
Host smart-7cda39c3-77a8-4749-8268-d5e173b76fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978009823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.3978009823
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1231645841
Short name T593
Test name
Test status
Simulation time 215249671 ps
CPU time 2.16 seconds
Started Aug 03 05:09:54 PM PDT 24
Finished Aug 03 05:09:56 PM PDT 24
Peak memory 201104 kb
Host smart-8471dfab-0cf1-48a9-b012-1c6c10080aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231645841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1231645841
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all_with_rand_reset.16579896
Short name T660
Test name
Test status
Simulation time 40596509676 ps
CPU time 444.76 seconds
Started Aug 03 05:09:59 PM PDT 24
Finished Aug 03 05:17:24 PM PDT 24
Peak memory 217896 kb
Host smart-2db0a35b-e713-47df-906c-5b2186f183ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=16579896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.16579896
Directory /workspace/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1944116056
Short name T701
Test name
Test status
Simulation time 28291145 ps
CPU time 0.87 seconds
Started Aug 03 05:09:50 PM PDT 24
Finished Aug 03 05:09:50 PM PDT 24
Peak memory 201048 kb
Host smart-d3ef0e95-ca99-4416-b7e4-e27bd751219b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944116056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1944116056
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.29936217
Short name T236
Test name
Test status
Simulation time 15023347 ps
CPU time 0.78 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:10 PM PDT 24
Peak memory 201096 kb
Host smart-ec45db24-26f4-405c-b49e-6911885c19af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29936217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr
_alert_test.29936217
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.2785610756
Short name T343
Test name
Test status
Simulation time 49906818 ps
CPU time 0.87 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 200892 kb
Host smart-9d3c7fa0-c63d-4557-b106-5efba0e30751
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785610756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.2785610756
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1628651422
Short name T748
Test name
Test status
Simulation time 55432348 ps
CPU time 0.85 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 200996 kb
Host smart-400584a1-4d42-411c-b201-77742c7e115d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628651422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1628651422
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2185216445
Short name T223
Test name
Test status
Simulation time 63856250 ps
CPU time 0.97 seconds
Started Aug 03 05:08:08 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 201080 kb
Host smart-4151d536-6722-48d1-9ae5-562395240cac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185216445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2185216445
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.2516746685
Short name T398
Test name
Test status
Simulation time 61027646 ps
CPU time 0.9 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 201032 kb
Host smart-ceb898fb-0a09-44d6-85c7-7e1e43948640
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516746685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.2516746685
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.407040349
Short name T120
Test name
Test status
Simulation time 942306097 ps
CPU time 4.69 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:11 PM PDT 24
Peak memory 201088 kb
Host smart-63ed0b93-411b-4371-a254-c6b60a02ffa8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407040349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.407040349
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.732504210
Short name T410
Test name
Test status
Simulation time 1461379977 ps
CPU time 10.81 seconds
Started Aug 03 05:08:04 PM PDT 24
Finished Aug 03 05:08:15 PM PDT 24
Peak memory 201172 kb
Host smart-de6976eb-e09e-40bd-9baa-4b962f52c113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732504210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim
eout.732504210
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.415460837
Short name T230
Test name
Test status
Simulation time 29803832 ps
CPU time 1 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 201076 kb
Host smart-587b748f-c1c0-41ef-878b-29ff16e15e73
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415460837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.clkmgr_idle_intersig_mubi.415460837
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3111180235
Short name T275
Test name
Test status
Simulation time 21429974 ps
CPU time 0.79 seconds
Started Aug 03 05:08:08 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 201032 kb
Host smart-b131b118-326f-4371-bf2a-8081f767058b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111180235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.3111180235
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.3278742349
Short name T442
Test name
Test status
Simulation time 19067699 ps
CPU time 0.91 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201048 kb
Host smart-6ed03728-5a49-4246-a155-567ca77fa674
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278742349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.3278742349
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.994689232
Short name T501
Test name
Test status
Simulation time 25085640 ps
CPU time 0.77 seconds
Started Aug 03 05:08:04 PM PDT 24
Finished Aug 03 05:08:05 PM PDT 24
Peak memory 200984 kb
Host smart-c06cb61c-449c-4f18-8212-a224d4aeb55e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994689232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.994689232
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.3839156481
Short name T374
Test name
Test status
Simulation time 933024361 ps
CPU time 5.56 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201220 kb
Host smart-11fb3e7b-ef0f-4371-869b-34020f0bc6fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839156481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3839156481
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.1157169920
Short name T730
Test name
Test status
Simulation time 61982572 ps
CPU time 0.98 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:11 PM PDT 24
Peak memory 200952 kb
Host smart-5bb5d482-8dad-4ffd-bc15-6d3a62172504
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157169920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.1157169920
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.3679502271
Short name T804
Test name
Test status
Simulation time 932855568 ps
CPU time 7.5 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:16 PM PDT 24
Peak memory 201352 kb
Host smart-f14ca115-b1ee-4afd-ad3d-f5874b87048c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679502271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.3679502271
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.3792427060
Short name T692
Test name
Test status
Simulation time 34639982 ps
CPU time 0.97 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:10 PM PDT 24
Peak memory 201092 kb
Host smart-751e0741-b270-4275-97a4-4f67b491d2b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792427060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3792427060
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.746801846
Short name T395
Test name
Test status
Simulation time 117809420 ps
CPU time 1.15 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 200400 kb
Host smart-f3f06568-1d57-4208-86ca-b88474240545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746801846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.746801846
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2978218451
Short name T503
Test name
Test status
Simulation time 31610933 ps
CPU time 0.81 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 200936 kb
Host smart-115a17d2-ffe9-46e0-a844-869ddb6b8e1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978218451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2978218451
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.4055349039
Short name T622
Test name
Test status
Simulation time 16715690 ps
CPU time 0.7 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 200288 kb
Host smart-24af0b17-1f48-45e5-986b-4a51cd93cd7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055349039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.4055349039
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.1121714787
Short name T348
Test name
Test status
Simulation time 61453020 ps
CPU time 0.92 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 200968 kb
Host smart-de3eb133-c31f-40fd-87f3-d7843552f1db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121714787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.1121714787
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2196022005
Short name T486
Test name
Test status
Simulation time 44052383 ps
CPU time 0.83 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:10 PM PDT 24
Peak memory 201052 kb
Host smart-666ffd18-6c53-4832-9b36-207bd53bd977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196022005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2196022005
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.715878625
Short name T407
Test name
Test status
Simulation time 1349735078 ps
CPU time 6.35 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201120 kb
Host smart-59e8c868-cf31-4852-ac2c-1a64fdcdd432
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715878625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.715878625
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.1962171090
Short name T320
Test name
Test status
Simulation time 974410448 ps
CPU time 7.53 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:15 PM PDT 24
Peak memory 200496 kb
Host smart-4501b6a4-1647-4a47-8e3e-0fba6337da8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962171090 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.1962171090
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.2120503450
Short name T180
Test name
Test status
Simulation time 26745047 ps
CPU time 0.88 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201032 kb
Host smart-38d59998-d191-4952-84ea-72eb5d4262b5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120503450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.2120503450
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2793869388
Short name T6
Test name
Test status
Simulation time 66651877 ps
CPU time 0.92 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:10 PM PDT 24
Peak memory 201084 kb
Host smart-a29e9f75-acd6-43ef-aeb0-526454c166f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793869388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2793869388
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.4003165568
Short name T378
Test name
Test status
Simulation time 31799555 ps
CPU time 0.93 seconds
Started Aug 03 05:08:08 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 201076 kb
Host smart-5c6aba3e-1d85-4c74-80b3-4f08a004d691
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003165568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.4003165568
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.3340825770
Short name T184
Test name
Test status
Simulation time 35241974 ps
CPU time 0.91 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:06 PM PDT 24
Peak memory 201000 kb
Host smart-b75e90f7-dede-43c9-b445-b1e88318d4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340825770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3340825770
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.580442977
Short name T294
Test name
Test status
Simulation time 668026495 ps
CPU time 2.96 seconds
Started Aug 03 05:08:08 PM PDT 24
Finished Aug 03 05:08:11 PM PDT 24
Peak memory 201208 kb
Host smart-333c1dcc-db47-480a-ab00-4895b39c3471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580442977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.580442977
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.2876057710
Short name T597
Test name
Test status
Simulation time 48215840 ps
CPU time 0.93 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201000 kb
Host smart-c753987e-8391-4b61-a7d4-025a7bc1885d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876057710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.2876057710
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.531341713
Short name T727
Test name
Test status
Simulation time 269909598096 ps
CPU time 1028.87 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:25:18 PM PDT 24
Peak memory 217900 kb
Host smart-f7a782d6-169e-4330-82aa-4ca053e6372a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=531341713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.531341713
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.4265206896
Short name T447
Test name
Test status
Simulation time 342865469 ps
CPU time 1.82 seconds
Started Aug 03 05:08:05 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201008 kb
Host smart-4fa7c852-88e6-4c8f-a201-704045b2d883
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265206896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.4265206896
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.708823681
Short name T192
Test name
Test status
Simulation time 39547377 ps
CPU time 0.83 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 200936 kb
Host smart-22bf33b3-47ed-40ab-a205-884afd5f3923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708823681 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.708823681
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1151999134
Short name T759
Test name
Test status
Simulation time 97012038 ps
CPU time 0.99 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201068 kb
Host smart-4fcd7e62-4a63-4a6d-a325-59c1d5e694c6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151999134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1151999134
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.1325328403
Short name T717
Test name
Test status
Simulation time 18139356 ps
CPU time 0.72 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 200288 kb
Host smart-3c947f72-57f1-4451-ac30-fe3eaa557831
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325328403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1325328403
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.49891615
Short name T611
Test name
Test status
Simulation time 28348464 ps
CPU time 0.83 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201016 kb
Host smart-9a1846bb-6a43-4940-a347-d854be87e8eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49891615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
clkmgr_div_intersig_mubi.49891615
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3533027643
Short name T468
Test name
Test status
Simulation time 142751542 ps
CPU time 1.23 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:08 PM PDT 24
Peak memory 201052 kb
Host smart-b87b4c20-ef7a-421d-a3fb-1e579e53ca47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533027643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3533027643
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.2139064870
Short name T233
Test name
Test status
Simulation time 2114822063 ps
CPU time 17.07 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:23 PM PDT 24
Peak memory 201296 kb
Host smart-b4d3bf81-4d02-4e13-b318-7c002c633943
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139064870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.2139064870
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.481261008
Short name T632
Test name
Test status
Simulation time 1038326541 ps
CPU time 4.75 seconds
Started Aug 03 05:08:09 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201152 kb
Host smart-7ea9a48a-7930-49a7-9083-96d58700e9c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481261008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_tim
eout.481261008
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1662145964
Short name T334
Test name
Test status
Simulation time 271715375 ps
CPU time 1.8 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:09 PM PDT 24
Peak memory 201048 kb
Host smart-a326448d-aeae-4abe-8859-2210ef8bbdb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662145964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1662145964
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1781596507
Short name T666
Test name
Test status
Simulation time 17892786 ps
CPU time 0.81 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 201120 kb
Host smart-bf9d0f51-0d79-45f6-b5d3-e37992df8e79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781596507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1781596507
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.1937819705
Short name T628
Test name
Test status
Simulation time 53206811 ps
CPU time 0.87 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 201068 kb
Host smart-10839491-33eb-44b8-953a-8b82d7e895dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937819705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.1937819705
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.2427930970
Short name T502
Test name
Test status
Simulation time 24222600 ps
CPU time 0.77 seconds
Started Aug 03 05:08:07 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201008 kb
Host smart-c73b08e3-d340-4c46-aeec-799d2ba0a750
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427930970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.2427930970
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.3922870645
Short name T633
Test name
Test status
Simulation time 440747038 ps
CPU time 2.12 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201032 kb
Host smart-0574fea1-9132-48a3-8a70-233c46c88ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922870645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3922870645
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.2016181087
Short name T139
Test name
Test status
Simulation time 82014118 ps
CPU time 1.14 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 200972 kb
Host smart-5133ee09-1015-4908-b567-05bfbf06142e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016181087 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.2016181087
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.2547842043
Short name T579
Test name
Test status
Simulation time 7044568375 ps
CPU time 30.24 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:44 PM PDT 24
Peak memory 201400 kb
Host smart-7836030e-90ca-4bbf-91b7-cfa4386b3049
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547842043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.2547842043
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.4095635388
Short name T380
Test name
Test status
Simulation time 21136331 ps
CPU time 0.81 seconds
Started Aug 03 05:08:06 PM PDT 24
Finished Aug 03 05:08:07 PM PDT 24
Peak memory 201072 kb
Host smart-d76d8264-077b-4987-8a3f-57574f3663aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095635388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.4095635388
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.1571165234
Short name T667
Test name
Test status
Simulation time 56152635 ps
CPU time 0.84 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201056 kb
Host smart-86c912c0-8ab1-4792-936e-1897177a3339
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571165234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.1571165234
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3078360022
Short name T94
Test name
Test status
Simulation time 108556537 ps
CPU time 1.11 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201064 kb
Host smart-86e1e972-f4c1-44f0-991f-c5d4bcb042c9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078360022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3078360022
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2259510379
Short name T160
Test name
Test status
Simulation time 79744329 ps
CPU time 0.86 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 200232 kb
Host smart-e724ea09-3a55-43ec-a752-2de44f16dfd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259510379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2259510379
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1168273373
Short name T282
Test name
Test status
Simulation time 51804298 ps
CPU time 0.99 seconds
Started Aug 03 05:08:16 PM PDT 24
Finished Aug 03 05:08:17 PM PDT 24
Peak memory 201072 kb
Host smart-03c6ee0a-57f1-4154-a69d-d2306fe228b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168273373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.1168273373
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.2228699249
Short name T749
Test name
Test status
Simulation time 19132811 ps
CPU time 0.79 seconds
Started Aug 03 05:08:15 PM PDT 24
Finished Aug 03 05:08:16 PM PDT 24
Peak memory 201040 kb
Host smart-22cfd18c-9623-4372-a96a-b05aeb044dc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228699249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.2228699249
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.1524354330
Short name T274
Test name
Test status
Simulation time 2113098157 ps
CPU time 8.7 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 201344 kb
Host smart-3394ffee-3bc9-4af9-aa35-640227c1b970
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524354330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1524354330
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.579296128
Short name T780
Test name
Test status
Simulation time 2184423539 ps
CPU time 12.54 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:24 PM PDT 24
Peak memory 201412 kb
Host smart-8fd1ab9d-8bec-43ba-9a77-b824b48b431b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579296128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim
eout.579296128
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.2549857301
Short name T435
Test name
Test status
Simulation time 36652509 ps
CPU time 0.89 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201060 kb
Host smart-f2192c9f-4cfc-4edd-a208-e3c2ff9c77ac
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549857301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.2549857301
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.2534672243
Short name T443
Test name
Test status
Simulation time 35321057 ps
CPU time 0.86 seconds
Started Aug 03 05:08:16 PM PDT 24
Finished Aug 03 05:08:17 PM PDT 24
Peak memory 201080 kb
Host smart-87efe666-b6a0-4356-9c79-cf35f063bba3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534672243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.2534672243
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1033897240
Short name T397
Test name
Test status
Simulation time 45125109 ps
CPU time 1.01 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201100 kb
Host smart-00fe0e28-f6eb-4d8c-8a67-b1520c45ddc4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033897240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1033897240
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3851036193
Short name T714
Test name
Test status
Simulation time 16807598 ps
CPU time 0.76 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201224 kb
Host smart-036e768c-b3b8-49ce-9b6e-40ef9ac2c92e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851036193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3851036193
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.3318787685
Short name T403
Test name
Test status
Simulation time 591289194 ps
CPU time 2.81 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:16 PM PDT 24
Peak memory 201444 kb
Host smart-8b33e119-2017-42c1-97e8-8cda10371c1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318787685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.3318787685
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.1752521220
Short name T422
Test name
Test status
Simulation time 18414411 ps
CPU time 0.82 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 200972 kb
Host smart-2f8fedf1-d79f-4c9e-b083-3c74fe4b0011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752521220 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.1752521220
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.941005121
Short name T96
Test name
Test status
Simulation time 2431726133 ps
CPU time 12.72 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:24 PM PDT 24
Peak memory 201360 kb
Host smart-66f48f46-c812-4e06-866e-e1d77e6e9877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941005121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.941005121
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.340505578
Short name T430
Test name
Test status
Simulation time 136337183 ps
CPU time 1.31 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 201060 kb
Host smart-57473fba-0445-4f6d-bedc-7b0a2a0416f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340505578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.340505578
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.1265375629
Short name T652
Test name
Test status
Simulation time 58898209 ps
CPU time 0.89 seconds
Started Aug 03 05:08:18 PM PDT 24
Finished Aug 03 05:08:19 PM PDT 24
Peak memory 200396 kb
Host smart-2425559b-0026-4a95-8e5b-b8aa8373189a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265375629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.1265375629
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1423933732
Short name T269
Test name
Test status
Simulation time 14211884 ps
CPU time 0.73 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201072 kb
Host smart-33cdb5ce-4154-45e2-a1d9-7b8505430f76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423933732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.1423933732
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.290072609
Short name T258
Test name
Test status
Simulation time 41342723 ps
CPU time 0.76 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 200268 kb
Host smart-aa0785a0-6088-460a-a0c2-cc2954e231bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290072609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.290072609
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3996564673
Short name T445
Test name
Test status
Simulation time 31861322 ps
CPU time 0.82 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201012 kb
Host smart-b8717054-6f50-412d-adbe-76091ca06767
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996564673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3996564673
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.225381228
Short name T420
Test name
Test status
Simulation time 22202078 ps
CPU time 0.81 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:08:18 PM PDT 24
Peak memory 201056 kb
Host smart-64a75760-fdaa-45de-9582-63a04803c583
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225381228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.225381228
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.806640187
Short name T739
Test name
Test status
Simulation time 2003501794 ps
CPU time 13.57 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:26 PM PDT 24
Peak memory 201312 kb
Host smart-d816fa50-51d9-40cc-962c-6187f53b6b5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806640187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.806640187
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.4163719017
Short name T460
Test name
Test status
Simulation time 1821666968 ps
CPU time 9.32 seconds
Started Aug 03 05:08:10 PM PDT 24
Finished Aug 03 05:08:20 PM PDT 24
Peak memory 201176 kb
Host smart-26e7efe6-cd0d-45d4-87c1-052aa85cc26f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163719017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.4163719017
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2419354903
Short name T262
Test name
Test status
Simulation time 35603099 ps
CPU time 1.05 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 200976 kb
Host smart-62adadfd-3213-42eb-89cc-6c9d8098b14b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419354903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.2419354903
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.848031102
Short name T617
Test name
Test status
Simulation time 120476591 ps
CPU time 1.16 seconds
Started Aug 03 05:08:15 PM PDT 24
Finished Aug 03 05:08:17 PM PDT 24
Peak memory 201092 kb
Host smart-67039edc-3ba5-47b2-81f0-d267dc59c3ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848031102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_clk_byp_req_intersig_mubi.848031102
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3423892914
Short name T546
Test name
Test status
Simulation time 41423045 ps
CPU time 0.9 seconds
Started Aug 03 05:08:11 PM PDT 24
Finished Aug 03 05:08:12 PM PDT 24
Peak memory 201020 kb
Host smart-668ab106-7abe-4935-92c3-a527d809d563
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423892914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.3423892914
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.3879375276
Short name T411
Test name
Test status
Simulation time 59042134 ps
CPU time 0.79 seconds
Started Aug 03 05:08:13 PM PDT 24
Finished Aug 03 05:08:14 PM PDT 24
Peak memory 201044 kb
Host smart-5623bc94-b806-43bc-bcab-7e9c43ad9382
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879375276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3879375276
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.242131704
Short name T83
Test name
Test status
Simulation time 1261790375 ps
CPU time 4.49 seconds
Started Aug 03 05:08:10 PM PDT 24
Finished Aug 03 05:08:15 PM PDT 24
Peak memory 201288 kb
Host smart-ecef0b65-1ae7-4019-b3ac-0c8c30883ba8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242131704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.242131704
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.2864358908
Short name T156
Test name
Test status
Simulation time 76419703 ps
CPU time 1 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201060 kb
Host smart-04743f4d-db0f-4f84-b578-6e62f0ba89bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864358908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2864358908
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1062701144
Short name T798
Test name
Test status
Simulation time 6422970690 ps
CPU time 32.97 seconds
Started Aug 03 05:08:19 PM PDT 24
Finished Aug 03 05:08:52 PM PDT 24
Peak memory 201428 kb
Host smart-c80ef2e8-f544-448d-905a-55f9c690698b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062701144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1062701144
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.3565292864
Short name T619
Test name
Test status
Simulation time 126647753681 ps
CPU time 796.32 seconds
Started Aug 03 05:08:17 PM PDT 24
Finished Aug 03 05:21:34 PM PDT 24
Peak memory 213536 kb
Host smart-410fd2b8-ed43-451f-a843-403142cda80c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3565292864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3565292864
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.843505942
Short name T684
Test name
Test status
Simulation time 79173422 ps
CPU time 1.12 seconds
Started Aug 03 05:08:12 PM PDT 24
Finished Aug 03 05:08:13 PM PDT 24
Peak memory 201000 kb
Host smart-aa6c559d-2531-4d49-aed2-cc2618c38db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843505942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.843505942
Directory /workspace/9.clkmgr_trans/latest
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