Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152171254

1

T8

3644

T9

2070

T6

38612

auto[1]

248726

1

T8

1230

T26

344

T35

56

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152138196

1

T8

4000

T9

2070

T6

38612

auto[1]

281784

1

T8

874

T26

224

T35

320

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

152104912

1

T8

3798

T9

2070

T6

38612

auto[1]

315068

1

T8

1076

T26

330

T35

338

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141894030

1

T8

4874

T9

2070

T6

38612

auto[1]

10525950

1

T26

1932

T35

3484

T64

2282

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91629656

1

T8

4638

T9

34

T6

38590

auto[1]

60790324

1

T8

236

T9

2036

T6

22

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

82465360

1

T8

3336

T9

34

T6

38590

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

59178376

1

T8

98

T9

2036

T6

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20392

1

T8

118

T26

6

T64

44

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

4150

1

T8

46

T20

4

T2

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

8769390

1

T26

1578

T35

3054

T64

1558

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

1544574

1

T26

80

T35

100

T64

182

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

28180

1

T26

84

T35

6

T64

108

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7254

1

T64

16

T20

100

T2

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50238

1

T8

20

T18

12

T19

18

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1096

1

T3

58

T119

20

T12

30

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

9306

1

T8

180

T18

164

T2

116

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1834

1

T119

42

T12

66

T174

46

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7402

1

T35

46

T64

48

T20

34

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1874

1

T2

16

T3

14

T73

12

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12166

1

T64

94

T3

100

T108

82

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3320

1

T2

62

T3

144

T14

334

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

31900

1

T8

66

T26

2

T20

20

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2328

1

T8

8

T18

30

T20

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

20628

1

T8

244

T26

38

T20

52

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4596

1

T8

84

T18

42

T20

70

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

18134

1

T26

10

T35

38

T64

16

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4736

1

T26

8

T35

26

T64

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

30882

1

T26

48

T64

72

T18

84

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7316

1

T64

62

T18

64

T2

54

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59218

1

T8

116

T26

16

T35

60

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3956

1

T26

22

T19

44

T2

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

32806

1

T8

558

T64

242

T2

146

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7846

1

T26

62

T2

60

T3

94

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

26842

1

T26

18

T35

164

T64

14

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5830

1

T64

32

T2

98

T3

54

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

46812

1

T26

106

T35

50

T64

74

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11238

1

T2

318

T3

146

T108

102