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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.47 99.11 95.68 100.00 100.00 98.71 97.02 98.80


Total test records in report: 978
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T800 /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2023367375 Aug 04 05:19:08 PM PDT 24 Aug 04 05:19:09 PM PDT 24 18754884 ps
T801 /workspace/coverage/default/41.clkmgr_stress_all.3457449587 Aug 04 05:19:06 PM PDT 24 Aug 04 05:20:01 PM PDT 24 7215005089 ps
T802 /workspace/coverage/default/29.clkmgr_frequency.4145015397 Aug 04 05:18:45 PM PDT 24 Aug 04 05:18:50 PM PDT 24 1030064432 ps
T803 /workspace/coverage/default/13.clkmgr_stress_all.874513791 Aug 04 05:18:08 PM PDT 24 Aug 04 05:18:57 PM PDT 24 7055915215 ps
T804 /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1993352736 Aug 04 05:18:04 PM PDT 24 Aug 04 05:18:05 PM PDT 24 47555363 ps
T805 /workspace/coverage/default/26.clkmgr_stress_all.4096989431 Aug 04 05:18:47 PM PDT 24 Aug 04 05:19:17 PM PDT 24 3703274673 ps
T806 /workspace/coverage/default/3.clkmgr_stress_all.3162035686 Aug 04 05:17:59 PM PDT 24 Aug 04 05:18:11 PM PDT 24 2406943866 ps
T807 /workspace/coverage/default/7.clkmgr_clk_status.2383465597 Aug 04 05:18:08 PM PDT 24 Aug 04 05:18:09 PM PDT 24 14259038 ps
T808 /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1990610703 Aug 04 05:18:16 PM PDT 24 Aug 04 05:18:16 PM PDT 24 18718671 ps
T809 /workspace/coverage/default/31.clkmgr_stress_all.421638874 Aug 04 05:18:59 PM PDT 24 Aug 04 05:19:16 PM PDT 24 4792414233 ps
T810 /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2227187086 Aug 04 05:18:51 PM PDT 24 Aug 04 05:18:52 PM PDT 24 23128490 ps
T811 /workspace/coverage/default/43.clkmgr_peri.513137462 Aug 04 05:19:09 PM PDT 24 Aug 04 05:19:10 PM PDT 24 18363910 ps
T812 /workspace/coverage/default/49.clkmgr_stress_all.3820738376 Aug 04 05:19:06 PM PDT 24 Aug 04 05:20:12 PM PDT 24 8953984436 ps
T813 /workspace/coverage/default/8.clkmgr_alert_test.787762157 Aug 04 05:18:06 PM PDT 24 Aug 04 05:18:07 PM PDT 24 28349084 ps
T814 /workspace/coverage/default/41.clkmgr_clk_status.3436552752 Aug 04 05:19:00 PM PDT 24 Aug 04 05:19:01 PM PDT 24 55697087 ps
T815 /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2647654807 Aug 04 05:18:13 PM PDT 24 Aug 04 05:18:15 PM PDT 24 93089344 ps
T816 /workspace/coverage/default/4.clkmgr_frequency_timeout.2316653934 Aug 04 05:17:55 PM PDT 24 Aug 04 05:17:59 PM PDT 24 753665940 ps
T817 /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3526804846 Aug 04 05:18:59 PM PDT 24 Aug 04 05:19:00 PM PDT 24 50262090 ps
T818 /workspace/coverage/default/37.clkmgr_smoke.1562319658 Aug 04 05:19:01 PM PDT 24 Aug 04 05:19:02 PM PDT 24 18285590 ps
T819 /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2490984912 Aug 04 05:19:05 PM PDT 24 Aug 04 05:19:06 PM PDT 24 28030091 ps
T820 /workspace/coverage/default/37.clkmgr_regwen.1582757423 Aug 04 05:18:56 PM PDT 24 Aug 04 05:19:02 PM PDT 24 1572560415 ps
T821 /workspace/coverage/default/12.clkmgr_frequency.976807798 Aug 04 05:18:09 PM PDT 24 Aug 04 05:18:18 PM PDT 24 1041226979 ps
T822 /workspace/coverage/default/18.clkmgr_peri.1996311424 Aug 04 05:18:05 PM PDT 24 Aug 04 05:18:06 PM PDT 24 34868553 ps
T823 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3474608647 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:14 PM PDT 24 23159147 ps
T824 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.583395059 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 12934686 ps
T82 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2847671966 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 34685849 ps
T110 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.95278071 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:26 PM PDT 24 80705927 ps
T83 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2970752162 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:22 PM PDT 24 24596542 ps
T166 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.19509351 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 26793086 ps
T825 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4223708451 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:17 PM PDT 24 46717371 ps
T826 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3454781193 Aug 04 04:32:52 PM PDT 24 Aug 04 04:32:53 PM PDT 24 32112114 ps
T54 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3635290322 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:39 PM PDT 24 833814651 ps
T57 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2753737052 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:30 PM PDT 24 200204311 ps
T827 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4143209261 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:18 PM PDT 24 192679315 ps
T828 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3954506982 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 26182097 ps
T58 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3021495584 Aug 04 04:33:00 PM PDT 24 Aug 04 04:33:02 PM PDT 24 128225650 ps
T55 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1272200291 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:21 PM PDT 24 313918852 ps
T829 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2390084425 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:36 PM PDT 24 33949384 ps
T84 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3680668007 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 157616950 ps
T830 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3901407578 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:17 PM PDT 24 132780576 ps
T56 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3305134628 Aug 04 04:32:44 PM PDT 24 Aug 04 04:32:46 PM PDT 24 113865335 ps
T85 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3030105022 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:32 PM PDT 24 16319688 ps
T86 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1823174918 Aug 04 04:32:37 PM PDT 24 Aug 04 04:32:38 PM PDT 24 30668525 ps
T59 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2725007118 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:22 PM PDT 24 437518296 ps
T102 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2629111870 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:26 PM PDT 24 188854843 ps
T831 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3562162995 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:16 PM PDT 24 12898785 ps
T63 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2037054805 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:23 PM PDT 24 517451441 ps
T87 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1794567768 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 34065648 ps
T103 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3605969489 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:50 PM PDT 24 470147800 ps
T60 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3942767612 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:33 PM PDT 24 148834084 ps
T832 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2539600140 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:13 PM PDT 24 49754829 ps
T61 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2697017591 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:11 PM PDT 24 384416347 ps
T833 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2039405937 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:22 PM PDT 24 184036487 ps
T834 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2315888379 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 12184815 ps
T835 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.644979900 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 45227329 ps
T62 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2785024908 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 74184435 ps
T126 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.384635703 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:17 PM PDT 24 212934910 ps
T836 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.111634085 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 43151628 ps
T837 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2955312692 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:39 PM PDT 24 40497541 ps
T138 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.906702190 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:47 PM PDT 24 129038368 ps
T137 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2881939805 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:16 PM PDT 24 138908392 ps
T838 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3042884422 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:23 PM PDT 24 113489950 ps
T127 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.204747696 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:20 PM PDT 24 302788937 ps
T839 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2236381197 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 22731386 ps
T840 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4137086515 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:22 PM PDT 24 47744068 ps
T841 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1131252278 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 14713742 ps
T842 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.4236173157 Aug 04 04:32:50 PM PDT 24 Aug 04 04:32:51 PM PDT 24 21820782 ps
T843 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3540959048 Aug 04 04:32:33 PM PDT 24 Aug 04 04:32:34 PM PDT 24 62713262 ps
T844 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1840967521 Aug 04 04:32:27 PM PDT 24 Aug 04 04:32:27 PM PDT 24 21526805 ps
T845 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2784008188 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:21 PM PDT 24 219135253 ps
T846 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2007516585 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:19 PM PDT 24 47316859 ps
T104 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1633050541 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:10 PM PDT 24 129347622 ps
T139 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2202000680 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:15 PM PDT 24 82195386 ps
T847 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.121382506 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 34479644 ps
T848 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.740651456 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:20 PM PDT 24 502527318 ps
T849 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2166049079 Aug 04 04:32:33 PM PDT 24 Aug 04 04:32:34 PM PDT 24 97643326 ps
T850 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.4272931992 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 14432984 ps
T851 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1016067487 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 10868184 ps
T852 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3968646752 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:52 PM PDT 24 21596936 ps
T135 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.556438724 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:11 PM PDT 24 152032443 ps
T128 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.392886764 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:13 PM PDT 24 162476998 ps
T853 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2052498541 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:22 PM PDT 24 46412293 ps
T854 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1679501684 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:10 PM PDT 24 37595990 ps
T855 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3062408540 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 13593142 ps
T856 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1837268850 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 14117098 ps
T857 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1399623389 Aug 04 04:33:01 PM PDT 24 Aug 04 04:33:02 PM PDT 24 118392135 ps
T858 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3655701809 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:23 PM PDT 24 137042299 ps
T131 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.390744520 Aug 04 04:33:00 PM PDT 24 Aug 04 04:33:04 PM PDT 24 516600756 ps
T859 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.305937264 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:15 PM PDT 24 1402390629 ps
T860 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3924978954 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:10 PM PDT 24 136223921 ps
T861 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3094165534 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:24 PM PDT 24 96410577 ps
T862 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.204399403 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:12 PM PDT 24 208373188 ps
T863 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2227247942 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:14 PM PDT 24 32205782 ps
T864 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3363064679 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:24 PM PDT 24 129391788 ps
T129 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1974796255 Aug 04 04:32:33 PM PDT 24 Aug 04 04:32:36 PM PDT 24 112505608 ps
T172 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2393644717 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:24 PM PDT 24 132640780 ps
T865 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3372382848 Aug 04 04:32:07 PM PDT 24 Aug 04 04:32:09 PM PDT 24 57046789 ps
T866 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3568297559 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:18 PM PDT 24 39616817 ps
T867 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1413814777 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:22 PM PDT 24 93501567 ps
T868 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2516466185 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:22 PM PDT 24 1395746797 ps
T869 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1578149060 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:30 PM PDT 24 12850496 ps
T870 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.545754406 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:32 PM PDT 24 33973601 ps
T871 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1761537397 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 43731847 ps
T872 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2492163829 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:14 PM PDT 24 96811981 ps
T873 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1343729256 Aug 04 04:32:08 PM PDT 24 Aug 04 04:32:09 PM PDT 24 43967756 ps
T874 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3484994155 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 48668736 ps
T875 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2208053199 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:38 PM PDT 24 44170614 ps
T130 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.745154398 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:24 PM PDT 24 158646562 ps
T876 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.826567481 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:21 PM PDT 24 94400445 ps
T877 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.357606897 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:24 PM PDT 24 26519617 ps
T105 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3143639612 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:12 PM PDT 24 192399683 ps
T878 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2685092668 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:23 PM PDT 24 33064655 ps
T879 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4171115313 Aug 04 04:32:36 PM PDT 24 Aug 04 04:32:37 PM PDT 24 12542089 ps
T880 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2676582951 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:16 PM PDT 24 44104333 ps
T881 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1489560992 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:39 PM PDT 24 35252684 ps
T882 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.208597866 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:20 PM PDT 24 34521105 ps
T111 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2458870493 Aug 04 04:32:38 PM PDT 24 Aug 04 04:32:43 PM PDT 24 684986067 ps
T883 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4276760280 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 19281651 ps
T112 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3251674882 Aug 04 04:32:48 PM PDT 24 Aug 04 04:32:50 PM PDT 24 181640363 ps
T115 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3642711289 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:25 PM PDT 24 771479864 ps
T884 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1166149841 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:29 PM PDT 24 337301110 ps
T885 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.819337011 Aug 04 04:32:37 PM PDT 24 Aug 04 04:32:38 PM PDT 24 56714274 ps
T886 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3148089424 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:22 PM PDT 24 134094409 ps
T887 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.487637770 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 20810470 ps
T888 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3508238877 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 37004856 ps
T889 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4088274288 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:23 PM PDT 24 78314643 ps
T890 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3302545588 Aug 04 04:33:06 PM PDT 24 Aug 04 04:33:07 PM PDT 24 52955134 ps
T113 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3808753937 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:18 PM PDT 24 415971376 ps
T891 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.488034070 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:13 PM PDT 24 32548394 ps
T892 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.167247622 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 73163416 ps
T893 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.379129735 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:21 PM PDT 24 283740498 ps
T894 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.624570120 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:12 PM PDT 24 19566573 ps
T895 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1315846512 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:24 PM PDT 24 34656806 ps
T896 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1429758104 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:14 PM PDT 24 132770047 ps
T133 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3853455242 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:16 PM PDT 24 200632899 ps
T897 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3325521689 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 87744072 ps
T898 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3219512213 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:12 PM PDT 24 86874721 ps
T899 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3823550854 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:35 PM PDT 24 24068732 ps
T900 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.58872034 Aug 04 04:32:59 PM PDT 24 Aug 04 04:33:00 PM PDT 24 12259762 ps
T901 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2096440382 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:21 PM PDT 24 34720742 ps
T902 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2727528122 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:39 PM PDT 24 37415052 ps
T132 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2120851675 Aug 04 04:32:37 PM PDT 24 Aug 04 04:32:38 PM PDT 24 153962105 ps
T903 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2354669497 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:34 PM PDT 24 18272973 ps
T904 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1577318330 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:23 PM PDT 24 102981586 ps
T905 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1073560922 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:33 PM PDT 24 531326118 ps
T906 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1729461586 Aug 04 04:32:27 PM PDT 24 Aug 04 04:32:28 PM PDT 24 64322132 ps
T136 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.679816587 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:11 PM PDT 24 109503882 ps
T907 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.462823506 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 43554013 ps
T117 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.918215084 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:22 PM PDT 24 69492748 ps
T908 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1000983934 Aug 04 04:32:45 PM PDT 24 Aug 04 04:32:46 PM PDT 24 56831492 ps
T909 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1865724631 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:17 PM PDT 24 45034844 ps
T114 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3625444182 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:26 PM PDT 24 74994830 ps
T910 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.73009623 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:20 PM PDT 24 211719382 ps
T911 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1260124351 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 21254817 ps
T912 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2477157870 Aug 04 04:32:09 PM PDT 24 Aug 04 04:32:10 PM PDT 24 20041684 ps
T913 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1083815719 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:26 PM PDT 24 23569643 ps
T914 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3603029752 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:19 PM PDT 24 47425162 ps
T141 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1040983764 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 154118583 ps
T915 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.96161818 Aug 04 04:32:26 PM PDT 24 Aug 04 04:32:27 PM PDT 24 31661597 ps
T916 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1947728408 Aug 04 04:32:42 PM PDT 24 Aug 04 04:32:44 PM PDT 24 34535449 ps
T917 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2851600691 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:14 PM PDT 24 14748637 ps
T918 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3313241213 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 14953820 ps
T919 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1005215395 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 12268515 ps
T106 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.881575893 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:21 PM PDT 24 231547343 ps
T920 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4139230527 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:26 PM PDT 24 286694230 ps
T921 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4102004005 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:14 PM PDT 24 19888419 ps
T140 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1464901598 Aug 04 04:32:03 PM PDT 24 Aug 04 04:32:05 PM PDT 24 128503847 ps
T922 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4017786285 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 66738954 ps
T923 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3423374364 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 30623474 ps
T924 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2456386068 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:12 PM PDT 24 24088654 ps
T925 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2887280812 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:20 PM PDT 24 125949527 ps
T926 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.154585935 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:25 PM PDT 24 441826315 ps
T927 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1341005911 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:27 PM PDT 24 32216321 ps
T928 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4077802107 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:21 PM PDT 24 208384349 ps
T929 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3901478535 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 16169227 ps
T930 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1876301913 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:47 PM PDT 24 11570271 ps
T931 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2005417463 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:19 PM PDT 24 650507447 ps
T932 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.513081925 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:29 PM PDT 24 78150688 ps
T933 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.349366134 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:18 PM PDT 24 102669057 ps
T934 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3941659086 Aug 04 04:32:34 PM PDT 24 Aug 04 04:32:35 PM PDT 24 11515546 ps
T935 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.850442696 Aug 04 04:32:43 PM PDT 24 Aug 04 04:32:44 PM PDT 24 10851009 ps
T936 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4006908308 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:23 PM PDT 24 182439736 ps
T937 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2501439772 Aug 04 04:33:02 PM PDT 24 Aug 04 04:33:03 PM PDT 24 87810149 ps
T938 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.133234526 Aug 04 04:32:15 PM PDT 24 Aug 04 04:32:17 PM PDT 24 101735106 ps
T939 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1166052596 Aug 04 04:32:27 PM PDT 24 Aug 04 04:32:28 PM PDT 24 51650767 ps
T940 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3158487395 Aug 04 04:32:57 PM PDT 24 Aug 04 04:32:57 PM PDT 24 30239704 ps
T173 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1661426395 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:31 PM PDT 24 64151189 ps
T941 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2546530825 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:25 PM PDT 24 12429396 ps
T134 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.4170104356 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:34 PM PDT 24 1063659249 ps
T942 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2750223441 Aug 04 04:32:13 PM PDT 24 Aug 04 04:32:14 PM PDT 24 96902950 ps
T943 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3321820849 Aug 04 04:32:35 PM PDT 24 Aug 04 04:32:36 PM PDT 24 74917046 ps
T944 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1526251136 Aug 04 04:32:46 PM PDT 24 Aug 04 04:32:47 PM PDT 24 44952273 ps
T945 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.303768195 Aug 04 04:32:21 PM PDT 24 Aug 04 04:32:22 PM PDT 24 11955115 ps
T946 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1391027549 Aug 04 04:32:17 PM PDT 24 Aug 04 04:32:18 PM PDT 24 36677866 ps
T947 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2263460775 Aug 04 04:32:51 PM PDT 24 Aug 04 04:32:52 PM PDT 24 29448874 ps
T948 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2172072430 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:24 PM PDT 24 12029159 ps
T949 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3434277567 Aug 04 04:32:10 PM PDT 24 Aug 04 04:32:11 PM PDT 24 31302316 ps
T950 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1845174138 Aug 04 04:32:12 PM PDT 24 Aug 04 04:32:13 PM PDT 24 150044573 ps
T951 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.593987911 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:24 PM PDT 24 2647341495 ps
T952 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3558584577 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:26 PM PDT 24 99315641 ps
T953 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.557294167 Aug 04 04:32:11 PM PDT 24 Aug 04 04:32:13 PM PDT 24 62634626 ps
T116 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1892234406 Aug 04 04:32:18 PM PDT 24 Aug 04 04:32:23 PM PDT 24 583403725 ps
T954 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1234164836 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:21 PM PDT 24 31150984 ps
T955 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.548185992 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:38 PM PDT 24 385640255 ps
T956 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.362805343 Aug 04 04:32:40 PM PDT 24 Aug 04 04:32:41 PM PDT 24 27445081 ps
T957 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.56370080 Aug 04 04:32:25 PM PDT 24 Aug 04 04:32:25 PM PDT 24 13266293 ps
T107 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4229652091 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:22 PM PDT 24 61532906 ps
T958 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3289899590 Aug 04 04:32:31 PM PDT 24 Aug 04 04:32:33 PM PDT 24 81669885 ps
T959 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.840894822 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 77880116 ps
T960 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.516710330 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:26 PM PDT 24 40829868 ps
T961 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1913945254 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:22 PM PDT 24 65581846 ps
T962 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.611644267 Aug 04 04:32:16 PM PDT 24 Aug 04 04:32:18 PM PDT 24 344454923 ps
T963 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1042792032 Aug 04 04:32:47 PM PDT 24 Aug 04 04:32:50 PM PDT 24 294617780 ps
T964 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.162742218 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:30 PM PDT 24 116429273 ps
T965 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2832585827 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:32 PM PDT 24 406828008 ps
T966 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3108511154 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:16 PM PDT 24 115681798 ps
T967 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1289901937 Aug 04 04:32:19 PM PDT 24 Aug 04 04:32:20 PM PDT 24 45013544 ps
T968 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3257131133 Aug 04 04:32:14 PM PDT 24 Aug 04 04:32:16 PM PDT 24 123601490 ps
T969 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.31647618 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 22287696 ps
T970 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2616555116 Aug 04 04:32:22 PM PDT 24 Aug 04 04:32:26 PM PDT 24 51287083 ps
T971 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.23242018 Aug 04 04:32:30 PM PDT 24 Aug 04 04:32:31 PM PDT 24 107502753 ps
T972 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.932103299 Aug 04 04:32:20 PM PDT 24 Aug 04 04:32:26 PM PDT 24 27756652 ps
T973 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2658843901 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:29 PM PDT 24 90373621 ps
T974 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3624737979 Aug 04 04:32:24 PM PDT 24 Aug 04 04:32:25 PM PDT 24 38390704 ps
T975 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.107154386 Aug 04 04:32:41 PM PDT 24 Aug 04 04:32:42 PM PDT 24 15597678 ps
T976 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1895094252 Aug 04 04:32:02 PM PDT 24 Aug 04 04:32:05 PM PDT 24 139974172 ps
T977 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3388541978 Aug 04 04:32:28 PM PDT 24 Aug 04 04:32:31 PM PDT 24 233189063 ps
T978 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1326494747 Aug 04 04:32:23 PM PDT 24 Aug 04 04:32:24 PM PDT 24 17626099 ps

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3140386273
Short name T27
Test name
Test status
Simulation time 2302209974 ps
CPU time 16.05 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 201364 kb
Host smart-0dede9d8-c533-437c-9fde-649f342f91bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140386273 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3140386273
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2300541060
Short name T2
Test name
Test status
Simulation time 4865000355 ps
CPU time 20.13 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:27 PM PDT 24
Peak memory 201348 kb
Host smart-32681cee-b807-42c4-85f0-750ba40e5eec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300541060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2300541060
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.673503383
Short name T29
Test name
Test status
Simulation time 150955724 ps
CPU time 1.18 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201076 kb
Host smart-38c1d9c5-6fe9-4501-9528-91d36c49fe63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673503383 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.673503383
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.3842516964
Short name T14
Test name
Test status
Simulation time 143359555892 ps
CPU time 978.91 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:35:21 PM PDT 24
Peak memory 209728 kb
Host smart-3631bf69-d934-46c9-952c-f918199e0127
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3842516964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.3842516964
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.2725007118
Short name T59
Test name
Test status
Simulation time 437518296 ps
CPU time 3.35 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 208880 kb
Host smart-35a43427-dd45-4346-a5dc-17e6fcc8063d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725007118 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.2725007118
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1150256606
Short name T36
Test name
Test status
Simulation time 819729511 ps
CPU time 3.2 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 201272 kb
Host smart-721b7931-58dd-46c9-8b49-5fcb8dd13867
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150256606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1150256606
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.530097746
Short name T42
Test name
Test status
Simulation time 146043459 ps
CPU time 1.96 seconds
Started Aug 04 05:17:29 PM PDT 24
Finished Aug 04 05:17:31 PM PDT 24
Peak memory 220448 kb
Host smart-17eadb1b-1113-4445-b7e7-a84c0d5de1ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530097746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.530097746
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.896813310
Short name T17
Test name
Test status
Simulation time 67827436 ps
CPU time 0.83 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 200276 kb
Host smart-e6c643c8-3638-4732-b7da-609fab9e3919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896813310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.896813310
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.44019830
Short name T122
Test name
Test status
Simulation time 26662523 ps
CPU time 0.89 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:18:48 PM PDT 24
Peak memory 201100 kb
Host smart-199801b6-efe1-45c7-827a-9ecfa71ba4bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44019830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.clkmgr_idle_intersig_mubi.44019830
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3251674882
Short name T112
Test name
Test status
Simulation time 181640363 ps
CPU time 1.99 seconds
Started Aug 04 04:32:48 PM PDT 24
Finished Aug 04 04:32:50 PM PDT 24
Peak memory 200412 kb
Host smart-51b99e7a-958c-49b2-ad9f-e13e6519cd8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251674882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3251674882
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.1974796255
Short name T129
Test name
Test status
Simulation time 112505608 ps
CPU time 2.1 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 200632 kb
Host smart-ac155a73-29b9-4d08-baa7-ec1c2dce1e8c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974796255 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.1974796255
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all_with_rand_reset.1922587637
Short name T12
Test name
Test status
Simulation time 56179151159 ps
CPU time 524.29 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:27:50 PM PDT 24
Peak memory 209768 kb
Host smart-c1152cb7-7091-4afe-af38-8d67aa1e41f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1922587637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.1922587637
Directory /workspace/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.476895678
Short name T18
Test name
Test status
Simulation time 1297764387 ps
CPU time 7.26 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201232 kb
Host smart-fb610953-8829-4364-b7aa-d26a9f6ca524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476895678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.476895678
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.2432615931
Short name T67
Test name
Test status
Simulation time 19095916228 ps
CPU time 311.77 seconds
Started Aug 04 05:18:42 PM PDT 24
Finished Aug 04 05:23:53 PM PDT 24
Peak memory 217964 kb
Host smart-4eb1bcde-a13f-4aaf-af2c-bd7cb7eba1f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2432615931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2432615931
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.544974891
Short name T204
Test name
Test status
Simulation time 16433034 ps
CPU time 0.8 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201096 kb
Host smart-bb494de5-83dc-42f2-8db4-558af584f6b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544974891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkm
gr_alert_test.544974891
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.384635703
Short name T126
Test name
Test status
Simulation time 212934910 ps
CPU time 1.98 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:17 PM PDT 24
Peak memory 200728 kb
Host smart-fab317e4-884a-4ca0-85a2-7b3e90da0243
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384635703 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.clkmgr_shadow_reg_errors.384635703
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.4223708451
Short name T825
Test name
Test status
Simulation time 46717371 ps
CPU time 0.99 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:17 PM PDT 24
Peak memory 200336 kb
Host smart-2d55e056-5eb3-4c66-808f-1d2250d16d38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223708451 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.4223708451
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.1892234406
Short name T116
Test name
Test status
Simulation time 583403725 ps
CPU time 4.26 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 200376 kb
Host smart-91d3ba70-2c48-48ae-8bb4-6f1724035d4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892234406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.1892234406
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.679816587
Short name T136
Test name
Test status
Simulation time 109503882 ps
CPU time 2 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 216948 kb
Host smart-4b42138f-76b5-47ae-8c0c-884d43dd80e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679816587 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.clkmgr_shadow_reg_errors.679816587
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.1130688227
Short name T274
Test name
Test status
Simulation time 369852992 ps
CPU time 1.84 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:54 PM PDT 24
Peak memory 200996 kb
Host smart-c2d860cf-e444-4511-974f-b8fac335b8e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130688227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1130688227
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.390744520
Short name T131
Test name
Test status
Simulation time 516600756 ps
CPU time 3.67 seconds
Started Aug 04 04:33:00 PM PDT 24
Finished Aug 04 04:33:04 PM PDT 24
Peak memory 200904 kb
Host smart-822938de-eda3-491a-9d14-8a587b6babcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390744520 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.390744520
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2853397790
Short name T40
Test name
Test status
Simulation time 5422045589 ps
CPU time 41.13 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 201404 kb
Host smart-8d401d08-dd4a-4f51-8c80-be91e0cfee30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853397790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2853397790
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1895094252
Short name T976
Test name
Test status
Simulation time 139974172 ps
CPU time 2.87 seconds
Started Aug 04 04:32:02 PM PDT 24
Finished Aug 04 04:32:05 PM PDT 24
Peak memory 200400 kb
Host smart-72bc7057-2b4e-421a-8d5f-5d8e94254c84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895094252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1895094252
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3143639612
Short name T105
Test name
Test status
Simulation time 192399683 ps
CPU time 2.49 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 200364 kb
Host smart-0b18ff8f-e9ef-46c4-81f3-6472705bb8e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143639612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.3143639612
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.624570120
Short name T894
Test name
Test status
Simulation time 19566573 ps
CPU time 1.06 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 200220 kb
Host smart-e975c72d-f51c-4e23-a8bc-4c860f1675b3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624570120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_aliasing.624570120
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.593987911
Short name T951
Test name
Test status
Simulation time 2647341495 ps
CPU time 9.72 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200412 kb
Host smart-4844000e-3680-4759-afc9-0f0a9d18cb5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593987911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.593987911
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.3434277567
Short name T949
Test name
Test status
Simulation time 31302316 ps
CPU time 0.84 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 200256 kb
Host smart-cc597775-2447-4b17-879d-1b14ada56940
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434277567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.3434277567
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.2539600140
Short name T832
Test name
Test status
Simulation time 49754829 ps
CPU time 1.26 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 200248 kb
Host smart-b4dd30d7-aff0-4859-8abe-a6767888bc57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539600140 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.2539600140
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2887280812
Short name T925
Test name
Test status
Simulation time 125949527 ps
CPU time 1.08 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 200192 kb
Host smart-7eac3af7-99c8-4000-a6bd-5cc4be889e97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887280812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2887280812
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3562162995
Short name T831
Test name
Test status
Simulation time 12898785 ps
CPU time 0.67 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 198876 kb
Host smart-b568f25a-2661-4dda-aa78-2801e48b0504
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562162995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.3562162995
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.488034070
Short name T891
Test name
Test status
Simulation time 32548394 ps
CPU time 1.08 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 200232 kb
Host smart-31f1ee38-9a73-4375-bc4f-aa7261a6017f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488034070 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.clkmgr_same_csr_outstanding.488034070
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.1272200291
Short name T55
Test name
Test status
Simulation time 313918852 ps
CPU time 1.85 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200496 kb
Host smart-ee3fba6d-7fb9-4499-98f4-d53245d41f1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272200291 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.1272200291
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.3219512213
Short name T898
Test name
Test status
Simulation time 86874721 ps
CPU time 1.97 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 208848 kb
Host smart-0e60af29-937b-4096-998a-c76211909786
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219512213 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3219512213
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.305937264
Short name T859
Test name
Test status
Simulation time 1402390629 ps
CPU time 6.07 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:15 PM PDT 24
Peak memory 200392 kb
Host smart-bdd4be72-8791-4df3-bfab-ea9f9a174754
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305937264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkm
gr_tl_errors.305937264
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.208597866
Short name T882
Test name
Test status
Simulation time 34521105 ps
CPU time 1.17 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 200200 kb
Host smart-0e8f4232-de99-4ac0-bdb1-dea02d7d2771
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208597866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.208597866
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.2039405937
Short name T833
Test name
Test status
Simulation time 184036487 ps
CPU time 3.53 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200380 kb
Host smart-da646521-dff1-49d7-9521-04b28a766118
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039405937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.2039405937
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2477157870
Short name T912
Test name
Test status
Simulation time 20041684 ps
CPU time 0.79 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:10 PM PDT 24
Peak memory 200144 kb
Host smart-74d68089-ef98-4ae4-91a1-f40621ef9f9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477157870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2477157870
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1343729256
Short name T873
Test name
Test status
Simulation time 43967756 ps
CPU time 1.07 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:09 PM PDT 24
Peak memory 200248 kb
Host smart-89a9a298-e0b9-44fd-a47e-7d8ba32383fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343729256 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.1343729256
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.1761537397
Short name T871
Test name
Test status
Simulation time 43731847 ps
CPU time 0.79 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200088 kb
Host smart-2558669c-13b3-4d2d-99fe-97c209c21648
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761537397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.1761537397
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.2851600691
Short name T917
Test name
Test status
Simulation time 14748637 ps
CPU time 0.63 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 198720 kb
Host smart-758e2621-9160-49cd-8559-8bc7d86f5c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851600691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.2851600691
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.3423374364
Short name T923
Test name
Test status
Simulation time 30623474 ps
CPU time 0.98 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 200132 kb
Host smart-d4d4fa56-def9-4cd3-8db7-0d300987b183
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423374364 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.3423374364
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1464901598
Short name T140
Test name
Test status
Simulation time 128503847 ps
CPU time 2.05 seconds
Started Aug 04 04:32:03 PM PDT 24
Finished Aug 04 04:32:05 PM PDT 24
Peak memory 217036 kb
Host smart-1fe09cff-c9d5-4676-a902-8a6b374c8116
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464901598 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.1464901598
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.2492163829
Short name T872
Test name
Test status
Simulation time 96811981 ps
CPU time 1.91 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 200736 kb
Host smart-91a6b4b4-a9a6-4fca-82cf-2adcdbcc048a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492163829 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.2492163829
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.3655701809
Short name T858
Test name
Test status
Simulation time 137042299 ps
CPU time 2.08 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 200764 kb
Host smart-191e003b-88de-499e-b4d4-7a8549cc7fe9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655701809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.3655701809
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1633050541
Short name T104
Test name
Test status
Simulation time 129347622 ps
CPU time 1.85 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:10 PM PDT 24
Peak memory 200368 kb
Host smart-323f2f2d-00ff-4763-aae0-86074ffab6da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633050541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.1633050541
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2052498541
Short name T853
Test name
Test status
Simulation time 46412293 ps
CPU time 1.29 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200232 kb
Host smart-e9d03b84-2dde-4e05-9591-6702ff4248e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052498541 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2052498541
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1326494747
Short name T978
Test name
Test status
Simulation time 17626099 ps
CPU time 0.82 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200188 kb
Host smart-9a227435-9ffd-4212-ba94-b941447ce2c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326494747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.1326494747
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1131252278
Short name T841
Test name
Test status
Simulation time 14713742 ps
CPU time 0.67 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198900 kb
Host smart-56367aec-e848-4062-8aaa-7adb277115a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131252278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1131252278
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3325521689
Short name T897
Test name
Test status
Simulation time 87744072 ps
CPU time 1.41 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200376 kb
Host smart-aa0b4c68-f2c7-41f1-b6d3-7da916b2c6a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325521689 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.3325521689
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.3305134628
Short name T56
Test name
Test status
Simulation time 113865335 ps
CPU time 1.69 seconds
Started Aug 04 04:32:44 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 200704 kb
Host smart-3214d81c-9c86-44b9-bb3d-c4e00f4bac0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305134628 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.3305134628
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2750223441
Short name T942
Test name
Test status
Simulation time 96902950 ps
CPU time 1.6 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 217040 kb
Host smart-789fd51e-66c3-4e3f-91ae-ea61091dc840
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750223441 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2750223441
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.545754406
Short name T870
Test name
Test status
Simulation time 33973601 ps
CPU time 1.92 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 200408 kb
Host smart-4e14cdf5-429b-4781-b598-4d650fa5fc43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545754406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_tl_errors.545754406
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1166149841
Short name T884
Test name
Test status
Simulation time 337301110 ps
CPU time 3.21 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 200444 kb
Host smart-c4ccb7e1-db9e-4c62-8e90-bdfb5953f2e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166149841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1166149841
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.362805343
Short name T956
Test name
Test status
Simulation time 27445081 ps
CPU time 0.84 seconds
Started Aug 04 04:32:40 PM PDT 24
Finished Aug 04 04:32:41 PM PDT 24
Peak memory 200248 kb
Host smart-86204c35-749a-450e-89cf-229bce1ef1ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362805343 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.362805343
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.96161818
Short name T915
Test name
Test status
Simulation time 31661597 ps
CPU time 0.9 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200180 kb
Host smart-12bb1265-d38c-4853-b809-a4050360a564
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96161818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.c
lkmgr_csr_rw.96161818
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.3042884422
Short name T838
Test name
Test status
Simulation time 113489950 ps
CPU time 0.88 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 198736 kb
Host smart-08118932-6821-4e62-b98b-4d22d84a1de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042884422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.3042884422
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.3302545588
Short name T890
Test name
Test status
Simulation time 52955134 ps
CPU time 1.44 seconds
Started Aug 04 04:33:06 PM PDT 24
Finished Aug 04 04:33:07 PM PDT 24
Peak memory 200356 kb
Host smart-58ad3a90-7a74-483c-ad7d-0ea094522713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302545588 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.3302545588
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2785024908
Short name T62
Test name
Test status
Simulation time 74184435 ps
CPU time 1.15 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 200416 kb
Host smart-0ced3e90-5381-428c-a78b-0eda6fd45bab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785024908 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 11.clkmgr_shadow_reg_errors.2785024908
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.349366134
Short name T933
Test name
Test status
Simulation time 102669057 ps
CPU time 1.69 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 216896 kb
Host smart-1f8d229a-7304-483b-b6f3-420535bda695
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349366134 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.349366134
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.1429758104
Short name T896
Test name
Test status
Simulation time 132770047 ps
CPU time 2.59 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 200368 kb
Host smart-4e473ca1-e7d2-431e-8d5e-301c0dc5216f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429758104 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.1429758104
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.3558584577
Short name T952
Test name
Test status
Simulation time 99315641 ps
CPU time 2.3 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200472 kb
Host smart-bb830182-db63-4cdd-8d52-896855af8a38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558584577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.3558584577
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1823174918
Short name T86
Test name
Test status
Simulation time 30668525 ps
CPU time 0.75 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 200136 kb
Host smart-94d44bcb-f655-4a2f-b7b9-9ad1c0b837f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823174918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.1823174918
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.3823550854
Short name T899
Test name
Test status
Simulation time 24068732 ps
CPU time 0.68 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 198836 kb
Host smart-7a55d645-7fa2-459e-89f8-cb60e0ae3611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823550854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.3823550854
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2658843901
Short name T973
Test name
Test status
Simulation time 90373621 ps
CPU time 1.07 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 200244 kb
Host smart-d13443b4-1db2-41a0-8222-37810af2cd06
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658843901 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.2658843901
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.3289899590
Short name T958
Test name
Test status
Simulation time 81669885 ps
CPU time 1.3 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 200480 kb
Host smart-78907bf5-b747-4b9f-afe6-a30cc1bef7bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289899590 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.3289899590
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3148089424
Short name T886
Test name
Test status
Simulation time 134094409 ps
CPU time 2.86 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200380 kb
Host smart-059a2fe0-8b2a-4a45-9209-c62651774d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148089424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3148089424
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.1042792032
Short name T963
Test name
Test status
Simulation time 294617780 ps
CPU time 2.89 seconds
Started Aug 04 04:32:47 PM PDT 24
Finished Aug 04 04:32:50 PM PDT 24
Peak memory 200420 kb
Host smart-80aa7340-8164-48d3-8672-2d8c77887d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042792032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.1042792032
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.1729461586
Short name T906
Test name
Test status
Simulation time 64322132 ps
CPU time 1.22 seconds
Started Aug 04 04:32:27 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 200216 kb
Host smart-c6df9e65-e9ca-41c0-9638-f301f1064724
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729461586 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.1729461586
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1260124351
Short name T911
Test name
Test status
Simulation time 21254817 ps
CPU time 0.82 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200212 kb
Host smart-98d98ad5-29f3-4763-84a1-61b4324839bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260124351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.1260124351
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.932103299
Short name T972
Test name
Test status
Simulation time 27756652 ps
CPU time 0.67 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198728 kb
Host smart-e077178e-020a-4a9d-a252-6a3620bec12c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932103299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_intr_test.932103299
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.819337011
Short name T885
Test name
Test status
Simulation time 56714274 ps
CPU time 1.26 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 200432 kb
Host smart-197f58c8-5892-4f60-9a0b-0def29bc96c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819337011 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 13.clkmgr_same_csr_outstanding.819337011
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.392886764
Short name T128
Test name
Test status
Simulation time 162476998 ps
CPU time 1.45 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 200520 kb
Host smart-aed6ba91-64db-45cd-8d18-4d1a75f26a1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392886764 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.clkmgr_shadow_reg_errors.392886764
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.1577318330
Short name T904
Test name
Test status
Simulation time 102981586 ps
CPU time 1.87 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 208884 kb
Host smart-6b2d9071-807f-4788-b6df-40e501321b88
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577318330 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.1577318330
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.4137086515
Short name T840
Test name
Test status
Simulation time 47744068 ps
CPU time 1.52 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200368 kb
Host smart-002719bd-67d4-4f69-9c46-b30cdd87410a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137086515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_tl_errors.4137086515
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.2393644717
Short name T172
Test name
Test status
Simulation time 132640780 ps
CPU time 1.56 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200376 kb
Host smart-a7f86c40-37bd-4fff-86fa-89dd5d1f8533
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393644717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.2393644717
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1526251136
Short name T944
Test name
Test status
Simulation time 44952273 ps
CPU time 1.32 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 200492 kb
Host smart-29da2675-ea32-4596-ba19-c29222dd1b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526251136 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1526251136
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.644979900
Short name T835
Test name
Test status
Simulation time 45227329 ps
CPU time 0.79 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 200200 kb
Host smart-1146f24c-b8dd-4b1f-9035-5564987e868d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644979900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
clkmgr_csr_rw.644979900
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.3474608647
Short name T823
Test name
Test status
Simulation time 23159147 ps
CPU time 0.69 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 198804 kb
Host smart-271ebded-2017-4e8e-b854-8810f2702631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474608647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.3474608647
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.2955312692
Short name T837
Test name
Test status
Simulation time 40497541 ps
CPU time 1.1 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 200236 kb
Host smart-ef39cbfe-1a58-4598-9652-0eb94e0c5896
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955312692 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.2955312692
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.1040983764
Short name T141
Test name
Test status
Simulation time 154118583 ps
CPU time 1.67 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 200472 kb
Host smart-d4ff4695-4bca-4074-834b-fffacb8b32c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040983764 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.1040983764
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.3388541978
Short name T977
Test name
Test status
Simulation time 233189063 ps
CPU time 2.87 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:31 PM PDT 24
Peak memory 216920 kb
Host smart-461ca620-edf9-44f3-a332-c919188a3f92
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388541978 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.3388541978
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.516710330
Short name T960
Test name
Test status
Simulation time 40829868 ps
CPU time 2.25 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200392 kb
Host smart-89ffbd0a-4a70-495e-8026-b162f1511ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516710330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clk
mgr_tl_errors.516710330
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.4102004005
Short name T921
Test name
Test status
Simulation time 19888419 ps
CPU time 0.88 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 200212 kb
Host smart-d1d5c0ad-23c0-404c-8d71-f31320b8145e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102004005 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.4102004005
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.2847671966
Short name T82
Test name
Test status
Simulation time 34685849 ps
CPU time 0.82 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 200264 kb
Host smart-dc1cd679-581f-4b72-b9ea-3110f222ee8a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847671966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.2847671966
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2390084425
Short name T829
Test name
Test status
Simulation time 33949384 ps
CPU time 0.7 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 198820 kb
Host smart-1f355089-4fea-4d01-84aa-69a30d0e10db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390084425 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2390084425
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.1315846512
Short name T895
Test name
Test status
Simulation time 34656806 ps
CPU time 1.24 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200392 kb
Host smart-54ba3516-eaa9-4855-a549-fd8be6832614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315846512 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.1315846512
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.4170104356
Short name T134
Test name
Test status
Simulation time 1063659249 ps
CPU time 4.21 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 216700 kb
Host smart-f1c38f13-4926-4418-9ffc-8a9c705b12f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170104356 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.4170104356
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3942767612
Short name T60
Test name
Test status
Simulation time 148834084 ps
CPU time 2.06 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 217024 kb
Host smart-c73e52b7-2177-4919-929b-40e13e11b727
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942767612 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3942767612
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1947728408
Short name T916
Test name
Test status
Simulation time 34535449 ps
CPU time 1.94 seconds
Started Aug 04 04:32:42 PM PDT 24
Finished Aug 04 04:32:44 PM PDT 24
Peak memory 200396 kb
Host smart-6f88304b-f466-465e-9e05-23c498d5679c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947728408 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.1947728408
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1913945254
Short name T961
Test name
Test status
Simulation time 65581846 ps
CPU time 1.63 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200368 kb
Host smart-f0dee1c3-cbcc-49d5-8e2d-4240140fd001
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913945254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.1913945254
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.19509351
Short name T166
Test name
Test status
Simulation time 26793086 ps
CPU time 0.93 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 200296 kb
Host smart-b892647f-cbd8-4588-87b9-44d4b082388c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509351 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.19509351
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.31647618
Short name T969
Test name
Test status
Simulation time 22287696 ps
CPU time 0.85 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 200220 kb
Host smart-bd0e397c-c647-4f46-b0cf-dd0236214d87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31647618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.c
lkmgr_csr_rw.31647618
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.56370080
Short name T957
Test name
Test status
Simulation time 13266293 ps
CPU time 0.64 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 198824 kb
Host smart-cec1392d-a6f9-4036-9563-6602f6bbfa24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56370080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkm
gr_intr_test.56370080
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.111634085
Short name T836
Test name
Test status
Simulation time 43151628 ps
CPU time 1.27 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200424 kb
Host smart-b5d66bc9-8958-402c-9d46-fb8194299fd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111634085 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 16.clkmgr_same_csr_outstanding.111634085
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2753737052
Short name T57
Test name
Test status
Simulation time 200204311 ps
CPU time 1.51 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 200504 kb
Host smart-a5eb81c1-5d36-46f0-8a30-0deecb3f9eb4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753737052 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.2753737052
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2208053199
Short name T875
Test name
Test status
Simulation time 44170614 ps
CPU time 1.43 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 200376 kb
Host smart-840b2d46-e641-4114-beef-be088e59eeb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208053199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2208053199
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1661426395
Short name T173
Test name
Test status
Simulation time 64151189 ps
CPU time 1.57 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:31 PM PDT 24
Peak memory 200456 kb
Host smart-16574abf-e703-4a22-8cee-1bd17a98cb87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661426395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.1661426395
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1341005911
Short name T927
Test name
Test status
Simulation time 32216321 ps
CPU time 1.09 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200296 kb
Host smart-e0dbd298-f186-4d30-b7a4-5bb5b4651a7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341005911 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.1341005911
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3030105022
Short name T85
Test name
Test status
Simulation time 16319688 ps
CPU time 0.82 seconds
Started Aug 04 04:32:31 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 200208 kb
Host smart-10c6e86e-26ef-4454-9540-8f229e867d6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030105022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.3030105022
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.2096440382
Short name T901
Test name
Test status
Simulation time 34720742 ps
CPU time 0.71 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 198820 kb
Host smart-1754074e-23ab-4544-a443-2addbab2c7c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096440382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.2096440382
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3968646752
Short name T852
Test name
Test status
Simulation time 21596936 ps
CPU time 0.91 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 200248 kb
Host smart-6cf58a3c-e617-4e21-8d47-db64526e3536
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968646752 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.3968646752
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.4006908308
Short name T936
Test name
Test status
Simulation time 182439736 ps
CPU time 1.85 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 208920 kb
Host smart-a8542eb1-26cb-4b31-8a56-a02b97c9e37e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006908308 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.4006908308
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4088274288
Short name T889
Test name
Test status
Simulation time 78314643 ps
CPU time 1.67 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 200864 kb
Host smart-49ccfb3c-1dca-4750-9a72-bdab8bf2a598
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088274288 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.4088274288
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2685092668
Short name T878
Test name
Test status
Simulation time 33064655 ps
CPU time 1.82 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 200360 kb
Host smart-5d80ad28-7c9c-42c3-a73a-180176f0bbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685092668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2685092668
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.3642711289
Short name T115
Test name
Test status
Simulation time 771479864 ps
CPU time 3.7 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 200412 kb
Host smart-e2730462-b163-4425-9d9a-1ebd111cd543
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642711289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.3642711289
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.167247622
Short name T892
Test name
Test status
Simulation time 73163416 ps
CPU time 1.18 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200232 kb
Host smart-5d6f8bc9-626f-4480-a6b2-2b2be191d438
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167247622 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.167247622
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1578149060
Short name T869
Test name
Test status
Simulation time 12850496 ps
CPU time 0.75 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 200176 kb
Host smart-926ea73b-c336-43a3-8c4d-aa32a2982e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578149060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.1578149060
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.3941659086
Short name T934
Test name
Test status
Simulation time 11515546 ps
CPU time 0.65 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 198860 kb
Host smart-16114b67-edb2-48d2-bf0d-a81beac0361b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941659086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.3941659086
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.3484994155
Short name T874
Test name
Test status
Simulation time 48668736 ps
CPU time 1.3 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200184 kb
Host smart-f8f8e751-6d58-4010-80f8-b892c5722ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484994155 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.3484994155
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.906702190
Short name T138
Test name
Test status
Simulation time 129038368 ps
CPU time 1.77 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 208892 kb
Host smart-ed86a4bd-0444-47c8-b539-cf36a0ac5c1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906702190 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.906702190
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.154585935
Short name T926
Test name
Test status
Simulation time 441826315 ps
CPU time 3.53 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 200380 kb
Host smart-70504183-3d34-469e-8522-6d861a8e4aac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154585935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clk
mgr_tl_errors.154585935
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.918215084
Short name T117
Test name
Test status
Simulation time 69492748 ps
CPU time 1.61 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200068 kb
Host smart-47b29304-c8ed-4e5e-9c63-49abfdbf3dc0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918215084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.clkmgr_tl_intg_err.918215084
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.3094165534
Short name T861
Test name
Test status
Simulation time 96410577 ps
CPU time 1.21 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200344 kb
Host smart-f80b44c8-3ebe-447b-b16b-35f7370198d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094165534 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.3094165534
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.357606897
Short name T877
Test name
Test status
Simulation time 26519617 ps
CPU time 0.82 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200212 kb
Host smart-44c49ca3-4749-4dff-95bb-5e920e5980b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357606897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.357606897
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.4272931992
Short name T850
Test name
Test status
Simulation time 14432984 ps
CPU time 0.67 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198816 kb
Host smart-02c0aac0-7e0b-445b-b444-642ab95a7cba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272931992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.4272931992
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.513081925
Short name T932
Test name
Test status
Simulation time 78150688 ps
CPU time 1.08 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:29 PM PDT 24
Peak memory 200176 kb
Host smart-5369d4dd-cbce-4803-ba3c-0acdf8608c49
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513081925 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 19.clkmgr_same_csr_outstanding.513081925
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3853455242
Short name T133
Test name
Test status
Simulation time 200632899 ps
CPU time 1.88 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 200624 kb
Host smart-31ed868f-8e2f-4ff2-8aba-1918e18f891b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853455242 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3853455242
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2037054805
Short name T63
Test name
Test status
Simulation time 517451441 ps
CPU time 3.77 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:23 PM PDT 24
Peak memory 208864 kb
Host smart-22fa6663-97c7-4a4c-88be-4a07ae1d3abe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037054805 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2037054805
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.2832585827
Short name T965
Test name
Test status
Simulation time 406828008 ps
CPU time 3.41 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:32 PM PDT 24
Peak memory 200388 kb
Host smart-8907c388-7b96-46b9-a224-aa0ed5691cab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832585827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.2832585827
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3605969489
Short name T103
Test name
Test status
Simulation time 470147800 ps
CPU time 3.55 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:50 PM PDT 24
Peak memory 200420 kb
Host smart-c81db8e7-6aab-47f7-9b0e-4d8374adaf18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605969489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.3605969489
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.3924978954
Short name T860
Test name
Test status
Simulation time 136223921 ps
CPU time 1.35 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:10 PM PDT 24
Peak memory 200232 kb
Host smart-e71e1214-268c-4947-858d-029f584faadc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924978954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.3924978954
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1073560922
Short name T905
Test name
Test status
Simulation time 531326118 ps
CPU time 8.04 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:33 PM PDT 24
Peak memory 200388 kb
Host smart-abd63485-9d8a-4b31-b8b0-8ff41df6728c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073560922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.1073560922
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2236381197
Short name T839
Test name
Test status
Simulation time 22731386 ps
CPU time 0.81 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 200208 kb
Host smart-ed87faed-ae60-4afa-b6ee-c713a2ff3773
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236381197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.2236381197
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3257131133
Short name T968
Test name
Test status
Simulation time 123601490 ps
CPU time 1.29 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 200312 kb
Host smart-67e29381-fe50-4085-917f-340fbf632a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257131133 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3257131133
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1000983934
Short name T908
Test name
Test status
Simulation time 56831492 ps
CPU time 0.88 seconds
Started Aug 04 04:32:45 PM PDT 24
Finished Aug 04 04:32:46 PM PDT 24
Peak memory 200228 kb
Host smart-fee24595-ab3b-4c75-aada-02190131c30a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000983934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.1000983934
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.826567481
Short name T876
Test name
Test status
Simulation time 94400445 ps
CPU time 0.84 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 198812 kb
Host smart-5e4204ba-2d1d-47b0-af1c-ec09a28e3662
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826567481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.826567481
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2007516585
Short name T846
Test name
Test status
Simulation time 47316859 ps
CPU time 1.25 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 200252 kb
Host smart-9a6063ec-2b2e-43d1-9b11-cf6e647e6ae4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007516585 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.2007516585
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.556438724
Short name T135
Test name
Test status
Simulation time 152032443 ps
CPU time 1.57 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 200512 kb
Host smart-52d43e7c-9f89-4bde-92d8-bff22dee67b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556438724 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.clkmgr_shadow_reg_errors.556438724
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2697017591
Short name T61
Test name
Test status
Simulation time 384416347 ps
CPU time 3.18 seconds
Started Aug 04 04:32:08 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 208888 kb
Host smart-9c4f9676-5330-4cf7-b3d1-667dda66f900
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697017591 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.2697017591
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.379129735
Short name T893
Test name
Test status
Simulation time 283740498 ps
CPU time 4.22 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200404 kb
Host smart-513fdb27-6c92-4aa3-9ee7-97f4254d9a9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379129735 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.379129735
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.2166049079
Short name T849
Test name
Test status
Simulation time 97643326 ps
CPU time 0.82 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 198900 kb
Host smart-0becd59e-2d1d-4857-864a-d9dd214234cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166049079 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.2166049079
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.3062408540
Short name T855
Test name
Test status
Simulation time 13593142 ps
CPU time 0.71 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 198884 kb
Host smart-a39a3cb9-f643-4941-a4da-5aba9ceb6ba3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062408540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.3062408540
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1083815719
Short name T913
Test name
Test status
Simulation time 23569643 ps
CPU time 0.66 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198900 kb
Host smart-1791c11d-954a-470c-bbb0-17dc20afe5b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083815719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.1083815719
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.107154386
Short name T975
Test name
Test status
Simulation time 15597678 ps
CPU time 0.69 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 198840 kb
Host smart-f26c246b-21d0-48a8-9cc4-91078f64e7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107154386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clk
mgr_intr_test.107154386
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.2227247942
Short name T863
Test name
Test status
Simulation time 32205782 ps
CPU time 0.7 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:14 PM PDT 24
Peak memory 198828 kb
Host smart-371cd3bf-fd9a-4a53-a864-056503087081
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227247942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.2227247942
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.583395059
Short name T824
Test name
Test status
Simulation time 12934686 ps
CPU time 0.7 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 198820 kb
Host smart-d327ea68-0a7c-4e8d-b115-b65770c5e375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583395059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clk
mgr_intr_test.583395059
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.3454781193
Short name T826
Test name
Test status
Simulation time 32112114 ps
CPU time 0.69 seconds
Started Aug 04 04:32:52 PM PDT 24
Finished Aug 04 04:32:53 PM PDT 24
Peak memory 198868 kb
Host smart-bf24d548-92a7-47d6-a092-4a64ba344e11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454781193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.3454781193
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1489560992
Short name T881
Test name
Test status
Simulation time 35252684 ps
CPU time 0.69 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 198816 kb
Host smart-d091fa9a-09aa-4059-a4d3-d23da2e70913
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489560992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1489560992
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.3624737979
Short name T974
Test name
Test status
Simulation time 38390704 ps
CPU time 0.72 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 198828 kb
Host smart-b14157a3-7dbb-485d-836a-6c521b2ed842
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624737979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.3624737979
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2172072430
Short name T948
Test name
Test status
Simulation time 12029159 ps
CPU time 0.63 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 198880 kb
Host smart-988330e0-e95d-421c-9729-d4399255f399
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172072430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.2172072430
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1679501684
Short name T854
Test name
Test status
Simulation time 37595990 ps
CPU time 1.5 seconds
Started Aug 04 04:32:09 PM PDT 24
Finished Aug 04 04:32:10 PM PDT 24
Peak memory 200404 kb
Host smart-1a2c1719-569a-4ccb-b6ec-e7f5e93cd257
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679501684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.1679501684
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.73009623
Short name T910
Test name
Test status
Simulation time 211719382 ps
CPU time 3.45 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 200448 kb
Host smart-fb4d03e0-aea3-4886-b9fb-9880776ea0e6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73009623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_csr_bit_bash.73009623
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1865724631
Short name T909
Test name
Test status
Simulation time 45034844 ps
CPU time 0.79 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:17 PM PDT 24
Peak memory 200172 kb
Host smart-deaba881-491d-401c-ac2f-562dc3207740
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865724631 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1865724631
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3372382848
Short name T865
Test name
Test status
Simulation time 57046789 ps
CPU time 1.64 seconds
Started Aug 04 04:32:07 PM PDT 24
Finished Aug 04 04:32:09 PM PDT 24
Peak memory 208672 kb
Host smart-0a3f08fb-b4bc-4ad5-b2b7-4152f8bdabb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372382848 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3372382848
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.3313241213
Short name T918
Test name
Test status
Simulation time 14953820 ps
CPU time 0.74 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200168 kb
Host smart-b8b9ad72-492e-4d94-b4a9-31308d9974ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313241213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.3313241213
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1837268850
Short name T856
Test name
Test status
Simulation time 14117098 ps
CPU time 0.7 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 198812 kb
Host smart-172fd1ff-94f3-45a2-a559-cdeb7fef4fde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837268850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.1837268850
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.2970752162
Short name T83
Test name
Test status
Simulation time 24596542 ps
CPU time 0.94 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200200 kb
Host smart-a1d8b420-0753-41b2-be94-40ef48881530
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970752162 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.2970752162
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1845174138
Short name T950
Test name
Test status
Simulation time 150044573 ps
CPU time 1.39 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 200456 kb
Host smart-55ef263c-2b37-4b8e-8dab-cff9f592705a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845174138 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.1845174138
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2005417463
Short name T931
Test name
Test status
Simulation time 650507447 ps
CPU time 3.9 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 200904 kb
Host smart-b6653721-15ba-48cb-841b-e91cee2e81ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005417463 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.2005417463
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.740651456
Short name T848
Test name
Test status
Simulation time 502527318 ps
CPU time 4.26 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 200368 kb
Host smart-e77e5f4e-5b2b-45fd-9814-b0541e71ddfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740651456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkm
gr_tl_errors.740651456
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.1876301913
Short name T930
Test name
Test status
Simulation time 11570271 ps
CPU time 0.64 seconds
Started Aug 04 04:32:46 PM PDT 24
Finished Aug 04 04:32:47 PM PDT 24
Peak memory 198912 kb
Host smart-735e46f0-0340-4ece-bf76-be9e169f1aa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876301913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.1876301913
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.2546530825
Short name T941
Test name
Test status
Simulation time 12429396 ps
CPU time 0.65 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:25 PM PDT 24
Peak memory 198828 kb
Host smart-57bab0c9-920e-48ea-86c6-38ffd3a0a3c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546530825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.2546530825
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.1840967521
Short name T844
Test name
Test status
Simulation time 21526805 ps
CPU time 0.66 seconds
Started Aug 04 04:32:27 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 198924 kb
Host smart-5622b7a4-7ba6-4964-a3c8-d70ae074d004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840967521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.1840967521
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.58872034
Short name T900
Test name
Test status
Simulation time 12259762 ps
CPU time 0.7 seconds
Started Aug 04 04:32:59 PM PDT 24
Finished Aug 04 04:33:00 PM PDT 24
Peak memory 198832 kb
Host smart-96d573e9-cf1b-4c5e-86d1-ba332ac978e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58872034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkm
gr_intr_test.58872034
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.121382506
Short name T847
Test name
Test status
Simulation time 34479644 ps
CPU time 0.68 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198728 kb
Host smart-37adb73c-26c7-464e-a15a-be902527ee8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121382506 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clk
mgr_intr_test.121382506
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.850442696
Short name T935
Test name
Test status
Simulation time 10851009 ps
CPU time 0.71 seconds
Started Aug 04 04:32:43 PM PDT 24
Finished Aug 04 04:32:44 PM PDT 24
Peak memory 198788 kb
Host smart-3ce1d90f-1000-4278-ab8a-1bbf329ca5e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850442696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clk
mgr_intr_test.850442696
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.1399623389
Short name T857
Test name
Test status
Simulation time 118392135 ps
CPU time 0.91 seconds
Started Aug 04 04:33:01 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 198876 kb
Host smart-2bd573c4-5098-49dd-84a4-39a5fb892070
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399623389 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.1399623389
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2315888379
Short name T834
Test name
Test status
Simulation time 12184815 ps
CPU time 0.7 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 198816 kb
Host smart-c3d8c33a-fb8c-401e-8176-c085674389e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315888379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.2315888379
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.303768195
Short name T945
Test name
Test status
Simulation time 11955115 ps
CPU time 0.72 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 198824 kb
Host smart-30bbb94a-de66-4cdc-ba92-53688b05ce95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303768195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clk
mgr_intr_test.303768195
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.3954506982
Short name T828
Test name
Test status
Simulation time 26182097 ps
CPU time 0.67 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 198804 kb
Host smart-7c4a2627-485b-4337-8652-655030b4a3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954506982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.3954506982
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.95278071
Short name T110
Test name
Test status
Simulation time 80705927 ps
CPU time 1.35 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200236 kb
Host smart-cd942164-4ca9-43fa-88fa-76363337a67d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95278071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.clkmgr_csr_aliasing.95278071
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.2516466185
Short name T868
Test name
Test status
Simulation time 1395746797 ps
CPU time 9.29 seconds
Started Aug 04 04:32:12 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200340 kb
Host smart-6dca527a-8c67-4bf4-9209-11048f16b72b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516466185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.2516466185
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1289901937
Short name T967
Test name
Test status
Simulation time 45013544 ps
CPU time 0.85 seconds
Started Aug 04 04:32:19 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 200200 kb
Host smart-85555e75-1893-4eea-8179-fdfe9f9972d7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289901937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1289901937
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1234164836
Short name T954
Test name
Test status
Simulation time 31150984 ps
CPU time 1.39 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200552 kb
Host smart-253fd795-f74b-4cde-bf6b-677898992e1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234164836 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1234164836
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.3568297559
Short name T866
Test name
Test status
Simulation time 39616817 ps
CPU time 0.8 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 200164 kb
Host smart-a952a684-f216-4733-9e16-ff547646091c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568297559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.3568297559
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.2676582951
Short name T880
Test name
Test status
Simulation time 44104333 ps
CPU time 0.72 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 198780 kb
Host smart-7642a051-f4ed-45cc-8687-fbfb5d8149ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676582951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.2676582951
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3508238877
Short name T888
Test name
Test status
Simulation time 37004856 ps
CPU time 1.2 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:11 PM PDT 24
Peak memory 200412 kb
Host smart-b1f139f8-24f4-49f9-83d3-4f57ab179c75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508238877 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3508238877
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.204747696
Short name T127
Test name
Test status
Simulation time 302788937 ps
CPU time 3.23 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:20 PM PDT 24
Peak memory 208928 kb
Host smart-095d60c5-ad85-44f8-9ca5-5a2e59b24ce1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204747696 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.204747696
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.2784008188
Short name T845
Test name
Test status
Simulation time 219135253 ps
CPU time 3.26 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200368 kb
Host smart-5fd7dce0-866a-4d94-8e4f-fb143dac34d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784008188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.2784008188
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.881575893
Short name T106
Test name
Test status
Simulation time 231547343 ps
CPU time 2.94 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200392 kb
Host smart-0015fa36-876a-45e3-b151-802c804183fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881575893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_tl_intg_err.881575893
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.4236173157
Short name T842
Test name
Test status
Simulation time 21820782 ps
CPU time 0.68 seconds
Started Aug 04 04:32:50 PM PDT 24
Finished Aug 04 04:32:51 PM PDT 24
Peak memory 198948 kb
Host smart-d38cfdd1-2d25-44d3-9791-ee3e6818e6a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236173157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.4236173157
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.2263460775
Short name T947
Test name
Test status
Simulation time 29448874 ps
CPU time 0.68 seconds
Started Aug 04 04:32:51 PM PDT 24
Finished Aug 04 04:32:52 PM PDT 24
Peak memory 198872 kb
Host smart-92dd50fc-aa95-47dc-b419-779da0b9dabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263460775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.cl
kmgr_intr_test.2263460775
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.1166052596
Short name T939
Test name
Test status
Simulation time 51650767 ps
CPU time 0.74 seconds
Started Aug 04 04:32:27 PM PDT 24
Finished Aug 04 04:32:28 PM PDT 24
Peak memory 198872 kb
Host smart-a02fe9a5-23af-4b6d-a24e-64447a979b1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166052596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.1166052596
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.2501439772
Short name T937
Test name
Test status
Simulation time 87810149 ps
CPU time 0.82 seconds
Started Aug 04 04:33:02 PM PDT 24
Finished Aug 04 04:33:03 PM PDT 24
Peak memory 198864 kb
Host smart-ba853fba-eab3-4053-b058-9841ab774ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501439772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.2501439772
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.2456386068
Short name T924
Test name
Test status
Simulation time 24088654 ps
CPU time 0.67 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 198884 kb
Host smart-2cf03484-9c06-435f-bef0-b232198e979c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456386068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.2456386068
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.4171115313
Short name T879
Test name
Test status
Simulation time 12542089 ps
CPU time 0.66 seconds
Started Aug 04 04:32:36 PM PDT 24
Finished Aug 04 04:32:37 PM PDT 24
Peak memory 198796 kb
Host smart-a709897f-4851-49f5-93dc-1c13c100f56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171115313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.4171115313
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.2354669497
Short name T903
Test name
Test status
Simulation time 18272973 ps
CPU time 0.72 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 198804 kb
Host smart-49c901f4-20c5-4f25-9f7d-9a6259247c4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354669497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.2354669497
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.3158487395
Short name T940
Test name
Test status
Simulation time 30239704 ps
CPU time 0.68 seconds
Started Aug 04 04:32:57 PM PDT 24
Finished Aug 04 04:32:57 PM PDT 24
Peak memory 198796 kb
Host smart-8cda9b5b-f95b-4704-82eb-000afd8eed5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158487395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.3158487395
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3901407578
Short name T830
Test name
Test status
Simulation time 132780576 ps
CPU time 0.9 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:17 PM PDT 24
Peak memory 198828 kb
Host smart-1c75405a-0e47-4fa2-a113-2bcdc7009b9e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901407578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.3901407578
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.1016067487
Short name T851
Test name
Test status
Simulation time 10868184 ps
CPU time 0.64 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 198816 kb
Host smart-1ec1dd50-016f-4288-8c48-ab8da342969c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016067487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.1016067487
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.162742218
Short name T964
Test name
Test status
Simulation time 116429273 ps
CPU time 1.95 seconds
Started Aug 04 04:32:28 PM PDT 24
Finished Aug 04 04:32:30 PM PDT 24
Peak memory 208776 kb
Host smart-78ff18b0-e09d-4c59-af16-81b25a5551b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162742218 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.162742218
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1391027549
Short name T946
Test name
Test status
Simulation time 36677866 ps
CPU time 0.8 seconds
Started Aug 04 04:32:17 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 199608 kb
Host smart-91545b27-24aa-4a17-93a9-4ad991b5e4ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391027549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.1391027549
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.1005215395
Short name T919
Test name
Test status
Simulation time 12268515 ps
CPU time 0.67 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 198792 kb
Host smart-17405b10-5dd2-48d5-a743-0eae9f27bce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005215395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.1005215395
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2616555116
Short name T970
Test name
Test status
Simulation time 51287083 ps
CPU time 1.17 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200236 kb
Host smart-0c8f9742-2612-4088-8a3d-2ac65a939454
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616555116 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2616555116
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.3321820849
Short name T943
Test name
Test status
Simulation time 74917046 ps
CPU time 1.44 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 200480 kb
Host smart-b6f8e292-24a0-4cfb-88f0-2644a5243dde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321820849 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.3321820849
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.745154398
Short name T130
Test name
Test status
Simulation time 158646562 ps
CPU time 2.86 seconds
Started Aug 04 04:32:21 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 208840 kb
Host smart-9755762d-0cff-43d4-9f0d-68477691fe02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745154398 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.745154398
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.4077802107
Short name T928
Test name
Test status
Simulation time 208384349 ps
CPU time 1.98 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200404 kb
Host smart-995964a8-7f68-4357-8d0a-33a13ccac041
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077802107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.4077802107
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.4229652091
Short name T107
Test name
Test status
Simulation time 61532906 ps
CPU time 1.49 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 200432 kb
Host smart-c47230b5-7106-4e0c-a1e8-06a411fbcffd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229652091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.4229652091
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3363064679
Short name T864
Test name
Test status
Simulation time 129391788 ps
CPU time 1.33 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:24 PM PDT 24
Peak memory 200324 kb
Host smart-fcc0be31-0c08-4a0f-9cc6-70e97ba9c232
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363064679 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3363064679
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.23242018
Short name T971
Test name
Test status
Simulation time 107502753 ps
CPU time 0.99 seconds
Started Aug 04 04:32:30 PM PDT 24
Finished Aug 04 04:32:31 PM PDT 24
Peak memory 200212 kb
Host smart-4361e9bb-2ca5-4282-ad06-9ecde848ebc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23242018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_
SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.cl
kmgr_csr_rw.23242018
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.3603029752
Short name T914
Test name
Test status
Simulation time 47425162 ps
CPU time 0.75 seconds
Started Aug 04 04:32:18 PM PDT 24
Finished Aug 04 04:32:19 PM PDT 24
Peak memory 198776 kb
Host smart-47874166-f32f-4a14-b451-d4f5239b2ffa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603029752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.3603029752
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1794567768
Short name T87
Test name
Test status
Simulation time 34065648 ps
CPU time 1.02 seconds
Started Aug 04 04:32:26 PM PDT 24
Finished Aug 04 04:32:27 PM PDT 24
Peak memory 200224 kb
Host smart-ab8eaefe-41c2-4cc3-a3f0-c6657b2b7846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794567768 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1794567768
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.3108511154
Short name T966
Test name
Test status
Simulation time 115681798 ps
CPU time 1.64 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 210032 kb
Host smart-da30a363-e634-4a55-9ecb-c2641f440308
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108511154 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.3108511154
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4143209261
Short name T827
Test name
Test status
Simulation time 192679315 ps
CPU time 1.75 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 200460 kb
Host smart-4b65a5d6-1aa0-4d8f-bcc9-db92caba97a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143209261 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.4143209261
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.2629111870
Short name T102
Test name
Test status
Simulation time 188854843 ps
CPU time 1.79 seconds
Started Aug 04 04:32:24 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200440 kb
Host smart-947663ec-4696-4ed2-b5dd-e7381e74f843
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629111870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.2629111870
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.204399403
Short name T862
Test name
Test status
Simulation time 208373188 ps
CPU time 1.5 seconds
Started Aug 04 04:32:10 PM PDT 24
Finished Aug 04 04:32:12 PM PDT 24
Peak memory 200664 kb
Host smart-00fadb98-2e80-4417-b88b-eecdf7f9da6a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204399403 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.204399403
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.840894822
Short name T959
Test name
Test status
Simulation time 77880116 ps
CPU time 0.91 seconds
Started Aug 04 04:32:41 PM PDT 24
Finished Aug 04 04:32:42 PM PDT 24
Peak memory 200240 kb
Host smart-92599e56-fabb-4ed5-80e5-a8d2f72604bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840894822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.c
lkmgr_csr_rw.840894822
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.3540959048
Short name T843
Test name
Test status
Simulation time 62713262 ps
CPU time 0.74 seconds
Started Aug 04 04:32:33 PM PDT 24
Finished Aug 04 04:32:34 PM PDT 24
Peak memory 198808 kb
Host smart-3c0cef54-cc74-4662-8fa1-4de5033fa3f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540959048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.3540959048
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.3680668007
Short name T84
Test name
Test status
Simulation time 157616950 ps
CPU time 1.47 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:36 PM PDT 24
Peak memory 200140 kb
Host smart-345fca51-2472-455c-aeb3-2af4001c67c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680668007 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.3680668007
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2202000680
Short name T139
Test name
Test status
Simulation time 82195386 ps
CPU time 1.42 seconds
Started Aug 04 04:32:13 PM PDT 24
Finished Aug 04 04:32:15 PM PDT 24
Peak memory 200428 kb
Host smart-e4dea82f-34ff-4880-af07-30d8a6da8a26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202000680 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.2202000680
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2881939805
Short name T137
Test name
Test status
Simulation time 138908392 ps
CPU time 2.12 seconds
Started Aug 04 04:32:14 PM PDT 24
Finished Aug 04 04:32:16 PM PDT 24
Peak memory 209896 kb
Host smart-7757f1e2-a4eb-47ec-b253-758102549569
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881939805 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2881939805
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.133234526
Short name T938
Test name
Test status
Simulation time 101735106 ps
CPU time 1.96 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:17 PM PDT 24
Peak memory 200340 kb
Host smart-0f13b41a-cbeb-48e0-95e9-3c260a9a5008
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133234526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_tl_errors.133234526
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3808753937
Short name T113
Test name
Test status
Simulation time 415971376 ps
CPU time 3.33 seconds
Started Aug 04 04:32:15 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 200408 kb
Host smart-c201a383-2d44-499b-a094-85895b967873
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808753937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3808753937
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.4017786285
Short name T922
Test name
Test status
Simulation time 66738954 ps
CPU time 1.04 seconds
Started Aug 04 04:32:34 PM PDT 24
Finished Aug 04 04:32:35 PM PDT 24
Peak memory 200316 kb
Host smart-83a92ded-7287-4d14-b40d-ababed877b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017786285 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.4017786285
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.4276760280
Short name T883
Test name
Test status
Simulation time 19281651 ps
CPU time 0.83 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200184 kb
Host smart-f6bc8c53-83c9-45e9-b539-0bf0fad2d8c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276760280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
clkmgr_csr_rw.4276760280
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.2727528122
Short name T902
Test name
Test status
Simulation time 37415052 ps
CPU time 0.68 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 198964 kb
Host smart-7e7f8db2-0212-410d-bf0f-f08240beb1e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727528122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.2727528122
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.557294167
Short name T953
Test name
Test status
Simulation time 62634626 ps
CPU time 1.34 seconds
Started Aug 04 04:32:11 PM PDT 24
Finished Aug 04 04:32:13 PM PDT 24
Peak memory 200348 kb
Host smart-f409e999-61ba-4f8f-af7b-43a99e5cd048
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557294167 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.clkmgr_same_csr_outstanding.557294167
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.2120851675
Short name T132
Test name
Test status
Simulation time 153962105 ps
CPU time 1.52 seconds
Started Aug 04 04:32:37 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 199872 kb
Host smart-1c34fbe8-311d-4c28-87f7-e590b685363c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120851675 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.2120851675
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3635290322
Short name T54
Test name
Test status
Simulation time 833814651 ps
CPU time 3.7 seconds
Started Aug 04 04:32:35 PM PDT 24
Finished Aug 04 04:32:39 PM PDT 24
Peak memory 208868 kb
Host smart-f85fe665-7502-4122-9b56-e45efb51f32b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635290322 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3635290322
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.548185992
Short name T955
Test name
Test status
Simulation time 385640255 ps
CPU time 3.45 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:38 PM PDT 24
Peak memory 200452 kb
Host smart-3c455d8b-d92e-4308-83bf-4aec5dbc623a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548185992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.548185992
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3625444182
Short name T114
Test name
Test status
Simulation time 74994830 ps
CPU time 1.63 seconds
Started Aug 04 04:32:23 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200400 kb
Host smart-5c810673-2ce0-4ace-adb6-ec40ea2ee1e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625444182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.3625444182
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.462823506
Short name T907
Test name
Test status
Simulation time 43554013 ps
CPU time 1.01 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200268 kb
Host smart-84cd81b6-ae90-4f09-8a6c-a125daeb2198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462823506 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.462823506
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.3901478535
Short name T929
Test name
Test status
Simulation time 16169227 ps
CPU time 0.75 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:21 PM PDT 24
Peak memory 200236 kb
Host smart-60f8e30f-c8fb-4c64-a8f0-409884cfed65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901478535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.3901478535
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.487637770
Short name T887
Test name
Test status
Simulation time 20810470 ps
CPU time 0.68 seconds
Started Aug 04 04:32:25 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 198764 kb
Host smart-77a09c77-0eb9-4edc-8202-ccc79e854edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487637770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_intr_test.487637770
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1413814777
Short name T867
Test name
Test status
Simulation time 93501567 ps
CPU time 1.18 seconds
Started Aug 04 04:32:20 PM PDT 24
Finished Aug 04 04:32:22 PM PDT 24
Peak memory 199764 kb
Host smart-e0d4565a-3ac7-408d-8e19-13b5b071d394
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413814777 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1413814777
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.611644267
Short name T962
Test name
Test status
Simulation time 344454923 ps
CPU time 1.81 seconds
Started Aug 04 04:32:16 PM PDT 24
Finished Aug 04 04:32:18 PM PDT 24
Peak memory 200472 kb
Host smart-22b12999-4745-4f64-9e83-dc6c117947dd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611644267 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.clkmgr_shadow_reg_errors.611644267
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.3021495584
Short name T58
Test name
Test status
Simulation time 128225650 ps
CPU time 1.73 seconds
Started Aug 04 04:33:00 PM PDT 24
Finished Aug 04 04:33:02 PM PDT 24
Peak memory 208852 kb
Host smart-17bdf979-9607-4a05-b19b-d1d2cb6d4613
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021495584 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3021495584
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4139230527
Short name T920
Test name
Test status
Simulation time 286694230 ps
CPU time 3.78 seconds
Started Aug 04 04:32:22 PM PDT 24
Finished Aug 04 04:32:26 PM PDT 24
Peak memory 200404 kb
Host smart-34b67bcc-87f0-4dd9-989a-140df7f7587d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139230527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.4139230527
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2458870493
Short name T111
Test name
Test status
Simulation time 684986067 ps
CPU time 5.14 seconds
Started Aug 04 04:32:38 PM PDT 24
Finished Aug 04 04:32:43 PM PDT 24
Peak memory 200392 kb
Host smart-7aff56d3-e3cf-4f35-adf2-2f5469aa6fca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458870493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2458870493
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.3712836214
Short name T459
Test name
Test status
Simulation time 16024395 ps
CPU time 0.78 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201116 kb
Host smart-88ba66ac-28fc-4e2a-8b0d-5da03669afc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712836214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.3712836214
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.3409906807
Short name T456
Test name
Test status
Simulation time 33159830 ps
CPU time 0.8 seconds
Started Aug 04 05:17:40 PM PDT 24
Finished Aug 04 05:17:41 PM PDT 24
Peak memory 200984 kb
Host smart-e7e4c0e6-7e9f-4e95-bd96-68261f503c0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409906807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.3409906807
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.3574700256
Short name T458
Test name
Test status
Simulation time 17014025 ps
CPU time 0.65 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:23 PM PDT 24
Peak memory 200188 kb
Host smart-d8d9018c-106e-49e1-9c4a-04be35970e69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574700256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3574700256
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.707933719
Short name T632
Test name
Test status
Simulation time 25126231 ps
CPU time 0.9 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 201056 kb
Host smart-07c1e38e-7859-4f40-84bc-fa131541caec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707933719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0
.clkmgr_div_intersig_mubi.707933719
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.2921437229
Short name T248
Test name
Test status
Simulation time 49393060 ps
CPU time 0.86 seconds
Started Aug 04 05:17:37 PM PDT 24
Finished Aug 04 05:17:37 PM PDT 24
Peak memory 201076 kb
Host smart-f240893d-dd6a-4b85-bb95-be03ff390545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921437229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2921437229
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.1132226608
Short name T542
Test name
Test status
Simulation time 984946017 ps
CPU time 3.87 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:27 PM PDT 24
Peak memory 201116 kb
Host smart-198595f7-0cd3-4271-99b8-f39791a2a13a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132226608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1132226608
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.17510921
Short name T219
Test name
Test status
Simulation time 1238803740 ps
CPU time 4.2 seconds
Started Aug 04 05:17:46 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201120 kb
Host smart-c43f32e3-e402-4196-89fb-661fab2739e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17510921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_time
out.17510921
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.4098896239
Short name T315
Test name
Test status
Simulation time 49683174 ps
CPU time 0.84 seconds
Started Aug 04 05:17:30 PM PDT 24
Finished Aug 04 05:17:31 PM PDT 24
Peak memory 200968 kb
Host smart-4ee4a625-8a0f-4dd7-b11e-26290496e0b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098896239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.4098896239
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.4065426447
Short name T760
Test name
Test status
Simulation time 87207897 ps
CPU time 0.98 seconds
Started Aug 04 05:17:29 PM PDT 24
Finished Aug 04 05:17:30 PM PDT 24
Peak memory 201032 kb
Host smart-33fc9be0-a0b1-4f83-af85-3f78c5c11664
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065426447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.4065426447
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.787189673
Short name T724
Test name
Test status
Simulation time 21798500 ps
CPU time 0.87 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:43 PM PDT 24
Peak memory 201100 kb
Host smart-13c3c0fc-5d8d-44c7-a49e-be5bf55ac333
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787189673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 0.clkmgr_lc_ctrl_intersig_mubi.787189673
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.248859350
Short name T240
Test name
Test status
Simulation time 13846080 ps
CPU time 0.73 seconds
Started Aug 04 05:17:23 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 201048 kb
Host smart-92af5da5-4f18-42e8-a83e-380476a65252
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248859350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.248859350
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.1643592005
Short name T259
Test name
Test status
Simulation time 148419314 ps
CPU time 1.34 seconds
Started Aug 04 05:17:42 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 201096 kb
Host smart-1b01c28a-706e-4250-8d14-e95316048cf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643592005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1643592005
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3492134073
Short name T341
Test name
Test status
Simulation time 46191897 ps
CPU time 0.94 seconds
Started Aug 04 05:17:24 PM PDT 24
Finished Aug 04 05:17:25 PM PDT 24
Peak memory 201100 kb
Host smart-0d5ee91f-e16d-4e3d-9792-78e88cbd3c70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492134073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3492134073
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.4062778120
Short name T142
Test name
Test status
Simulation time 7632053612 ps
CPU time 28.33 seconds
Started Aug 04 05:17:36 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201464 kb
Host smart-bfc5fdb3-5ba0-464d-88d8-f2f81a767fe0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062778120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.4062778120
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2907804469
Short name T197
Test name
Test status
Simulation time 105752646 ps
CPU time 1.09 seconds
Started Aug 04 05:17:22 PM PDT 24
Finished Aug 04 05:17:24 PM PDT 24
Peak memory 201104 kb
Host smart-0ca39c5c-ec94-4e30-becc-547eabb2287e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907804469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2907804469
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.714814233
Short name T623
Test name
Test status
Simulation time 18408039 ps
CPU time 0.74 seconds
Started Aug 04 05:17:46 PM PDT 24
Finished Aug 04 05:17:46 PM PDT 24
Peak memory 200988 kb
Host smart-edec3d22-d25a-43f4-8af6-483c069165ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714814233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_alert_test.714814233
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.321856685
Short name T733
Test name
Test status
Simulation time 125134302 ps
CPU time 1.22 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201036 kb
Host smart-746a9444-e705-4c35-ab7f-c98a5e5d3951
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321856685 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.321856685
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.1563775219
Short name T265
Test name
Test status
Simulation time 159664906 ps
CPU time 1.05 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:55 PM PDT 24
Peak memory 200192 kb
Host smart-1652c3bb-0d30-48e0-b884-8f2d57a2ea9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563775219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1563775219
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.2884504745
Short name T599
Test name
Test status
Simulation time 24497106 ps
CPU time 0.89 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:48 PM PDT 24
Peak memory 201316 kb
Host smart-b7c6d7c9-457c-442a-91b8-c4729df0fce0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884504745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.2884504745
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.4023398483
Short name T244
Test name
Test status
Simulation time 167189365 ps
CPU time 1.22 seconds
Started Aug 04 05:17:42 PM PDT 24
Finished Aug 04 05:17:43 PM PDT 24
Peak memory 201024 kb
Host smart-f0c55ba9-f06f-4e88-8e19-d2bf53643e63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023398483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.4023398483
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3111587520
Short name T400
Test name
Test status
Simulation time 2253950720 ps
CPU time 11.55 seconds
Started Aug 04 05:17:55 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201228 kb
Host smart-0ec1f4bc-da1a-4723-bd00-e41f43aef88f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111587520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3111587520
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.1796451332
Short name T7
Test name
Test status
Simulation time 771733389 ps
CPU time 3.48 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 201388 kb
Host smart-82d6332f-12f7-4ffe-89bb-5810474cd54c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796451332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.1796451332
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.3660353066
Short name T175
Test name
Test status
Simulation time 48632488 ps
CPU time 0.97 seconds
Started Aug 04 05:17:51 PM PDT 24
Finished Aug 04 05:17:52 PM PDT 24
Peak memory 201044 kb
Host smart-d0979410-7960-4eec-b714-1fde36a4693e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660353066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.3660353066
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3680209393
Short name T656
Test name
Test status
Simulation time 19385014 ps
CPU time 0.8 seconds
Started Aug 04 05:17:49 PM PDT 24
Finished Aug 04 05:17:50 PM PDT 24
Peak memory 201036 kb
Host smart-d44a7d7c-4619-459d-85c0-a0f22a3f523f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680209393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3680209393
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.1060962109
Short name T598
Test name
Test status
Simulation time 193922261 ps
CPU time 1.32 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 201004 kb
Host smart-a4ca092e-5768-48b7-bf1f-2378d674b3cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060962109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.1060962109
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.1160552198
Short name T634
Test name
Test status
Simulation time 30437414 ps
CPU time 0.83 seconds
Started Aug 04 05:17:50 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201080 kb
Host smart-1aeacd03-b115-49b4-9268-c5030ae8e216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160552198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.1160552198
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.1777271775
Short name T462
Test name
Test status
Simulation time 1437589246 ps
CPU time 5.3 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201188 kb
Host smart-9abbdebc-05d2-416d-9bc6-4ec444cafcb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777271775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1777271775
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.1774684566
Short name T45
Test name
Test status
Simulation time 302249745 ps
CPU time 3.44 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 217948 kb
Host smart-5df632d6-dd2c-48d2-99c4-32c6c31d9658
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774684566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.1774684566
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.1361092089
Short name T521
Test name
Test status
Simulation time 75784518 ps
CPU time 1.02 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201112 kb
Host smart-5a13a5e3-9332-4421-a166-332c48c02c6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361092089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.1361092089
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.935587526
Short name T799
Test name
Test status
Simulation time 3013940149 ps
CPU time 19.29 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201304 kb
Host smart-a23ab840-01f8-467c-8e55-fc32a80ccf09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935587526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.935587526
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.2280652730
Short name T558
Test name
Test status
Simulation time 17752982013 ps
CPU time 336.88 seconds
Started Aug 04 05:17:40 PM PDT 24
Finished Aug 04 05:23:17 PM PDT 24
Peak memory 209776 kb
Host smart-b51a6ac5-5661-4053-9ca5-76f38b01998b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2280652730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.2280652730
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.503571243
Short name T734
Test name
Test status
Simulation time 16799724 ps
CPU time 0.76 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201076 kb
Host smart-a481f4c2-a35d-4b50-8df3-13e49ac37083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503571243 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.503571243
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1026114360
Short name T405
Test name
Test status
Simulation time 30910605 ps
CPU time 0.76 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201104 kb
Host smart-64e367dc-ffd5-4a62-a5ad-bd63dd87f12e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026114360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1026114360
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1262340915
Short name T227
Test name
Test status
Simulation time 41408006 ps
CPU time 0.88 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:03 PM PDT 24
Peak memory 201036 kb
Host smart-c74890d4-664c-478d-8f44-5ca6c959a504
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262340915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1262340915
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.310760130
Short name T270
Test name
Test status
Simulation time 95133325 ps
CPU time 0.89 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201016 kb
Host smart-f86541a5-78a1-4a46-8f38-d1487ac7e91a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310760130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.310760130
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1396452343
Short name T74
Test name
Test status
Simulation time 20227499 ps
CPU time 0.8 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200992 kb
Host smart-893a0c74-a899-48c3-bf06-0ef71073aa68
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396452343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1396452343
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.622265099
Short name T513
Test name
Test status
Simulation time 40482354 ps
CPU time 0.87 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201028 kb
Host smart-f92252d3-be15-4296-a874-18f3d33ec199
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622265099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.622265099
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.3012725071
Short name T518
Test name
Test status
Simulation time 2269753919 ps
CPU time 9.42 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201348 kb
Host smart-01ddb0a0-c919-4f15-be8c-3a9aa1948ec8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012725071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.3012725071
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3897336667
Short name T475
Test name
Test status
Simulation time 788995806 ps
CPU time 3.94 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201172 kb
Host smart-73f4df38-581b-46cf-af54-b89175f931f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897336667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3897336667
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.3287761784
Short name T417
Test name
Test status
Simulation time 79863125 ps
CPU time 0.93 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 201072 kb
Host smart-efb64f36-5a7b-445c-b035-adbad94c4233
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287761784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_idle_intersig_mubi.3287761784
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2710033810
Short name T201
Test name
Test status
Simulation time 74032032 ps
CPU time 0.95 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201044 kb
Host smart-67942314-a567-4c78-91a4-3b7a7a7b0955
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710033810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2710033810
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.1870563796
Short name T79
Test name
Test status
Simulation time 27990603 ps
CPU time 0.76 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201100 kb
Host smart-d9349549-0812-44c2-a382-90da96c34c71
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870563796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.1870563796
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.3117873989
Short name T187
Test name
Test status
Simulation time 27328935 ps
CPU time 0.78 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201056 kb
Host smart-dc6fe11e-0628-4898-979b-42463c016b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117873989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.3117873989
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.848976621
Short name T222
Test name
Test status
Simulation time 1792976514 ps
CPU time 5.79 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201188 kb
Host smart-6dd7300b-4da9-4eb5-9d8d-936ce832f53c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848976621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.848976621
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.2388424544
Short name T123
Test name
Test status
Simulation time 18231382 ps
CPU time 0.79 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201048 kb
Host smart-aecbdaec-d6ea-437c-94c3-07b98b05163d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388424544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2388424544
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.2383334505
Short name T540
Test name
Test status
Simulation time 3882456916 ps
CPU time 20.37 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201400 kb
Host smart-40d8513e-bfaa-4dc0-9d45-28eb1bbc1902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383334505 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.2383334505
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_trans.838720375
Short name T262
Test name
Test status
Simulation time 22076027 ps
CPU time 0.82 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200972 kb
Host smart-3b3a1c6f-359e-45a0-930c-427d9547c3f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838720375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.838720375
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.3946559422
Short name T764
Test name
Test status
Simulation time 146330957 ps
CPU time 1.25 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200956 kb
Host smart-7c35c531-ec6e-47b0-96cc-965caedeba6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946559422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.3946559422
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1117606226
Short name T98
Test name
Test status
Simulation time 45750277 ps
CPU time 0.96 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201092 kb
Host smart-70474841-9d6b-47a5-94c8-89a429fc38df
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117606226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1117606226
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.2361831197
Short name T242
Test name
Test status
Simulation time 52078383 ps
CPU time 0.79 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200924 kb
Host smart-1b6d74db-74e9-41c7-8692-1847be36e475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361831197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.2361831197
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.2851269938
Short name T269
Test name
Test status
Simulation time 17782535 ps
CPU time 0.78 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201052 kb
Host smart-d2bced62-6941-4f41-ae4f-2b73e1913fe9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851269938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.2851269938
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2441414066
Short name T603
Test name
Test status
Simulation time 239860152 ps
CPU time 1.43 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200916 kb
Host smart-8d562d0e-c98f-4f97-a79d-0d197b4a751a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441414066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2441414066
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.3085755626
Short name T34
Test name
Test status
Simulation time 697985989 ps
CPU time 3.52 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:20 PM PDT 24
Peak memory 201160 kb
Host smart-bb907c9b-ecae-4509-8891-206a86265687
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085755626 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.3085755626
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.2882752589
Short name T494
Test name
Test status
Simulation time 1939632682 ps
CPU time 14.85 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:22 PM PDT 24
Peak memory 201132 kb
Host smart-e547dc66-e7ae-4dba-a909-0689f7d601d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882752589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.2882752589
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.2629730303
Short name T551
Test name
Test status
Simulation time 89651967 ps
CPU time 1.17 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 201068 kb
Host smart-d00157ef-e402-4e0a-b441-e635a707026e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629730303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.2629730303
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.30395913
Short name T35
Test name
Test status
Simulation time 20828130 ps
CPU time 0.82 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201024 kb
Host smart-c8fb9297-39c9-458a-b79c-4f5c4e096afa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30395913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_lc_clk_byp_req_intersig_mubi.30395913
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.3988742761
Short name T738
Test name
Test status
Simulation time 129453137 ps
CPU time 1.17 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201044 kb
Host smart-fdea7afe-e593-48ab-9bfb-e178adcf5ebe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988742761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.3988742761
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.2051438668
Short name T569
Test name
Test status
Simulation time 58808286 ps
CPU time 0.87 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200948 kb
Host smart-61a2f6aa-6146-438a-880b-82e2e66ab87d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051438668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.2051438668
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.739360459
Short name T557
Test name
Test status
Simulation time 1115417247 ps
CPU time 6.59 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201268 kb
Host smart-4201b89a-e804-4b3d-9785-0c1decb41404
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739360459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.739360459
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.329648581
Short name T411
Test name
Test status
Simulation time 19647142 ps
CPU time 0.83 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201068 kb
Host smart-7d58e111-f257-4806-89c2-9eb03cc60b28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329648581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.329648581
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2055157429
Short name T174
Test name
Test status
Simulation time 3160386348 ps
CPU time 13.11 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:19 PM PDT 24
Peak memory 201420 kb
Host smart-659ddf36-27dd-4dba-add0-d33b42314093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055157429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2055157429
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all_with_rand_reset.2837478320
Short name T70
Test name
Test status
Simulation time 16581048860 ps
CPU time 240.48 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:22:13 PM PDT 24
Peak memory 209732 kb
Host smart-a73abc5d-3f37-42d7-8bb7-f0db4262ba9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2837478320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.2837478320
Directory /workspace/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.clkmgr_trans.2598051052
Short name T482
Test name
Test status
Simulation time 25896132 ps
CPU time 0.93 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:03 PM PDT 24
Peak memory 200984 kb
Host smart-fc693d87-0d8e-4a94-a7f4-e9240192812c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598051052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2598051052
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2902442128
Short name T709
Test name
Test status
Simulation time 71074315 ps
CPU time 0.88 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 200956 kb
Host smart-d338530b-4270-4813-b81f-f130d179b80b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902442128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2902442128
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.824187472
Short name T200
Test name
Test status
Simulation time 97381549 ps
CPU time 1.13 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201072 kb
Host smart-825ed523-8cfe-426f-98e6-c2c8004a858c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824187472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.824187472
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.427699373
Short name T46
Test name
Test status
Simulation time 38800510 ps
CPU time 0.89 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201092 kb
Host smart-0872c622-3231-48d9-9d69-29f34f2d5c0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427699373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_div_intersig_mubi.427699373
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.2162315099
Short name T556
Test name
Test status
Simulation time 54512724 ps
CPU time 0.85 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200984 kb
Host smart-6422f890-67ff-434e-94fb-08ef1b195f98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162315099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.2162315099
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.976807798
Short name T821
Test name
Test status
Simulation time 1041226979 ps
CPU time 8.34 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201012 kb
Host smart-91b0aafe-2c22-47fb-bb76-72eef6893f35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976807798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.976807798
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2765085233
Short name T382
Test name
Test status
Simulation time 1734441484 ps
CPU time 7.48 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201092 kb
Host smart-b9f5c904-8d50-4fc3-a9fd-0400269e366f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765085233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2765085233
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.796134013
Short name T663
Test name
Test status
Simulation time 50030002 ps
CPU time 1.02 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201100 kb
Host smart-44ea7ce6-36c3-45b2-b189-77cdefbdcab5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796134013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.clkmgr_idle_intersig_mubi.796134013
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.862649485
Short name T685
Test name
Test status
Simulation time 49223860 ps
CPU time 0.86 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200956 kb
Host smart-6b0038ee-3691-4a1b-98be-33f902c3ae93
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862649485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.862649485
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.3463132216
Short name T206
Test name
Test status
Simulation time 18862845 ps
CPU time 0.81 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201096 kb
Host smart-08b181c6-c9e4-42f2-ba84-ea881fb15f21
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463132216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.3463132216
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.1089955891
Short name T460
Test name
Test status
Simulation time 30737591 ps
CPU time 0.75 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 200948 kb
Host smart-388f12e5-8545-43ff-b742-d219c227f877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089955891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.1089955891
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.2910654128
Short name T795
Test name
Test status
Simulation time 1118932882 ps
CPU time 4.28 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201308 kb
Host smart-cb6df727-49da-4e51-b6ca-2b07bc364f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910654128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2910654128
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.2267279146
Short name T322
Test name
Test status
Simulation time 17396683 ps
CPU time 0.84 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200968 kb
Host smart-fed11370-68d0-440a-9a09-0cfba8c5440f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267279146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.2267279146
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.1041797740
Short name T655
Test name
Test status
Simulation time 11671703298 ps
CPU time 46.03 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:53 PM PDT 24
Peak memory 201384 kb
Host smart-09fd9881-0165-4b76-a760-fbfa575d2cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041797740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.1041797740
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.516316790
Short name T202
Test name
Test status
Simulation time 390604779 ps
CPU time 1.85 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201104 kb
Host smart-264efd0a-4791-45fe-8dfa-feafa438aa18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516316790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.516316790
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.3712166532
Short name T585
Test name
Test status
Simulation time 15797038 ps
CPU time 0.79 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200984 kb
Host smart-32e681dd-c503-47c3-a34d-e13ae2d919eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712166532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.3712166532
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.4177971321
Short name T402
Test name
Test status
Simulation time 12265259 ps
CPU time 0.72 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201068 kb
Host smart-bba738cf-cf47-4faf-a38e-eeb4ebea2492
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177971321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.4177971321
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.1984225560
Short name T552
Test name
Test status
Simulation time 19759061 ps
CPU time 0.68 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200172 kb
Host smart-18e281b0-5e19-4f00-afba-263000f9ea1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984225560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1984225560
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1276402773
Short name T148
Test name
Test status
Simulation time 76847627 ps
CPU time 0.88 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201016 kb
Host smart-eae339bf-a8b3-412f-9d3d-1ff575159c6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276402773 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1276402773
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.3776429366
Short name T548
Test name
Test status
Simulation time 170269645 ps
CPU time 1.34 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 200928 kb
Host smart-1d0c0a65-15d9-463d-a662-9414848ce59b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776429366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3776429366
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.98987183
Short name T31
Test name
Test status
Simulation time 340001230 ps
CPU time 2.04 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201036 kb
Host smart-be03be83-6fbd-4010-bd63-cfd3fb701d24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98987183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.98987183
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3982779619
Short name T653
Test name
Test status
Simulation time 1282942022 ps
CPU time 5.6 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201228 kb
Host smart-0253ceb5-4815-4bc6-b315-f064c1a00cc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982779619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3982779619
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.2419909263
Short name T593
Test name
Test status
Simulation time 39484391 ps
CPU time 0.98 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 201036 kb
Host smart-b78385a8-f35e-4601-ab57-5535d20be5f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419909263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.2419909263
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.239769355
Short name T357
Test name
Test status
Simulation time 40466679 ps
CPU time 0.78 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200988 kb
Host smart-edef95e9-d41c-4c8b-98d7-12b7c2f7951d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239769355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_clk_byp_req_intersig_mubi.239769355
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.555148855
Short name T19
Test name
Test status
Simulation time 36794775 ps
CPU time 0.82 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 201096 kb
Host smart-1d1cbbdd-9076-46e5-a780-a9ac98fdcef4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555148855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.555148855
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.875798015
Short name T768
Test name
Test status
Simulation time 66379572 ps
CPU time 0.86 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 200968 kb
Host smart-cb120573-b2c5-4c7e-80b7-e66b44355be0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875798015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.875798015
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.3309603776
Short name T790
Test name
Test status
Simulation time 1185921182 ps
CPU time 4.59 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201188 kb
Host smart-91c140b8-320d-4c81-b284-b593c911a731
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309603776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.3309603776
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.2422109169
Short name T220
Test name
Test status
Simulation time 85517151 ps
CPU time 1.04 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200936 kb
Host smart-1bd51dfc-6c69-45e2-884a-56371bb03d04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422109169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2422109169
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.874513791
Short name T803
Test name
Test status
Simulation time 7055915215 ps
CPU time 49.2 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201364 kb
Host smart-d7c03bce-92b5-451b-aa9e-ee720beb8f32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874513791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.874513791
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.3534908956
Short name T717
Test name
Test status
Simulation time 33741837313 ps
CPU time 383.25 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:24:32 PM PDT 24
Peak memory 209684 kb
Host smart-9f597b71-9ad9-4ad0-81c5-d817753f39df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3534908956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.3534908956
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2785655831
Short name T366
Test name
Test status
Simulation time 44379733 ps
CPU time 0.78 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200968 kb
Host smart-97805e62-14fd-4eba-9064-d75ee4b1c78b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785655831 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2785655831
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.135219946
Short name T520
Test name
Test status
Simulation time 31512836 ps
CPU time 0.79 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:03 PM PDT 24
Peak memory 200956 kb
Host smart-20853b6c-5dc3-49c7-8b22-813159725127
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135219946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.135219946
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.979978548
Short name T533
Test name
Test status
Simulation time 13330108 ps
CPU time 0.67 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 200180 kb
Host smart-ef8908e5-2f81-4288-b17d-242756c9b44f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979978548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.979978548
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.271587030
Short name T767
Test name
Test status
Simulation time 61159724 ps
CPU time 0.94 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 201052 kb
Host smart-f89343f4-66ee-44c4-a3e2-44bce52296f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271587030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_div_intersig_mubi.271587030
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.1080939062
Short name T119
Test name
Test status
Simulation time 195029331 ps
CPU time 1.43 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201100 kb
Host smart-38b3a4d9-3518-4804-990e-fd1526c4a6e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080939062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1080939062
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1439123770
Short name T596
Test name
Test status
Simulation time 1635539243 ps
CPU time 12.51 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 201064 kb
Host smart-dd2d709e-9811-4e52-bdd9-6cb5b5f9b31c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439123770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1439123770
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.420078818
Short name T229
Test name
Test status
Simulation time 2318024105 ps
CPU time 8.93 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201336 kb
Host smart-1cfcaa79-e1af-4926-84c5-5205106c9c26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420078818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.420078818
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3460250836
Short name T312
Test name
Test status
Simulation time 60062718 ps
CPU time 1.03 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201064 kb
Host smart-fe02b4b8-8f17-4381-bca3-ced50995782e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460250836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3460250836
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.232502152
Short name T158
Test name
Test status
Simulation time 76757523 ps
CPU time 1.02 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201044 kb
Host smart-8a82898a-54ef-4fd1-89c4-f62eb91dee3b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232502152 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_clk_byp_req_intersig_mubi.232502152
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3030600476
Short name T669
Test name
Test status
Simulation time 70594361 ps
CPU time 0.93 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200976 kb
Host smart-bcdfeb29-c506-43fb-8433-79b5e6acc2dd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030600476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3030600476
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.2466245048
Short name T761
Test name
Test status
Simulation time 28205433 ps
CPU time 0.79 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201072 kb
Host smart-4ef3deb1-c2ff-45cd-9711-52d384e1de08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466245048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2466245048
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.3346836779
Short name T476
Test name
Test status
Simulation time 1325837848 ps
CPU time 4.89 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201232 kb
Host smart-3cf29fe4-f9ad-46af-a68c-d99280987eec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346836779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.3346836779
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1047407518
Short name T272
Test name
Test status
Simulation time 24517735 ps
CPU time 0.89 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201040 kb
Host smart-99b1bd3f-b8bf-44b8-9435-09870cee0e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047407518 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1047407518
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2322247032
Short name T144
Test name
Test status
Simulation time 5320799819 ps
CPU time 38.94 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201448 kb
Host smart-5dc9bcbb-abc3-4204-bffb-f083527f38e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322247032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2322247032
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2034443534
Short name T296
Test name
Test status
Simulation time 45674486 ps
CPU time 0.93 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 200952 kb
Host smart-dc6905c7-4bfb-4514-a715-1d874952efaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034443534 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2034443534
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1012262386
Short name T442
Test name
Test status
Simulation time 35093487 ps
CPU time 0.85 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201072 kb
Host smart-11ce79d1-5cdf-488d-a26b-0e40096ad592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012262386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1012262386
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.2077261990
Short name T109
Test name
Test status
Simulation time 20660485 ps
CPU time 0.84 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201052 kb
Host smart-1607fb9f-3018-4d8f-80a8-029e60f33739
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077261990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.2077261990
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.2063510614
Short name T662
Test name
Test status
Simulation time 44774019 ps
CPU time 0.76 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200264 kb
Host smart-1295e888-1947-40ef-becd-15f800c041a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063510614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2063510614
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.994144252
Short name T194
Test name
Test status
Simulation time 66854789 ps
CPU time 0.9 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201060 kb
Host smart-7a57e2e9-3008-4f96-82d5-d9bdaf62957c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994144252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.994144252
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.2048362500
Short name T659
Test name
Test status
Simulation time 29211182 ps
CPU time 0.84 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201032 kb
Host smart-5d945160-1f50-45d6-aeaa-8654fbf1f691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048362500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.2048362500
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.2100842661
Short name T481
Test name
Test status
Simulation time 1725937969 ps
CPU time 8.03 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201156 kb
Host smart-b7d8bff1-dc6f-469f-8658-3bd15990c60f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100842661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2100842661
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3961161862
Short name T619
Test name
Test status
Simulation time 1099945099 ps
CPU time 8.56 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201140 kb
Host smart-583f6628-e512-4cc0-8f8c-275fac638ccc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961161862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3961161862
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.209057694
Short name T179
Test name
Test status
Simulation time 92260418 ps
CPU time 1.19 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 200996 kb
Host smart-0bd632bd-18be-4ade-8f0b-26470f2e0801
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209057694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.209057694
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.542620969
Short name T624
Test name
Test status
Simulation time 21919038 ps
CPU time 0.88 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200940 kb
Host smart-36fd4c88-cb46-48c2-9115-4433c235866a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542620969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.clkmgr_lc_clk_byp_req_intersig_mubi.542620969
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.1460331368
Short name T465
Test name
Test status
Simulation time 21116618 ps
CPU time 0.8 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:20 PM PDT 24
Peak memory 201100 kb
Host smart-0a5769bd-fdcd-438e-81a5-5457207cbe82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460331368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.1460331368
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.1505526617
Short name T578
Test name
Test status
Simulation time 18377497 ps
CPU time 0.8 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201072 kb
Host smart-93b6af03-8f38-42c6-9d62-6b6710aa3161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505526617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1505526617
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.338117746
Short name T51
Test name
Test status
Simulation time 540616880 ps
CPU time 2.47 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201260 kb
Host smart-093686e0-3146-425e-bbc6-24a639c66c14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338117746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.338117746
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1778148844
Short name T582
Test name
Test status
Simulation time 90165324 ps
CPU time 1.02 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201044 kb
Host smart-9015f1b8-23fd-4802-8df1-39ade5458e85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778148844 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1778148844
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.613210429
Short name T583
Test name
Test status
Simulation time 5428042172 ps
CPU time 40.49 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201408 kb
Host smart-be06a59c-7c99-4ae5-87c5-28402fb3f960
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613210429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.613210429
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.3506379469
Short name T203
Test name
Test status
Simulation time 37346594 ps
CPU time 0.92 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201064 kb
Host smart-51d33c5c-01b8-4369-ad70-a19dca2aaefb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506379469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3506379469
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.3932924647
Short name T181
Test name
Test status
Simulation time 36661233 ps
CPU time 0.79 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200936 kb
Host smart-0dc62a19-e654-4fac-947a-db92bd42bbb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932924647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.3932924647
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.233309946
Short name T641
Test name
Test status
Simulation time 26692834 ps
CPU time 0.89 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200968 kb
Host smart-1229a6ff-fb3a-4e29-85dd-a8e77072192c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233309946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.233309946
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.3429545045
Short name T589
Test name
Test status
Simulation time 16862091 ps
CPU time 0.73 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 200236 kb
Host smart-5d3754f7-303d-4e26-b11a-784bb54208a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429545045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.3429545045
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.4202232834
Short name T350
Test name
Test status
Simulation time 29285916 ps
CPU time 0.88 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201100 kb
Host smart-3893ee45-b87b-4fcd-b111-b222863aa8cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202232834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.4202232834
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.3875437111
Short name T512
Test name
Test status
Simulation time 17353518 ps
CPU time 0.73 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201100 kb
Host smart-c434a989-4b68-4c5e-b962-5791530a4823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875437111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.3875437111
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.242195459
Short name T263
Test name
Test status
Simulation time 2238412126 ps
CPU time 18.46 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:33 PM PDT 24
Peak memory 201428 kb
Host smart-13062fa7-17b7-40a0-923d-6147fcb99a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242195459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.242195459
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.1419754776
Short name T300
Test name
Test status
Simulation time 1953506025 ps
CPU time 7.9 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201052 kb
Host smart-df9785cd-ac55-4d78-9a31-746e0463db7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419754776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.1419754776
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.3525242008
Short name T719
Test name
Test status
Simulation time 65836630 ps
CPU time 0.89 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201044 kb
Host smart-6d2a6675-966b-4780-a844-f8bca7eb963f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525242008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.3525242008
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.555483088
Short name T185
Test name
Test status
Simulation time 34372197 ps
CPU time 0.87 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201040 kb
Host smart-66b08abe-2fb2-407e-8cf9-45caf31b833d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555483088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_clk_byp_req_intersig_mubi.555483088
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.771013315
Short name T93
Test name
Test status
Simulation time 25040136 ps
CPU time 0.86 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200920 kb
Host smart-5d1f9471-1391-4633-88d2-72b0553b7ee6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771013315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_ctrl_intersig_mubi.771013315
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.2439313641
Short name T333
Test name
Test status
Simulation time 38892543 ps
CPU time 0.84 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200996 kb
Host smart-a757ea87-81c0-496b-8aa8-4288eb03e7fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439313641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.2439313641
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.2931042108
Short name T297
Test name
Test status
Simulation time 753847134 ps
CPU time 2.75 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201288 kb
Host smart-7c51ebb8-b9cf-4778-9664-0c972102dd9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931042108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2931042108
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.3081824643
Short name T564
Test name
Test status
Simulation time 16159762 ps
CPU time 0.81 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200940 kb
Host smart-30c901f6-06f9-4bf0-83fb-14c9178bbc26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081824643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3081824643
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3350540613
Short name T565
Test name
Test status
Simulation time 24351721 ps
CPU time 0.83 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201020 kb
Host smart-29f04088-527a-4ea0-bfe4-8cd56dce7aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350540613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3350540613
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.631435930
Short name T177
Test name
Test status
Simulation time 22493474 ps
CPU time 0.73 seconds
Started Aug 04 05:18:26 PM PDT 24
Finished Aug 04 05:18:27 PM PDT 24
Peak memory 201036 kb
Host smart-04e4b7bb-2be1-42cb-9d68-27698e46cdf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631435930 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.631435930
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2718977384
Short name T336
Test name
Test status
Simulation time 31678363 ps
CPU time 0.74 seconds
Started Aug 04 05:18:18 PM PDT 24
Finished Aug 04 05:18:19 PM PDT 24
Peak memory 200932 kb
Host smart-eed0c024-2cf9-4d6c-aace-59a34a109d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718977384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2718977384
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.1355831028
Short name T554
Test name
Test status
Simulation time 34480349 ps
CPU time 0.82 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201048 kb
Host smart-889ac53e-ad76-4933-bd0e-953cb083da39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355831028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.1355831028
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.3997629646
Short name T742
Test name
Test status
Simulation time 69087873 ps
CPU time 0.85 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200156 kb
Host smart-4b5c0304-c1b7-4691-a40f-32069d237e3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997629646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3997629646
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.1603596151
Short name T772
Test name
Test status
Simulation time 51524177 ps
CPU time 0.86 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201112 kb
Host smart-77ab99b9-912c-408e-804b-bef96ef94f9e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603596151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.1603596151
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.2323580160
Short name T317
Test name
Test status
Simulation time 22360030 ps
CPU time 0.87 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 200952 kb
Host smart-ddcfe04b-512e-48de-aa42-3037288d2bd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323580160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2323580160
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.1127494050
Short name T783
Test name
Test status
Simulation time 2372011404 ps
CPU time 10.26 seconds
Started Aug 04 05:18:27 PM PDT 24
Finished Aug 04 05:18:37 PM PDT 24
Peak memory 201288 kb
Host smart-8d3de19f-d6af-4b8b-8ebb-7ea8e62c5c0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127494050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.1127494050
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.3327667361
Short name T418
Test name
Test status
Simulation time 374587787 ps
CPU time 3.25 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201124 kb
Host smart-4c5aa6c5-f5bf-4587-bbbb-d73ace306710
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327667361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.3327667361
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2464094195
Short name T281
Test name
Test status
Simulation time 21135738 ps
CPU time 0.7 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 200936 kb
Host smart-6f9b22a8-3706-4dde-b899-fca18d696a2d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464094195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2464094195
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.859404247
Short name T73
Test name
Test status
Simulation time 21118557 ps
CPU time 0.81 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201048 kb
Host smart-04942053-400e-4f19-8248-e1ec4a7b3599
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859404247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_clk_byp_req_intersig_mubi.859404247
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.3385895148
Short name T78
Test name
Test status
Simulation time 79060777 ps
CPU time 0.96 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201048 kb
Host smart-f37dd8c3-93e8-49ab-be26-c2bc77c1a2ba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385895148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.3385895148
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1406969590
Short name T23
Test name
Test status
Simulation time 49467755 ps
CPU time 0.85 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200916 kb
Host smart-d567bd71-a078-4f4f-86e9-6d26e1007c17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406969590 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1406969590
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.3755791873
Short name T651
Test name
Test status
Simulation time 756459540 ps
CPU time 2.88 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201152 kb
Host smart-5dcbd53d-5f71-49b8-a0ac-1b1b9a2c359f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755791873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.3755791873
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.259194596
Short name T145
Test name
Test status
Simulation time 24922987 ps
CPU time 0.88 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201068 kb
Host smart-4301f870-5c2a-4537-a740-c90b81b1a1c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259194596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.259194596
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all_with_rand_reset.1782790349
Short name T71
Test name
Test status
Simulation time 33880061172 ps
CPU time 504.12 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:26:28 PM PDT 24
Peak memory 209820 kb
Host smart-d703f4c9-78b3-4166-ac03-12f9859ae5e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1782790349 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.1782790349
Directory /workspace/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.clkmgr_trans.2100689094
Short name T75
Test name
Test status
Simulation time 62393379 ps
CPU time 0.9 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201092 kb
Host smart-5b277b94-33b6-432a-9329-78fd5a8d4154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100689094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.2100689094
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.2388744294
Short name T301
Test name
Test status
Simulation time 145487401 ps
CPU time 1.14 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201024 kb
Host smart-d0cccc75-9e5f-48c4-911c-c37684c5aa8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388744294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.2388744294
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.1641253033
Short name T543
Test name
Test status
Simulation time 22151928 ps
CPU time 0.83 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201092 kb
Host smart-6d5b8504-10f5-4df3-844d-7c03da5c6d42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641253033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.1641253033
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.369916812
Short name T355
Test name
Test status
Simulation time 14715237 ps
CPU time 0.68 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200180 kb
Host smart-887f35ba-90b3-480a-b712-932da37b0336
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369916812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.369916812
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1054725155
Short name T744
Test name
Test status
Simulation time 110550350 ps
CPU time 1.08 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 200968 kb
Host smart-dcfad3b4-56d6-4c17-aec3-d805ce4d2640
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054725155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1054725155
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.411444141
Short name T487
Test name
Test status
Simulation time 19290205 ps
CPU time 0.78 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 200920 kb
Host smart-1407b8e2-8ee6-4f96-991e-aba1a8b42f3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411444141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.411444141
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1872989045
Short name T496
Test name
Test status
Simulation time 1522357487 ps
CPU time 12.44 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201040 kb
Host smart-f0d2d963-1d98-4558-9e9f-7945cc0d1fe2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872989045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1872989045
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.1080646651
Short name T708
Test name
Test status
Simulation time 1939755104 ps
CPU time 14.22 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:30 PM PDT 24
Peak memory 201048 kb
Host smart-29ee3e2b-d29d-41e7-b116-f63908d86b44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080646651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.1080646651
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.2279483887
Short name T729
Test name
Test status
Simulation time 27805049 ps
CPU time 0.82 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201084 kb
Host smart-d18a1f62-b3d4-40ac-b405-de5d72099c30
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279483887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.2279483887
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.1966299228
Short name T519
Test name
Test status
Simulation time 22190588 ps
CPU time 0.86 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200944 kb
Host smart-dc26c102-d0c4-4ee0-8265-30cef3268853
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966299228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.1966299228
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3101447580
Short name T339
Test name
Test status
Simulation time 23605585 ps
CPU time 0.89 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 200976 kb
Host smart-e01c1358-70a2-4443-accf-af4207ad562f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101447580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.3101447580
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.1996311424
Short name T822
Test name
Test status
Simulation time 34868553 ps
CPU time 0.76 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 200992 kb
Host smart-c6159b67-006f-4aca-8bb7-1f6dfdf455a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996311424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1996311424
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.3840561012
Short name T178
Test name
Test status
Simulation time 481902823 ps
CPU time 2.21 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201000 kb
Host smart-a33b7204-4ba0-4a6d-9bb6-87b5048ec602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840561012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.3840561012
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.3838844851
Short name T192
Test name
Test status
Simulation time 43288537 ps
CPU time 0.85 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200908 kb
Host smart-3219a00f-aac4-4e80-8097-62642b0cdbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838844851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.3838844851
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.1364265046
Short name T774
Test name
Test status
Simulation time 6458680728 ps
CPU time 47.55 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201332 kb
Host smart-15745564-760d-442c-b1dd-a75faf559aab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364265046 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.1364265046
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all_with_rand_reset.1110109245
Short name T176
Test name
Test status
Simulation time 93740089191 ps
CPU time 964.33 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:34:18 PM PDT 24
Peak memory 216628 kb
Host smart-52e5b29b-b571-4b91-8759-500075e047ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1110109245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.1110109245
Directory /workspace/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.clkmgr_trans.3764377504
Short name T182
Test name
Test status
Simulation time 100064522 ps
CPU time 1.17 seconds
Started Aug 04 05:18:25 PM PDT 24
Finished Aug 04 05:18:26 PM PDT 24
Peak memory 200904 kb
Host smart-9eff4b64-372d-4417-ae57-cfa792e2bd47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764377504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.3764377504
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.3414452622
Short name T390
Test name
Test status
Simulation time 45014832 ps
CPU time 0.81 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201112 kb
Host smart-8cdb1dd8-1f98-4580-9e7f-3875836a8e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414452622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.3414452622
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1513346361
Short name T100
Test name
Test status
Simulation time 30557297 ps
CPU time 0.89 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200976 kb
Host smart-980980dc-2748-4dfe-9f59-8c8d5f122052
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513346361 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1513346361
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.2750415827
Short name T696
Test name
Test status
Simulation time 18663503 ps
CPU time 0.7 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 200868 kb
Host smart-efe963b0-907f-4a28-9529-54de6a7aaa99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750415827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.2750415827
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.1529867619
Short name T360
Test name
Test status
Simulation time 30793162 ps
CPU time 0.77 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200956 kb
Host smart-d334b3a9-de07-4744-82e1-9cc8979bff59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529867619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.1529867619
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2785493255
Short name T228
Test name
Test status
Simulation time 24477017 ps
CPU time 0.73 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201068 kb
Host smart-76ba427a-f3fa-47ed-863b-727d720936b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785493255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2785493255
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.2265436830
Short name T399
Test name
Test status
Simulation time 2283108618 ps
CPU time 11.39 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:23 PM PDT 24
Peak memory 201360 kb
Host smart-56c97e6a-1c6c-4d46-a3d4-0d8b033a7918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265436830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.2265436830
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2455626816
Short name T186
Test name
Test status
Simulation time 1456395587 ps
CPU time 10.57 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:26 PM PDT 24
Peak memory 201124 kb
Host smart-96e2613b-0286-4b30-b683-cb630c33b18d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455626816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2455626816
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2956541792
Short name T485
Test name
Test status
Simulation time 13831524 ps
CPU time 0.74 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200996 kb
Host smart-987f815f-a713-442e-87a3-843990bb8cec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956541792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.2956541792
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2019942074
Short name T594
Test name
Test status
Simulation time 52737484 ps
CPU time 0.83 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 200932 kb
Host smart-16389ec6-a696-410d-829a-b329f29cb8f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019942074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2019942074
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2069824552
Short name T477
Test name
Test status
Simulation time 79874820 ps
CPU time 1.03 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201036 kb
Host smart-1747b455-87a6-4d9e-87fb-db595c4df336
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069824552 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.2069824552
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.569670902
Short name T601
Test name
Test status
Simulation time 131878026 ps
CPU time 1.09 seconds
Started Aug 04 05:18:25 PM PDT 24
Finished Aug 04 05:18:26 PM PDT 24
Peak memory 200936 kb
Host smart-573a0445-3f50-4dcf-9469-8d8bfb59fa8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569670902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.569670902
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.1566933514
Short name T779
Test name
Test status
Simulation time 225265592 ps
CPU time 1.31 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200976 kb
Host smart-622b468e-86ba-4426-ab3c-bd0cdbd27472
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566933514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.1566933514
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.3850466214
Short name T607
Test name
Test status
Simulation time 43052725 ps
CPU time 0.92 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 200952 kb
Host smart-d0d97bc4-5c31-48ff-8e96-2b4ac1abaa67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850466214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3850466214
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.2630054435
Short name T257
Test name
Test status
Simulation time 6767557028 ps
CPU time 48.45 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:54 PM PDT 24
Peak memory 201504 kb
Host smart-f36a2b1c-2baa-4211-96a8-dcf6dde4504e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630054435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.2630054435
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.3467864816
Short name T676
Test name
Test status
Simulation time 204569953 ps
CPU time 1.31 seconds
Started Aug 04 05:18:22 PM PDT 24
Finished Aug 04 05:18:24 PM PDT 24
Peak memory 200904 kb
Host smart-4f2ae0e8-e1da-4bee-a218-a415a6fd045f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467864816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.3467864816
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.3636910764
Short name T199
Test name
Test status
Simulation time 34870396 ps
CPU time 0.79 seconds
Started Aug 04 05:17:45 PM PDT 24
Finished Aug 04 05:17:46 PM PDT 24
Peak memory 201024 kb
Host smart-4e30ce1b-ef57-449d-be2e-b50ebe8abaf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636910764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.3636910764
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.2642115617
Short name T590
Test name
Test status
Simulation time 39960564 ps
CPU time 0.85 seconds
Started Aug 04 05:17:49 PM PDT 24
Finished Aug 04 05:17:50 PM PDT 24
Peak memory 201028 kb
Host smart-91d8f1f2-3e88-4f0f-92b0-00b6659c435b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642115617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.2642115617
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.4059229546
Short name T375
Test name
Test status
Simulation time 23302646 ps
CPU time 0.73 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:48 PM PDT 24
Peak memory 200204 kb
Host smart-06eb70bb-6105-488f-a886-9e070fd111b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059229546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.4059229546
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.1472661911
Short name T217
Test name
Test status
Simulation time 94890149 ps
CPU time 1.13 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 200988 kb
Host smart-5bd14442-ec4c-4e80-aeef-167c2ead7299
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472661911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.1472661911
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1788248148
Short name T214
Test name
Test status
Simulation time 14632152 ps
CPU time 0.76 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:48 PM PDT 24
Peak memory 201036 kb
Host smart-dc03d14b-49fd-4899-abdd-fa30467c4564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788248148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1788248148
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1853356042
Short name T441
Test name
Test status
Simulation time 2118883277 ps
CPU time 16.26 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201276 kb
Host smart-f1428175-7abe-4e96-8126-c309c4b64d23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853356042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1853356042
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.815908177
Short name T498
Test name
Test status
Simulation time 637406047 ps
CPU time 2.71 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:56 PM PDT 24
Peak memory 201152 kb
Host smart-5f221633-ae44-4096-b923-2409c0b2f379
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815908177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_tim
eout.815908177
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1252013025
Short name T720
Test name
Test status
Simulation time 51560532 ps
CPU time 1.07 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 201108 kb
Host smart-fc273849-4432-487e-8b78-bddaae1e2f92
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252013025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1252013025
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2836810072
Short name T575
Test name
Test status
Simulation time 65718180 ps
CPU time 0.97 seconds
Started Aug 04 05:17:32 PM PDT 24
Finished Aug 04 05:17:34 PM PDT 24
Peak memory 201040 kb
Host smart-8b02e684-9cd4-4016-a287-376a463fcd48
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836810072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.2836810072
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.2597956332
Short name T438
Test name
Test status
Simulation time 87509956 ps
CPU time 1.05 seconds
Started Aug 04 05:17:55 PM PDT 24
Finished Aug 04 05:17:56 PM PDT 24
Peak memory 200972 kb
Host smart-e3986c31-d54d-4b0a-8715-5377dc621259
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597956332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.2597956332
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2074267241
Short name T644
Test name
Test status
Simulation time 18594603 ps
CPU time 0.73 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 200996 kb
Host smart-debbd27f-7602-4183-947a-70a54522a7a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074267241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2074267241
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.1865042598
Short name T53
Test name
Test status
Simulation time 315975115 ps
CPU time 2.31 seconds
Started Aug 04 05:17:45 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 216440 kb
Host smart-d4327a06-ddac-4a0f-86dc-c738dff76bbb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865042598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.1865042598
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.2391541596
Short name T356
Test name
Test status
Simulation time 78650029 ps
CPU time 1.05 seconds
Started Aug 04 05:17:46 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 201080 kb
Host smart-f52f97ea-5679-4407-a0e3-3f4504596ad7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391541596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.2391541596
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2502932050
Short name T553
Test name
Test status
Simulation time 2785684750 ps
CPU time 12.05 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201336 kb
Host smart-68e5a06b-8946-4c1d-a92d-20ee1cdda531
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502932050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2502932050
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_trans.1182191853
Short name T715
Test name
Test status
Simulation time 385750307 ps
CPU time 2.01 seconds
Started Aug 04 05:17:48 PM PDT 24
Finished Aug 04 05:17:50 PM PDT 24
Peak memory 201000 kb
Host smart-df83afc1-db48-422d-bfc6-6ab9df21bf8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182191853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1182191853
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.2372937740
Short name T461
Test name
Test status
Simulation time 11903439 ps
CPU time 0.72 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201024 kb
Host smart-a664658d-18dc-4105-8648-fa6d60edf9f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372937740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.2372937740
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3540138489
Short name T561
Test name
Test status
Simulation time 107814611 ps
CPU time 1.15 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201056 kb
Host smart-396cf05a-70bf-43ee-982d-c2b439bca1c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540138489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.3540138489
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.2560720519
Short name T377
Test name
Test status
Simulation time 28106968 ps
CPU time 0.73 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 200932 kb
Host smart-89ecbd7b-d126-473d-97e1-98067add0123
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560720519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.2560720519
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.233261058
Short name T730
Test name
Test status
Simulation time 28783022 ps
CPU time 0.84 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201040 kb
Host smart-e8fcaa7d-c1ad-4cdb-830c-e21275133bb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233261058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_div_intersig_mubi.233261058
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3947954417
Short name T588
Test name
Test status
Simulation time 148544069 ps
CPU time 1.25 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201024 kb
Host smart-4b82f0b3-6b07-4c1c-810f-c22d6c77a559
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947954417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3947954417
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.4294146417
Short name T436
Test name
Test status
Simulation time 1284903355 ps
CPU time 7.78 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201144 kb
Host smart-bac3a6f4-19c3-482c-a72c-cc6b0c812e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294146417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.4294146417
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.3941650375
Short name T614
Test name
Test status
Simulation time 1339764705 ps
CPU time 10 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:28 PM PDT 24
Peak memory 201440 kb
Host smart-b7d30f07-54fa-4caa-8d41-44e80aad5243
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941650375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_t
imeout.3941650375
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.1216374154
Short name T797
Test name
Test status
Simulation time 220494585 ps
CPU time 1.41 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200984 kb
Host smart-46dd0bf9-6f36-481c-8d73-88f9783b3808
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216374154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.1216374154
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2429425687
Short name T787
Test name
Test status
Simulation time 52268721 ps
CPU time 0.89 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200968 kb
Host smart-11a32667-4dd5-45b8-b89b-2512c77c67ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429425687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2429425687
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3648298211
Short name T319
Test name
Test status
Simulation time 20079727 ps
CPU time 0.84 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 200992 kb
Host smart-424ed250-2f38-49b3-b26d-bc7e0a050803
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648298211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3648298211
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.3972580076
Short name T420
Test name
Test status
Simulation time 47719758 ps
CPU time 0.78 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 200972 kb
Host smart-e193352e-bfc8-4b54-a2c2-b21c84440efd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972580076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.3972580076
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.1682478878
Short name T714
Test name
Test status
Simulation time 1068474238 ps
CPU time 4.08 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201284 kb
Host smart-81c568a2-1f52-4a6f-9a6f-322af2ef5789
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682478878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1682478878
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.785593216
Short name T28
Test name
Test status
Simulation time 55682520 ps
CPU time 0.89 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201076 kb
Host smart-ed9f0bc3-69fa-49c7-bab6-037419c12c85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785593216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.785593216
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.4071452455
Short name T332
Test name
Test status
Simulation time 3823473193 ps
CPU time 16.75 seconds
Started Aug 04 05:18:27 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201368 kb
Host smart-4d53f185-645e-4adb-9610-64078db7634e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071452455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.4071452455
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.3939272640
Short name T625
Test name
Test status
Simulation time 22673052823 ps
CPU time 407.38 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:24:57 PM PDT 24
Peak memory 217988 kb
Host smart-3d5d1013-26bf-4410-878f-a9dd0787701f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3939272640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3939272640
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.1793370841
Short name T608
Test name
Test status
Simulation time 25565077 ps
CPU time 0.83 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201080 kb
Host smart-1aee68a1-1bd8-4d1b-b6e7-44c56289fa51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793370841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.1793370841
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.307508796
Short name T193
Test name
Test status
Simulation time 21385170 ps
CPU time 0.72 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201072 kb
Host smart-1aea37df-6ce6-4281-a7e7-1fd6fb4dcff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307508796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkm
gr_alert_test.307508796
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.4084749224
Short name T505
Test name
Test status
Simulation time 29056484 ps
CPU time 0.82 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201012 kb
Host smart-336ea16c-21c7-4e4f-b46a-97a1f43bfb91
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084749224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.4084749224
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.2260824680
Short name T159
Test name
Test status
Simulation time 24446904 ps
CPU time 0.72 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 200896 kb
Host smart-03a4c269-abab-4fe0-8e5f-74f2f4523c6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260824680 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2260824680
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.4177012216
Short name T380
Test name
Test status
Simulation time 17692555 ps
CPU time 0.77 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200980 kb
Host smart-7300b244-bbb4-453a-a639-bf40c9ac5f7f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177012216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.4177012216
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.2961707616
Short name T638
Test name
Test status
Simulation time 124649470 ps
CPU time 1.25 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 200984 kb
Host smart-acc488a8-dc67-4dbf-9f05-df24a6b74788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961707616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.2961707616
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.3409367815
Short name T327
Test name
Test status
Simulation time 2100585751 ps
CPU time 9.54 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201320 kb
Host smart-9a596731-63e0-41e8-87b4-5495cb1345f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409367815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3409367815
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3779652628
Short name T246
Test name
Test status
Simulation time 2297073380 ps
CPU time 17.18 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:30 PM PDT 24
Peak memory 201404 kb
Host smart-f0838752-ed46-40b4-ad0a-3c8da52ce61a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779652628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3779652628
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.490017749
Short name T722
Test name
Test status
Simulation time 27063929 ps
CPU time 0.89 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201084 kb
Host smart-7ee846fc-7ce8-4a99-9c2e-4bbe7fbd08f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490017749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_idle_intersig_mubi.490017749
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.2462588863
Short name T359
Test name
Test status
Simulation time 21320807 ps
CPU time 0.8 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201088 kb
Host smart-7cd865c4-4492-465b-8060-b832275fdc4c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462588863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.2462588863
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1264453620
Short name T8
Test name
Test status
Simulation time 26230399 ps
CPU time 0.89 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 200972 kb
Host smart-9393716e-595a-4269-a0f0-730ce53ce09b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264453620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.1264453620
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.4082834459
Short name T748
Test name
Test status
Simulation time 109153060 ps
CPU time 0.96 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201068 kb
Host smart-6447faa6-8624-4b93-9a0a-78322d8fff81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082834459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.4082834459
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.192593100
Short name T5
Test name
Test status
Simulation time 1658844020 ps
CPU time 5.61 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201244 kb
Host smart-ec5852f9-ad0b-4572-a129-dcae5cab5899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192593100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.192593100
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.262387910
Short name T309
Test name
Test status
Simulation time 19148717 ps
CPU time 0.85 seconds
Started Aug 04 05:18:33 PM PDT 24
Finished Aug 04 05:18:34 PM PDT 24
Peak memory 201000 kb
Host smart-edffea28-34c6-49d4-a69d-0ec4053c38c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262387910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.262387910
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.3770567955
Short name T587
Test name
Test status
Simulation time 3234981642 ps
CPU time 17.85 seconds
Started Aug 04 05:18:22 PM PDT 24
Finished Aug 04 05:18:40 PM PDT 24
Peak memory 201416 kb
Host smart-ba9ae2a8-b0dd-4428-b0c9-9c89ab22024e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770567955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.3770567955
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all_with_rand_reset.659027903
Short name T775
Test name
Test status
Simulation time 129334252780 ps
CPU time 730.58 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:30:19 PM PDT 24
Peak memory 212772 kb
Host smart-ade4522f-2a93-4b9f-9698-111ac3e9250e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=659027903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.659027903
Directory /workspace/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.clkmgr_trans.247975170
Short name T489
Test name
Test status
Simulation time 48745916 ps
CPU time 0.84 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201100 kb
Host smart-82f880f9-9cd7-40b3-9f2a-e110373707fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247975170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.247975170
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.2345959817
Short name T741
Test name
Test status
Simulation time 17550914 ps
CPU time 0.75 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201076 kb
Host smart-5c1437b9-0a08-4ef6-aee3-6c7f6d95f59c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345959817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.2345959817
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.281795333
Short name T191
Test name
Test status
Simulation time 255397485 ps
CPU time 1.56 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201072 kb
Host smart-0a665935-d32d-4d93-9f5a-d88b00cdc529
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281795333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.281795333
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.3117468410
Short name T723
Test name
Test status
Simulation time 14363657 ps
CPU time 0.69 seconds
Started Aug 04 05:18:26 PM PDT 24
Finished Aug 04 05:18:27 PM PDT 24
Peak memory 200172 kb
Host smart-88950a60-1b05-4130-94ce-2956fe1c99bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117468410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.3117468410
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.469452541
Short name T207
Test name
Test status
Simulation time 122837118 ps
CPU time 1.11 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 201060 kb
Host smart-ce95b1a0-a3e3-43c3-b052-ff4c3e27bc33
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469452541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_div_intersig_mubi.469452541
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.1332194548
Short name T293
Test name
Test status
Simulation time 60454263 ps
CPU time 0.9 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 200900 kb
Host smart-d130af1a-62f7-4310-b344-4efdf7df526a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332194548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.1332194548
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.826974146
Short name T756
Test name
Test status
Simulation time 1180832905 ps
CPU time 5.71 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201164 kb
Host smart-129a7eb3-b543-4795-973e-12b1d0ce7753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826974146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.826974146
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.147936310
Short name T455
Test name
Test status
Simulation time 1456887454 ps
CPU time 10.18 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:25 PM PDT 24
Peak memory 201104 kb
Host smart-951c6539-dab3-4923-91a7-5b5f55a7d602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147936310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.147936310
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.2894805045
Short name T491
Test name
Test status
Simulation time 25656927 ps
CPU time 0.87 seconds
Started Aug 04 05:18:22 PM PDT 24
Finished Aug 04 05:18:23 PM PDT 24
Peak memory 201084 kb
Host smart-b19d83c3-5296-45e9-9e1d-84b3834f7333
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894805045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.2894805045
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2460652521
Short name T330
Test name
Test status
Simulation time 31407762 ps
CPU time 0.86 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201072 kb
Host smart-bc58f06d-ef39-4f9c-8637-1e66d3d122ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460652521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.2460652521
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.416674563
Short name T766
Test name
Test status
Simulation time 16596058 ps
CPU time 0.8 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201084 kb
Host smart-277ff077-ed8e-4433-be9a-83ab5f0cd587
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416674563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_ctrl_intersig_mubi.416674563
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3407748803
Short name T92
Test name
Test status
Simulation time 21303454 ps
CPU time 0.74 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201040 kb
Host smart-1dfbf0d0-fa77-4f1b-9e37-b0988a693c17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407748803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3407748803
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.1096050993
Short name T349
Test name
Test status
Simulation time 807231282 ps
CPU time 3.06 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201152 kb
Host smart-401c38ee-a7d3-4d61-bcd0-e72f23e5a0d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096050993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.1096050993
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.508137123
Short name T511
Test name
Test status
Simulation time 48345342 ps
CPU time 0.99 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201024 kb
Host smart-017d2d84-5011-44bd-aeaf-056a0f0e1100
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508137123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.508137123
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3658794826
Short name T574
Test name
Test status
Simulation time 809356987 ps
CPU time 6.77 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201204 kb
Host smart-5c319eb3-4cd8-4a59-b167-e332fead1217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658794826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3658794826
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.1555901499
Short name T631
Test name
Test status
Simulation time 18088380 ps
CPU time 0.74 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:20 PM PDT 24
Peak memory 201072 kb
Host smart-08a9ea74-5242-427b-9fce-9878e212bcb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555901499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.1555901499
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.3404381545
Short name T358
Test name
Test status
Simulation time 19562351 ps
CPU time 0.75 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201020 kb
Host smart-92c690f5-135f-47b1-b70a-d65083cdb5bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404381545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.3404381545
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3323621480
Short name T96
Test name
Test status
Simulation time 109652783 ps
CPU time 0.97 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200988 kb
Host smart-12597591-e999-49cb-80e4-cec1ba7313d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323621480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.3323621480
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3885845153
Short name T170
Test name
Test status
Simulation time 29221126 ps
CPU time 0.72 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201020 kb
Host smart-e30c09d0-58b2-4ee6-b0a4-6511f8839d1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885845153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3885845153
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.2647654807
Short name T815
Test name
Test status
Simulation time 93089344 ps
CPU time 1.1 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200988 kb
Host smart-c5adff62-b1e9-4ffe-a8a2-c93e3393d00c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647654807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.2647654807
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.995280816
Short name T687
Test name
Test status
Simulation time 22706656 ps
CPU time 0.85 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201060 kb
Host smart-86bf87f8-ab35-43a0-a3c8-8ba91018007f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995280816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.995280816
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.392651206
Short name T559
Test name
Test status
Simulation time 1036787597 ps
CPU time 8.63 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:22 PM PDT 24
Peak memory 201080 kb
Host smart-84bd79f4-7a37-4d45-9656-3000d707b7a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392651206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.392651206
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.476081902
Short name T531
Test name
Test status
Simulation time 1617493697 ps
CPU time 6.62 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 201172 kb
Host smart-615004a9-23f0-4586-8d51-f9aa7d9a0d42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476081902 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.476081902
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1891161854
Short name T705
Test name
Test status
Simulation time 23260893 ps
CPU time 0.83 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 200984 kb
Host smart-bccaf64a-1796-4e4e-b182-5d00d5ede3bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891161854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.1891161854
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1149557221
Short name T284
Test name
Test status
Simulation time 17099829 ps
CPU time 0.82 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201092 kb
Host smart-71211e02-b036-4eb4-8d44-33329b377e2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149557221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1149557221
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.445052948
Short name T209
Test name
Test status
Simulation time 122979586 ps
CPU time 1.1 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200968 kb
Host smart-9a77f586-ac61-49ab-b57c-ef85d820c06b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445052948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_ctrl_intersig_mubi.445052948
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.2088993829
Short name T763
Test name
Test status
Simulation time 26470246 ps
CPU time 0.8 seconds
Started Aug 04 05:18:24 PM PDT 24
Finished Aug 04 05:18:25 PM PDT 24
Peak memory 200952 kb
Host smart-63909f92-e31c-472d-a991-4b76bf6c513e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088993829 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.2088993829
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.805723579
Short name T393
Test name
Test status
Simulation time 1376352826 ps
CPU time 5.16 seconds
Started Aug 04 05:18:38 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201232 kb
Host smart-d835e250-6900-4426-9a06-c80c648bcf6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805723579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.805723579
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.200550292
Short name T778
Test name
Test status
Simulation time 1024980760 ps
CPU time 5.66 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201244 kb
Host smart-177a1378-ac84-4361-80b8-2b15f5783f36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200550292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.200550292
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.2770361040
Short name T448
Test name
Test status
Simulation time 129921123 ps
CPU time 1.17 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200984 kb
Host smart-56db10b2-a4cf-485c-905d-4d249838ef10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770361040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.2770361040
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.272361989
Short name T612
Test name
Test status
Simulation time 74376276 ps
CPU time 0.86 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 201000 kb
Host smart-d27c7f17-f6b2-4237-b863-9c65fc5760ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272361989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkm
gr_alert_test.272361989
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3196958858
Short name T20
Test name
Test status
Simulation time 210788069 ps
CPU time 1.31 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200384 kb
Host smart-449e994b-697c-4c0f-8d05-c8b3d3d66b37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196958858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3196958858
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.716560094
Short name T211
Test name
Test status
Simulation time 49497599 ps
CPU time 0.77 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200128 kb
Host smart-b106ceeb-ff0c-4e0e-adbf-cbd67580e210
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716560094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.716560094
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.1003618824
Short name T690
Test name
Test status
Simulation time 42646563 ps
CPU time 0.94 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201076 kb
Host smart-0075a0be-33c6-4b51-8db5-c2a71ed94869
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003618824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.1003618824
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2000187770
Short name T351
Test name
Test status
Simulation time 24436446 ps
CPU time 0.85 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200912 kb
Host smart-d7a382c3-fc9d-4a1f-8cf0-972f77fad042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000187770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2000187770
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.1383674686
Short name T695
Test name
Test status
Simulation time 2355269726 ps
CPU time 17.62 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:26 PM PDT 24
Peak memory 201252 kb
Host smart-9fd82add-a720-4d5f-9eba-282843917530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383674686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1383674686
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.338737045
Short name T392
Test name
Test status
Simulation time 2299154645 ps
CPU time 15.88 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:28 PM PDT 24
Peak memory 201448 kb
Host smart-11723910-63fa-492b-9399-b18855ddd32a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338737045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti
meout.338737045
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.746845370
Short name T264
Test name
Test status
Simulation time 17880861 ps
CPU time 0.75 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200940 kb
Host smart-160d8d75-865c-4566-85b3-2f9ec81c2ea0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746845370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
4.clkmgr_idle_intersig_mubi.746845370
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2826527394
Short name T604
Test name
Test status
Simulation time 59731866 ps
CPU time 0.95 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201076 kb
Host smart-13e5520c-5b63-40dc-a367-eaafa337f73e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826527394 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2826527394
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3273306594
Short name T324
Test name
Test status
Simulation time 44839800 ps
CPU time 0.91 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200932 kb
Host smart-3b973236-c67c-446e-b974-ad5f27ec8b68
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273306594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.3273306594
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.1484024088
Short name T635
Test name
Test status
Simulation time 20385250 ps
CPU time 0.76 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201004 kb
Host smart-b995728b-740c-4003-8e4a-46073db061c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484024088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.1484024088
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.400623151
Short name T584
Test name
Test status
Simulation time 699259706 ps
CPU time 2.78 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201304 kb
Host smart-e602fa57-2846-4690-8111-6a0cb514ba74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400623151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.400623151
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.611367545
Short name T258
Test name
Test status
Simulation time 45858358 ps
CPU time 0.89 seconds
Started Aug 04 05:18:17 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 200972 kb
Host smart-44438490-178a-4f1e-b6c2-41b73c0a4409
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611367545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.611367545
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.2280449954
Short name T230
Test name
Test status
Simulation time 3654709133 ps
CPU time 20.37 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:35 PM PDT 24
Peak memory 201324 kb
Host smart-374ff9c0-4150-4909-b2bc-c692faf66b9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280449954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.2280449954
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.3377817918
Short name T304
Test name
Test status
Simulation time 16408680 ps
CPU time 0.76 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201024 kb
Host smart-ef49d3b7-e26d-4020-9cbd-a70cea10931c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377817918 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.3377817918
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3290511568
Short name T545
Test name
Test status
Simulation time 223081670 ps
CPU time 1.37 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201112 kb
Host smart-968f2174-4d40-45de-855d-75c9b6ee0ec7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290511568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3290511568
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1990610703
Short name T808
Test name
Test status
Simulation time 18718671 ps
CPU time 0.82 seconds
Started Aug 04 05:18:16 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201012 kb
Host smart-f382f85b-8281-4a05-9f7b-6dba35fae21d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990610703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1990610703
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.1068488882
Short name T431
Test name
Test status
Simulation time 19145008 ps
CPU time 0.72 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200248 kb
Host smart-c4c1ebc7-45cc-4a40-bfcb-461494dc59c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068488882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1068488882
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.347628517
Short name T285
Test name
Test status
Simulation time 127113524 ps
CPU time 1.13 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200976 kb
Host smart-0ea09d51-11b2-41d6-906b-fc2ef107e718
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347628517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.347628517
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.3003173053
Short name T276
Test name
Test status
Simulation time 41171955 ps
CPU time 0.81 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200944 kb
Host smart-0899c6dc-958d-4eae-8808-6a40440187ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003173053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.3003173053
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.545390056
Short name T1
Test name
Test status
Simulation time 1539417373 ps
CPU time 6.84 seconds
Started Aug 04 05:18:18 PM PDT 24
Finished Aug 04 05:18:25 PM PDT 24
Peak memory 200988 kb
Host smart-4b2c40af-a6b8-42db-ae2c-b5bfbb1b4f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545390056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.545390056
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.707233118
Short name T664
Test name
Test status
Simulation time 906779067 ps
CPU time 4.22 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201160 kb
Host smart-350204a6-92ed-45c1-ab12-ca02dbb7fc2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707233118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_ti
meout.707233118
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.522178574
Short name T735
Test name
Test status
Simulation time 39425390 ps
CPU time 1.05 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 200944 kb
Host smart-3ea0a3e0-a33f-45cc-8e39-62b3be3b57ca
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522178574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_idle_intersig_mubi.522178574
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.216430868
Short name T422
Test name
Test status
Simulation time 19066607 ps
CPU time 0.84 seconds
Started Aug 04 05:18:34 PM PDT 24
Finished Aug 04 05:18:35 PM PDT 24
Peak memory 201096 kb
Host smart-291eb9bd-328a-464b-889d-71bb35e30f3d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216430868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_clk_byp_req_intersig_mubi.216430868
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.2808128665
Short name T611
Test name
Test status
Simulation time 21211520 ps
CPU time 0.79 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201080 kb
Host smart-324d92e8-03cd-4b17-bc58-584eca7c52f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808128665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.2808128665
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.1543381179
Short name T762
Test name
Test status
Simulation time 14510679 ps
CPU time 0.77 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200984 kb
Host smart-7730210e-acb4-4f20-aba2-70793879c971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543381179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.1543381179
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.21370772
Short name T626
Test name
Test status
Simulation time 1461544111 ps
CPU time 5.22 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201268 kb
Host smart-2f58b906-221b-40ef-9c0d-e3f00e9bb169
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21370772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.21370772
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.1526724695
Short name T523
Test name
Test status
Simulation time 59206687 ps
CPU time 0.93 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201108 kb
Host smart-8457aff7-816f-4510-8fd1-a731612212fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526724695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.1526724695
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.169766583
Short name T143
Test name
Test status
Simulation time 4095184365 ps
CPU time 16.31 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:31 PM PDT 24
Peak memory 201372 kb
Host smart-cb8d77bb-9ac6-43e1-9b30-45a3b328fc38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169766583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.169766583
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all_with_rand_reset.3172766782
Short name T66
Test name
Test status
Simulation time 77414396620 ps
CPU time 500.98 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:26:35 PM PDT 24
Peak memory 217908 kb
Host smart-148c0c2f-430f-4954-ba1f-b5c516921d6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3172766782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.3172766782
Directory /workspace/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.clkmgr_trans.84791020
Short name T326
Test name
Test status
Simulation time 133379260 ps
CPU time 1.34 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201044 kb
Host smart-5484a85a-aa1a-43c8-8c2d-d5b079b0c1fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84791020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.84791020
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3583633359
Short name T251
Test name
Test status
Simulation time 15545121 ps
CPU time 0.78 seconds
Started Aug 04 05:18:42 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 200996 kb
Host smart-5f3dbee8-bdba-4ba9-a47a-0c810420d725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583633359 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3583633359
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3343903819
Short name T101
Test name
Test status
Simulation time 98087626 ps
CPU time 1.12 seconds
Started Aug 04 05:18:48 PM PDT 24
Finished Aug 04 05:18:49 PM PDT 24
Peak memory 201004 kb
Host smart-e0b24b25-bae4-4391-8e0f-8967aa0bf1b2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343903819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3343903819
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.1855776055
Short name T675
Test name
Test status
Simulation time 48816959 ps
CPU time 0.78 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 200980 kb
Host smart-6f4a072e-c093-4133-94d4-a845fa96e785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855776055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.1855776055
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.4049055067
Short name T310
Test name
Test status
Simulation time 15589900 ps
CPU time 0.79 seconds
Started Aug 04 05:18:43 PM PDT 24
Finished Aug 04 05:18:44 PM PDT 24
Peak memory 201024 kb
Host smart-e542d296-47bd-488d-949d-c78b2442c5a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049055067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.4049055067
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.4173310354
Short name T365
Test name
Test status
Simulation time 86405637 ps
CPU time 1.02 seconds
Started Aug 04 05:18:14 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201048 kb
Host smart-d2010980-73dc-42a4-9872-c8c6e9b17e4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173310354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.4173310354
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.3194034396
Short name T514
Test name
Test status
Simulation time 1354248922 ps
CPU time 6.4 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:22 PM PDT 24
Peak memory 201044 kb
Host smart-914fcd0a-5b3f-4406-926d-85ccdb27b113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194034396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.3194034396
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1368467695
Short name T30
Test name
Test status
Simulation time 391572854 ps
CPU time 2.1 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:22 PM PDT 24
Peak memory 201228 kb
Host smart-c6b90c18-4ee4-42c1-856f-f607beaddd91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368467695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1368467695
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2306725542
Short name T323
Test name
Test status
Simulation time 58291828 ps
CPU time 0.92 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 200972 kb
Host smart-dd183519-e7b3-457f-9949-aa528f2efe65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306725542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.2306725542
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1131064983
Short name T428
Test name
Test status
Simulation time 21766900 ps
CPU time 0.85 seconds
Started Aug 04 05:18:28 PM PDT 24
Finished Aug 04 05:18:29 PM PDT 24
Peak memory 201040 kb
Host smart-40d1f9c7-8e73-4ca3-826b-6e8f44270171
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131064983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.1131064983
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2454485823
Short name T674
Test name
Test status
Simulation time 29203686 ps
CPU time 0.87 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 201036 kb
Host smart-16253af5-054a-48a6-969f-49487731a76b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454485823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.2454485823
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.1606678524
Short name T298
Test name
Test status
Simulation time 13576775 ps
CPU time 0.71 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:14 PM PDT 24
Peak memory 201088 kb
Host smart-88c6bc1f-1190-430b-96d7-d3dce4a9148a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606678524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.1606678524
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.1391576986
Short name T154
Test name
Test status
Simulation time 819596832 ps
CPU time 4.44 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:29 PM PDT 24
Peak memory 201232 kb
Host smart-9e36456b-57ba-4fb8-ba1f-be86183951bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391576986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1391576986
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.1520261804
Short name T378
Test name
Test status
Simulation time 26058493 ps
CPU time 0.8 seconds
Started Aug 04 05:18:20 PM PDT 24
Finished Aug 04 05:18:21 PM PDT 24
Peak memory 201044 kb
Host smart-aa89cdf5-681b-4465-80e9-551771fe57b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520261804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.1520261804
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.4096989431
Short name T805
Test name
Test status
Simulation time 3703274673 ps
CPU time 30.31 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:19:17 PM PDT 24
Peak memory 201276 kb
Host smart-6ad6d0c4-aa2c-4ec6-924f-affd03dafded
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096989431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.4096989431
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.2114548923
Short name T650
Test name
Test status
Simulation time 25206263 ps
CPU time 0.92 seconds
Started Aug 04 05:18:15 PM PDT 24
Finished Aug 04 05:18:17 PM PDT 24
Peak memory 200952 kb
Host smart-3b8c3493-f2cf-457e-a82b-d4e5f8cfc142
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114548923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.2114548923
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.1334420068
Short name T76
Test name
Test status
Simulation time 34425047 ps
CPU time 0.76 seconds
Started Aug 04 05:18:43 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201064 kb
Host smart-d40186f9-ad97-441a-b706-5a6244f65aa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334420068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.1334420068
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.4082828907
Short name T595
Test name
Test status
Simulation time 54356056 ps
CPU time 0.96 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:43 PM PDT 24
Peak memory 201036 kb
Host smart-11af9da1-5f15-4c53-8251-b72d5b7f1699
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082828907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.4082828907
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.1352082333
Short name T245
Test name
Test status
Simulation time 24188080 ps
CPU time 0.72 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 200304 kb
Host smart-a27cbe1c-3645-4da8-9c5f-1f434e3e3706
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352082333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.1352082333
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.738699451
Short name T454
Test name
Test status
Simulation time 31862298 ps
CPU time 0.96 seconds
Started Aug 04 05:18:36 PM PDT 24
Finished Aug 04 05:18:37 PM PDT 24
Peak memory 201088 kb
Host smart-687c6cce-c6f8-4d62-a50d-9057e745585b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738699451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_div_intersig_mubi.738699451
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.3524575299
Short name T617
Test name
Test status
Simulation time 70491675 ps
CPU time 0.98 seconds
Started Aug 04 05:18:31 PM PDT 24
Finished Aug 04 05:18:32 PM PDT 24
Peak memory 201084 kb
Host smart-41bad597-a79d-4676-bf7d-23b36a894678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524575299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3524575299
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.197410285
Short name T678
Test name
Test status
Simulation time 1411739007 ps
CPU time 7.85 seconds
Started Aug 04 05:18:25 PM PDT 24
Finished Aug 04 05:18:33 PM PDT 24
Peak memory 201148 kb
Host smart-fa2ad060-2b7b-43a3-a71d-29c250efb303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197410285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.197410285
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3097187985
Short name T385
Test name
Test status
Simulation time 1703485881 ps
CPU time 8.58 seconds
Started Aug 04 05:18:19 PM PDT 24
Finished Aug 04 05:18:27 PM PDT 24
Peak memory 201176 kb
Host smart-ee9f59c4-f327-44ab-bf3a-6e48f076a1ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097187985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3097187985
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.251256956
Short name T550
Test name
Test status
Simulation time 80738502 ps
CPU time 1.05 seconds
Started Aug 04 05:18:36 PM PDT 24
Finished Aug 04 05:18:37 PM PDT 24
Peak memory 201008 kb
Host smart-4530e6b1-6159-4c45-9045-3680124721ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251256956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_idle_intersig_mubi.251256956
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.2524920168
Short name T629
Test name
Test status
Simulation time 16249006 ps
CPU time 0.77 seconds
Started Aug 04 05:18:39 PM PDT 24
Finished Aug 04 05:18:40 PM PDT 24
Peak memory 201084 kb
Host smart-9ee11d74-1c05-4da6-8fc6-cd96657b801e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524920168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.2524920168
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.4076494582
Short name T639
Test name
Test status
Simulation time 58606920 ps
CPU time 0.89 seconds
Started Aug 04 05:18:30 PM PDT 24
Finished Aug 04 05:18:31 PM PDT 24
Peak memory 201032 kb
Host smart-48f45c7d-214a-47c8-8404-d849cc7b8a51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076494582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.4076494582
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.4227661490
Short name T416
Test name
Test status
Simulation time 35084580 ps
CPU time 0.81 seconds
Started Aug 04 05:18:35 PM PDT 24
Finished Aug 04 05:18:36 PM PDT 24
Peak memory 201064 kb
Host smart-8f788896-a86a-4dd7-805c-a63c11a8bc9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227661490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.4227661490
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1950514197
Short name T497
Test name
Test status
Simulation time 113184918 ps
CPU time 1.19 seconds
Started Aug 04 05:18:40 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 201104 kb
Host smart-7455683a-91f7-4bbf-be1b-09e2bc4aa8ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950514197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1950514197
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1257891353
Short name T22
Test name
Test status
Simulation time 20896965 ps
CPU time 0.82 seconds
Started Aug 04 05:18:36 PM PDT 24
Finished Aug 04 05:18:37 PM PDT 24
Peak memory 201008 kb
Host smart-937169e3-2ea7-46c5-8acb-8e036cb490d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257891353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1257891353
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.2721167687
Short name T77
Test name
Test status
Simulation time 65450302 ps
CPU time 1.13 seconds
Started Aug 04 05:18:37 PM PDT 24
Finished Aug 04 05:18:39 PM PDT 24
Peak memory 201108 kb
Host smart-37a38d04-f7bd-4854-a1dc-8cba180630eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721167687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.2721167687
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_trans.2253057762
Short name T470
Test name
Test status
Simulation time 165269962 ps
CPU time 1.44 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 201120 kb
Host smart-c34ff0f9-50ac-4fc4-92fe-ef5745da5804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253057762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2253057762
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.2905395167
Short name T314
Test name
Test status
Simulation time 18476821 ps
CPU time 0.76 seconds
Started Aug 04 05:18:39 PM PDT 24
Finished Aug 04 05:18:40 PM PDT 24
Peak memory 200988 kb
Host smart-a942ab82-f94e-44b2-ae48-9b6697a0ffa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905395167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.2905395167
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.617006252
Short name T688
Test name
Test status
Simulation time 222687250 ps
CPU time 1.45 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 201048 kb
Host smart-a56f7823-80e0-4e7d-9293-df58ef91b5b6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617006252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.617006252
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.4178563745
Short name T412
Test name
Test status
Simulation time 44030650 ps
CPU time 0.73 seconds
Started Aug 04 05:18:40 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 200136 kb
Host smart-b9ea28ee-493b-483b-8902-01acddf4d543
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178563745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.4178563745
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.4061133582
Short name T286
Test name
Test status
Simulation time 20107898 ps
CPU time 0.81 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:42 PM PDT 24
Peak memory 201088 kb
Host smart-37bd2fb9-69ee-4717-a732-a3291edc0f08
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061133582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.4061133582
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.3603829657
Short name T671
Test name
Test status
Simulation time 18094258 ps
CPU time 0.73 seconds
Started Aug 04 05:18:40 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 200996 kb
Host smart-93b97071-51c2-46a1-8aff-cc035c071785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603829657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.3603829657
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.3192755130
Short name T32
Test name
Test status
Simulation time 339072141 ps
CPU time 1.77 seconds
Started Aug 04 05:18:39 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 201144 kb
Host smart-36f380f1-55b1-4c25-85d3-de42bc0fcd98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192755130 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3192755130
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.3210346814
Short name T287
Test name
Test status
Simulation time 2304314653 ps
CPU time 12.57 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201428 kb
Host smart-0e866c4f-6ad5-431a-ab79-8855ba29a2ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210346814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.3210346814
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.2568128981
Short name T785
Test name
Test status
Simulation time 83876424 ps
CPU time 1.05 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 200992 kb
Host smart-0131f90f-23ce-4abb-8fa1-52a0b504ba1c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568128981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.2568128981
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.1787639818
Short name T396
Test name
Test status
Simulation time 29167611 ps
CPU time 0.9 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:42 PM PDT 24
Peak memory 201076 kb
Host smart-9ba9d8b7-5cc7-4c75-ba4b-fdb941f5af11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787639818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.1787639818
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3061607294
Short name T464
Test name
Test status
Simulation time 52934912 ps
CPU time 1 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201012 kb
Host smart-9bed4dcf-aeb2-4607-91ca-eb33b4ea6494
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061607294 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.3061607294
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.2046562475
Short name T331
Test name
Test status
Simulation time 48891846 ps
CPU time 0.86 seconds
Started Aug 04 05:18:39 PM PDT 24
Finished Aug 04 05:18:40 PM PDT 24
Peak memory 201072 kb
Host smart-520ed231-dfc7-45df-a0f7-3bda63d2f5c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046562475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2046562475
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2575201360
Short name T613
Test name
Test status
Simulation time 432545708 ps
CPU time 2.6 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:48 PM PDT 24
Peak memory 201072 kb
Host smart-603f4e4b-f672-4826-8b99-1839e5724e71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575201360 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2575201360
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.4145466723
Short name T335
Test name
Test status
Simulation time 15511425 ps
CPU time 0.82 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:42 PM PDT 24
Peak memory 201100 kb
Host smart-665016c4-3747-4278-b5ba-5e7ba5076fff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145466723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.4145466723
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.870869465
Short name T628
Test name
Test status
Simulation time 2922479269 ps
CPU time 15.64 seconds
Started Aug 04 05:18:42 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201504 kb
Host smart-1018492d-1cea-4dc3-9483-bfa32706933f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870869465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.870869465
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1587965988
Short name T308
Test name
Test status
Simulation time 51827917 ps
CPU time 0.86 seconds
Started Aug 04 05:18:40 PM PDT 24
Finished Aug 04 05:18:41 PM PDT 24
Peak memory 201088 kb
Host smart-033ef24f-1681-4d3c-adea-1ec6ae8a4fef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587965988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1587965988
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.2532505541
Short name T754
Test name
Test status
Simulation time 66956633 ps
CPU time 0.87 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 201016 kb
Host smart-22526d7c-1fd7-46b3-bc55-961598f6aea2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532505541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.2532505541
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.3700072707
Short name T479
Test name
Test status
Simulation time 22030113 ps
CPU time 0.82 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 200796 kb
Host smart-531fdd45-6f4e-422d-b8a9-fcbaeb764ad5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700072707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.3700072707
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.2039757654
Short name T667
Test name
Test status
Simulation time 29987285 ps
CPU time 0.72 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 200948 kb
Host smart-92dda3ba-0b53-488d-bb7d-4325a07752fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039757654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.2039757654
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.2613229628
Short name T50
Test name
Test status
Simulation time 53556559 ps
CPU time 0.92 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 201080 kb
Host smart-608d9025-5f0a-4d6d-a649-0584197bd6db
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613229628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.2613229628
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.3483573876
Short name T389
Test name
Test status
Simulation time 17856844 ps
CPU time 0.76 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 201084 kb
Host smart-cda02d4b-5338-41dc-80fe-89f026dd51a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483573876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3483573876
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.4145015397
Short name T802
Test name
Test status
Simulation time 1030064432 ps
CPU time 4.41 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:50 PM PDT 24
Peak memory 201184 kb
Host smart-fa0d2851-9716-419e-9610-0065232ac28f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145015397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.4145015397
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.3401396667
Short name T81
Test name
Test status
Simulation time 500796784 ps
CPU time 4.21 seconds
Started Aug 04 05:18:43 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 201160 kb
Host smart-71573735-ae5e-4f56-bdfe-b67aa22051cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401396667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.3401396667
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.2713623802
Short name T156
Test name
Test status
Simulation time 19670701 ps
CPU time 0.8 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 201108 kb
Host smart-79dfe8c8-b158-4bd8-aa03-493de811d1b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713623802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.2713623802
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1241906993
Short name T517
Test name
Test status
Simulation time 27291107 ps
CPU time 0.91 seconds
Started Aug 04 05:18:48 PM PDT 24
Finished Aug 04 05:18:49 PM PDT 24
Peak memory 201044 kb
Host smart-0dd5a04f-f9d5-40bb-b7e7-8b98eb8b4f87
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241906993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1241906993
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.133219118
Short name T499
Test name
Test status
Simulation time 140344250 ps
CPU time 1.27 seconds
Started Aug 04 05:18:43 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 200980 kb
Host smart-8ff149fc-538c-4521-834e-17a34d76d766
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133219118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.133219118
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.3787493491
Short name T283
Test name
Test status
Simulation time 22344139 ps
CPU time 0.75 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:18:45 PM PDT 24
Peak memory 200960 kb
Host smart-49550540-9b41-48fe-8f55-b8baec9cbeee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787493491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.3787493491
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.3554942467
Short name T118
Test name
Test status
Simulation time 87208308 ps
CPU time 0.94 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 201104 kb
Host smart-204afc45-19bd-410b-b4c2-346e5d284663
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554942467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.3554942467
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1659545004
Short name T426
Test name
Test status
Simulation time 72654073 ps
CPU time 0.98 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:42 PM PDT 24
Peak memory 200964 kb
Host smart-8c43ad01-b347-4480-9ea8-73ad83b3dec1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659545004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1659545004
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.606443705
Short name T750
Test name
Test status
Simulation time 2212927570 ps
CPU time 17.35 seconds
Started Aug 04 05:18:44 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201500 kb
Host smart-e3a6838e-a66d-4027-820b-12f686fbbe97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606443705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.606443705
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.2795431380
Short name T509
Test name
Test status
Simulation time 19672610 ps
CPU time 0.81 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 201104 kb
Host smart-c0cb0edb-db23-4725-9a83-8be310c15797
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795431380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2795431380
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.262491449
Short name T48
Test name
Test status
Simulation time 17034470 ps
CPU time 0.75 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 201100 kb
Host smart-6bd5f02e-64ce-4984-8c08-394cd6f7bb3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262491449 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_alert_test.262491449
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.1400952683
Short name T661
Test name
Test status
Simulation time 127977621 ps
CPU time 1.14 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201040 kb
Host smart-2a3e79b6-9966-477e-961c-b09e8c31f148
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400952683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.1400952683
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2520756745
Short name T568
Test name
Test status
Simulation time 31980000 ps
CPU time 0.72 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 200300 kb
Host smart-809982e5-0c04-493e-984d-49f56eec99bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520756745 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2520756745
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.1482507138
Short name T646
Test name
Test status
Simulation time 15585357 ps
CPU time 0.77 seconds
Started Aug 04 05:17:57 PM PDT 24
Finished Aug 04 05:17:58 PM PDT 24
Peak memory 201284 kb
Host smart-bcd9b7ab-081e-417a-9217-4260427c1cab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482507138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.1482507138
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.2344943308
Short name T367
Test name
Test status
Simulation time 45124238 ps
CPU time 0.85 seconds
Started Aug 04 05:17:39 PM PDT 24
Finished Aug 04 05:17:40 PM PDT 24
Peak memory 200928 kb
Host smart-6b0f137b-7512-49f7-b350-e0f4716cf0ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344943308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.2344943308
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.3338146622
Short name T694
Test name
Test status
Simulation time 333704993 ps
CPU time 2.17 seconds
Started Aug 04 05:17:43 PM PDT 24
Finished Aug 04 05:17:45 PM PDT 24
Peak memory 201172 kb
Host smart-7fa67fa2-061b-4eb0-b861-230e19cb9b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338146622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.3338146622
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.1421169438
Short name T492
Test name
Test status
Simulation time 260094585 ps
CPU time 2.63 seconds
Started Aug 04 05:17:41 PM PDT 24
Finished Aug 04 05:17:44 PM PDT 24
Peak memory 201176 kb
Host smart-4c948a60-b067-4f17-a8ed-13237fa6bc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421169438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.1421169438
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3126270747
Short name T765
Test name
Test status
Simulation time 20445956 ps
CPU time 0.82 seconds
Started Aug 04 05:17:48 PM PDT 24
Finished Aug 04 05:17:49 PM PDT 24
Peak memory 201032 kb
Host smart-74f68bd7-1f9f-4f6c-9356-f3ea5d0986b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126270747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3126270747
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1203791052
Short name T606
Test name
Test status
Simulation time 14565998 ps
CPU time 0.74 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:54 PM PDT 24
Peak memory 201112 kb
Host smart-04cc78a2-c8df-4524-a028-e6381ce79b13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203791052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1203791052
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.254343014
Short name T271
Test name
Test status
Simulation time 95243054 ps
CPU time 1.07 seconds
Started Aug 04 05:17:54 PM PDT 24
Finished Aug 04 05:17:55 PM PDT 24
Peak memory 201124 kb
Host smart-661b5931-a4ed-4697-bdc2-69244b0eeb96
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254343014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_ctrl_intersig_mubi.254343014
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.1892230022
Short name T397
Test name
Test status
Simulation time 23735487 ps
CPU time 0.78 seconds
Started Aug 04 05:17:50 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 200944 kb
Host smart-e8b340bc-c781-4b60-8cea-84292d443e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892230022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1892230022
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.2079184266
Short name T713
Test name
Test status
Simulation time 282620904 ps
CPU time 1.71 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:55 PM PDT 24
Peak memory 201124 kb
Host smart-a0f4479e-aa84-412e-be45-56deb37d0111
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079184266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.2079184266
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.4266837612
Short name T43
Test name
Test status
Simulation time 881273605 ps
CPU time 4.79 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 216520 kb
Host smart-1fb04e64-6c74-445c-86d5-7899b3fd2c98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266837612 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.4266837612
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.3020146056
Short name T777
Test name
Test status
Simulation time 14786098 ps
CPU time 0.77 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:54 PM PDT 24
Peak memory 200992 kb
Host smart-56de40f3-df93-4529-903d-d1a147436629
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020146056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3020146056
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.3162035686
Short name T806
Test name
Test status
Simulation time 2406943866 ps
CPU time 11.52 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201308 kb
Host smart-b2e1f6ea-3019-48e5-8766-4e83c4d304e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162035686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.3162035686
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.4089432545
Short name T407
Test name
Test status
Simulation time 136549226 ps
CPU time 1.36 seconds
Started Aug 04 05:17:55 PM PDT 24
Finished Aug 04 05:17:57 PM PDT 24
Peak memory 201120 kb
Host smart-40fed85d-039b-43eb-95ad-3a4890831b35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089432545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.4089432545
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.2998786994
Short name T773
Test name
Test status
Simulation time 22167999 ps
CPU time 0.85 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 200992 kb
Host smart-e60f43e4-8654-414f-b29f-85d79a918c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998786994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.2998786994
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.702441458
Short name T232
Test name
Test status
Simulation time 19082982 ps
CPU time 0.78 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201036 kb
Host smart-4d33c2e9-c940-40f6-aead-c324a27c4193
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702441458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.702441458
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.3006543071
Short name T313
Test name
Test status
Simulation time 24283187 ps
CPU time 0.74 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 200252 kb
Host smart-aae7cac4-9e78-4f08-b65c-8cabba002b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006543071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.3006543071
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.354579279
Short name T527
Test name
Test status
Simulation time 20800394 ps
CPU time 0.89 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201052 kb
Host smart-ffa6e776-2c5e-4a9c-9945-953287722d39
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354579279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
0.clkmgr_div_intersig_mubi.354579279
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1758089413
Short name T666
Test name
Test status
Simulation time 51774068 ps
CPU time 0.9 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 200948 kb
Host smart-616368c6-b806-4d72-a1bc-02d8e9dd9498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758089413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1758089413
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2840106181
Short name T703
Test name
Test status
Simulation time 1064108564 ps
CPU time 5.14 seconds
Started Aug 04 05:18:41 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 201076 kb
Host smart-6ec13c7e-cf4f-42cd-b4dd-993f1c9532e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840106181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2840106181
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.904210969
Short name T256
Test name
Test status
Simulation time 1269931672 ps
CPU time 5.45 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:50 PM PDT 24
Peak memory 201184 kb
Host smart-68e75e82-0c8b-4515-ab71-49584f17c724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904210969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_ti
meout.904210969
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3927834036
Short name T586
Test name
Test status
Simulation time 74670032 ps
CPU time 0.92 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:18:48 PM PDT 24
Peak memory 201112 kb
Host smart-fe1d726b-5db8-4e20-a469-5e8ab8f21ca1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927834036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3927834036
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.388988579
Short name T120
Test name
Test status
Simulation time 26614969 ps
CPU time 0.83 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201112 kb
Host smart-bb6033da-6ac1-44d9-a8a1-79ccb29cfe85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388988579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.388988579
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3292526733
Short name T630
Test name
Test status
Simulation time 29125374 ps
CPU time 0.9 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 201076 kb
Host smart-f7334cc3-9f30-4f35-a90b-45ef43d5b6d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292526733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3292526733
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.2200783216
Short name T430
Test name
Test status
Simulation time 24511446 ps
CPU time 0.77 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:54 PM PDT 24
Peak memory 200988 kb
Host smart-aaca2b6b-afa9-4db5-9f4b-5dff4f887b81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200783216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2200783216
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.3118601915
Short name T152
Test name
Test status
Simulation time 864797026 ps
CPU time 4.59 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201268 kb
Host smart-850dc8c2-e3ab-4bc6-92a9-29dda7f51ea7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118601915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3118601915
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.1981305679
Short name T535
Test name
Test status
Simulation time 23912079 ps
CPU time 0.84 seconds
Started Aug 04 05:18:48 PM PDT 24
Finished Aug 04 05:18:48 PM PDT 24
Peak memory 200940 kb
Host smart-453134dd-2168-4679-a368-bd7c4f2b1770
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981305679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.1981305679
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.2680951052
Short name T645
Test name
Test status
Simulation time 906539297 ps
CPU time 7.27 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 201232 kb
Host smart-1c778b00-2b9d-43d8-8f08-535e0f02ef5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680951052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.2680951052
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.4231027657
Short name T88
Test name
Test status
Simulation time 111727283 ps
CPU time 1.23 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201108 kb
Host smart-30a2f7c4-59d3-48dc-b1e9-9552c6f85bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231027657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.4231027657
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.2453930662
Short name T372
Test name
Test status
Simulation time 15824430 ps
CPU time 0.73 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 200996 kb
Host smart-0a87bc86-d752-465f-92b1-4e021bee6678
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453930662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.2453930662
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.160199637
Short name T99
Test name
Test status
Simulation time 81442960 ps
CPU time 1.03 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:53 PM PDT 24
Peak memory 201108 kb
Host smart-9389a9e3-0a20-439c-b827-d470a22db2b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160199637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.160199637
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1431201954
Short name T537
Test name
Test status
Simulation time 12594711 ps
CPU time 0.68 seconds
Started Aug 04 05:18:50 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 200148 kb
Host smart-0dc6a373-b381-41dc-9cc3-46f5c605128b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431201954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1431201954
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.3204322057
Short name T731
Test name
Test status
Simulation time 59374170 ps
CPU time 0.96 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 201104 kb
Host smart-14056e80-52d8-4ad4-a98f-f4a4e90fa7d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204322057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.3204322057
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.957281766
Short name T363
Test name
Test status
Simulation time 54946987 ps
CPU time 0.84 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201088 kb
Host smart-fddde09b-4aef-4e0d-90b3-3465deca5e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957281766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.957281766
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.1307621285
Short name T311
Test name
Test status
Simulation time 1824042893 ps
CPU time 7.52 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 201012 kb
Host smart-7fcb58eb-3edc-4d60-81af-b8c769bb814d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307621285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.1307621285
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3770081083
Short name T642
Test name
Test status
Simulation time 2357510804 ps
CPU time 7.68 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201300 kb
Host smart-1fa60341-23f5-4215-aeee-ab42d0713b5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770081083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3770081083
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.704545894
Short name T221
Test name
Test status
Simulation time 28574967 ps
CPU time 0.96 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201056 kb
Host smart-9c9186f4-7dff-437b-89fc-25bc3615e256
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704545894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_idle_intersig_mubi.704545894
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2074630297
Short name T376
Test name
Test status
Simulation time 27786685 ps
CPU time 0.79 seconds
Started Aug 04 05:18:45 PM PDT 24
Finished Aug 04 05:18:46 PM PDT 24
Peak memory 200972 kb
Host smart-33b6f455-d1da-4c24-b8da-5adcd1692a72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074630297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2074630297
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.4133588767
Short name T679
Test name
Test status
Simulation time 16154307 ps
CPU time 0.76 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201052 kb
Host smart-17f3f5d7-78c6-4e12-9082-25213aab9127
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133588767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.4133588767
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.3025494392
Short name T739
Test name
Test status
Simulation time 42290847 ps
CPU time 0.82 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:18:48 PM PDT 24
Peak memory 201072 kb
Host smart-696c78ff-adc1-4ecd-b0f0-695e1977aa34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025494392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.3025494392
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.2731594274
Short name T445
Test name
Test status
Simulation time 667630139 ps
CPU time 2.47 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201044 kb
Host smart-a6128263-198e-40e4-8842-d15dc651011e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731594274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.2731594274
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.4066858617
Short name T580
Test name
Test status
Simulation time 14743314 ps
CPU time 0.86 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201004 kb
Host smart-47c0945a-ebf6-4778-8ea3-2bbb3f354183
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066858617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.4066858617
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.421638874
Short name T809
Test name
Test status
Simulation time 4792414233 ps
CPU time 16.54 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:16 PM PDT 24
Peak memory 201508 kb
Host smart-5c3ff539-1f61-4077-933e-d62d9fe672a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421638874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.421638874
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all_with_rand_reset.467593891
Short name T164
Test name
Test status
Simulation time 101160831514 ps
CPU time 833.09 seconds
Started Aug 04 05:18:49 PM PDT 24
Finished Aug 04 05:32:42 PM PDT 24
Peak memory 209760 kb
Host smart-3dd710fc-cd8d-4014-b1d8-c530f2beebfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=467593891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.467593891
Directory /workspace/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.clkmgr_trans.7306296
Short name T732
Test name
Test status
Simulation time 64399097 ps
CPU time 0.94 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201020 kb
Host smart-14b59c6f-1591-4f79-9d55-a9bbb3ed60fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7306296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.7306296
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.3454477934
Short name T640
Test name
Test status
Simulation time 47932578 ps
CPU time 0.83 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201132 kb
Host smart-83e68ada-f61b-4cde-82c0-bb447ba0990c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454477934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.3454477934
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.1169897784
Short name T52
Test name
Test status
Simulation time 64003284 ps
CPU time 0.94 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201116 kb
Host smart-22393d5f-5eaf-49e1-a8c1-38aaaeee0d13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169897784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.1169897784
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.3752266742
Short name T24
Test name
Test status
Simulation time 13990007 ps
CPU time 0.68 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200308 kb
Host smart-765649a8-df6b-4a60-bf3f-b157c7a8a80c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752266742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.3752266742
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.12889943
Short name T64
Test name
Test status
Simulation time 101983218 ps
CPU time 1.1 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:53 PM PDT 24
Peak memory 201100 kb
Host smart-0f956c4c-5ec5-4f7a-ab3d-ab7896cb368b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12889943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.clkmgr_div_intersig_mubi.12889943
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.2416994153
Short name T472
Test name
Test status
Simulation time 36326645 ps
CPU time 0.87 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200936 kb
Host smart-b9920a77-ec5d-4a8c-a9a0-ced758b04478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416994153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.2416994153
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.1831683662
Short name T490
Test name
Test status
Simulation time 1410331622 ps
CPU time 7.56 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201104 kb
Host smart-2af38154-f96b-46c7-9372-89c4866b4c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831683662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.1831683662
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.2555632969
Short name T784
Test name
Test status
Simulation time 1273703459 ps
CPU time 5.5 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 200956 kb
Host smart-c42afd74-0b22-41ec-adc2-f14bc2857d17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555632969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.2555632969
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.3927929474
Short name T267
Test name
Test status
Simulation time 39049694 ps
CPU time 1.08 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200980 kb
Host smart-0fc80743-6fa7-4082-a0c3-241f59ac7de5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927929474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.3927929474
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.3758732008
Short name T343
Test name
Test status
Simulation time 79114016 ps
CPU time 0.99 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 200936 kb
Host smart-71b19d50-b28b-480d-82e0-fe8575fa2770
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758732008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.3758732008
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.211126434
Short name T368
Test name
Test status
Simulation time 16153025 ps
CPU time 0.74 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201028 kb
Host smart-cae66a3a-355d-4e4d-a0da-531cd4a27097
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211126434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.211126434
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.76755693
Short name T163
Test name
Test status
Simulation time 11922825 ps
CPU time 0.69 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 200924 kb
Host smart-6b5f0462-dbf9-49d6-a45a-df1f6753e921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76755693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.76755693
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.2745318760
Short name T150
Test name
Test status
Simulation time 926086793 ps
CPU time 5.26 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201292 kb
Host smart-38e5140b-c649-469d-9ac7-931cedbcc752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745318760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2745318760
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.3788726178
Short name T571
Test name
Test status
Simulation time 24092497 ps
CPU time 0.88 seconds
Started Aug 04 05:18:49 PM PDT 24
Finished Aug 04 05:18:50 PM PDT 24
Peak memory 200976 kb
Host smart-f0458e0c-8895-4b65-b9df-da357f413a31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788726178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.3788726178
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.4194027737
Short name T673
Test name
Test status
Simulation time 24492940 ps
CPU time 0.84 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200988 kb
Host smart-016e0e29-6f41-4220-854e-012c389fa829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194027737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.4194027737
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.1698199471
Short name T290
Test name
Test status
Simulation time 152998965 ps
CPU time 1.19 seconds
Started Aug 04 05:18:46 PM PDT 24
Finished Aug 04 05:18:47 PM PDT 24
Peak memory 201020 kb
Host smart-ad1ff00b-3cb0-4141-b0d1-6faee0c5aba2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698199471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1698199471
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1423293595
Short name T577
Test name
Test status
Simulation time 22033794 ps
CPU time 0.71 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 201048 kb
Host smart-4f4f0f54-6cb6-4f2d-b2af-8f69287fc6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423293595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1423293595
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3581419817
Short name T566
Test name
Test status
Simulation time 29740220 ps
CPU time 0.82 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201036 kb
Host smart-3bcb9219-daf1-4041-a02d-385ee4bf993f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581419817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3581419817
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.1422215779
Short name T215
Test name
Test status
Simulation time 17565478 ps
CPU time 0.7 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 200172 kb
Host smart-c2e19e59-e5d3-4b40-98bf-56d4d2cd6520
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422215779 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.1422215779
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.2696481300
Short name T362
Test name
Test status
Simulation time 40214850 ps
CPU time 0.97 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201080 kb
Host smart-af87cbda-da44-47d4-ab4f-29d9ab21577b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696481300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.2696481300
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.4123742507
Short name T413
Test name
Test status
Simulation time 41323644 ps
CPU time 0.78 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 200924 kb
Host smart-dda3fc9c-a91c-4e1a-b838-5363d694635c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123742507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.4123742507
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.477701914
Short name T320
Test name
Test status
Simulation time 1275839607 ps
CPU time 9.92 seconds
Started Aug 04 05:18:50 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201220 kb
Host smart-5e84b2fe-88e6-46b6-8548-41c44194c167
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477701914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.477701914
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.1257327301
Short name T429
Test name
Test status
Simulation time 1617634635 ps
CPU time 6.67 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201180 kb
Host smart-9d220e13-761d-4444-bc1d-07c46fb0d7a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257327301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.1257327301
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.2180058968
Short name T546
Test name
Test status
Simulation time 34459084 ps
CPU time 0.84 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201000 kb
Host smart-b992f7f4-078e-4e78-a8a8-1329d093f524
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180058968 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.2180058968
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.3394894580
Short name T278
Test name
Test status
Simulation time 80187476 ps
CPU time 0.96 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201040 kb
Host smart-efb92a75-3079-4581-b3cb-29cabb5fa17a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394894580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.3394894580
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.813175592
Short name T702
Test name
Test status
Simulation time 41745732 ps
CPU time 0.93 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201028 kb
Host smart-7cfddd5b-436b-4968-81a4-b83b27354062
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813175592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 33.clkmgr_lc_ctrl_intersig_mubi.813175592
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.1330310570
Short name T743
Test name
Test status
Simulation time 55567579 ps
CPU time 0.82 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201092 kb
Host smart-de8db498-0a22-4e2e-96d9-cf1202ff34db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330310570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.1330310570
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.2632540951
Short name T160
Test name
Test status
Simulation time 894505254 ps
CPU time 3.58 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 201196 kb
Host smart-295537b9-0bd6-4f36-a3f2-5c4e4cba85c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632540951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2632540951
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.3984471076
Short name T147
Test name
Test status
Simulation time 38156373 ps
CPU time 0.9 seconds
Started Aug 04 05:18:50 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 201088 kb
Host smart-2672e635-508d-474f-9b6b-69e3910d41e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984471076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.3984471076
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.432852139
Short name T423
Test name
Test status
Simulation time 4003205209 ps
CPU time 17.58 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:18 PM PDT 24
Peak memory 201384 kb
Host smart-89384f42-2ec4-492f-8682-66d407d12bef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432852139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.432852139
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.1282286548
Short name T183
Test name
Test status
Simulation time 34286095 ps
CPU time 1.04 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201032 kb
Host smart-baa8dbcc-f7c4-426b-aca9-1c0145c545c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282286548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1282286548
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.4233224900
Short name T218
Test name
Test status
Simulation time 28302711 ps
CPU time 0.82 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200992 kb
Host smart-5dd6a728-a0c1-4f14-8c39-5595d69edf59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233224900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.4233224900
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3526804846
Short name T817
Test name
Test status
Simulation time 50262090 ps
CPU time 0.98 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 200996 kb
Host smart-ab902b35-bc8c-4641-85da-eff752f635d8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526804846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3526804846
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.15438707
Short name T452
Test name
Test status
Simulation time 47939418 ps
CPU time 0.81 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 200232 kb
Host smart-62b579fa-db9b-432f-9a04-c8fcca45f2b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15438707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.15438707
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.1873622257
Short name T478
Test name
Test status
Simulation time 101460363 ps
CPU time 1.01 seconds
Started Aug 04 05:18:49 PM PDT 24
Finished Aug 04 05:18:50 PM PDT 24
Peak memory 200984 kb
Host smart-ad6b386f-79ea-4feb-8dc2-c3db9fd11dfb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873622257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.1873622257
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.3498087452
Short name T570
Test name
Test status
Simulation time 27400032 ps
CPU time 0.78 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201016 kb
Host smart-978c0af8-9f32-4841-9532-71c48a9bc297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498087452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3498087452
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.2090690555
Short name T555
Test name
Test status
Simulation time 1279149632 ps
CPU time 7.34 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201196 kb
Host smart-b68383e5-c668-4a48-86c3-dce106f5811c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090690555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.2090690555
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1317916057
Short name T247
Test name
Test status
Simulation time 736438266 ps
CPU time 6.3 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 201100 kb
Host smart-cf9f7b59-9bdf-436d-a7c9-c78d5d4850de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317916057 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1317916057
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.4040704730
Short name T239
Test name
Test status
Simulation time 54494716 ps
CPU time 0.89 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201080 kb
Host smart-f174ffec-d30d-4780-a726-7743f65d0be0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040704730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.4040704730
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.2915575810
Short name T243
Test name
Test status
Simulation time 21755943 ps
CPU time 0.8 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201096 kb
Host smart-172ef635-59cf-463d-a9ac-ed0f067c514f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915575810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.2915575810
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.1536935514
Short name T205
Test name
Test status
Simulation time 44216203 ps
CPU time 0.82 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200964 kb
Host smart-be2426f2-25a7-4f5c-ae3a-6c3ff1d6ee8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536935514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1536935514
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.1850672426
Short name T4
Test name
Test status
Simulation time 560187174 ps
CPU time 2.39 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201080 kb
Host smart-48005428-31ab-45ac-9127-c5a062d3fe7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850672426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.1850672426
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.2341373502
Short name T794
Test name
Test status
Simulation time 33807054 ps
CPU time 0.92 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200948 kb
Host smart-62100b79-a4de-4ab5-bd21-4c5f5cbbfe92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341373502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.2341373502
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.1849587447
Short name T409
Test name
Test status
Simulation time 5590342866 ps
CPU time 23.79 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:23 PM PDT 24
Peak memory 201460 kb
Host smart-7eee2751-0177-4ee8-a02e-8d2a45cfc7fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849587447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.1849587447
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.4075095109
Short name T9
Test name
Test status
Simulation time 24118261 ps
CPU time 0.73 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201088 kb
Host smart-f54bcb5c-343c-46a7-bec4-48e106ccf752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075095109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.4075095109
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.1461994859
Short name T534
Test name
Test status
Simulation time 32382923 ps
CPU time 0.74 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:53 PM PDT 24
Peak memory 201280 kb
Host smart-d8c261bb-097e-41e3-8cd3-9bbec351ccd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461994859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.1461994859
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.2737252651
Short name T361
Test name
Test status
Simulation time 17896007 ps
CPU time 0.8 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201024 kb
Host smart-b0dedece-c3b8-4890-b511-9dd809be1393
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737252651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.2737252651
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.4096531985
Short name T757
Test name
Test status
Simulation time 127819080 ps
CPU time 0.97 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 200244 kb
Host smart-5fb336b1-a0f6-405a-83a2-fd20ace0ebb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096531985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.4096531985
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2787366939
Short name T231
Test name
Test status
Simulation time 24880298 ps
CPU time 0.86 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 201100 kb
Host smart-266d864c-2385-4d9d-b843-297de0e67674
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787366939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2787366939
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.3488710265
Short name T544
Test name
Test status
Simulation time 22696452 ps
CPU time 0.85 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200968 kb
Host smart-677fb93d-ceea-4c7e-8a9a-19a96d54ef38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488710265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.3488710265
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2692999406
Short name T282
Test name
Test status
Simulation time 797625240 ps
CPU time 6.31 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201112 kb
Host smart-0e8ee945-b8a5-4d8a-a651-6afa068fee4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692999406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2692999406
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3603313305
Short name T425
Test name
Test status
Simulation time 926884750 ps
CPU time 4.1 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201088 kb
Host smart-621fd480-fe6a-4767-84e6-d4f9eb34185c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603313305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3603313305
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.3963350348
Short name T321
Test name
Test status
Simulation time 118521598 ps
CPU time 1.01 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201004 kb
Host smart-b2403c01-812e-4b51-aa25-1f0863cc90fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963350348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.3963350348
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.2221334340
Short name T447
Test name
Test status
Simulation time 24828605 ps
CPU time 0.76 seconds
Started Aug 04 05:19:07 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200964 kb
Host smart-b2788f0b-6f3e-47c8-8b42-f9096f0c2021
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221334340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.2221334340
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1461930469
Short name T292
Test name
Test status
Simulation time 87179198 ps
CPU time 1.1 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200992 kb
Host smart-51c540e0-18b2-4d97-a643-4727288da1da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461930469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.1461930469
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.524650897
Short name T184
Test name
Test status
Simulation time 23609191 ps
CPU time 0.76 seconds
Started Aug 04 05:18:53 PM PDT 24
Finished Aug 04 05:18:54 PM PDT 24
Peak memory 200976 kb
Host smart-8ec5e49f-ea53-4df6-adea-ff556c4a5a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524650897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.524650897
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.2467654325
Short name T398
Test name
Test status
Simulation time 777791059 ps
CPU time 3.25 seconds
Started Aug 04 05:18:47 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 201152 kb
Host smart-dd7f1227-48c2-4104-ba89-510e0e41c43f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467654325 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2467654325
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.330749663
Short name T395
Test name
Test status
Simulation time 39031032 ps
CPU time 0.87 seconds
Started Aug 04 05:18:52 PM PDT 24
Finished Aug 04 05:18:53 PM PDT 24
Peak memory 200948 kb
Host smart-d6514c33-7142-4c40-9499-d7c36c94c245
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330749663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.330749663
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.680389701
Short name T294
Test name
Test status
Simulation time 8703209206 ps
CPU time 61.29 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:20:04 PM PDT 24
Peak memory 201420 kb
Host smart-0dc9acc9-cc29-4424-a2f0-527155732aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680389701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.680389701
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.3124077763
Short name T725
Test name
Test status
Simulation time 123840624 ps
CPU time 1.24 seconds
Started Aug 04 05:18:53 PM PDT 24
Finished Aug 04 05:18:54 PM PDT 24
Peak memory 200988 kb
Host smart-b5645b36-2662-4c95-a8f1-f13c2513e2fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124077763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3124077763
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.3220241813
Short name T369
Test name
Test status
Simulation time 75596408 ps
CPU time 0.92 seconds
Started Aug 04 05:18:53 PM PDT 24
Finished Aug 04 05:18:54 PM PDT 24
Peak memory 201056 kb
Host smart-ad1753f4-4bdb-4173-948b-e5ef143587f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220241813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.3220241813
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.626937786
Short name T237
Test name
Test status
Simulation time 40063355 ps
CPU time 0.84 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201024 kb
Host smart-88b46718-a6f6-4c37-a0c0-01f65529da38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626937786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.626937786
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.2125891289
Short name T49
Test name
Test status
Simulation time 13406118 ps
CPU time 0.71 seconds
Started Aug 04 05:18:50 PM PDT 24
Finished Aug 04 05:18:51 PM PDT 24
Peak memory 200300 kb
Host smart-a774e27f-23e8-4ca0-aa2a-a52ff1741017
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125891289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.2125891289
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.4155737784
Short name T510
Test name
Test status
Simulation time 39905068 ps
CPU time 0.86 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201028 kb
Host smart-b2098d10-6279-4b80-8965-14e2a7f340e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155737784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.4155737784
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.822638145
Short name T255
Test name
Test status
Simulation time 92984638 ps
CPU time 1.02 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 201040 kb
Host smart-9228041f-bf62-4c23-8475-57b142a5d0ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822638145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.822638145
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.1566287333
Short name T318
Test name
Test status
Simulation time 797314190 ps
CPU time 6.39 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201112 kb
Host smart-f864397d-4302-467e-8f8f-d9609693f1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566287333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1566287333
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.3015437801
Short name T484
Test name
Test status
Simulation time 855471298 ps
CPU time 6.54 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 201128 kb
Host smart-2e69bfc8-4c79-45bd-b8f4-81ba99546f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015437801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.3015437801
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3378986911
Short name T383
Test name
Test status
Simulation time 40685870 ps
CPU time 1.06 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201016 kb
Host smart-79884d04-76c6-4c22-b796-0fcea47ad8bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378986911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.3378986911
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3689076430
Short name T198
Test name
Test status
Simulation time 24191961 ps
CPU time 0.79 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201028 kb
Host smart-7e57ec7f-c559-45f0-9e81-b0d671c8c5e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689076430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.3689076430
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.1174325651
Short name T354
Test name
Test status
Simulation time 42934059 ps
CPU time 0.86 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201020 kb
Host smart-cf7cfc2b-963e-40fb-a090-6b5846005a6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174325651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.1174325651
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.1094725793
Short name T241
Test name
Test status
Simulation time 39507054 ps
CPU time 0.8 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 201004 kb
Host smart-32de405a-91fb-44c0-ba6f-37c158413b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094725793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.1094725793
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.2715173813
Short name T210
Test name
Test status
Simulation time 408456411 ps
CPU time 2.59 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 201104 kb
Host smart-2783a2e0-494a-43d9-9306-e2acc278e3e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715173813 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.2715173813
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3539855234
Short name T121
Test name
Test status
Simulation time 96056756 ps
CPU time 1.04 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201052 kb
Host smart-5e7f0609-1976-4ea5-a9cc-211daab34b0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539855234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3539855234
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.664163656
Short name T507
Test name
Test status
Simulation time 6973081980 ps
CPU time 35.74 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:37 PM PDT 24
Peak memory 201424 kb
Host smart-48a90df6-5c78-4e76-bc6f-5124c1811fc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664163656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.664163656
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1623614720
Short name T91
Test name
Test status
Simulation time 64843225 ps
CPU time 0.96 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201276 kb
Host smart-c0f2bc82-a398-4b03-b65c-665c1ae3c0e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623614720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1623614720
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.3010004655
Short name T268
Test name
Test status
Simulation time 18938126 ps
CPU time 0.81 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201028 kb
Host smart-16a00e19-3bf6-45bc-9f68-7f2c2d23388e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010004655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.3010004655
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.2227187086
Short name T810
Test name
Test status
Simulation time 23128490 ps
CPU time 0.81 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 201064 kb
Host smart-52287a69-c2fd-4056-a8aa-046a339c6407
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227187086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.2227187086
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.267184355
Short name T681
Test name
Test status
Simulation time 18503083 ps
CPU time 0.71 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200488 kb
Host smart-62b3bbe2-f8bb-412c-a128-7e1d63a783d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267184355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.267184355
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.1029182746
Short name T266
Test name
Test status
Simulation time 16004850 ps
CPU time 0.75 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200992 kb
Host smart-d9b4e641-c138-4c27-bcd2-d94b8c9a4231
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029182746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.1029182746
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.2703036763
Short name T421
Test name
Test status
Simulation time 79232697 ps
CPU time 0.98 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200996 kb
Host smart-39891ecd-898c-4050-b342-7b8b7b2ac51b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703036763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.2703036763
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.2960192048
Short name T11
Test name
Test status
Simulation time 1546974051 ps
CPU time 7.39 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201084 kb
Host smart-0940bca0-735c-47b5-9f9f-9409b9bce720
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960192048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.2960192048
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.1188539496
Short name T235
Test name
Test status
Simulation time 2187440926 ps
CPU time 7.89 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201404 kb
Host smart-17adb66f-28a5-4930-b9ae-ccf1d6a1df86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188539496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.1188539496
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.337450143
Short name T348
Test name
Test status
Simulation time 51454550 ps
CPU time 0.97 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 201036 kb
Host smart-67aeb8b1-ca34-4e25-8aff-c742fe37d7ce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337450143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.clkmgr_idle_intersig_mubi.337450143
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.4032369717
Short name T226
Test name
Test status
Simulation time 68770073 ps
CPU time 0.94 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201024 kb
Host smart-a1e2c4e7-5434-48de-a61a-0e1de8ad6cdd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032369717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.4032369717
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.547550940
Short name T740
Test name
Test status
Simulation time 95285220 ps
CPU time 1.02 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201008 kb
Host smart-90841149-8c09-483e-80b0-ae2454ceadbb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547550940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 37.clkmgr_lc_ctrl_intersig_mubi.547550940
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.1874735974
Short name T328
Test name
Test status
Simulation time 85695489 ps
CPU time 0.92 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201024 kb
Host smart-f0db2670-f561-4fac-981d-ee68aa5da780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874735974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.1874735974
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1582757423
Short name T820
Test name
Test status
Simulation time 1572560415 ps
CPU time 5.78 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201196 kb
Host smart-64d2cadc-dd47-453e-b4ab-7bc0297004ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582757423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1582757423
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.1562319658
Short name T818
Test name
Test status
Simulation time 18285590 ps
CPU time 0.81 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201016 kb
Host smart-0a57d6fc-68d3-4946-9167-63f1d300c569
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562319658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1562319658
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.3684515458
Short name T3
Test name
Test status
Simulation time 4673786731 ps
CPU time 25.99 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:29 PM PDT 24
Peak memory 201652 kb
Host smart-0c10e4d4-d434-42cf-ab53-879c1d7a695d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684515458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.3684515458
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.2401000509
Short name T386
Test name
Test status
Simulation time 136369551 ps
CPU time 1.33 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201012 kb
Host smart-015c1de6-e0e7-43cb-ac23-48816faba6dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401000509 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.2401000509
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.1717567775
Short name T38
Test name
Test status
Simulation time 16628788 ps
CPU time 0.75 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201012 kb
Host smart-b486b3f7-e992-49be-a528-754a16f2fa23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717567775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.1717567775
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.275302868
Short name T190
Test name
Test status
Simulation time 17538059 ps
CPU time 0.76 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201036 kb
Host smart-bc03cfc7-cdf6-4892-a257-409882166a8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275302868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.275302868
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.2303445646
Short name T633
Test name
Test status
Simulation time 15612961 ps
CPU time 0.71 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 200920 kb
Host smart-ae7970bb-94a1-4c90-aabe-017530df0ff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303445646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2303445646
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.4207682215
Short name T712
Test name
Test status
Simulation time 26958956 ps
CPU time 0.79 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201036 kb
Host smart-dc0e645a-f2e5-4230-9f4d-2632fa461e80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207682215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.4207682215
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.1093845986
Short name T749
Test name
Test status
Simulation time 54198990 ps
CPU time 0.89 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201272 kb
Host smart-bdcc3301-1c66-4d91-8776-58cafabe5957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093845986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.1093845986
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.2549561616
Short name T692
Test name
Test status
Simulation time 2402921217 ps
CPU time 8.98 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201408 kb
Host smart-19a2341d-62ba-4ea7-9740-5c521aae6e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549561616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2549561616
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.924232448
Short name T437
Test name
Test status
Simulation time 155508816 ps
CPU time 1.27 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201132 kb
Host smart-ae8c6913-95ea-4765-9784-2893b63d8c6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924232448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti
meout.924232448
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.1379999623
Short name T473
Test name
Test status
Simulation time 20982624 ps
CPU time 0.8 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201032 kb
Host smart-0452dfe1-1347-451a-8da7-976aea45fa11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379999623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.1379999623
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2609388853
Short name T299
Test name
Test status
Simulation time 28156327 ps
CPU time 0.75 seconds
Started Aug 04 05:18:48 PM PDT 24
Finished Aug 04 05:18:49 PM PDT 24
Peak memory 200972 kb
Host smart-aa37adcf-9d59-4afb-9641-101ddb691ba7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609388853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2609388853
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3278567037
Short name T374
Test name
Test status
Simulation time 42848678 ps
CPU time 0.91 seconds
Started Aug 04 05:19:07 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 201020 kb
Host smart-35f5d155-c844-4f8e-961c-53fa83b450af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278567037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.3278567037
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.3336030938
Short name T602
Test name
Test status
Simulation time 24296735 ps
CPU time 0.77 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201268 kb
Host smart-9453c04e-de7c-43c7-9443-2cab38bd73bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336030938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.3336030938
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2063240984
Short name T573
Test name
Test status
Simulation time 25870603 ps
CPU time 0.86 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200968 kb
Host smart-f503bb65-dd3d-4755-8752-31ed7ebb7d0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063240984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2063240984
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.57268481
Short name T364
Test name
Test status
Simulation time 2762441148 ps
CPU time 20.35 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:19:17 PM PDT 24
Peak memory 201372 kb
Host smart-add3be8b-61f7-46f1-8b69-be4ed5f87d2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57268481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_stress_all.57268481
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.2106651116
Short name T72
Test name
Test status
Simulation time 16616050 ps
CPU time 0.74 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 200988 kb
Host smart-045c73d3-8aa0-4a7c-a1eb-8724f90f4229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106651116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.2106651116
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.2097201068
Short name T504
Test name
Test status
Simulation time 46683621 ps
CPU time 0.86 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201072 kb
Host smart-6f34f376-715c-4fa6-8342-9acc3f5d01c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097201068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clk
mgr_alert_test.2097201068
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.115363892
Short name T627
Test name
Test status
Simulation time 18660983 ps
CPU time 0.75 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200956 kb
Host smart-50ec2ed4-2ddb-483e-bca2-86420d1feb5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115363892 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.115363892
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.215127559
Short name T410
Test name
Test status
Simulation time 18662651 ps
CPU time 0.79 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200216 kb
Host smart-806cb54d-e876-4e8a-91f2-e0af556e7558
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215127559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.215127559
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2992669645
Short name T451
Test name
Test status
Simulation time 45119022 ps
CPU time 0.82 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201084 kb
Host smart-4b83ba5b-9e18-4f63-a4eb-3e2ec0d4c3c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992669645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.2992669645
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2536420805
Short name T581
Test name
Test status
Simulation time 23800609 ps
CPU time 0.8 seconds
Started Aug 04 05:18:51 PM PDT 24
Finished Aug 04 05:18:52 PM PDT 24
Peak memory 200932 kb
Host smart-c2063915-5509-4e48-81cd-b8cc1cc7af30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536420805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2536420805
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.2484910654
Short name T16
Test name
Test status
Simulation time 1282406617 ps
CPU time 10.85 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201064 kb
Host smart-e0dfe0ba-20cd-45fd-b410-264a28486126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484910654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2484910654
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.521033756
Short name T501
Test name
Test status
Simulation time 269374723 ps
CPU time 1.57 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201092 kb
Host smart-f963d339-be89-4c12-9339-b42ca3d3eb10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521033756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_ti
meout.521033756
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3974562119
Short name T277
Test name
Test status
Simulation time 93312103 ps
CPU time 0.98 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200388 kb
Host smart-fcadb7b6-ac7c-4b35-ab02-d10f92d1998e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974562119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3974562119
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.14914653
Short name T370
Test name
Test status
Simulation time 327110169 ps
CPU time 1.75 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201020 kb
Host smart-92e7af53-ed46-4ee3-9715-46385f059107
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_lc_clk_byp_req_intersig_mubi.14914653
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.90200262
Short name T216
Test name
Test status
Simulation time 18419777 ps
CPU time 0.8 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201024 kb
Host smart-fdd2a0c4-9f6a-4354-86f9-764feee1fa99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90200262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_lc_ctrl_intersig_mubi.90200262
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.3660866563
Short name T495
Test name
Test status
Simulation time 29046272 ps
CPU time 0.74 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201028 kb
Host smart-247aa5c0-f362-4bb0-a917-2559764419fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660866563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.3660866563
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1158042637
Short name T704
Test name
Test status
Simulation time 1361466726 ps
CPU time 5.33 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201276 kb
Host smart-b4832fc1-1e76-40fe-a6d0-c1285cd86f23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158042637 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1158042637
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.3428484700
Short name T657
Test name
Test status
Simulation time 32185346 ps
CPU time 0.87 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 200940 kb
Host smart-7dacc185-96e3-429a-8779-13ddc34d1ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428484700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.3428484700
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.223806619
Short name T547
Test name
Test status
Simulation time 9861056098 ps
CPU time 32.57 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:34 PM PDT 24
Peak memory 201500 kb
Host smart-5e219ee5-ac49-4521-8afc-ef35241d0009
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223806619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.223806619
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.951694214
Short name T195
Test name
Test status
Simulation time 16478149 ps
CPU time 0.74 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200376 kb
Host smart-cbf78ecf-e760-4e52-8307-c6f3925d7121
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951694214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.951694214
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.589563094
Short name T329
Test name
Test status
Simulation time 22422729 ps
CPU time 0.85 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:54 PM PDT 24
Peak memory 201028 kb
Host smart-cba09969-97a1-4326-97f2-e29ab8b31a17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589563094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_alert_test.589563094
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.929758045
Short name T213
Test name
Test status
Simulation time 32229944 ps
CPU time 0.94 seconds
Started Aug 04 05:17:46 PM PDT 24
Finished Aug 04 05:17:47 PM PDT 24
Peak memory 201036 kb
Host smart-26fa6fb7-23bd-4e9d-9225-4836232bc06e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929758045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.929758045
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.3047116973
Short name T728
Test name
Test status
Simulation time 81655186 ps
CPU time 0.86 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:52 PM PDT 24
Peak memory 200300 kb
Host smart-4be403a9-1656-40fb-b35a-08bd12e8f921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047116973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.3047116973
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.2874479316
Short name T401
Test name
Test status
Simulation time 34022890 ps
CPU time 0.89 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:03 PM PDT 24
Peak memory 201100 kb
Host smart-905a0211-cfa6-419f-b899-61ba5b40ba11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874479316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.2874479316
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.3938853071
Short name T291
Test name
Test status
Simulation time 17247421 ps
CPU time 0.78 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 200992 kb
Host smart-9117e038-89b5-4b6b-9e4e-0c891e9ed928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938853071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3938853071
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.3515106316
Short name T125
Test name
Test status
Simulation time 941608580 ps
CPU time 4.67 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201176 kb
Host smart-040da046-bb04-4dc8-91ed-cb6a2d874003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515106316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3515106316
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.2316653934
Short name T816
Test name
Test status
Simulation time 753665940 ps
CPU time 3.4 seconds
Started Aug 04 05:17:55 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201172 kb
Host smart-229f81a8-d088-4e15-be3f-d54a0ab6b003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316653934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.2316653934
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.2427498771
Short name T516
Test name
Test status
Simulation time 26722079 ps
CPU time 0.91 seconds
Started Aug 04 05:17:47 PM PDT 24
Finished Aug 04 05:17:48 PM PDT 24
Peak memory 201072 kb
Host smart-97775f6c-b98b-49d0-a40a-b0bf728e2141
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427498771 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.2427498771
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.3366294064
Short name T751
Test name
Test status
Simulation time 50035181 ps
CPU time 0.84 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 201000 kb
Host smart-2ea2b393-061e-48bd-93b6-10cea248de06
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366294064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.3366294064
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2022942524
Short name T503
Test name
Test status
Simulation time 33195866 ps
CPU time 0.77 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201032 kb
Host smart-f00f0012-9a7d-4652-88e3-dc53fb09d565
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022942524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2022942524
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.3783063078
Short name T373
Test name
Test status
Simulation time 57085179 ps
CPU time 0.88 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201084 kb
Host smart-5b1546c3-9b68-42d0-9227-775951b34042
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783063078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3783063078
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.3982919334
Short name T155
Test name
Test status
Simulation time 1283357625 ps
CPU time 5.7 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201288 kb
Host smart-7aec8e00-92a0-43ca-815c-07946d469934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982919334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.3982919334
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.2178162218
Short name T44
Test name
Test status
Simulation time 302075255 ps
CPU time 2.24 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:56 PM PDT 24
Peak memory 216500 kb
Host smart-7603b468-ffd1-400e-ab35-9400856d066d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178162218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.2178162218
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.593942017
Short name T394
Test name
Test status
Simulation time 16293933 ps
CPU time 0.8 seconds
Started Aug 04 05:17:57 PM PDT 24
Finished Aug 04 05:17:58 PM PDT 24
Peak memory 201120 kb
Host smart-cc065a63-62d5-476a-815c-5312c5e7256f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593942017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.593942017
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.1051235191
Short name T444
Test name
Test status
Simulation time 5255524954 ps
CPU time 25.84 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:18:19 PM PDT 24
Peak memory 201680 kb
Host smart-ecdf9c66-24b6-4031-a305-4701f6c4a736
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051235191 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.1051235191
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1895547419
Short name T288
Test name
Test status
Simulation time 80918674 ps
CPU time 1 seconds
Started Aug 04 05:17:51 PM PDT 24
Finished Aug 04 05:17:52 PM PDT 24
Peak memory 201008 kb
Host smart-cec28348-e5e5-4d67-ab46-15ca086a5fbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895547419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1895547419
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.668835283
Short name T524
Test name
Test status
Simulation time 129918204 ps
CPU time 1.17 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201104 kb
Host smart-fdd7694b-8bfc-4a26-99f3-d23489da1c14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668835283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkm
gr_alert_test.668835283
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.2085748971
Short name T95
Test name
Test status
Simulation time 23416328 ps
CPU time 0.92 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200984 kb
Host smart-39deca5d-0a80-4b3c-93cd-35f78ea713a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085748971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.2085748971
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1239747219
Short name T168
Test name
Test status
Simulation time 19412232 ps
CPU time 0.77 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 200292 kb
Host smart-98e5cfab-5b90-4c6d-ba03-d1b9b30eef2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239747219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1239747219
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.4069366433
Short name T691
Test name
Test status
Simulation time 15524026 ps
CPU time 0.78 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201076 kb
Host smart-1ad3c928-5cf5-4bc7-904e-6cd5523f3b6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069366433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_div_intersig_mubi.4069366433
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1898833705
Short name T789
Test name
Test status
Simulation time 35347575 ps
CPU time 0.89 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201220 kb
Host smart-f3104c2a-6a8d-4f27-8db2-526b43ea7e08
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898833705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1898833705
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1059520400
Short name T449
Test name
Test status
Simulation time 1275793581 ps
CPU time 9.81 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 201068 kb
Host smart-415aca90-fcb1-4236-93b3-47da3ea98bb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059520400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1059520400
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1327165306
Short name T647
Test name
Test status
Simulation time 1798393009 ps
CPU time 6.57 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201212 kb
Host smart-b53115c8-2057-4179-9563-05f27e595a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327165306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1327165306
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1863240050
Short name T786
Test name
Test status
Simulation time 91759242 ps
CPU time 1.11 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201076 kb
Host smart-27d99980-8687-4b07-bd5d-e6fbe62f97d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863240050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1863240050
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.2737378852
Short name T427
Test name
Test status
Simulation time 20510033 ps
CPU time 0.87 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200632 kb
Host smart-c3ad4142-ffb0-450a-a4f6-19386490e3bc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737378852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.2737378852
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2187384704
Short name T670
Test name
Test status
Simulation time 18983014 ps
CPU time 0.79 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201296 kb
Host smart-6a4c4303-6019-4887-905f-fc6d217396e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187384704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2187384704
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2952996676
Short name T706
Test name
Test status
Simulation time 48356625 ps
CPU time 0.85 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200980 kb
Host smart-9fad3d2c-ed98-4a2a-b832-52063f3c41cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952996676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2952996676
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3341936033
Short name T344
Test name
Test status
Simulation time 1424290885 ps
CPU time 4.7 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201244 kb
Host smart-d2f8e039-ae41-40a0-ac48-5b5a4e99525a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341936033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3341936033
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.575051932
Short name T658
Test name
Test status
Simulation time 23346934 ps
CPU time 0.85 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201028 kb
Host smart-d5c8e137-5248-426a-aeab-ab964b30cb70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575051932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.575051932
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.1247954008
Short name T433
Test name
Test status
Simulation time 3441830813 ps
CPU time 26.34 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:35 PM PDT 24
Peak memory 201328 kb
Host smart-bc83f62b-8328-4516-a993-90eec7e6aa2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247954008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.1247954008
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all_with_rand_reset.3801885527
Short name T165
Test name
Test status
Simulation time 40380674625 ps
CPU time 348.44 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:24:59 PM PDT 24
Peak memory 209564 kb
Host smart-5611bc33-16bc-4723-994c-6859b7f38085
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3801885527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all_with_rand_reset.3801885527
Directory /workspace/40.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.clkmgr_trans.3183311783
Short name T379
Test name
Test status
Simulation time 23971370 ps
CPU time 0.83 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:14 PM PDT 24
Peak memory 201064 kb
Host smart-4c96bae4-bc4c-4e5c-86c1-d5eb866804f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183311783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.3183311783
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1951357931
Short name T466
Test name
Test status
Simulation time 54625472 ps
CPU time 0.81 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201096 kb
Host smart-558c6fe4-71f0-49c6-985e-374bf25ca380
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951357931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1951357931
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.2848336912
Short name T597
Test name
Test status
Simulation time 67076430 ps
CPU time 0.99 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201116 kb
Host smart-c24fe4e9-193f-4de3-88e6-50fb3dad290f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848336912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.2848336912
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3436552752
Short name T814
Test name
Test status
Simulation time 55697087 ps
CPU time 0.83 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200248 kb
Host smart-510b8b37-8c75-49f0-a214-b155c00cb611
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436552752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3436552752
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.1955252729
Short name T252
Test name
Test status
Simulation time 21689707 ps
CPU time 0.83 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201088 kb
Host smart-3fbc3704-a434-4232-b7b4-2252f740ad32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955252729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.1955252729
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.3902936081
Short name T600
Test name
Test status
Simulation time 41736674 ps
CPU time 0.81 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 200972 kb
Host smart-21bbfd18-84d2-4009-82bd-0aa3255c48f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902936081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.3902936081
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.2187111348
Short name T684
Test name
Test status
Simulation time 1239179823 ps
CPU time 5.48 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201136 kb
Host smart-393b58dd-30c3-4718-91ad-f75b1bca11de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187111348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.2187111348
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.1959007840
Short name T788
Test name
Test status
Simulation time 281955291 ps
CPU time 1.44 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200916 kb
Host smart-2fc15991-cd1c-44c4-8e6b-e7b895fb4f44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959007840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.1959007840
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1985235304
Short name T381
Test name
Test status
Simulation time 28702106 ps
CPU time 0.92 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201072 kb
Host smart-5eda0e69-698d-4064-84da-439321e33454
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985235304 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1985235304
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3486017180
Short name T668
Test name
Test status
Simulation time 62113378 ps
CPU time 0.99 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201096 kb
Host smart-5bca538e-7d09-41a9-a62f-89f4b4729cb0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486017180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3486017180
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3463169922
Short name T467
Test name
Test status
Simulation time 23965542 ps
CPU time 0.83 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200996 kb
Host smart-b3615e47-9c92-4a68-b43e-647ab9518dfa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463169922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.3463169922
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.426762608
Short name T769
Test name
Test status
Simulation time 35678746 ps
CPU time 0.81 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200968 kb
Host smart-4022b12a-2746-417e-bb3f-cd473e6cb308
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426762608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.426762608
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.3779801310
Short name T162
Test name
Test status
Simulation time 298475217 ps
CPU time 2.22 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201072 kb
Host smart-16d4bcdb-12ba-430b-9d24-4e8644b28a1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779801310 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3779801310
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.2172836414
Short name T515
Test name
Test status
Simulation time 74493637 ps
CPU time 0.99 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 201016 kb
Host smart-ab1599a0-f651-4636-927e-9bab74ad2f1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172836414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.2172836414
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.3457449587
Short name T801
Test name
Test status
Simulation time 7215005089 ps
CPU time 54.83 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:20:01 PM PDT 24
Peak memory 201460 kb
Host smart-51b5ad25-b034-437d-97ed-b596344235e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457449587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.3457449587
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.2076717175
Short name T196
Test name
Test status
Simulation time 22180388 ps
CPU time 0.87 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201040 kb
Host smart-2ae28083-1ec3-487e-a089-a893e35af438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076717175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.2076717175
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.3871368516
Short name T37
Test name
Test status
Simulation time 61335165 ps
CPU time 0.95 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201068 kb
Host smart-ad548ebd-7a95-4244-ae5f-fb745680599f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871368516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.3871368516
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2051031470
Short name T94
Test name
Test status
Simulation time 50576154 ps
CPU time 0.99 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201048 kb
Host smart-4a649f51-c0ec-4b1f-b61c-f20f5af0ee65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051031470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2051031470
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.1558879520
Short name T782
Test name
Test status
Simulation time 27675966 ps
CPU time 0.75 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200148 kb
Host smart-8dc6c6b8-be72-478d-a58c-5c7374ca00f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558879520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1558879520
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.3679370148
Short name T615
Test name
Test status
Simulation time 48490564 ps
CPU time 1.02 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201316 kb
Host smart-a752aed7-52b6-44e8-8aa7-2e6f51e03637
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679370148 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.3679370148
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.482646382
Short name T502
Test name
Test status
Simulation time 45631688 ps
CPU time 0.93 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201056 kb
Host smart-0c403846-06c6-46c0-b43b-647c7695f5a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482646382 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.482646382
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.3478650194
Short name T726
Test name
Test status
Simulation time 676670871 ps
CPU time 5.54 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201060 kb
Host smart-63432844-d723-47df-9d8f-b7264087e513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478650194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.3478650194
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.2497721793
Short name T660
Test name
Test status
Simulation time 1842684279 ps
CPU time 7.87 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201176 kb
Host smart-2d7eb10e-f128-4493-b39e-7f53fd5f6d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497721793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.2497721793
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.2531142199
Short name T563
Test name
Test status
Simulation time 13227403 ps
CPU time 0.81 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200964 kb
Host smart-90bcd6aa-ab9a-4932-ae0c-27ab8122ac5f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531142199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.2531142199
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.840921440
Short name T698
Test name
Test status
Simulation time 77380089 ps
CPU time 1.03 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200980 kb
Host smart-c8be35ef-a728-4a53-bf0b-1bb8caed3248
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840921440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_clk_byp_req_intersig_mubi.840921440
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.2520518327
Short name T747
Test name
Test status
Simulation time 93917514 ps
CPU time 1.08 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200996 kb
Host smart-4728f8b5-f26a-4f73-b9d1-05423481f28d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520518327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.2520518327
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.1503621095
Short name T618
Test name
Test status
Simulation time 14925111 ps
CPU time 0.79 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201288 kb
Host smart-ca60d21c-deab-4c83-ad55-f2a9442058d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503621095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1503621095
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.2724217772
Short name T279
Test name
Test status
Simulation time 645742700 ps
CPU time 2.73 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201152 kb
Host smart-f05fabea-da02-4ea3-978c-98102cae4803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724217772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2724217772
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.1163984898
Short name T306
Test name
Test status
Simulation time 18415205 ps
CPU time 0.86 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200940 kb
Host smart-6b6364ef-7b0c-4c75-9ac8-b817a0d29ab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163984898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.1163984898
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.3261586161
Short name T532
Test name
Test status
Simulation time 1603848147 ps
CPU time 12.7 seconds
Started Aug 04 05:19:11 PM PDT 24
Finished Aug 04 05:19:24 PM PDT 24
Peak memory 201608 kb
Host smart-f98a75b0-ecf9-4b5d-afd5-c185c631aff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261586161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.3261586161
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.1871106986
Short name T610
Test name
Test status
Simulation time 135314941533 ps
CPU time 657.72 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:30:08 PM PDT 24
Peak memory 217808 kb
Host smart-e784cf4f-917b-4250-9ee0-2a5ddc0d02fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1871106986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.1871106986
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1905825895
Short name T686
Test name
Test status
Simulation time 61139712 ps
CPU time 1.04 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200984 kb
Host smart-ec47b07a-86a6-4397-a202-51ca3eaa8bbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905825895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1905825895
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.2996628236
Short name T752
Test name
Test status
Simulation time 88641354 ps
CPU time 0.98 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201112 kb
Host smart-b4d3b9a0-1ab2-4372-b1f2-42ddea19e0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996628236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.2996628236
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.606548397
Short name T716
Test name
Test status
Simulation time 31861386 ps
CPU time 1.08 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201036 kb
Host smart-f7a78971-8a66-45f7-831a-2fe429f7b90f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606548397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.606548397
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.3066004812
Short name T169
Test name
Test status
Simulation time 44884536 ps
CPU time 0.79 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 200284 kb
Host smart-3f879014-88c6-4923-9d85-54329c8b3b45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066004812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3066004812
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2118340713
Short name T161
Test name
Test status
Simulation time 30902908 ps
CPU time 0.94 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201008 kb
Host smart-e1ae2d9f-47f0-4bce-9f16-f438a815b906
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118340713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2118340713
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.6714818
Short name T388
Test name
Test status
Simulation time 24362613 ps
CPU time 0.77 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201288 kb
Host smart-31fd1369-dd58-4a6d-875a-9383e39e5128
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6714818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.6714818
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.477275231
Short name T33
Test name
Test status
Simulation time 1651749390 ps
CPU time 9.73 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201164 kb
Host smart-bc699b43-fd37-44c9-85f4-385bcbb89cf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477275231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.477275231
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.3420255724
Short name T529
Test name
Test status
Simulation time 12757182 ps
CPU time 0.73 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 201092 kb
Host smart-2615202b-dd06-4e60-a126-4c721ea7935a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420255724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.3420255724
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1448678064
Short name T718
Test name
Test status
Simulation time 29811791 ps
CPU time 0.8 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201100 kb
Host smart-4ba921d2-1ffc-46d3-a474-f3700b912968
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448678064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.1448678064
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.447167447
Short name T233
Test name
Test status
Simulation time 104329551 ps
CPU time 1.03 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201056 kb
Host smart-bb9cb895-ae69-42bc-86da-a2efe3a0a743
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447167447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.447167447
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.513137462
Short name T811
Test name
Test status
Simulation time 18363910 ps
CPU time 0.81 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201032 kb
Host smart-078f8e57-ad2a-4ff6-b4ec-bf5eb667b2dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513137462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.513137462
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.907918315
Short name T151
Test name
Test status
Simulation time 112146713 ps
CPU time 1.15 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200976 kb
Host smart-95ef61da-bad3-4589-b93f-e8cb06cfc776
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907918315 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.907918315
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.3595170708
Short name T146
Test name
Test status
Simulation time 24436414 ps
CPU time 0.91 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 201312 kb
Host smart-b3e31de8-8051-4671-adf8-8811ba4c07b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595170708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3595170708
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.2763783986
Short name T408
Test name
Test status
Simulation time 4168559452 ps
CPU time 23.93 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:27 PM PDT 24
Peak memory 201508 kb
Host smart-1d66cd7e-5672-4ec4-87a1-23ca9ef0d6d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763783986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.2763783986
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2430481260
Short name T440
Test name
Test status
Simulation time 14831994 ps
CPU time 0.78 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200968 kb
Host smart-eea28b19-a68d-4afc-be89-588e6d1d130f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430481260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2430481260
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.2759964661
Short name T424
Test name
Test status
Simulation time 13719248 ps
CPU time 0.74 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200888 kb
Host smart-2f63386f-5380-4a02-bca6-a109b0d24507
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759964661 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.2759964661
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1553438216
Short name T280
Test name
Test status
Simulation time 17760982 ps
CPU time 0.78 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200932 kb
Host smart-3515991b-135e-4821-a9d1-fd658580c4e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553438216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1553438216
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.497602859
Short name T683
Test name
Test status
Simulation time 75651015 ps
CPU time 0.84 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200152 kb
Host smart-3e940f88-db20-4fb7-99a9-95e7fc2599d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497602859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.497602859
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.564394515
Short name T474
Test name
Test status
Simulation time 28419146 ps
CPU time 0.75 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201012 kb
Host smart-c1dd13bb-9fee-4e57-a52a-579019f8d926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564394515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.564394515
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2923559314
Short name T798
Test name
Test status
Simulation time 951363853 ps
CPU time 4.64 seconds
Started Aug 04 05:19:07 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201096 kb
Host smart-57a5f7e5-4a81-4a73-98fa-6235805e2a09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923559314 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2923559314
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.4116455651
Short name T6
Test name
Test status
Simulation time 773958117 ps
CPU time 3.66 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201164 kb
Host smart-243ac825-c8e2-4cd2-8c73-b01343295287
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116455651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.4116455651
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.432048539
Short name T371
Test name
Test status
Simulation time 324363815 ps
CPU time 1.7 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 200960 kb
Host smart-d0e06359-02a1-45d0-8fb4-aac233b08343
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432048539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.432048539
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3533664151
Short name T406
Test name
Test status
Simulation time 70451436 ps
CPU time 0.98 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201108 kb
Host smart-0db27b75-263c-42eb-90dc-80b81082da29
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533664151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3533664151
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3667680215
Short name T672
Test name
Test status
Simulation time 127199108 ps
CPU time 1.22 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201100 kb
Host smart-3f0a8e45-ea9f-47f0-aaba-d8197381d96c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667680215 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.3667680215
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.970793845
Short name T254
Test name
Test status
Simulation time 14502533 ps
CPU time 0.73 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200948 kb
Host smart-1d72eb46-9c10-48b6-98db-4a7f20b5e48e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970793845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.970793845
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.1532036231
Short name T387
Test name
Test status
Simulation time 1129790790 ps
CPU time 6.2 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201244 kb
Host smart-a33f3195-d9dc-4e5c-a020-e95824b22ed6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532036231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1532036231
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1572533904
Short name T560
Test name
Test status
Simulation time 21442060 ps
CPU time 0.88 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 200880 kb
Host smart-f46bedb4-53e2-4599-83df-75f3a878eb60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572533904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1572533904
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.807893139
Short name T347
Test name
Test status
Simulation time 4238838600 ps
CPU time 19.09 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:29 PM PDT 24
Peak memory 201308 kb
Host smart-9508d1de-7139-45e0-8e6f-698339aef0bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807893139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.807893139
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.2169666949
Short name T275
Test name
Test status
Simulation time 39113348 ps
CPU time 1.1 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200972 kb
Host smart-e05bdee5-f1f0-48be-a40c-eaa88d297a9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169666949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.2169666949
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.1370209443
Short name T755
Test name
Test status
Simulation time 127566852 ps
CPU time 1.04 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201104 kb
Host smart-9d400128-7c22-472f-ba80-acf75a9b7872
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370209443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.1370209443
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.1965721570
Short name T567
Test name
Test status
Simulation time 30034184 ps
CPU time 0.78 seconds
Started Aug 04 05:19:12 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 200944 kb
Host smart-f286f206-9d3e-40b6-a8cd-4be1d921acaf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965721570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.1965721570
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3669521531
Short name T353
Test name
Test status
Simulation time 29315459 ps
CPU time 0.76 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200976 kb
Host smart-50c5df86-1e95-4447-9b97-667969eb215e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669521531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3669521531
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.3340762032
Short name T736
Test name
Test status
Simulation time 115561198 ps
CPU time 1.19 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201100 kb
Host smart-a28b35d1-d2cc-4e8e-b67c-459fda6dd838
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340762032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.3340762032
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.2996964392
Short name T753
Test name
Test status
Simulation time 19627588 ps
CPU time 0.84 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201032 kb
Host smart-de6e774a-eba8-4068-8ae7-f1c60aa504ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996964392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2996964392
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.2152113765
Short name T471
Test name
Test status
Simulation time 2241460529 ps
CPU time 9.73 seconds
Started Aug 04 05:19:31 PM PDT 24
Finished Aug 04 05:19:41 PM PDT 24
Peak memory 201308 kb
Host smart-96f06616-e8ae-45ff-aeeb-6330838e4c6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152113765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.2152113765
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.4152846081
Short name T480
Test name
Test status
Simulation time 1215864467 ps
CPU time 9.34 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:14 PM PDT 24
Peak memory 201108 kb
Host smart-10c4bfab-0593-4440-8417-dde6f04be6e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152846081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.4152846081
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2726746532
Short name T403
Test name
Test status
Simulation time 51351103 ps
CPU time 1.06 seconds
Started Aug 04 05:18:54 PM PDT 24
Finished Aug 04 05:18:55 PM PDT 24
Peak memory 201004 kb
Host smart-fb69abfe-5935-46ae-8cad-3d588a375312
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726746532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2726746532
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1124614060
Short name T384
Test name
Test status
Simulation time 24088740 ps
CPU time 0.86 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201000 kb
Host smart-9e221fba-e2d0-428a-acd3-5ec1f0a0032e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124614060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1124614060
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.401462203
Short name T346
Test name
Test status
Simulation time 39047569 ps
CPU time 0.86 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201004 kb
Host smart-7f987367-a1dd-46c7-a79c-ebb6b8dfc6a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401462203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 45.clkmgr_lc_ctrl_intersig_mubi.401462203
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.1679659298
Short name T693
Test name
Test status
Simulation time 17654749 ps
CPU time 0.77 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201096 kb
Host smart-7a7d5fb4-e9f1-4fb1-b030-bf8ad0bb9530
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679659298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.1679659298
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.1484882884
Short name T89
Test name
Test status
Simulation time 304250791 ps
CPU time 2.19 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 200952 kb
Host smart-8f3ffb3f-79f3-44fa-9d0b-ce0504d40666
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484882884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.1484882884
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2066322860
Short name T469
Test name
Test status
Simulation time 90707267 ps
CPU time 1.05 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 200948 kb
Host smart-d3e61399-8a35-4596-9f83-8aa5c90a4db6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066322860 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2066322860
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.73687093
Short name T10
Test name
Test status
Simulation time 5663263651 ps
CPU time 36.99 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:19:50 PM PDT 24
Peak memory 201492 kb
Host smart-5a5d3be9-3838-460f-8716-394da24c5824
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73687093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_stress_all.73687093
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3297223723
Short name T446
Test name
Test status
Simulation time 72251031 ps
CPU time 1.11 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:00 PM PDT 24
Peak memory 201076 kb
Host smart-cc3f67fc-722a-4462-b07f-c37146087cfc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297223723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3297223723
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3884966410
Short name T796
Test name
Test status
Simulation time 49274261 ps
CPU time 0.84 seconds
Started Aug 04 05:19:45 PM PDT 24
Finished Aug 04 05:19:46 PM PDT 24
Peak memory 201080 kb
Host smart-adf2fd2e-3368-43e1-bc0d-a6ae869cb68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884966410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3884966410
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.842179316
Short name T108
Test name
Test status
Simulation time 38451128 ps
CPU time 0.85 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201008 kb
Host smart-b8c1213d-7f4a-4b0b-a5ec-ab6262e3719b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842179316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.842179316
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.610488056
Short name T508
Test name
Test status
Simulation time 15097381 ps
CPU time 0.71 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 200196 kb
Host smart-ddd84abb-6dcb-41ef-b0b5-1d07384000c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610488056 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.610488056
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.376125459
Short name T453
Test name
Test status
Simulation time 237811658 ps
CPU time 1.49 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200996 kb
Host smart-1d4e62fa-ca53-4b8d-a2fe-644591156664
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376125459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_div_intersig_mubi.376125459
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.3742871770
Short name T302
Test name
Test status
Simulation time 25202033 ps
CPU time 0.88 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:02 PM PDT 24
Peak memory 200976 kb
Host smart-a39ca942-098f-43e2-90e6-8c3afea9d02a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742871770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.3742871770
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.3823861418
Short name T636
Test name
Test status
Simulation time 936165472 ps
CPU time 4.6 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 201068 kb
Host smart-4ec69f87-2aad-45e7-91f4-b07682925a2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823861418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3823861418
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.1705135570
Short name T536
Test name
Test status
Simulation time 2156688835 ps
CPU time 8.62 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:17 PM PDT 24
Peak memory 201348 kb
Host smart-6921fdf8-a7ce-408f-a592-4fffad2adfd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705135570 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.1705135570
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.3168199446
Short name T439
Test name
Test status
Simulation time 26229349 ps
CPU time 0.86 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201084 kb
Host smart-9dc910b9-35c0-44aa-a32b-7be2aae626c0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168199446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.3168199446
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3095524313
Short name T273
Test name
Test status
Simulation time 36932213 ps
CPU time 0.89 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200940 kb
Host smart-728dacfb-5350-4861-aa71-832bb6c9fcf3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095524313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_clk_byp_req_intersig_mubi.3095524313
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.2578422451
Short name T391
Test name
Test status
Simulation time 27638875 ps
CPU time 0.79 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201104 kb
Host smart-738591fa-9495-415c-a9da-8b92a3b007b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578422451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.2578422451
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.442099267
Short name T707
Test name
Test status
Simulation time 36330370 ps
CPU time 0.75 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201080 kb
Host smart-2718715a-cf9a-4e31-b0ac-d7a90799a067
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442099267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.442099267
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.178350838
Short name T605
Test name
Test status
Simulation time 884501227 ps
CPU time 3.49 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201252 kb
Host smart-fe9e299a-0693-40be-b46d-278c82a31769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178350838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.178350838
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.3096934649
Short name T592
Test name
Test status
Simulation time 26485712 ps
CPU time 0.81 seconds
Started Aug 04 05:19:07 PM PDT 24
Finished Aug 04 05:19:08 PM PDT 24
Peak memory 201000 kb
Host smart-a7b6dd59-3917-46c5-9b08-5559cd557859
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096934649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3096934649
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.2164421136
Short name T253
Test name
Test status
Simulation time 6185413027 ps
CPU time 46.39 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:49 PM PDT 24
Peak memory 201344 kb
Host smart-8a2e5d26-b29b-4c18-9d18-c9568fdb05aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164421136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.2164421136
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.705080517
Short name T69
Test name
Test status
Simulation time 18355958924 ps
CPU time 279.61 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:23:43 PM PDT 24
Peak memory 217808 kb
Host smart-6ec3e4d5-f6a8-4431-b9a6-96c1f5b5a485
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=705080517 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.705080517
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.591867160
Short name T700
Test name
Test status
Simulation time 109711643 ps
CPU time 1.24 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200956 kb
Host smart-9a96fe77-287a-4ee1-813d-87668a281d47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591867160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.591867160
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.540607269
Short name T236
Test name
Test status
Simulation time 25345912 ps
CPU time 0.8 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 201072 kb
Host smart-7affb78b-b53d-4fc5-92cd-25ae8649ac22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540607269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkm
gr_alert_test.540607269
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2490984912
Short name T819
Test name
Test status
Simulation time 28030091 ps
CPU time 0.76 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 200972 kb
Host smart-4d777963-a16d-467b-a6a2-40fbbd5136b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490984912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2490984912
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1127985352
Short name T522
Test name
Test status
Simulation time 40751334 ps
CPU time 0.77 seconds
Started Aug 04 05:19:09 PM PDT 24
Finished Aug 04 05:19:10 PM PDT 24
Peak memory 200172 kb
Host smart-5580b1bf-a15d-4e29-9a43-aa7c3dae57d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127985352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1127985352
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.263399167
Short name T746
Test name
Test status
Simulation time 58993555 ps
CPU time 0.89 seconds
Started Aug 04 05:19:04 PM PDT 24
Finished Aug 04 05:19:05 PM PDT 24
Peak memory 201040 kb
Host smart-7494f3e4-3287-4226-8e48-d2f43a4f5969
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263399167 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.clkmgr_div_intersig_mubi.263399167
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.442703894
Short name T701
Test name
Test status
Simulation time 68043234 ps
CPU time 0.94 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201036 kb
Host smart-df751afd-6ddf-436d-a9ec-741cb119e00d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442703894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.442703894
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.3611545387
Short name T414
Test name
Test status
Simulation time 2179810922 ps
CPU time 9.06 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201360 kb
Host smart-96c91fa8-f678-4232-a49c-3dd9c015e306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611545387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3611545387
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.608863956
Short name T47
Test name
Test status
Simulation time 137250923 ps
CPU time 1.53 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:57 PM PDT 24
Peak memory 201176 kb
Host smart-4b32c8c5-28a0-424d-9ab4-12c83c8b51cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608863956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.608863956
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.56366292
Short name T711
Test name
Test status
Simulation time 45088942 ps
CPU time 0.86 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201028 kb
Host smart-fb4e81a6-14e5-421d-af92-a21693584c16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56366292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.clkmgr_idle_intersig_mubi.56366292
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3355842825
Short name T792
Test name
Test status
Simulation time 76122946 ps
CPU time 1.04 seconds
Started Aug 04 05:18:57 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 201100 kb
Host smart-c125dcf0-99ca-44a5-98f3-cb74f6796bd5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355842825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3355842825
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.2711046164
Short name T689
Test name
Test status
Simulation time 58228376 ps
CPU time 0.81 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 201080 kb
Host smart-1be0a360-59fe-4a08-a4c1-0a1d10ff993c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711046164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.2711046164
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.373400757
Short name T621
Test name
Test status
Simulation time 105872800 ps
CPU time 0.99 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 201080 kb
Host smart-8cf3dc61-903f-4ff5-9737-bd5331dfd2e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373400757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.373400757
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.2556013306
Short name T153
Test name
Test status
Simulation time 128412744 ps
CPU time 1.05 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 200984 kb
Host smart-1e576488-4bdc-4a60-9448-3e02cae309b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556013306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.2556013306
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.1364068992
Short name T562
Test name
Test status
Simulation time 21125280 ps
CPU time 0.85 seconds
Started Aug 04 05:18:59 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201084 kb
Host smart-6c0dc381-612e-49a6-a977-c1f1db3a1202
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364068992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1364068992
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_trans.2412345086
Short name T591
Test name
Test status
Simulation time 37265422 ps
CPU time 1.04 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 201100 kb
Host smart-c9660324-34bc-450b-8415-0600d897bd1f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412345086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.2412345086
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.402021329
Short name T261
Test name
Test status
Simulation time 13940590 ps
CPU time 0.77 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 200996 kb
Host smart-c5f510fe-9780-475d-9d83-46f5f7359be8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402021329 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkm
gr_alert_test.402021329
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.411996032
Short name T541
Test name
Test status
Simulation time 50558823 ps
CPU time 0.84 seconds
Started Aug 04 05:19:11 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201032 kb
Host smart-0e208995-dd42-4336-b3b3-3f7dfd99f6d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411996032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.411996032
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.1137458281
Short name T345
Test name
Test status
Simulation time 16058913 ps
CPU time 0.72 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 200312 kb
Host smart-5da32f34-c350-4d42-9980-d76c1990608b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137458281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.1137458281
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.2723171317
Short name T337
Test name
Test status
Simulation time 158820395 ps
CPU time 1.19 seconds
Started Aug 04 05:19:12 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 200948 kb
Host smart-be2fa348-9604-401f-8419-155623d80eb6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723171317 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.2723171317
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.830211248
Short name T488
Test name
Test status
Simulation time 61242881 ps
CPU time 0.99 seconds
Started Aug 04 05:19:11 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 201084 kb
Host smart-f0437a71-6bff-47f3-9279-f789f658ded5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830211248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.830211248
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.431056781
Short name T648
Test name
Test status
Simulation time 561532678 ps
CPU time 5.01 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 201164 kb
Host smart-50fd2ab4-c956-43e9-897f-585be3e6a62c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431056781 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.431056781
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.250383555
Short name T526
Test name
Test status
Simulation time 866477444 ps
CPU time 4.95 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 201020 kb
Host smart-889adb78-c7fa-4b90-90ab-59fe375e8191
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250383555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_ti
meout.250383555
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.2268605198
Short name T180
Test name
Test status
Simulation time 29093967 ps
CPU time 0.78 seconds
Started Aug 04 05:18:55 PM PDT 24
Finished Aug 04 05:18:56 PM PDT 24
Peak memory 201088 kb
Host smart-67d17782-4f76-4667-8f34-84ed8f5cb258
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268605198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.2268605198
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1872182532
Short name T224
Test name
Test status
Simulation time 94660613 ps
CPU time 1.09 seconds
Started Aug 04 05:19:12 PM PDT 24
Finished Aug 04 05:19:13 PM PDT 24
Peak memory 201100 kb
Host smart-19800eec-f5da-424e-a73e-3dfaf76e6d46
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872182532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.1872182532
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.2840235067
Short name T793
Test name
Test status
Simulation time 185010406 ps
CPU time 1.26 seconds
Started Aug 04 05:18:56 PM PDT 24
Finished Aug 04 05:18:58 PM PDT 24
Peak memory 200988 kb
Host smart-4439dc8b-fd1d-4834-83a0-415a00e0b802
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840235067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.2840235067
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.4175797149
Short name T654
Test name
Test status
Simulation time 34966203 ps
CPU time 0.77 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201056 kb
Host smart-bb401795-e299-4b89-9ba5-f78e458456e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175797149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.4175797149
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.2212404880
Short name T538
Test name
Test status
Simulation time 376315158 ps
CPU time 1.87 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201036 kb
Host smart-46209b99-f5bc-477e-978b-6d4323f5ffca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212404880 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.2212404880
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.2300912938
Short name T419
Test name
Test status
Simulation time 95169696 ps
CPU time 1.09 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:07 PM PDT 24
Peak memory 200940 kb
Host smart-59955a43-e623-4c3d-a99d-85e483d4cd0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300912938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.2300912938
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.3943998287
Short name T781
Test name
Test status
Simulation time 2107987102 ps
CPU time 9.48 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:14 PM PDT 24
Peak memory 201220 kb
Host smart-8033c231-f323-4617-88e8-a7bf4c6dd27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943998287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.3943998287
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.3578076480
Short name T225
Test name
Test status
Simulation time 42008839 ps
CPU time 0.8 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:01 PM PDT 24
Peak memory 201044 kb
Host smart-f5293561-964c-4576-afd7-c8d524720990
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578076480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.3578076480
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1467868217
Short name T680
Test name
Test status
Simulation time 14484357 ps
CPU time 0.76 seconds
Started Aug 04 05:19:02 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200960 kb
Host smart-cdda312c-f102-4128-bead-6fd28a1cf6db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467868217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1467868217
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.2669341665
Short name T616
Test name
Test status
Simulation time 25507595 ps
CPU time 0.92 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200984 kb
Host smart-a4a598a3-f604-433b-aae0-584f2f6edfe7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669341665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.2669341665
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.515337468
Short name T41
Test name
Test status
Simulation time 97478846 ps
CPU time 0.92 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:03 PM PDT 24
Peak memory 200276 kb
Host smart-7d008a98-cc5e-45e3-ab9f-d099ac491393
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515337468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.515337468
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2330933352
Short name T483
Test name
Test status
Simulation time 37001346 ps
CPU time 0.8 seconds
Started Aug 04 05:19:11 PM PDT 24
Finished Aug 04 05:19:12 PM PDT 24
Peak memory 200992 kb
Host smart-07c50cbb-fef6-4ba6-91cb-101148151f6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330933352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2330933352
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.1053004074
Short name T334
Test name
Test status
Simulation time 25470487 ps
CPU time 0.93 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 200984 kb
Host smart-38078741-0e78-4edf-b237-8ddd5ddd8e76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053004074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.1053004074
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.3757926258
Short name T124
Test name
Test status
Simulation time 1881841473 ps
CPU time 14.81 seconds
Started Aug 04 05:19:00 PM PDT 24
Finished Aug 04 05:19:15 PM PDT 24
Peak memory 201276 kb
Host smart-42a53f23-8d1a-4ffc-947a-358c17f883ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757926258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3757926258
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.276527279
Short name T188
Test name
Test status
Simulation time 1817238365 ps
CPU time 12.77 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:21 PM PDT 24
Peak memory 201108 kb
Host smart-bb539009-b099-4562-b474-5376f8fbcc3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276527279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti
meout.276527279
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2181621433
Short name T457
Test name
Test status
Simulation time 48411039 ps
CPU time 0.85 seconds
Started Aug 04 05:19:29 PM PDT 24
Finished Aug 04 05:19:30 PM PDT 24
Peak memory 201076 kb
Host smart-00b6db68-7316-4c17-a4e2-b2fab15aa53a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181621433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2181621433
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2023367375
Short name T800
Test name
Test status
Simulation time 18754884 ps
CPU time 0.76 seconds
Started Aug 04 05:19:08 PM PDT 24
Finished Aug 04 05:19:09 PM PDT 24
Peak memory 200924 kb
Host smart-24c22b69-caa3-4645-a80a-c8f94c3912fb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023367375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2023367375
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.675992438
Short name T468
Test name
Test status
Simulation time 51229411 ps
CPU time 0.86 seconds
Started Aug 04 05:19:10 PM PDT 24
Finished Aug 04 05:19:11 PM PDT 24
Peak memory 200956 kb
Host smart-b630905f-de37-4a41-a400-81c8504da8ad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675992438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 49.clkmgr_lc_ctrl_intersig_mubi.675992438
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1882626678
Short name T727
Test name
Test status
Simulation time 61037948 ps
CPU time 0.85 seconds
Started Aug 04 05:19:05 PM PDT 24
Finished Aug 04 05:19:06 PM PDT 24
Peak memory 200960 kb
Host smart-81639c6f-e80c-446d-8a75-b5cfafa5a036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882626678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1882626678
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.3130347340
Short name T305
Test name
Test status
Simulation time 669043166 ps
CPU time 2.68 seconds
Started Aug 04 05:19:01 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201292 kb
Host smart-2a5e09bd-6b73-4d3f-8dfb-c097f579db41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130347340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3130347340
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.1093475832
Short name T710
Test name
Test status
Simulation time 71814857 ps
CPU time 0.94 seconds
Started Aug 04 05:19:03 PM PDT 24
Finished Aug 04 05:19:04 PM PDT 24
Peak memory 201020 kb
Host smart-b04fd9c9-09e4-4487-91b5-3d76a1e310da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093475832 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1093475832
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.3820738376
Short name T812
Test name
Test status
Simulation time 8953984436 ps
CPU time 65.85 seconds
Started Aug 04 05:19:06 PM PDT 24
Finished Aug 04 05:20:12 PM PDT 24
Peak memory 201352 kb
Host smart-98bcf84c-519b-46af-9e4f-081d2041267a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820738376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.3820738376
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.1644464522
Short name T500
Test name
Test status
Simulation time 59604849 ps
CPU time 0.89 seconds
Started Aug 04 05:18:58 PM PDT 24
Finished Aug 04 05:18:59 PM PDT 24
Peak memory 201084 kb
Host smart-e0022fbd-972a-4029-ad12-3dd309f4da14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644464522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.1644464522
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.2945630942
Short name T316
Test name
Test status
Simulation time 16707733 ps
CPU time 0.77 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:17:56 PM PDT 24
Peak memory 201100 kb
Host smart-92b918fe-0ab8-4604-8ed6-3019ca63b5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945630942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.2945630942
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1806590237
Short name T572
Test name
Test status
Simulation time 28882277 ps
CPU time 0.81 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201116 kb
Host smart-b46dac6a-57a1-4ca5-946a-107ded50f23b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806590237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.1806590237
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.2846738803
Short name T249
Test name
Test status
Simulation time 23686174 ps
CPU time 0.72 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 200328 kb
Host smart-6262f425-15e0-480b-b221-74c45f10805b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846738803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2846738803
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.2138985340
Short name T791
Test name
Test status
Simulation time 26522610 ps
CPU time 0.89 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 201092 kb
Host smart-ac9b2935-6447-41f3-8648-42a93999972e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138985340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.2138985340
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.3159062250
Short name T530
Test name
Test status
Simulation time 23401427 ps
CPU time 0.82 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201100 kb
Host smart-fdeede9d-3485-4a1a-a89e-afe916d34e47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159062250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.3159062250
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.1586371217
Short name T576
Test name
Test status
Simulation time 463359937 ps
CPU time 2.64 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201088 kb
Host smart-89e44f92-28e1-4234-abd6-d2cc67a60412
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586371217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.1586371217
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.464824307
Short name T289
Test name
Test status
Simulation time 256165906 ps
CPU time 2.45 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 201160 kb
Host smart-6e049501-fe8c-4e86-9997-154c81d5a4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464824307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim
eout.464824307
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.2918493604
Short name T609
Test name
Test status
Simulation time 40930849 ps
CPU time 1.09 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201092 kb
Host smart-04f79fd3-9a3f-4473-8231-6fa51c17facb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918493604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.2918493604
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.4159441077
Short name T506
Test name
Test status
Simulation time 165605009 ps
CPU time 1.26 seconds
Started Aug 04 05:17:54 PM PDT 24
Finished Aug 04 05:17:55 PM PDT 24
Peak memory 201036 kb
Host smart-5cb4c805-dcc7-4e6e-8074-745f6d37be6a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159441077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.4159441077
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.2328205260
Short name T450
Test name
Test status
Simulation time 71034419 ps
CPU time 1 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 201028 kb
Host smart-4eb84c84-0e74-46c4-bb57-3c5c2a359853
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328205260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_ctrl_intersig_mubi.2328205260
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3040852475
Short name T525
Test name
Test status
Simulation time 16679449 ps
CPU time 0.75 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 201068 kb
Host smart-998b2516-d472-4dd8-bc0d-a07442269020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040852475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3040852475
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.1410696172
Short name T697
Test name
Test status
Simulation time 1223936218 ps
CPU time 4.31 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201176 kb
Host smart-76930220-23a2-4fcf-9095-ed7a65eb734b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410696172 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.1410696172
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.286579227
Short name T90
Test name
Test status
Simulation time 16849446 ps
CPU time 0.81 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201068 kb
Host smart-daae966d-0e00-44d1-ae1a-c4dda81b46cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286579227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.286579227
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.113946109
Short name T622
Test name
Test status
Simulation time 2796321207 ps
CPU time 11.75 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201408 kb
Host smart-049454e1-0195-4b72-9817-783c1734ce1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113946109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.113946109
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.3099280554
Short name T68
Test name
Test status
Simulation time 101952889777 ps
CPU time 649.94 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:28:56 PM PDT 24
Peak memory 217872 kb
Host smart-4fc4e0e0-369c-4d3e-8d38-1d28a1c70627
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3099280554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.3099280554
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.4285180133
Short name T493
Test name
Test status
Simulation time 70295803 ps
CPU time 1.16 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201112 kb
Host smart-23179ac8-5566-45fe-9540-81104ab05cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285180133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.4285180133
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.2260402754
Short name T39
Test name
Test status
Simulation time 70482183 ps
CPU time 0.98 seconds
Started Aug 04 05:17:50 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201124 kb
Host smart-df25296a-954e-45c6-8e86-a957d4844c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260402754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.2260402754
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.2683936355
Short name T549
Test name
Test status
Simulation time 89940109 ps
CPU time 1.07 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200936 kb
Host smart-a073db22-c038-43d2-af64-ee1650ea4e5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683936355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.2683936355
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.3554159487
Short name T171
Test name
Test status
Simulation time 63359029 ps
CPU time 0.79 seconds
Started Aug 04 05:17:58 PM PDT 24
Finished Aug 04 05:17:59 PM PDT 24
Peak memory 200212 kb
Host smart-dd1fd871-3cd4-4725-b179-6704ff9e7e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554159487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.3554159487
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.3295587541
Short name T737
Test name
Test status
Simulation time 18702105 ps
CPU time 0.77 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:13 PM PDT 24
Peak memory 200932 kb
Host smart-604c4329-6cdb-49d9-95d2-80c704f68826
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295587541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.3295587541
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.3479501135
Short name T208
Test name
Test status
Simulation time 48282593 ps
CPU time 0.91 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 201076 kb
Host smart-b26b6d9b-a3f0-4b12-9da8-4971d6bb5598
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479501135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.3479501135
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.4253761982
Short name T432
Test name
Test status
Simulation time 2362029457 ps
CPU time 13.26 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201416 kb
Host smart-8aadc71b-5813-4603-a792-fd58abbf98c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253761982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.4253761982
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.741001443
Short name T295
Test name
Test status
Simulation time 134650357 ps
CPU time 1.62 seconds
Started Aug 04 05:18:02 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201120 kb
Host smart-59ff360a-6a35-4114-ad37-3ddf0acc2c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741001443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim
eout.741001443
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3174523112
Short name T338
Test name
Test status
Simulation time 22916104 ps
CPU time 0.88 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201004 kb
Host smart-5b389f0f-2177-4f74-975c-c9157453efce
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174523112 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3174523112
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.1880104488
Short name T665
Test name
Test status
Simulation time 25793966 ps
CPU time 0.76 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201008 kb
Host smart-2e79e3fc-4e28-47ce-b682-b774e12bd2fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880104488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.1880104488
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.1775334492
Short name T303
Test name
Test status
Simulation time 44999348 ps
CPU time 0.84 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201060 kb
Host smart-4bc3cedc-6579-4401-9a3e-a52867e1f914
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775334492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.1775334492
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.1970175907
Short name T758
Test name
Test status
Simulation time 44890635 ps
CPU time 0.81 seconds
Started Aug 04 05:17:52 PM PDT 24
Finished Aug 04 05:17:53 PM PDT 24
Peak memory 200996 kb
Host smart-3ecbd356-481d-459e-bae7-aaed9e6984e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970175907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1970175907
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.2366429280
Short name T539
Test name
Test status
Simulation time 992499739 ps
CPU time 5.46 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201244 kb
Host smart-0c54d746-0e04-46b5-8712-48fe8c622512
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366429280 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2366429280
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.2471901972
Short name T80
Test name
Test status
Simulation time 27172205 ps
CPU time 0.9 seconds
Started Aug 04 05:17:59 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 200948 kb
Host smart-72595345-8ae3-430f-bc48-dc888c2c6600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471901972 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.2471901972
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_trans.3261227460
Short name T528
Test name
Test status
Simulation time 21422167 ps
CPU time 0.88 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201088 kb
Host smart-3019687b-be10-46d4-8288-f3f34bd275a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261227460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.3261227460
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.2004712762
Short name T677
Test name
Test status
Simulation time 19110817 ps
CPU time 0.82 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:17:57 PM PDT 24
Peak memory 201092 kb
Host smart-0587337e-208a-4d47-bee6-2d6da0ee3795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004712762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.2004712762
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1043224337
Short name T652
Test name
Test status
Simulation time 14069279 ps
CPU time 0.75 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:00 PM PDT 24
Peak memory 201072 kb
Host smart-59e9ec0f-146e-419f-87c7-74b1709878b0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043224337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1043224337
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2383465597
Short name T807
Test name
Test status
Simulation time 14259038 ps
CPU time 0.71 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 200224 kb
Host smart-ef9a8c3b-a4c5-4e23-a1fa-7895ad353a79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383465597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2383465597
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.2013681810
Short name T643
Test name
Test status
Simulation time 74882710 ps
CPU time 1.01 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 201044 kb
Host smart-26fc8bd7-efcb-4d63-a040-de550006dc0e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013681810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.2013681810
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.478967934
Short name T443
Test name
Test status
Simulation time 71718579 ps
CPU time 1.05 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 200908 kb
Host smart-ef6ea829-8bfd-4a08-b847-049f219670ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478967934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.478967934
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.3947006766
Short name T745
Test name
Test status
Simulation time 1305809794 ps
CPU time 6.27 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201040 kb
Host smart-2b83c184-8b89-4468-9853-d8abad93c7f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947006766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3947006766
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.3590810223
Short name T157
Test name
Test status
Simulation time 1217271094 ps
CPU time 8.4 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201164 kb
Host smart-5ef4f5da-7065-4552-a50a-79619d95a550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590810223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.3590810223
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3854992197
Short name T780
Test name
Test status
Simulation time 47915049 ps
CPU time 0.93 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201036 kb
Host smart-c3ecc1b7-4d3e-4c88-b7f0-631579a0ba44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854992197 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.3854992197
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.4163375067
Short name T435
Test name
Test status
Simulation time 37116109 ps
CPU time 0.93 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201096 kb
Host smart-af046e46-f5c0-4e61-a070-6bcc6d80a823
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163375067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.4163375067
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.1497481352
Short name T776
Test name
Test status
Simulation time 63509828 ps
CPU time 0.92 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:09 PM PDT 24
Peak memory 201308 kb
Host smart-ea34583c-e69d-4744-be13-ab7a88dc5cf8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497481352 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.1497481352
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.3990585516
Short name T415
Test name
Test status
Simulation time 29942850 ps
CPU time 0.74 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201084 kb
Host smart-edcc3ce9-7431-41af-9244-bc91085fa2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990585516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3990585516
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.3243272252
Short name T260
Test name
Test status
Simulation time 608297004 ps
CPU time 2.93 seconds
Started Aug 04 05:18:05 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 201232 kb
Host smart-7c5c92d6-32f3-4922-a212-381e19ce7bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243272252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.3243272252
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.154952495
Short name T307
Test name
Test status
Simulation time 19420790 ps
CPU time 0.8 seconds
Started Aug 04 05:17:50 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 200952 kb
Host smart-449fad6d-3e45-4c68-a68d-9a82673abab5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154952495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.154952495
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.778973658
Short name T771
Test name
Test status
Simulation time 5361430697 ps
CPU time 30.04 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:33 PM PDT 24
Peak memory 201396 kb
Host smart-0225633b-45b1-40e0-bae2-7922f79598a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778973658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.778973658
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all_with_rand_reset.836796846
Short name T65
Test name
Test status
Simulation time 93149756431 ps
CPU time 670.18 seconds
Started Aug 04 05:17:49 PM PDT 24
Finished Aug 04 05:28:59 PM PDT 24
Peak memory 209736 kb
Host smart-00f7f775-3212-4751-8962-f60cb85f42d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=836796846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.836796846
Directory /workspace/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.clkmgr_trans.3693200528
Short name T770
Test name
Test status
Simulation time 560645562 ps
CPU time 2.57 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 201008 kb
Host smart-5c489c43-d9d4-4ba4-9557-ba537e4fa041
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693200528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3693200528
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.787762157
Short name T813
Test name
Test status
Simulation time 28349084 ps
CPU time 0.78 seconds
Started Aug 04 05:18:06 PM PDT 24
Finished Aug 04 05:18:07 PM PDT 24
Peak memory 201088 kb
Host smart-75360ac4-1e25-458f-b32e-98b99497d245
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787762157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.787762157
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3121444965
Short name T223
Test name
Test status
Simulation time 78387964 ps
CPU time 1 seconds
Started Aug 04 05:18:11 PM PDT 24
Finished Aug 04 05:18:12 PM PDT 24
Peak memory 200936 kb
Host smart-aec5ab47-9bb3-4424-bdd9-43641fff931b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121444965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3121444965
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2080901262
Short name T759
Test name
Test status
Simulation time 44802505 ps
CPU time 0.79 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 200300 kb
Host smart-5d062017-41d8-4916-9bee-580f6eee9ad1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080901262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2080901262
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.4244014704
Short name T238
Test name
Test status
Simulation time 69055066 ps
CPU time 1.04 seconds
Started Aug 04 05:17:50 PM PDT 24
Finished Aug 04 05:17:51 PM PDT 24
Peak memory 201004 kb
Host smart-5b7712c6-07d9-4aca-8180-872efa190a1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244014704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.4244014704
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.1898664092
Short name T342
Test name
Test status
Simulation time 24595356 ps
CPU time 0.88 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:17:57 PM PDT 24
Peak memory 201004 kb
Host smart-784589bb-d506-4c57-875a-9912171f8e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898664092 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.1898664092
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.2273887447
Short name T620
Test name
Test status
Simulation time 2050566344 ps
CPU time 9.24 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:19 PM PDT 24
Peak memory 201220 kb
Host smart-79f716d2-7247-4e9b-8d42-a3b7420a2e49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273887447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2273887447
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1616410810
Short name T325
Test name
Test status
Simulation time 2335049363 ps
CPU time 8.71 seconds
Started Aug 04 05:17:57 PM PDT 24
Finished Aug 04 05:18:06 PM PDT 24
Peak memory 201364 kb
Host smart-01f648a7-c976-4db7-8063-ddf74efc047c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616410810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1616410810
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1993352736
Short name T804
Test name
Test status
Simulation time 47555363 ps
CPU time 0.84 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201004 kb
Host smart-2184d6cb-d59a-42b5-9fcb-bb4648f282e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993352736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1993352736
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.139117140
Short name T212
Test name
Test status
Simulation time 85343937 ps
CPU time 1.07 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201068 kb
Host smart-02e38c17-9467-4d4d-ab56-757925feb9a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139117140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_clk_byp_req_intersig_mubi.139117140
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.3830792589
Short name T149
Test name
Test status
Simulation time 34223236 ps
CPU time 0.82 seconds
Started Aug 04 05:17:56 PM PDT 24
Finished Aug 04 05:17:57 PM PDT 24
Peak memory 201048 kb
Host smart-7e904c34-0c25-4691-8c10-8c2507cdae0d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830792589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.3830792589
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3876451562
Short name T189
Test name
Test status
Simulation time 12840370 ps
CPU time 0.71 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201020 kb
Host smart-f79258b8-aef2-4e42-a2ed-d5967a1ac0e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876451562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3876451562
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.305284929
Short name T352
Test name
Test status
Simulation time 432342537 ps
CPU time 2.81 seconds
Started Aug 04 05:18:12 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 200980 kb
Host smart-246980eb-b6fd-4f38-84b7-9d2141ae5e94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305284929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.305284929
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.3522427014
Short name T637
Test name
Test status
Simulation time 89654269 ps
CPU time 1.05 seconds
Started Aug 04 05:17:53 PM PDT 24
Finished Aug 04 05:17:54 PM PDT 24
Peak memory 201064 kb
Host smart-0b99dc2c-cbf8-46dc-97e8-829bbc5082fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522427014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3522427014
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.2355019618
Short name T649
Test name
Test status
Simulation time 4493877342 ps
CPU time 31.8 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:39 PM PDT 24
Peak memory 201412 kb
Host smart-ef59b2e4-ca36-4a5a-8264-25f61785aada
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355019618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.2355019618
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all_with_rand_reset.65618179
Short name T699
Test name
Test status
Simulation time 178728453986 ps
CPU time 1059.03 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:35:41 PM PDT 24
Peak memory 216884 kb
Host smart-25106625-1490-46a8-bca2-f1c68c957046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=65618179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.65618179
Directory /workspace/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.clkmgr_trans.773728932
Short name T340
Test name
Test status
Simulation time 66631951 ps
CPU time 0.92 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 200976 kb
Host smart-5fa9c37a-026a-4f77-bf1c-10658eaa2595
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773728932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.773728932
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.2561416738
Short name T250
Test name
Test status
Simulation time 30420468 ps
CPU time 0.78 seconds
Started Aug 04 05:18:17 PM PDT 24
Finished Aug 04 05:18:18 PM PDT 24
Peak memory 201088 kb
Host smart-8f64d2aa-2e8d-4897-90c3-5adb99cdbc1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561416738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.2561416738
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3094644279
Short name T97
Test name
Test status
Simulation time 17947878 ps
CPU time 0.79 seconds
Started Aug 04 05:18:04 PM PDT 24
Finished Aug 04 05:18:05 PM PDT 24
Peak memory 201104 kb
Host smart-b370dd7d-527a-4c6b-a75b-c2c66e6e7fab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094644279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.3094644279
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.3875582171
Short name T167
Test name
Test status
Simulation time 29768140 ps
CPU time 0.81 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:08 PM PDT 24
Peak memory 200276 kb
Host smart-3eb65abd-9571-4392-b04c-42cc444ebb43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875582171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3875582171
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.4192584052
Short name T26
Test name
Test status
Simulation time 83380398 ps
CPU time 1 seconds
Started Aug 04 05:18:09 PM PDT 24
Finished Aug 04 05:18:10 PM PDT 24
Peak memory 201076 kb
Host smart-210aed82-32b5-4736-aa28-84d04edab488
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192584052 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.4192584052
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.487281014
Short name T579
Test name
Test status
Simulation time 32913154 ps
CPU time 0.86 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:11 PM PDT 24
Peak memory 201064 kb
Host smart-2f9442eb-b35c-46ac-bc3a-e6dc4cbfbff5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487281014 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.487281014
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.3614033411
Short name T13
Test name
Test status
Simulation time 1737733499 ps
CPU time 6.59 seconds
Started Aug 04 05:18:08 PM PDT 24
Finished Aug 04 05:18:15 PM PDT 24
Peak memory 201108 kb
Host smart-aba30740-3f1f-417b-a8f8-45ceb30acfad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614033411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.3614033411
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.3452172128
Short name T434
Test name
Test status
Simulation time 1478560760 ps
CPU time 6.38 seconds
Started Aug 04 05:18:10 PM PDT 24
Finished Aug 04 05:18:16 PM PDT 24
Peak memory 201116 kb
Host smart-07bf8aa6-9fe6-4fc8-af75-9b425789cccb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452172128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.3452172128
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.3711200553
Short name T21
Test name
Test status
Simulation time 62595124 ps
CPU time 0.94 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201048 kb
Host smart-22a1b3ec-7060-4f71-afdb-b45cc33d4760
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711200553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.3711200553
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2115920254
Short name T404
Test name
Test status
Simulation time 41674718 ps
CPU time 0.94 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 200892 kb
Host smart-814cb22d-7312-4571-b81d-f8f50bc102d2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115920254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.2115920254
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.911161447
Short name T463
Test name
Test status
Simulation time 61371041 ps
CPU time 0.91 seconds
Started Aug 04 05:18:00 PM PDT 24
Finished Aug 04 05:18:01 PM PDT 24
Peak memory 201032 kb
Host smart-bfd2955f-52dc-4f38-97ad-fcb69210764d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911161447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_ctrl_intersig_mubi.911161447
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1706960666
Short name T721
Test name
Test status
Simulation time 32813713 ps
CPU time 0.76 seconds
Started Aug 04 05:17:55 PM PDT 24
Finished Aug 04 05:17:55 PM PDT 24
Peak memory 201024 kb
Host smart-e21edfe4-ef0a-4e0f-afa5-6b674825fe00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706960666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1706960666
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.923313901
Short name T682
Test name
Test status
Simulation time 1258048359 ps
CPU time 5.16 seconds
Started Aug 04 05:18:13 PM PDT 24
Finished Aug 04 05:18:19 PM PDT 24
Peak memory 201176 kb
Host smart-3045e23a-72c5-412f-806b-d29f6a288ad3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923313901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.923313901
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.3396826421
Short name T25
Test name
Test status
Simulation time 19250037 ps
CPU time 0.83 seconds
Started Aug 04 05:18:01 PM PDT 24
Finished Aug 04 05:18:02 PM PDT 24
Peak memory 201028 kb
Host smart-f3bb6e44-4f19-4d15-b898-3d243050b045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396826421 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.3396826421
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.482130992
Short name T486
Test name
Test status
Simulation time 2517617721 ps
CPU time 20.09 seconds
Started Aug 04 05:18:07 PM PDT 24
Finished Aug 04 05:18:28 PM PDT 24
Peak memory 201416 kb
Host smart-8a4dacdf-5e37-49e3-9cba-f289fc300c19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482130992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.482130992
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.927156790
Short name T15
Test name
Test status
Simulation time 253821934704 ps
CPU time 1447.35 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:42:11 PM PDT 24
Peak memory 215736 kb
Host smart-14d09ad8-cbaa-4e3f-8e7f-84174c07d0d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=927156790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.927156790
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.2786536237
Short name T234
Test name
Test status
Simulation time 122349745 ps
CPU time 1.17 seconds
Started Aug 04 05:18:03 PM PDT 24
Finished Aug 04 05:18:04 PM PDT 24
Peak memory 201024 kb
Host smart-fe9f8a96-e691-4e2c-9acd-7b823ee85bad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786536237 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2786536237
Directory /workspace/9.clkmgr_trans/latest
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