Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 117272800 1 T5 175088 T7 2760 T8 2886
auto[1] 211732 1 T7 548 T8 446 T28 204


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 117198078 1 T5 175088 T7 3180 T8 2914
auto[1] 286454 1 T7 128 T8 418 T28 162


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 117145544 1 T5 175088 T7 2846 T8 2778
auto[1] 338988 1 T7 462 T8 554 T28 226


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 113621020 1 T5 175088 T7 2682 T8 1760
auto[1] 3863512 1 T7 626 T8 1572 T28 444


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74902514 1 T5 172486 T7 2772 T8 2830
auto[1] 42582018 1 T5 2602 T7 536 T8 502


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 72432662 1 T5 172486 T7 2112 T8 1686
auto[0] auto[0] auto[0] auto[0] auto[1] 40913110 1 T5 2602 T7 68 T26 460
auto[0] auto[0] auto[0] auto[1] auto[0] 14950 1 T7 84 T35 4 T2 14
auto[0] auto[0] auto[0] auto[1] auto[1] 3614 1 T7 24 T2 38 T12 84
auto[0] auto[0] auto[1] auto[0] auto[0] 2073966 1 T7 206 T8 538 T28 236
auto[0] auto[0] auto[1] auto[0] auto[1] 1611092 1 T7 236 T8 332 T12 2210
auto[0] auto[0] auto[1] auto[1] auto[0] 25394 1 T8 70 T28 28 T1 28
auto[0] auto[0] auto[1] auto[1] auto[1] 5536 1 T7 10 T8 6 T12 236
auto[0] auto[1] auto[0] auto[0] auto[0] 37256 1 T7 46 T2 8 T21 1834
auto[0] auto[1] auto[0] auto[0] auto[1] 904 1 T12 20 T15 66 T168 2
auto[0] auto[1] auto[0] auto[1] auto[0] 7720 1 T7 60 T2 62 T22 76
auto[0] auto[1] auto[0] auto[1] auto[1] 1910 1 T12 62 T15 148 T168 48
auto[0] auto[1] auto[1] auto[0] auto[0] 4712 1 T8 38 T28 20 T1 40
auto[0] auto[1] auto[1] auto[0] auto[1] 1248 1 T12 6 T77 10 T79 8
auto[0] auto[1] auto[1] auto[1] auto[0] 9176 1 T8 108 T12 250 T80 188
auto[0] auto[1] auto[1] auto[1] auto[1] 2294 1 T12 42 T77 72 T79 68
auto[1] auto[0] auto[0] auto[0] auto[0] 44178 1 T7 28 T8 60 T22 16
auto[1] auto[0] auto[0] auto[0] auto[1] 2014 1 T7 10 T2 20 T12 2
auto[1] auto[0] auto[0] auto[1] auto[0] 17874 1 T7 196 T22 172 T12 280
auto[1] auto[0] auto[0] auto[1] auto[1] 4470 1 T7 54 T2 60 T12 78
auto[1] auto[0] auto[1] auto[0] auto[0] 13116 1 T7 18 T8 64 T28 12
auto[1] auto[0] auto[1] auto[0] auto[1] 3638 1 T7 14 T8 30 T12 86
auto[1] auto[0] auto[1] auto[1] auto[0] 25920 1 T8 128 T28 72 T2 132
auto[1] auto[0] auto[1] auto[1] auto[1] 6544 1 T7 120 T12 280 T79 76
auto[1] auto[1] auto[0] auto[0] auto[0] 104798 1 T8 14 T28 24 T4 852
auto[1] auto[1] auto[0] auto[0] auto[1] 3216 1 T1 50 T2 32 T12 24
auto[1] auto[1] auto[0] auto[1] auto[0] 25958 1 T28 42 T35 44 T2 56
auto[1] auto[1] auto[0] auto[1] auto[1] 6386 1 T2 38 T12 140 T169 66
auto[1] auto[1] auto[1] auto[0] auto[0] 21512 1 T7 22 T8 50 T28 14
auto[1] auto[1] auto[1] auto[0] auto[1] 5378 1 T8 74 T12 86 T80 44
auto[1] auto[1] auto[1] auto[1] auto[0] 43322 1 T8 74 T28 62 T1 78
auto[1] auto[1] auto[1] auto[1] auto[1] 10664 1 T8 60 T12 198 T80 206

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