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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 974
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T804 /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.4074031510 Aug 05 06:25:28 PM PDT 24 Aug 05 06:25:29 PM PDT 24 23391303 ps
T805 /workspace/coverage/default/6.clkmgr_peri.4136975293 Aug 05 06:23:51 PM PDT 24 Aug 05 06:23:52 PM PDT 24 25280044 ps
T806 /workspace/coverage/default/42.clkmgr_stress_all.1892801798 Aug 05 06:26:16 PM PDT 24 Aug 05 06:26:46 PM PDT 24 5680116975 ps
T807 /workspace/coverage/default/43.clkmgr_clk_status.3463808946 Aug 05 06:26:19 PM PDT 24 Aug 05 06:26:20 PM PDT 24 14349219 ps
T808 /workspace/coverage/default/18.clkmgr_alert_test.4180863683 Aug 05 06:24:54 PM PDT 24 Aug 05 06:24:55 PM PDT 24 51492198 ps
T809 /workspace/coverage/default/15.clkmgr_frequency.2820291635 Aug 05 06:24:41 PM PDT 24 Aug 05 06:24:53 PM PDT 24 2131647379 ps
T810 /workspace/coverage/default/33.clkmgr_regwen.2393887312 Aug 05 06:25:47 PM PDT 24 Aug 05 06:25:51 PM PDT 24 722627269 ps
T811 /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2481318924 Aug 05 06:25:37 PM PDT 24 Aug 05 06:25:39 PM PDT 24 163151831 ps
T812 /workspace/coverage/default/38.clkmgr_clk_status.2451354342 Aug 05 06:26:04 PM PDT 24 Aug 05 06:26:05 PM PDT 24 13183246 ps
T813 /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1528513020 Aug 05 06:25:48 PM PDT 24 Aug 05 06:25:49 PM PDT 24 45512699 ps
T814 /workspace/coverage/default/12.clkmgr_frequency_timeout.535670497 Aug 05 06:24:26 PM PDT 24 Aug 05 06:24:37 PM PDT 24 2520082110 ps
T815 /workspace/coverage/default/0.clkmgr_stress_all.247808098 Aug 05 06:23:09 PM PDT 24 Aug 05 06:24:00 PM PDT 24 13322052572 ps
T816 /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1261719602 Aug 05 06:26:19 PM PDT 24 Aug 05 06:26:21 PM PDT 24 199609534 ps
T817 /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3609360427 Aug 05 06:26:23 PM PDT 24 Aug 05 06:26:24 PM PDT 24 69935034 ps
T818 /workspace/coverage/default/40.clkmgr_div_intersig_mubi.396860945 Aug 05 06:26:09 PM PDT 24 Aug 05 06:26:10 PM PDT 24 25037630 ps
T819 /workspace/coverage/default/13.clkmgr_peri.1219386138 Aug 05 06:24:31 PM PDT 24 Aug 05 06:24:32 PM PDT 24 97323612 ps
T820 /workspace/coverage/default/42.clkmgr_extclk.1819680410 Aug 05 06:26:18 PM PDT 24 Aug 05 06:26:19 PM PDT 24 65433285 ps
T821 /workspace/coverage/default/43.clkmgr_alert_test.4153887651 Aug 05 06:26:23 PM PDT 24 Aug 05 06:26:24 PM PDT 24 52656422 ps
T822 /workspace/coverage/default/12.clkmgr_extclk.75685521 Aug 05 06:24:23 PM PDT 24 Aug 05 06:24:24 PM PDT 24 36316687 ps
T59 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.693740201 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:52 PM PDT 24 134309784 ps
T98 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1728368155 Aug 05 05:58:52 PM PDT 24 Aug 05 05:58:55 PM PDT 24 332926273 ps
T823 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2797887001 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 17232076 ps
T56 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.799710109 Aug 05 05:59:47 PM PDT 24 Aug 05 05:59:50 PM PDT 24 92792859 ps
T83 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2964484754 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:02 PM PDT 24 31894077 ps
T99 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3778310062 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:30 PM PDT 24 173612491 ps
T57 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1421451419 Aug 05 05:59:31 PM PDT 24 Aug 05 05:59:35 PM PDT 24 481508067 ps
T824 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4227512149 Aug 05 05:59:51 PM PDT 24 Aug 05 05:59:52 PM PDT 24 17727699 ps
T825 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.4092489723 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:55 PM PDT 24 238007594 ps
T826 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.617309559 Aug 05 05:59:02 PM PDT 24 Aug 05 05:59:04 PM PDT 24 165992030 ps
T84 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3927365002 Aug 05 05:59:40 PM PDT 24 Aug 05 05:59:42 PM PDT 24 80783517 ps
T827 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.891089013 Aug 05 05:59:14 PM PDT 24 Aug 05 05:59:15 PM PDT 24 35513790 ps
T828 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.111463257 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:02 PM PDT 24 12513733 ps
T829 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.882257422 Aug 05 05:58:57 PM PDT 24 Aug 05 05:58:58 PM PDT 24 18720894 ps
T830 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2307209573 Aug 05 05:59:12 PM PDT 24 Aug 05 05:59:13 PM PDT 24 30162263 ps
T831 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.43398192 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:50 PM PDT 24 19571526 ps
T58 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.683984641 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:53 PM PDT 24 138890536 ps
T832 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2280959968 Aug 05 05:59:16 PM PDT 24 Aug 05 05:59:17 PM PDT 24 42613872 ps
T60 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2302141163 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:29 PM PDT 24 91022315 ps
T61 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1149988830 Aug 05 05:58:54 PM PDT 24 Aug 05 05:58:57 PM PDT 24 137766866 ps
T833 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.537388673 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 37119734 ps
T834 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.383415072 Aug 05 05:59:20 PM PDT 24 Aug 05 05:59:21 PM PDT 24 104117948 ps
T835 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.127816870 Aug 05 06:00:09 PM PDT 24 Aug 05 06:00:10 PM PDT 24 13941409 ps
T85 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.498694640 Aug 05 05:59:55 PM PDT 24 Aug 05 05:59:56 PM PDT 24 30599914 ps
T836 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.827016058 Aug 05 05:59:10 PM PDT 24 Aug 05 05:59:11 PM PDT 24 14039112 ps
T837 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2738113723 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:56 PM PDT 24 207086692 ps
T86 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3144459190 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 25275306 ps
T838 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.878067895 Aug 05 06:00:07 PM PDT 24 Aug 05 06:00:08 PM PDT 24 36790747 ps
T87 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2680411530 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:54 PM PDT 24 103001455 ps
T100 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1407935117 Aug 05 05:59:18 PM PDT 24 Aug 05 05:59:21 PM PDT 24 190215174 ps
T839 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.4260476285 Aug 05 05:59:23 PM PDT 24 Aug 05 05:59:24 PM PDT 24 113892234 ps
T156 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4019890119 Aug 05 05:59:33 PM PDT 24 Aug 05 05:59:37 PM PDT 24 722838928 ps
T67 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3907301621 Aug 05 05:59:00 PM PDT 24 Aug 05 05:59:02 PM PDT 24 137407540 ps
T840 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1715250391 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:29 PM PDT 24 41166120 ps
T841 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3330233971 Aug 05 05:59:39 PM PDT 24 Aug 05 05:59:40 PM PDT 24 15757636 ps
T65 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1891401374 Aug 05 05:59:05 PM PDT 24 Aug 05 05:59:07 PM PDT 24 147785048 ps
T842 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.265128137 Aug 05 05:59:11 PM PDT 24 Aug 05 05:59:12 PM PDT 24 44147344 ps
T843 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1293212168 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:50 PM PDT 24 15339325 ps
T844 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1717352416 Aug 05 06:00:03 PM PDT 24 Aug 05 06:00:07 PM PDT 24 39010648 ps
T845 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4028577912 Aug 05 05:59:03 PM PDT 24 Aug 05 05:59:04 PM PDT 24 24928000 ps
T68 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2388421342 Aug 05 05:59:14 PM PDT 24 Aug 05 05:59:17 PM PDT 24 157000876 ps
T846 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.540699879 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 15197046 ps
T103 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.408765629 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:31 PM PDT 24 157961400 ps
T62 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.6563980 Aug 05 05:59:39 PM PDT 24 Aug 05 05:59:42 PM PDT 24 130921719 ps
T63 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1911706094 Aug 05 05:59:36 PM PDT 24 Aug 05 05:59:40 PM PDT 24 472441400 ps
T64 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2312605594 Aug 05 05:59:32 PM PDT 24 Aug 05 05:59:34 PM PDT 24 140900556 ps
T847 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2463454804 Aug 05 05:59:30 PM PDT 24 Aug 05 05:59:31 PM PDT 24 18157612 ps
T848 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.3071396123 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:50 PM PDT 24 18560541 ps
T849 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1014071257 Aug 05 06:00:11 PM PDT 24 Aug 05 06:00:12 PM PDT 24 28876601 ps
T850 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.499704804 Aug 05 05:59:34 PM PDT 24 Aug 05 05:59:34 PM PDT 24 13096244 ps
T851 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1225748755 Aug 05 05:59:14 PM PDT 24 Aug 05 05:59:15 PM PDT 24 41392406 ps
T852 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1458698528 Aug 05 05:58:55 PM PDT 24 Aug 05 05:58:56 PM PDT 24 50636270 ps
T853 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1446325337 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:53 PM PDT 24 13372345 ps
T854 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2113358608 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 28012338 ps
T855 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.160097586 Aug 05 05:59:34 PM PDT 24 Aug 05 05:59:35 PM PDT 24 49567633 ps
T166 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1379830772 Aug 05 05:58:58 PM PDT 24 Aug 05 05:59:01 PM PDT 24 130291995 ps
T856 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1705403967 Aug 05 05:59:05 PM PDT 24 Aug 05 05:59:06 PM PDT 24 28364183 ps
T66 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3071324377 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:31 PM PDT 24 114932918 ps
T857 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1880771505 Aug 05 06:00:03 PM PDT 24 Aug 05 06:00:07 PM PDT 24 47826049 ps
T858 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2134066809 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:03 PM PDT 24 128566595 ps
T859 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2407282850 Aug 05 05:59:51 PM PDT 24 Aug 05 05:59:52 PM PDT 24 118917352 ps
T114 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.879043426 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:03 PM PDT 24 312792600 ps
T860 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.4188559426 Aug 05 05:59:48 PM PDT 24 Aug 05 05:59:49 PM PDT 24 13600624 ps
T861 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3493987456 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:50 PM PDT 24 78642406 ps
T167 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.4188275288 Aug 05 05:59:55 PM PDT 24 Aug 05 05:59:57 PM PDT 24 127094024 ps
T862 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.969622247 Aug 05 06:00:12 PM PDT 24 Aug 05 06:00:13 PM PDT 24 12441784 ps
T115 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3353852940 Aug 05 05:59:51 PM PDT 24 Aug 05 05:59:54 PM PDT 24 255669649 ps
T863 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1940079695 Aug 05 06:00:02 PM PDT 24 Aug 05 06:00:08 PM PDT 24 56252334 ps
T864 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1504318279 Aug 05 05:58:52 PM PDT 24 Aug 05 05:58:54 PM PDT 24 67217265 ps
T865 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1262381484 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 11223841 ps
T866 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1757773384 Aug 05 05:59:24 PM PDT 24 Aug 05 05:59:25 PM PDT 24 22680316 ps
T867 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1376482377 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 14139479 ps
T868 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1177233404 Aug 05 05:59:18 PM PDT 24 Aug 05 05:59:18 PM PDT 24 38401496 ps
T869 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1191294471 Aug 05 05:59:06 PM PDT 24 Aug 05 05:59:08 PM PDT 24 33740913 ps
T870 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1591102129 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:51 PM PDT 24 35339756 ps
T871 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2579775335 Aug 05 05:59:07 PM PDT 24 Aug 05 05:59:08 PM PDT 24 30302846 ps
T872 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1777022551 Aug 05 06:00:05 PM PDT 24 Aug 05 06:00:07 PM PDT 24 11822893 ps
T873 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.332966347 Aug 05 05:59:24 PM PDT 24 Aug 05 05:59:26 PM PDT 24 239003371 ps
T116 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2461303812 Aug 05 05:59:59 PM PDT 24 Aug 05 06:00:01 PM PDT 24 293112787 ps
T101 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2058155269 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:55 PM PDT 24 295625431 ps
T109 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1500931367 Aug 05 05:59:08 PM PDT 24 Aug 05 05:59:11 PM PDT 24 400814729 ps
T874 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2891860469 Aug 05 05:59:10 PM PDT 24 Aug 05 05:59:12 PM PDT 24 103219003 ps
T875 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3866034382 Aug 05 05:59:53 PM PDT 24 Aug 05 05:59:55 PM PDT 24 118050870 ps
T117 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2653039671 Aug 05 05:59:23 PM PDT 24 Aug 05 05:59:25 PM PDT 24 379392090 ps
T876 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3413370913 Aug 05 05:59:39 PM PDT 24 Aug 05 05:59:41 PM PDT 24 179081826 ps
T877 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2205447229 Aug 05 05:59:59 PM PDT 24 Aug 05 05:59:59 PM PDT 24 14536155 ps
T878 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4098548706 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:29 PM PDT 24 34703339 ps
T165 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2074271964 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:03 PM PDT 24 129407685 ps
T879 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2164484699 Aug 05 05:58:57 PM PDT 24 Aug 05 05:58:58 PM PDT 24 31150341 ps
T880 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2502086514 Aug 05 05:59:02 PM PDT 24 Aug 05 05:59:03 PM PDT 24 29992674 ps
T881 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3596556232 Aug 05 06:00:11 PM PDT 24 Aug 05 06:00:12 PM PDT 24 35185188 ps
T882 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1494760205 Aug 05 05:59:09 PM PDT 24 Aug 05 05:59:16 PM PDT 24 679161722 ps
T131 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.729219495 Aug 05 05:59:24 PM PDT 24 Aug 05 05:59:27 PM PDT 24 167359984 ps
T883 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1350771862 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 135887632 ps
T118 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.4189233140 Aug 05 05:59:34 PM PDT 24 Aug 05 05:59:37 PM PDT 24 294395492 ps
T884 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3369319049 Aug 05 05:59:10 PM PDT 24 Aug 05 05:59:10 PM PDT 24 49697068 ps
T885 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.180208094 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:26 PM PDT 24 12696081 ps
T886 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.381033313 Aug 05 05:59:36 PM PDT 24 Aug 05 05:59:38 PM PDT 24 54345021 ps
T887 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.862462982 Aug 05 05:59:30 PM PDT 24 Aug 05 05:59:35 PM PDT 24 1447977734 ps
T888 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2699565109 Aug 05 06:00:07 PM PDT 24 Aug 05 06:00:08 PM PDT 24 15311746 ps
T121 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4028387686 Aug 05 05:59:54 PM PDT 24 Aug 05 05:59:59 PM PDT 24 533671377 ps
T889 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3592097895 Aug 05 05:58:59 PM PDT 24 Aug 05 05:59:02 PM PDT 24 142277057 ps
T110 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.248108859 Aug 05 05:59:37 PM PDT 24 Aug 05 05:59:40 PM PDT 24 261145768 ps
T890 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3655399019 Aug 05 06:00:02 PM PDT 24 Aug 05 06:00:07 PM PDT 24 21108899 ps
T891 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1510149633 Aug 05 05:59:37 PM PDT 24 Aug 05 05:59:39 PM PDT 24 279670963 ps
T892 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3813455084 Aug 05 05:59:44 PM PDT 24 Aug 05 05:59:46 PM PDT 24 31610391 ps
T122 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2984776868 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:28 PM PDT 24 217221921 ps
T893 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2713347035 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 17886081 ps
T894 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3454846372 Aug 05 05:59:56 PM PDT 24 Aug 05 05:59:59 PM PDT 24 84401595 ps
T129 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3175200179 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 58849649 ps
T895 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1019164531 Aug 05 06:00:09 PM PDT 24 Aug 05 06:00:10 PM PDT 24 33345497 ps
T896 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1213188097 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:54 PM PDT 24 169587104 ps
T897 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1150547062 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:29 PM PDT 24 76337394 ps
T898 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1463500638 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:26 PM PDT 24 72962076 ps
T899 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3584445775 Aug 05 06:00:03 PM PDT 24 Aug 05 06:00:07 PM PDT 24 104723188 ps
T900 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2250024650 Aug 05 05:58:53 PM PDT 24 Aug 05 05:58:54 PM PDT 24 31573038 ps
T130 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1399053473 Aug 05 05:59:03 PM PDT 24 Aug 05 05:59:05 PM PDT 24 263960757 ps
T901 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2071392053 Aug 05 05:58:51 PM PDT 24 Aug 05 05:58:52 PM PDT 24 37474905 ps
T902 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3201919562 Aug 05 05:59:02 PM PDT 24 Aug 05 05:59:13 PM PDT 24 1648441201 ps
T903 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4056783071 Aug 05 06:00:05 PM PDT 24 Aug 05 06:00:07 PM PDT 24 16476216 ps
T904 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3856151108 Aug 05 05:59:58 PM PDT 24 Aug 05 05:59:59 PM PDT 24 75600757 ps
T123 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.258469121 Aug 05 05:59:05 PM PDT 24 Aug 05 05:59:08 PM PDT 24 320061926 ps
T124 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1656568577 Aug 05 05:59:13 PM PDT 24 Aug 05 05:59:14 PM PDT 24 256171804 ps
T905 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4132759916 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:30 PM PDT 24 245398422 ps
T906 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1704638487 Aug 05 05:59:47 PM PDT 24 Aug 05 05:59:48 PM PDT 24 25128652 ps
T907 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1362175892 Aug 05 06:00:02 PM PDT 24 Aug 05 06:00:08 PM PDT 24 207950766 ps
T908 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2399367319 Aug 05 05:59:10 PM PDT 24 Aug 05 05:59:13 PM PDT 24 231504263 ps
T909 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3200587509 Aug 05 05:59:52 PM PDT 24 Aug 05 05:59:53 PM PDT 24 169057066 ps
T104 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.851109839 Aug 05 05:59:40 PM PDT 24 Aug 05 05:59:43 PM PDT 24 447070090 ps
T910 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.513962262 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:51 PM PDT 24 12789708 ps
T911 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.64642073 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:50 PM PDT 24 86902248 ps
T912 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1311797530 Aug 05 06:00:06 PM PDT 24 Aug 05 06:00:07 PM PDT 24 26112140 ps
T913 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3061038617 Aug 05 05:59:43 PM PDT 24 Aug 05 05:59:45 PM PDT 24 69840323 ps
T914 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2300309978 Aug 05 06:00:11 PM PDT 24 Aug 05 06:00:12 PM PDT 24 120279949 ps
T915 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.902035371 Aug 05 05:59:30 PM PDT 24 Aug 05 05:59:30 PM PDT 24 37823761 ps
T916 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3886629496 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 10298737 ps
T917 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1729055427 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:02 PM PDT 24 107309820 ps
T918 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3760715943 Aug 05 06:00:08 PM PDT 24 Aug 05 06:00:09 PM PDT 24 26936585 ps
T919 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.788287991 Aug 05 05:59:08 PM PDT 24 Aug 05 05:59:11 PM PDT 24 42187656 ps
T125 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1635997915 Aug 05 05:59:58 PM PDT 24 Aug 05 06:00:01 PM PDT 24 167630348 ps
T920 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1687154714 Aug 05 05:59:28 PM PDT 24 Aug 05 05:59:29 PM PDT 24 53130975 ps
T921 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3328864102 Aug 05 05:59:48 PM PDT 24 Aug 05 05:59:49 PM PDT 24 21387822 ps
T922 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.619119750 Aug 05 06:00:07 PM PDT 24 Aug 05 06:00:08 PM PDT 24 54738505 ps
T923 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2617381267 Aug 05 06:00:07 PM PDT 24 Aug 05 06:00:08 PM PDT 24 15764892 ps
T924 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1685470422 Aug 05 05:59:29 PM PDT 24 Aug 05 05:59:32 PM PDT 24 268870963 ps
T105 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3299392901 Aug 05 05:59:13 PM PDT 24 Aug 05 05:59:14 PM PDT 24 77384470 ps
T925 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3608939819 Aug 05 06:00:05 PM PDT 24 Aug 05 06:00:07 PM PDT 24 14129895 ps
T127 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1314403221 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:05 PM PDT 24 541115279 ps
T926 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3394377157 Aug 05 05:59:32 PM PDT 24 Aug 05 05:59:34 PM PDT 24 45004088 ps
T119 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2245071032 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:52 PM PDT 24 214942745 ps
T927 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2966313850 Aug 05 05:59:13 PM PDT 24 Aug 05 05:59:16 PM PDT 24 130403946 ps
T928 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4208388624 Aug 05 05:59:18 PM PDT 24 Aug 05 05:59:20 PM PDT 24 163537537 ps
T929 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1073765399 Aug 05 06:00:03 PM PDT 24 Aug 05 06:00:08 PM PDT 24 96643215 ps
T930 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.874514761 Aug 05 06:00:04 PM PDT 24 Aug 05 06:00:07 PM PDT 24 19522899 ps
T931 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3417023253 Aug 05 06:00:04 PM PDT 24 Aug 05 06:00:07 PM PDT 24 24493590 ps
T932 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4294289216 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:26 PM PDT 24 32694499 ps
T933 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1655335323 Aug 05 05:59:17 PM PDT 24 Aug 05 05:59:19 PM PDT 24 54257148 ps
T934 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.17455252 Aug 05 05:59:40 PM PDT 24 Aug 05 05:59:42 PM PDT 24 113540660 ps
T935 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1375654511 Aug 05 05:58:52 PM PDT 24 Aug 05 05:58:53 PM PDT 24 18665299 ps
T936 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1286130433 Aug 05 06:00:10 PM PDT 24 Aug 05 06:00:10 PM PDT 24 37692661 ps
T937 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3976124926 Aug 05 05:59:55 PM PDT 24 Aug 05 05:59:55 PM PDT 24 11776555 ps
T938 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.392537327 Aug 05 05:59:49 PM PDT 24 Aug 05 05:59:50 PM PDT 24 74020068 ps
T939 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.403767475 Aug 05 05:59:47 PM PDT 24 Aug 05 05:59:49 PM PDT 24 197139238 ps
T940 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.19108412 Aug 05 05:59:34 PM PDT 24 Aug 05 05:59:35 PM PDT 24 20799390 ps
T941 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2754723461 Aug 05 05:59:34 PM PDT 24 Aug 05 05:59:35 PM PDT 24 25572139 ps
T942 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1254786211 Aug 05 06:00:10 PM PDT 24 Aug 05 06:00:11 PM PDT 24 16244842 ps
T943 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1697731307 Aug 05 05:59:58 PM PDT 24 Aug 05 06:00:00 PM PDT 24 237000571 ps
T126 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.172375005 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:52 PM PDT 24 60729911 ps
T944 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.457182166 Aug 05 05:59:46 PM PDT 24 Aug 05 05:59:47 PM PDT 24 86694389 ps
T128 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.228499131 Aug 05 05:59:29 PM PDT 24 Aug 05 05:59:32 PM PDT 24 527251103 ps
T106 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1983441499 Aug 05 05:59:24 PM PDT 24 Aug 05 05:59:27 PM PDT 24 474992638 ps
T945 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.213397951 Aug 05 05:59:51 PM PDT 24 Aug 05 05:59:56 PM PDT 24 619875592 ps
T946 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2752972347 Aug 05 06:00:13 PM PDT 24 Aug 05 06:00:14 PM PDT 24 22324249 ps
T947 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1216103619 Aug 05 05:59:19 PM PDT 24 Aug 05 05:59:20 PM PDT 24 132581513 ps
T108 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3766775536 Aug 05 05:59:29 PM PDT 24 Aug 05 05:59:31 PM PDT 24 98863327 ps
T948 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3242843835 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:27 PM PDT 24 30760817 ps
T949 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1852327085 Aug 05 05:59:25 PM PDT 24 Aug 05 05:59:37 PM PDT 24 2555926687 ps
T950 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3169321059 Aug 05 05:59:35 PM PDT 24 Aug 05 05:59:37 PM PDT 24 29468485 ps
T951 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1995201795 Aug 05 05:59:48 PM PDT 24 Aug 05 05:59:49 PM PDT 24 17791312 ps
T952 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2490368445 Aug 05 05:59:33 PM PDT 24 Aug 05 05:59:34 PM PDT 24 22203867 ps
T953 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3655557685 Aug 05 05:59:18 PM PDT 24 Aug 05 05:59:19 PM PDT 24 181884515 ps
T954 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.116205125 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:53 PM PDT 24 123325683 ps
T955 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3521136551 Aug 05 06:00:04 PM PDT 24 Aug 05 06:00:08 PM PDT 24 89604247 ps
T956 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.883194205 Aug 05 05:58:47 PM PDT 24 Aug 05 05:58:49 PM PDT 24 153233968 ps
T957 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1025557914 Aug 05 05:59:27 PM PDT 24 Aug 05 05:59:28 PM PDT 24 34565356 ps
T958 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.378220483 Aug 05 05:59:12 PM PDT 24 Aug 05 05:59:19 PM PDT 24 1016744839 ps
T959 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2598509806 Aug 05 05:59:36 PM PDT 24 Aug 05 05:59:37 PM PDT 24 37165822 ps
T107 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3215325786 Aug 05 05:59:51 PM PDT 24 Aug 05 05:59:53 PM PDT 24 144443402 ps
T960 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3854113041 Aug 05 06:00:11 PM PDT 24 Aug 05 06:00:12 PM PDT 24 38334023 ps
T961 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2236159240 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:52 PM PDT 24 149754130 ps
T962 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.67744768 Aug 05 05:58:57 PM PDT 24 Aug 05 05:58:58 PM PDT 24 27798918 ps
T963 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3550860812 Aug 05 05:59:17 PM PDT 24 Aug 05 05:59:19 PM PDT 24 401269499 ps
T964 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3243116433 Aug 05 05:59:50 PM PDT 24 Aug 05 05:59:50 PM PDT 24 13580986 ps
T965 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2166462466 Aug 05 05:59:47 PM PDT 24 Aug 05 05:59:50 PM PDT 24 139661458 ps
T102 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.943119952 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:03 PM PDT 24 98681755 ps
T966 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.597774132 Aug 05 06:00:00 PM PDT 24 Aug 05 06:00:01 PM PDT 24 12765108 ps
T967 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2926014271 Aug 05 05:59:58 PM PDT 24 Aug 05 06:00:01 PM PDT 24 351490198 ps
T968 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.278919779 Aug 05 05:59:48 PM PDT 24 Aug 05 05:59:50 PM PDT 24 93858663 ps
T969 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3956062874 Aug 05 06:00:01 PM PDT 24 Aug 05 06:00:03 PM PDT 24 81421270 ps
T970 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2513977041 Aug 05 05:58:53 PM PDT 24 Aug 05 05:58:55 PM PDT 24 68683327 ps
T971 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1221928878 Aug 05 05:59:47 PM PDT 24 Aug 05 05:59:49 PM PDT 24 179430697 ps
T120 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.983253723 Aug 05 05:59:36 PM PDT 24 Aug 05 05:59:39 PM PDT 24 412315814 ps
T972 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.330739992 Aug 05 06:00:09 PM PDT 24 Aug 05 06:00:10 PM PDT 24 15340107 ps
T973 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.571804587 Aug 05 05:59:57 PM PDT 24 Aug 05 05:59:58 PM PDT 24 50658837 ps
T974 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1533257977 Aug 05 05:59:33 PM PDT 24 Aug 05 05:59:35 PM PDT 24 52052044 ps

Test location /workspace/coverage/default/24.clkmgr_stress_all.3156204271
Short name T5
Test name
Test status
Simulation time 1795153773 ps
CPU time 9.69 seconds
Started Aug 05 06:25:17 PM PDT 24
Finished Aug 05 06:25:27 PM PDT 24
Peak memory 201324 kb
Host smart-9ec60829-5b76-4588-a14a-4ce2488bc015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156204271 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.3156204271
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.4190250401
Short name T12
Test name
Test status
Simulation time 92470599294 ps
CPU time 417.15 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:33:25 PM PDT 24
Peak memory 209764 kb
Host smart-673934e4-8da5-4db3-ac52-de4dbd7407ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4190250401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.4190250401
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.1149988830
Short name T61
Test name
Test status
Simulation time 137766866 ps
CPU time 2.91 seconds
Started Aug 05 05:58:54 PM PDT 24
Finished Aug 05 05:58:57 PM PDT 24
Peak memory 209044 kb
Host smart-58ebd6c9-76f9-4bcb-9347-0ccb43880b24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149988830 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.1149988830
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.3903489641
Short name T9
Test name
Test status
Simulation time 843868860 ps
CPU time 4.62 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:21 PM PDT 24
Peak memory 201300 kb
Host smart-ea8d52e3-eba3-4243-90dd-c7cefca877b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903489641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.3903489641
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.2331837966
Short name T43
Test name
Test status
Simulation time 151237591 ps
CPU time 2 seconds
Started Aug 05 06:23:08 PM PDT 24
Finished Aug 05 06:23:10 PM PDT 24
Peak memory 216516 kb
Host smart-3bc97102-5875-4ad0-8a21-496b730fef0b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331837966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmg
r_sec_cm.2331837966
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.2279398173
Short name T19
Test name
Test status
Simulation time 92474310 ps
CPU time 0.93 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:24:59 PM PDT 24
Peak memory 200272 kb
Host smart-aac9ab94-cf1c-4306-83ca-86dc3d65853e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279398173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.2279398173
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.2653039671
Short name T117
Test name
Test status
Simulation time 379392090 ps
CPU time 2.21 seconds
Started Aug 05 05:59:23 PM PDT 24
Finished Aug 05 05:59:25 PM PDT 24
Peak memory 200852 kb
Host smart-3bc9af0f-94ec-4c77-99d6-2d947e615f5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653039671 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.2653039671
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.817123807
Short name T314
Test name
Test status
Simulation time 22462041 ps
CPU time 0.92 seconds
Started Aug 05 06:24:14 PM PDT 24
Finished Aug 05 06:24:15 PM PDT 24
Peak memory 201100 kb
Host smart-bdee8db5-d60a-45ed-99f8-e68c982bc86a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817123807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_idle_intersig_mubi.817123807
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.661333594
Short name T36
Test name
Test status
Simulation time 52561610 ps
CPU time 0.83 seconds
Started Aug 05 06:23:28 PM PDT 24
Finished Aug 05 06:23:28 PM PDT 24
Peak memory 201092 kb
Host smart-6dd090f2-f106-4ec5-9044-4b948c85fa60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661333594 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_alert_test.661333594
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.1728368155
Short name T98
Test name
Test status
Simulation time 332926273 ps
CPU time 3.05 seconds
Started Aug 05 05:58:52 PM PDT 24
Finished Aug 05 05:58:55 PM PDT 24
Peak memory 200616 kb
Host smart-43157b32-0481-4309-acaa-9e2993313aab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728368155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.clkmgr_tl_intg_err.1728368155
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.1309359048
Short name T7
Test name
Test status
Simulation time 69657266 ps
CPU time 0.93 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201060 kb
Host smart-9c5b9003-c422-4598-ac78-d74c8c7f729e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309359048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.1309359048
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.1172727675
Short name T15
Test name
Test status
Simulation time 472244296951 ps
CPU time 2037.48 seconds
Started Aug 05 06:25:01 PM PDT 24
Finished Aug 05 06:58:58 PM PDT 24
Peak memory 209740 kb
Host smart-70282cf5-d511-4b23-b537-7cad5dbc401c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1172727675 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.1172727675
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.2109619432
Short name T80
Test name
Test status
Simulation time 27410006 ps
CPU time 0.95 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201116 kb
Host smart-f157bfd5-9d29-4ea0-81d6-7c0ef8ad6c3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109619432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.2109619432
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2058155269
Short name T101
Test name
Test status
Simulation time 295625431 ps
CPU time 2.72 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:55 PM PDT 24
Peak memory 200548 kb
Host smart-c40a3bd5-65aa-4c85-9304-9196665477ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058155269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.2058155269
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.683984641
Short name T58
Test name
Test status
Simulation time 138890536 ps
CPU time 1.39 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 200660 kb
Host smart-62a56517-48e6-4d73-8172-4469b0432076
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683984641 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.clkmgr_shadow_reg_errors.683984641
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1891401374
Short name T65
Test name
Test status
Simulation time 147785048 ps
CPU time 1.95 seconds
Started Aug 05 05:59:05 PM PDT 24
Finished Aug 05 05:59:07 PM PDT 24
Peak memory 200808 kb
Host smart-cfd7e3d7-ddf1-4685-a24e-b774181a8f66
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891401374 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.1891401374
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.851109839
Short name T104
Test name
Test status
Simulation time 447070090 ps
CPU time 3.6 seconds
Started Aug 05 05:59:40 PM PDT 24
Finished Aug 05 05:59:43 PM PDT 24
Peak memory 200616 kb
Host smart-ec818064-f7b5-4905-9939-6739739287fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851109839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_tl_intg_err.851109839
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.2829806388
Short name T39
Test name
Test status
Simulation time 6006478068 ps
CPU time 25.25 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:44 PM PDT 24
Peak memory 201436 kb
Host smart-a9ce26b2-23ae-496b-83e7-9372bfee22c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829806388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.2829806388
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.408765629
Short name T103
Test name
Test status
Simulation time 157961400 ps
CPU time 2.47 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:31 PM PDT 24
Peak memory 200548 kb
Host smart-f5d06c4e-dc9c-4e2e-b0bf-c8f0b5e7d5dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408765629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_tl_intg_err.408765629
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.3817783373
Short name T327
Test name
Test status
Simulation time 234210521 ps
CPU time 1.69 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201080 kb
Host smart-6db18bdc-62a6-40f8-8ec4-b9f27f537b5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817783373 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.3817783373
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.1504318279
Short name T864
Test name
Test status
Simulation time 67217265 ps
CPU time 1.76 seconds
Started Aug 05 05:58:52 PM PDT 24
Finished Aug 05 05:58:54 PM PDT 24
Peak memory 200552 kb
Host smart-f297dc9b-031a-430d-83e0-a30591862153
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504318279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.1504318279
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.3592097895
Short name T889
Test name
Test status
Simulation time 142277057 ps
CPU time 3.64 seconds
Started Aug 05 05:58:59 PM PDT 24
Finished Aug 05 05:59:02 PM PDT 24
Peak memory 200572 kb
Host smart-bec4970f-c2b8-47ad-b4ee-50beca3a6505
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592097895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_bit_bash.3592097895
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.2250024650
Short name T900
Test name
Test status
Simulation time 31573038 ps
CPU time 0.88 seconds
Started Aug 05 05:58:53 PM PDT 24
Finished Aug 05 05:58:54 PM PDT 24
Peak memory 200556 kb
Host smart-4090cae9-d257-48fe-b2f4-00a234d50614
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250024650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.2250024650
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.67744768
Short name T962
Test name
Test status
Simulation time 27798918 ps
CPU time 1.02 seconds
Started Aug 05 05:58:57 PM PDT 24
Finished Aug 05 05:58:58 PM PDT 24
Peak memory 200552 kb
Host smart-de9cbcb4-bed6-41c1-94dc-90f462fe2980
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67744768 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.67744768
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.2071392053
Short name T901
Test name
Test status
Simulation time 37474905 ps
CPU time 0.85 seconds
Started Aug 05 05:58:51 PM PDT 24
Finished Aug 05 05:58:52 PM PDT 24
Peak memory 200384 kb
Host smart-8fd675e2-acdd-4a09-b106-41d261b67b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071392053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.2071392053
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.1375654511
Short name T935
Test name
Test status
Simulation time 18665299 ps
CPU time 0.67 seconds
Started Aug 05 05:58:52 PM PDT 24
Finished Aug 05 05:58:53 PM PDT 24
Peak memory 198992 kb
Host smart-1fba9077-97a0-4d86-8c8e-ea129f866d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375654511 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.1375654511
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.1458698528
Short name T852
Test name
Test status
Simulation time 50636270 ps
CPU time 1.35 seconds
Started Aug 05 05:58:55 PM PDT 24
Finished Aug 05 05:58:56 PM PDT 24
Peak memory 200396 kb
Host smart-1247b167-4a19-4352-9c47-d618ac4fd8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458698528 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.1458698528
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.883194205
Short name T956
Test name
Test status
Simulation time 153233968 ps
CPU time 2.24 seconds
Started Aug 05 05:58:47 PM PDT 24
Finished Aug 05 05:58:49 PM PDT 24
Peak memory 217124 kb
Host smart-478db6c9-db7d-4ef7-8a35-845144606fe3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883194205 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.clkmgr_shadow_reg_errors.883194205
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.2513977041
Short name T970
Test name
Test status
Simulation time 68683327 ps
CPU time 2.36 seconds
Started Aug 05 05:58:53 PM PDT 24
Finished Aug 05 05:58:55 PM PDT 24
Peak memory 200568 kb
Host smart-ebabf9cf-39d0-45f5-9cbc-14234ed5535d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513977041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.2513977041
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.617309559
Short name T826
Test name
Test status
Simulation time 165992030 ps
CPU time 1.46 seconds
Started Aug 05 05:59:02 PM PDT 24
Finished Aug 05 05:59:04 PM PDT 24
Peak memory 200340 kb
Host smart-7065b76a-2b5d-41ff-bb8d-4ba992f462ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617309559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_aliasing.617309559
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3201919562
Short name T902
Test name
Test status
Simulation time 1648441201 ps
CPU time 10.98 seconds
Started Aug 05 05:59:02 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 200592 kb
Host smart-6d476841-93c0-4abf-8194-2987fab998c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201919562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_bit_bash.3201919562
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1705403967
Short name T856
Test name
Test status
Simulation time 28364183 ps
CPU time 0.85 seconds
Started Aug 05 05:59:05 PM PDT 24
Finished Aug 05 05:59:06 PM PDT 24
Peak memory 200368 kb
Host smart-27cce490-edb6-4daf-91cf-93c5931d4495
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705403967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.1705403967
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.4028577912
Short name T845
Test name
Test status
Simulation time 24928000 ps
CPU time 0.96 seconds
Started Aug 05 05:59:03 PM PDT 24
Finished Aug 05 05:59:04 PM PDT 24
Peak memory 200468 kb
Host smart-09ea0fed-b121-46cb-840f-84e925e19575
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028577912 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.4028577912
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.2164484699
Short name T879
Test name
Test status
Simulation time 31150341 ps
CPU time 0.87 seconds
Started Aug 05 05:58:57 PM PDT 24
Finished Aug 05 05:58:58 PM PDT 24
Peak memory 200368 kb
Host smart-55947d39-de69-4c4d-ad04-0c6043a707f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164484699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
clkmgr_csr_rw.2164484699
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.882257422
Short name T829
Test name
Test status
Simulation time 18720894 ps
CPU time 0.67 seconds
Started Aug 05 05:58:57 PM PDT 24
Finished Aug 05 05:58:58 PM PDT 24
Peak memory 198948 kb
Host smart-86627cbf-7768-4754-b3d6-ece8fd4fc541
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882257422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkm
gr_intr_test.882257422
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2502086514
Short name T880
Test name
Test status
Simulation time 29992674 ps
CPU time 1.05 seconds
Started Aug 05 05:59:02 PM PDT 24
Finished Aug 05 05:59:03 PM PDT 24
Peak memory 200380 kb
Host smart-be4f4667-d6de-4413-9e2e-c996e8b9671b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502086514 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.2502086514
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.258469121
Short name T123
Test name
Test status
Simulation time 320061926 ps
CPU time 2.36 seconds
Started Aug 05 05:59:05 PM PDT 24
Finished Aug 05 05:59:08 PM PDT 24
Peak memory 200772 kb
Host smart-f7c9210d-317c-4c99-992b-aef9998c288b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258469121 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.258469121
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.1191294471
Short name T869
Test name
Test status
Simulation time 33740913 ps
CPU time 2.02 seconds
Started Aug 05 05:59:06 PM PDT 24
Finished Aug 05 05:59:08 PM PDT 24
Peak memory 200488 kb
Host smart-1fd277ad-d338-430d-873f-472ee1dba762
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191294471 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.1191294471
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.1379830772
Short name T166
Test name
Test status
Simulation time 130291995 ps
CPU time 2.65 seconds
Started Aug 05 05:58:58 PM PDT 24
Finished Aug 05 05:59:01 PM PDT 24
Peak memory 200600 kb
Host smart-b6518ed3-f977-4740-aeee-43af6f0360c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379830772 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.1379830772
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.43398192
Short name T831
Test name
Test status
Simulation time 19571526 ps
CPU time 1.02 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 200432 kb
Host smart-1735a5c1-4271-4893-a5f9-febd022592ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43398192 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.43398192
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.1591102129
Short name T870
Test name
Test status
Simulation time 35339756 ps
CPU time 0.8 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:51 PM PDT 24
Peak memory 200332 kb
Host smart-ddec4b6e-64ed-44a9-9e90-6c9bacc91a93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591102129 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.1591102129
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.1995201795
Short name T951
Test name
Test status
Simulation time 17791312 ps
CPU time 0.69 seconds
Started Aug 05 05:59:48 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 198960 kb
Host smart-191ced5f-5b00-41a4-820a-63a5c8dbbd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995201795 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_intr_test.1995201795
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3927365002
Short name T84
Test name
Test status
Simulation time 80783517 ps
CPU time 1.33 seconds
Started Aug 05 05:59:40 PM PDT 24
Finished Aug 05 05:59:42 PM PDT 24
Peak memory 200520 kb
Host smart-426317b0-0cd7-445d-9f6d-6d70b82a3bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927365002 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.3927365002
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.1221928878
Short name T971
Test name
Test status
Simulation time 179430697 ps
CPU time 1.71 seconds
Started Aug 05 05:59:47 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 200688 kb
Host smart-1858a0c1-69b2-4aa6-8a98-ae8f856ebde7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221928878 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.1221928878
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.2166462466
Short name T965
Test name
Test status
Simulation time 139661458 ps
CPU time 1.97 seconds
Started Aug 05 05:59:47 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 208980 kb
Host smart-16251af2-6acc-4a10-879c-bde8defcaaac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166462466 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2166462466
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.213397951
Short name T945
Test name
Test status
Simulation time 619875592 ps
CPU time 5.06 seconds
Started Aug 05 05:59:51 PM PDT 24
Finished Aug 05 05:59:56 PM PDT 24
Peak memory 200540 kb
Host smart-96ce6ddc-c269-4c02-946f-fa64588f822e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213397951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_tl_errors.213397951
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.248108859
Short name T110
Test name
Test status
Simulation time 261145768 ps
CPU time 2.28 seconds
Started Aug 05 05:59:37 PM PDT 24
Finished Aug 05 05:59:40 PM PDT 24
Peak memory 200600 kb
Host smart-6a686075-d46c-4f7e-beb9-f2852efba762
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248108859 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_tl_intg_err.248108859
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3493987456
Short name T861
Test name
Test status
Simulation time 78642406 ps
CPU time 1.17 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 200356 kb
Host smart-6a831506-f93c-4ecc-a689-5ce655951ed1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493987456 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3493987456
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.3330233971
Short name T841
Test name
Test status
Simulation time 15757636 ps
CPU time 0.73 seconds
Started Aug 05 05:59:39 PM PDT 24
Finished Aug 05 05:59:40 PM PDT 24
Peak memory 200308 kb
Host smart-74e3d1ba-b980-4e28-8e9d-384ff78bf323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330233971 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.3330233971
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.513962262
Short name T910
Test name
Test status
Simulation time 12789708 ps
CPU time 0.68 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:51 PM PDT 24
Peak memory 198944 kb
Host smart-e8820b94-52a4-4643-a3f8-6cb2d56de1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513962262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clk
mgr_intr_test.513962262
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.457182166
Short name T944
Test name
Test status
Simulation time 86694389 ps
CPU time 1.24 seconds
Started Aug 05 05:59:46 PM PDT 24
Finished Aug 05 05:59:47 PM PDT 24
Peak memory 200516 kb
Host smart-c85ed629-4e35-4ae3-ab63-c6ecafbb9574
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457182166 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 11.clkmgr_same_csr_outstanding.457182166
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.17455252
Short name T934
Test name
Test status
Simulation time 113540660 ps
CPU time 1.42 seconds
Started Aug 05 05:59:40 PM PDT 24
Finished Aug 05 05:59:42 PM PDT 24
Peak memory 200604 kb
Host smart-8afa1536-a59e-4ba2-a25a-d086cb774857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17455252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_
test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.clkmgr_shadow_reg_errors.17455252
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.6563980
Short name T62
Test name
Test status
Simulation time 130921719 ps
CPU time 2.69 seconds
Started Aug 05 05:59:39 PM PDT 24
Finished Aug 05 05:59:42 PM PDT 24
Peak memory 217192 kb
Host smart-c63da4f4-fade-49a5-acc7-7afcb728b304
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6563980 -assert nopostproc +UVM_TESTNAME=c
lkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.6563980
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.3413370913
Short name T876
Test name
Test status
Simulation time 179081826 ps
CPU time 2.07 seconds
Started Aug 05 05:59:39 PM PDT 24
Finished Aug 05 05:59:41 PM PDT 24
Peak memory 200596 kb
Host smart-89c7e470-f309-405b-af98-dae3f23762fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413370913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.3413370913
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.2236159240
Short name T961
Test name
Test status
Simulation time 149754130 ps
CPU time 1.53 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 200428 kb
Host smart-cc363acc-1f3d-4f2a-a56c-d995009c986b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236159240 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.2236159240
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.1446325337
Short name T853
Test name
Test status
Simulation time 13372345 ps
CPU time 0.8 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 200336 kb
Host smart-74647aef-a1f8-45c8-b23a-73fa4253e6d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446325337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.1446325337
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.4188559426
Short name T860
Test name
Test status
Simulation time 13600624 ps
CPU time 0.69 seconds
Started Aug 05 05:59:48 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 198972 kb
Host smart-a6d6f940-643e-4ac0-bba4-86d9222e8db3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188559426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.4188559426
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3328864102
Short name T921
Test name
Test status
Simulation time 21387822 ps
CPU time 0.91 seconds
Started Aug 05 05:59:48 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 200364 kb
Host smart-db0d0530-d874-4b26-97b6-7d7c00a178b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328864102 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.3328864102
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.403767475
Short name T939
Test name
Test status
Simulation time 197139238 ps
CPU time 1.78 seconds
Started Aug 05 05:59:47 PM PDT 24
Finished Aug 05 05:59:49 PM PDT 24
Peak memory 200808 kb
Host smart-3b06ab7f-c899-4850-a65f-2a147bda88b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403767475 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.clkmgr_shadow_reg_errors.403767475
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.799710109
Short name T56
Test name
Test status
Simulation time 92792859 ps
CPU time 1.92 seconds
Started Aug 05 05:59:47 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 210032 kb
Host smart-90a2441d-73e4-4792-b12a-2de5997b83bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799710109 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.799710109
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.3813455084
Short name T892
Test name
Test status
Simulation time 31610391 ps
CPU time 1.68 seconds
Started Aug 05 05:59:44 PM PDT 24
Finished Aug 05 05:59:46 PM PDT 24
Peak memory 200552 kb
Host smart-2e8aab97-9976-4b1b-9d91-78d089d960ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813455084 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.3813455084
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.4188275288
Short name T167
Test name
Test status
Simulation time 127094024 ps
CPU time 2.62 seconds
Started Aug 05 05:59:55 PM PDT 24
Finished Aug 05 05:59:57 PM PDT 24
Peak memory 200564 kb
Host smart-f557a6d7-b291-4c6f-8d1b-1df72991d490
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188275288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.clkmgr_tl_intg_err.4188275288
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.2407282850
Short name T859
Test name
Test status
Simulation time 118917352 ps
CPU time 1.36 seconds
Started Aug 05 05:59:51 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 200444 kb
Host smart-afe07f2b-7099-4dca-a5ea-fa9b99b44f08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407282850 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.2407282850
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1704638487
Short name T906
Test name
Test status
Simulation time 25128652 ps
CPU time 0.8 seconds
Started Aug 05 05:59:47 PM PDT 24
Finished Aug 05 05:59:48 PM PDT 24
Peak memory 200360 kb
Host smart-a03ed641-e638-4266-9d3a-aa9497a6a2fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704638487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.1704638487
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.4227512149
Short name T824
Test name
Test status
Simulation time 17727699 ps
CPU time 0.67 seconds
Started Aug 05 05:59:51 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 198996 kb
Host smart-7b49a67c-964a-494e-b83f-50d01f4803ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227512149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.4227512149
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3200587509
Short name T909
Test name
Test status
Simulation time 169057066 ps
CPU time 1.56 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 200552 kb
Host smart-8ec90df2-f81f-4182-87e0-110dfc91903f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200587509 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 13.clkmgr_same_csr_outstanding.3200587509
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2245071032
Short name T119
Test name
Test status
Simulation time 214942745 ps
CPU time 2.04 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 217048 kb
Host smart-83c7ccee-37b7-4f41-9628-dfd7f5b551c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245071032 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2245071032
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.278919779
Short name T968
Test name
Test status
Simulation time 93858663 ps
CPU time 1.71 seconds
Started Aug 05 05:59:48 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 209032 kb
Host smart-194e587b-4e2a-4fae-8ac4-3601e9da65be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278919779 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.278919779
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.116205125
Short name T954
Test name
Test status
Simulation time 123325683 ps
CPU time 2.2 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 200528 kb
Host smart-ca763ac0-fd31-4b1c-94e3-fefdce093f8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116205125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_tl_errors.116205125
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3061038617
Short name T913
Test name
Test status
Simulation time 69840323 ps
CPU time 1.62 seconds
Started Aug 05 05:59:43 PM PDT 24
Finished Aug 05 05:59:45 PM PDT 24
Peak memory 200536 kb
Host smart-3fb13550-440e-41b5-ad7d-ef71bc040929
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061038617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.clkmgr_tl_intg_err.3061038617
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.392537327
Short name T938
Test name
Test status
Simulation time 74020068 ps
CPU time 1.14 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 200444 kb
Host smart-339e40bf-5237-47e8-8da0-d5bf5ad66de2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392537327 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.392537327
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.3243116433
Short name T964
Test name
Test status
Simulation time 13580986 ps
CPU time 0.78 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 200356 kb
Host smart-0c9ec289-6708-42fc-8fbf-67011712e5af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243116433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.3243116433
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.64642073
Short name T911
Test name
Test status
Simulation time 86902248 ps
CPU time 0.83 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 198960 kb
Host smart-1dbcf41c-f646-4a4d-929d-8806b1aa364d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64642073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkm
gr_intr_test.64642073
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1213188097
Short name T896
Test name
Test status
Simulation time 169587104 ps
CPU time 1.68 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:54 PM PDT 24
Peak memory 200552 kb
Host smart-fd66e37d-e0a0-4e76-8e9e-e1602ed1d8e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213188097 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1213188097
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.693740201
Short name T59
Test name
Test status
Simulation time 134309784 ps
CPU time 1.84 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 209044 kb
Host smart-4ad95a16-e00d-4f3b-a2cb-cf3b326c8b11
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693740201 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.693740201
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.4092489723
Short name T825
Test name
Test status
Simulation time 238007594 ps
CPU time 2.28 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:55 PM PDT 24
Peak memory 200480 kb
Host smart-28c28475-6948-450a-bb8c-6f10b6f9d6af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092489723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.4092489723
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3215325786
Short name T107
Test name
Test status
Simulation time 144443402 ps
CPU time 2.37 seconds
Started Aug 05 05:59:51 PM PDT 24
Finished Aug 05 05:59:53 PM PDT 24
Peak memory 200576 kb
Host smart-8c02162c-795f-41a3-b5ad-4b3791dab609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215325786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.3215325786
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.3866034382
Short name T875
Test name
Test status
Simulation time 118050870 ps
CPU time 1.54 seconds
Started Aug 05 05:59:53 PM PDT 24
Finished Aug 05 05:59:55 PM PDT 24
Peak memory 200364 kb
Host smart-e2a02896-6dbf-4561-ba9a-4ec75b42b58b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866034382 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.3866034382
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.3071396123
Short name T848
Test name
Test status
Simulation time 18560541 ps
CPU time 0.81 seconds
Started Aug 05 05:59:49 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 200368 kb
Host smart-a71d0e57-0465-412d-91fc-fe8e55e1f5c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071396123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.3071396123
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.1293212168
Short name T843
Test name
Test status
Simulation time 15339325 ps
CPU time 0.66 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:50 PM PDT 24
Peak memory 198972 kb
Host smart-25a1d06d-ab9a-4f7a-8975-2cc203f931d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293212168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.1293212168
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.2680411530
Short name T87
Test name
Test status
Simulation time 103001455 ps
CPU time 1.27 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:54 PM PDT 24
Peak memory 200280 kb
Host smart-47af20d6-67dd-4aa4-8e8e-0101b6092146
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680411530 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.2680411530
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.172375005
Short name T126
Test name
Test status
Simulation time 60729911 ps
CPU time 1.32 seconds
Started Aug 05 05:59:50 PM PDT 24
Finished Aug 05 05:59:52 PM PDT 24
Peak memory 200640 kb
Host smart-fe567680-d22f-4b77-9d65-72240b84ea0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172375005 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.clkmgr_shadow_reg_errors.172375005
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3353852940
Short name T115
Test name
Test status
Simulation time 255669649 ps
CPU time 2.63 seconds
Started Aug 05 05:59:51 PM PDT 24
Finished Aug 05 05:59:54 PM PDT 24
Peak memory 208920 kb
Host smart-0c435ab1-c321-4e2b-84e4-1405b07d8546
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353852940 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3353852940
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.2738113723
Short name T837
Test name
Test status
Simulation time 207086692 ps
CPU time 3.39 seconds
Started Aug 05 05:59:52 PM PDT 24
Finished Aug 05 05:59:56 PM PDT 24
Peak memory 200584 kb
Host smart-27737f3c-1dc0-42a7-ad80-32a0bd2a50ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738113723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.2738113723
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.571804587
Short name T973
Test name
Test status
Simulation time 50658837 ps
CPU time 1.07 seconds
Started Aug 05 05:59:57 PM PDT 24
Finished Aug 05 05:59:58 PM PDT 24
Peak memory 200484 kb
Host smart-3098c080-98f2-4b93-95f4-98305805a9f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571804587 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.571804587
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.498694640
Short name T85
Test name
Test status
Simulation time 30599914 ps
CPU time 0.79 seconds
Started Aug 05 05:59:55 PM PDT 24
Finished Aug 05 05:59:56 PM PDT 24
Peak memory 200272 kb
Host smart-aaeb21e7-8ac8-435c-a5d6-1f2336baf92a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498694640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
clkmgr_csr_rw.498694640
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.2205447229
Short name T877
Test name
Test status
Simulation time 14536155 ps
CPU time 0.69 seconds
Started Aug 05 05:59:59 PM PDT 24
Finished Aug 05 05:59:59 PM PDT 24
Peak memory 199040 kb
Host smart-28c3b2f3-ad06-48c3-8a2d-2bbaf6cb62e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205447229 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.2205447229
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1697731307
Short name T943
Test name
Test status
Simulation time 237000571 ps
CPU time 1.88 seconds
Started Aug 05 05:59:58 PM PDT 24
Finished Aug 05 06:00:00 PM PDT 24
Peak memory 200564 kb
Host smart-dc48b733-fa1a-4f47-b011-985cb3918ed5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697731307 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.1697731307
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.879043426
Short name T114
Test name
Test status
Simulation time 312792600 ps
CPU time 2.26 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:03 PM PDT 24
Peak memory 217148 kb
Host smart-98a03cc9-b5f0-4731-b9f4-85019320e829
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879043426 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.clkmgr_shadow_reg_errors.879043426
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1635997915
Short name T125
Test name
Test status
Simulation time 167630348 ps
CPU time 2.79 seconds
Started Aug 05 05:59:58 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 209064 kb
Host smart-b9743fd0-d4b4-485c-9a6c-ec1a59c443f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635997915 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.1635997915
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.3454846372
Short name T894
Test name
Test status
Simulation time 84401595 ps
CPU time 2.82 seconds
Started Aug 05 05:59:56 PM PDT 24
Finished Aug 05 05:59:59 PM PDT 24
Peak memory 200568 kb
Host smart-9d1646e3-8712-42b7-b512-f6cafbb7023a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454846372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.3454846372
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.3856151108
Short name T904
Test name
Test status
Simulation time 75600757 ps
CPU time 1.75 seconds
Started Aug 05 05:59:58 PM PDT 24
Finished Aug 05 05:59:59 PM PDT 24
Peak memory 200604 kb
Host smart-8e3ac579-d12e-4da0-bcb6-d2d9ec0d4d22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856151108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.3856151108
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1729055427
Short name T917
Test name
Test status
Simulation time 107309820 ps
CPU time 1.37 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 200456 kb
Host smart-f6d688a5-8b06-4aec-b2aa-e9c5d14caba4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729055427 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.1729055427
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.3417023253
Short name T931
Test name
Test status
Simulation time 24493590 ps
CPU time 0.81 seconds
Started Aug 05 06:00:04 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 199960 kb
Host smart-ec77801d-7f4b-4090-b9cf-92bd3ad9df97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417023253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.clkmgr_csr_rw.3417023253
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.3976124926
Short name T937
Test name
Test status
Simulation time 11776555 ps
CPU time 0.67 seconds
Started Aug 05 05:59:55 PM PDT 24
Finished Aug 05 05:59:55 PM PDT 24
Peak memory 199044 kb
Host smart-1f687dc6-7301-4370-ab36-3bf594e62a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976124926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.3976124926
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2964484754
Short name T83
Test name
Test status
Simulation time 31894077 ps
CPU time 1.05 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 200392 kb
Host smart-44448e2c-f53b-4b39-8cfe-e7bccc598280
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964484754 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2964484754
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.2926014271
Short name T967
Test name
Test status
Simulation time 351490198 ps
CPU time 2.75 seconds
Started Aug 05 05:59:58 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 200924 kb
Host smart-ca67ffcd-8912-49df-b63a-a2da5151e71f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926014271 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.2926014271
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4028387686
Short name T121
Test name
Test status
Simulation time 533671377 ps
CPU time 3.91 seconds
Started Aug 05 05:59:54 PM PDT 24
Finished Aug 05 05:59:59 PM PDT 24
Peak memory 217208 kb
Host smart-16176a58-e4b1-4227-9c32-7cba5415f2bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028387686 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.4028387686
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.2134066809
Short name T858
Test name
Test status
Simulation time 128566595 ps
CPU time 2.45 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:03 PM PDT 24
Peak memory 200528 kb
Host smart-43d6a4a2-5894-419e-850d-8c740cf5e4a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134066809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.2134066809
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.943119952
Short name T102
Test name
Test status
Simulation time 98681755 ps
CPU time 2.34 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:03 PM PDT 24
Peak memory 200616 kb
Host smart-cb3d2207-d484-4c1a-aad9-59c27447eb77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943119952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_tl_intg_err.943119952
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.1717352416
Short name T844
Test name
Test status
Simulation time 39010648 ps
CPU time 1 seconds
Started Aug 05 06:00:03 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 200412 kb
Host smart-a767677c-bae0-424e-ba77-6ad5bbda4a56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717352416 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.1717352416
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.3144459190
Short name T86
Test name
Test status
Simulation time 25275306 ps
CPU time 0.84 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 200364 kb
Host smart-2c8b566b-bf2a-4fdd-84d6-85f8fd946452
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144459190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.3144459190
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1376482377
Short name T867
Test name
Test status
Simulation time 14139479 ps
CPU time 0.7 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 198972 kb
Host smart-59fa9e1f-fd08-4c21-ae03-0172bd5da4c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376482377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.1376482377
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1940079695
Short name T863
Test name
Test status
Simulation time 56252334 ps
CPU time 1.47 seconds
Started Aug 05 06:00:02 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 200528 kb
Host smart-287d6dae-55f3-4b3f-bd4d-d22b20cbbef4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940079695 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1940079695
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2461303812
Short name T116
Test name
Test status
Simulation time 293112787 ps
CPU time 2.28 seconds
Started Aug 05 05:59:59 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 217096 kb
Host smart-8e1d7c91-abc3-4add-88be-cc0620fb4bca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461303812 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2461303812
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.1362175892
Short name T907
Test name
Test status
Simulation time 207950766 ps
CPU time 2.09 seconds
Started Aug 05 06:00:02 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 209004 kb
Host smart-77a95ccd-f612-4bf9-a722-b7dbda37bbac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362175892 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1362175892
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3521136551
Short name T955
Test name
Test status
Simulation time 89604247 ps
CPU time 2.26 seconds
Started Aug 05 06:00:04 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 200200 kb
Host smart-d6be2903-3667-44ea-855f-57541a4624e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521136551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3521136551
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.2074271964
Short name T165
Test name
Test status
Simulation time 129407685 ps
CPU time 2.55 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:03 PM PDT 24
Peak memory 200548 kb
Host smart-d2140a1e-4bc4-4ed7-9c60-550bbd8b525b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074271964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.clkmgr_tl_intg_err.2074271964
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1350771862
Short name T883
Test name
Test status
Simulation time 135887632 ps
CPU time 1.58 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 200424 kb
Host smart-057756f8-5f91-4241-b63c-40600a7187bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350771862 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1350771862
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.874514761
Short name T930
Test name
Test status
Simulation time 19522899 ps
CPU time 0.76 seconds
Started Aug 05 06:00:04 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 200148 kb
Host smart-721ec41a-a25e-46ed-a890-7420aa194fc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874514761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.874514761
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.3584445775
Short name T899
Test name
Test status
Simulation time 104723188 ps
CPU time 0.88 seconds
Started Aug 05 06:00:03 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198972 kb
Host smart-33b5bc39-f11f-456c-a4f7-4c4a4705ddc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584445775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.3584445775
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.1880771505
Short name T857
Test name
Test status
Simulation time 47826049 ps
CPU time 1.21 seconds
Started Aug 05 06:00:03 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 200308 kb
Host smart-9d7985cd-eaa4-4f85-83de-1731cb334a15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880771505 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.1880771505
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3175200179
Short name T129
Test name
Test status
Simulation time 58849649 ps
CPU time 1.3 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 200640 kb
Host smart-de50863b-b318-4880-a223-ef5bdb44cf2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175200179 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.3175200179
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.1314403221
Short name T127
Test name
Test status
Simulation time 541115279 ps
CPU time 3.89 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:05 PM PDT 24
Peak memory 200992 kb
Host smart-8642edcc-fea5-4ce6-8e9f-9fe9947416f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314403221 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1314403221
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.1073765399
Short name T929
Test name
Test status
Simulation time 96643215 ps
CPU time 1.9 seconds
Started Aug 05 06:00:03 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 200524 kb
Host smart-26379303-584c-41ed-ab91-d6453bd15eb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073765399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_tl_errors.1073765399
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.3956062874
Short name T969
Test name
Test status
Simulation time 81421270 ps
CPU time 1.6 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:03 PM PDT 24
Peak memory 200616 kb
Host smart-78c661d9-0e23-489f-b86a-175df5a2fce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956062874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.clkmgr_tl_intg_err.3956062874
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.2399367319
Short name T908
Test name
Test status
Simulation time 231504263 ps
CPU time 2.2 seconds
Started Aug 05 05:59:10 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 200552 kb
Host smart-e6cff896-d6eb-4ede-8f9b-6aa8aa6a6646
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399367319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.2399367319
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.1494760205
Short name T882
Test name
Test status
Simulation time 679161722 ps
CPU time 7.16 seconds
Started Aug 05 05:59:09 PM PDT 24
Finished Aug 05 05:59:16 PM PDT 24
Peak memory 200580 kb
Host smart-d52f6039-bffb-41e9-beb5-19a905a2982e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494760205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.1494760205
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.3369319049
Short name T884
Test name
Test status
Simulation time 49697068 ps
CPU time 0.83 seconds
Started Aug 05 05:59:10 PM PDT 24
Finished Aug 05 05:59:10 PM PDT 24
Peak memory 200260 kb
Host smart-1630b540-3ecb-4c4d-b338-a2a8f1a06fba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369319049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_hw_reset.3369319049
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.1225748755
Short name T851
Test name
Test status
Simulation time 41392406 ps
CPU time 1.21 seconds
Started Aug 05 05:59:14 PM PDT 24
Finished Aug 05 05:59:15 PM PDT 24
Peak memory 200452 kb
Host smart-654c48d8-32ee-4ed6-aaad-2c5927f98a23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225748755 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.1225748755
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.2579775335
Short name T871
Test name
Test status
Simulation time 30302846 ps
CPU time 0.8 seconds
Started Aug 05 05:59:07 PM PDT 24
Finished Aug 05 05:59:08 PM PDT 24
Peak memory 200396 kb
Host smart-d43b5d8d-4b76-4120-aa42-2b1630f65b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579775335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.2579775335
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.827016058
Short name T836
Test name
Test status
Simulation time 14039112 ps
CPU time 0.69 seconds
Started Aug 05 05:59:10 PM PDT 24
Finished Aug 05 05:59:11 PM PDT 24
Peak memory 198992 kb
Host smart-61cf3207-f521-4bb1-9a58-f03d20e812c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827016058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_intr_test.827016058
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.2891860469
Short name T874
Test name
Test status
Simulation time 103219003 ps
CPU time 1.62 seconds
Started Aug 05 05:59:10 PM PDT 24
Finished Aug 05 05:59:12 PM PDT 24
Peak memory 200548 kb
Host smart-8d5b211f-f42d-4afd-b058-827972d4629f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891860469 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.clkmgr_same_csr_outstanding.2891860469
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1399053473
Short name T130
Test name
Test status
Simulation time 263960757 ps
CPU time 2.27 seconds
Started Aug 05 05:59:03 PM PDT 24
Finished Aug 05 05:59:05 PM PDT 24
Peak memory 200852 kb
Host smart-c0a78cae-1d3a-46c9-abaa-b23a4eeb1653
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399053473 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.1399053473
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.3907301621
Short name T67
Test name
Test status
Simulation time 137407540 ps
CPU time 1.88 seconds
Started Aug 05 05:59:00 PM PDT 24
Finished Aug 05 05:59:02 PM PDT 24
Peak memory 216896 kb
Host smart-3bb84d9e-ab9b-453d-82ab-625b4d0253e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907301621 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.3907301621
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.788287991
Short name T919
Test name
Test status
Simulation time 42187656 ps
CPU time 2.42 seconds
Started Aug 05 05:59:08 PM PDT 24
Finished Aug 05 05:59:11 PM PDT 24
Peak memory 200556 kb
Host smart-a5bbbe62-ec70-484e-81c7-c6d1306ebd32
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788287991 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.788287991
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.1500931367
Short name T109
Test name
Test status
Simulation time 400814729 ps
CPU time 2.32 seconds
Started Aug 05 05:59:08 PM PDT 24
Finished Aug 05 05:59:11 PM PDT 24
Peak memory 200532 kb
Host smart-e8d21add-0f81-452e-9683-0759d87daaec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500931367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.clkmgr_tl_intg_err.1500931367
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3886629496
Short name T916
Test name
Test status
Simulation time 10298737 ps
CPU time 0.64 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 198972 kb
Host smart-eca4ca9b-7b6a-4468-a2e9-963a5c251f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886629496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.3886629496
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.111463257
Short name T828
Test name
Test status
Simulation time 12513733 ps
CPU time 0.67 seconds
Started Aug 05 06:00:01 PM PDT 24
Finished Aug 05 06:00:02 PM PDT 24
Peak memory 199052 kb
Host smart-929e468e-4fad-441b-a439-abbdae6413bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111463257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clk
mgr_intr_test.111463257
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.597774132
Short name T966
Test name
Test status
Simulation time 12765108 ps
CPU time 0.67 seconds
Started Aug 05 06:00:00 PM PDT 24
Finished Aug 05 06:00:01 PM PDT 24
Peak memory 198952 kb
Host smart-41ce84ae-ff80-44fc-b16a-157ee26c7624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597774132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clk
mgr_intr_test.597774132
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3655399019
Short name T890
Test name
Test status
Simulation time 21108899 ps
CPU time 0.68 seconds
Started Aug 05 06:00:02 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 199020 kb
Host smart-a7fad092-7731-46d9-b0a2-7f06e849470d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655399019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3655399019
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.3608939819
Short name T925
Test name
Test status
Simulation time 14129895 ps
CPU time 0.67 seconds
Started Aug 05 06:00:05 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198960 kb
Host smart-f05034c5-04cb-4d64-b310-1b8a150ccaa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608939819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.3608939819
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2113358608
Short name T854
Test name
Test status
Simulation time 28012338 ps
CPU time 0.69 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 199080 kb
Host smart-65f79323-45fe-4a41-b86a-8883ff5dd3c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113358608 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2113358608
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.1777022551
Short name T872
Test name
Test status
Simulation time 11822893 ps
CPU time 0.66 seconds
Started Aug 05 06:00:05 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198916 kb
Host smart-5fbfef95-5bdd-4d0b-83d5-1fb7d7f71844
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777022551 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.cl
kmgr_intr_test.1777022551
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.1286130433
Short name T936
Test name
Test status
Simulation time 37692661 ps
CPU time 0.74 seconds
Started Aug 05 06:00:10 PM PDT 24
Finished Aug 05 06:00:10 PM PDT 24
Peak memory 199044 kb
Host smart-a96aac81-f772-434e-bce5-4a5686316083
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286130433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.1286130433
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2713347035
Short name T893
Test name
Test status
Simulation time 17886081 ps
CPU time 0.68 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198980 kb
Host smart-7cbc2024-35ad-4c6a-a512-625480fb6db6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713347035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.2713347035
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.2617381267
Short name T923
Test name
Test status
Simulation time 15764892 ps
CPU time 0.66 seconds
Started Aug 05 06:00:07 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 198972 kb
Host smart-6cea2e8f-0e14-4da1-b046-c4abd5f7b0ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617381267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.2617381267
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.891089013
Short name T827
Test name
Test status
Simulation time 35513790 ps
CPU time 1.18 seconds
Started Aug 05 05:59:14 PM PDT 24
Finished Aug 05 05:59:15 PM PDT 24
Peak memory 200400 kb
Host smart-97327ec4-2869-4112-88bf-c438d4094a5c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891089013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_aliasing.891089013
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.378220483
Short name T958
Test name
Test status
Simulation time 1016744839 ps
CPU time 6.57 seconds
Started Aug 05 05:59:12 PM PDT 24
Finished Aug 05 05:59:19 PM PDT 24
Peak memory 200560 kb
Host smart-250c3b62-2c90-4528-92bd-bb4ff76efefd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378220483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_bit_bash.378220483
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.265128137
Short name T842
Test name
Test status
Simulation time 44147344 ps
CPU time 0.87 seconds
Started Aug 05 05:59:11 PM PDT 24
Finished Aug 05 05:59:12 PM PDT 24
Peak memory 200340 kb
Host smart-e15e4ef4-2838-4f42-b1c7-483448275af9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265128137 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_csr_hw_reset.265128137
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.2280959968
Short name T832
Test name
Test status
Simulation time 42613872 ps
CPU time 1.08 seconds
Started Aug 05 05:59:16 PM PDT 24
Finished Aug 05 05:59:17 PM PDT 24
Peak memory 200460 kb
Host smart-097803da-97a5-4ce9-9f55-aa12e0627689
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280959968 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.2280959968
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1177233404
Short name T868
Test name
Test status
Simulation time 38401496 ps
CPU time 0.83 seconds
Started Aug 05 05:59:18 PM PDT 24
Finished Aug 05 05:59:18 PM PDT 24
Peak memory 200360 kb
Host smart-3ff27ccc-cdd5-4ff9-9cb9-ae58e9ed9a5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177233404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1177233404
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.2307209573
Short name T830
Test name
Test status
Simulation time 30162263 ps
CPU time 0.69 seconds
Started Aug 05 05:59:12 PM PDT 24
Finished Aug 05 05:59:13 PM PDT 24
Peak memory 198972 kb
Host smart-f9f452db-6924-4e25-a500-7bccc6b1c012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307209573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.2307209573
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1216103619
Short name T947
Test name
Test status
Simulation time 132581513 ps
CPU time 1.15 seconds
Started Aug 05 05:59:19 PM PDT 24
Finished Aug 05 05:59:20 PM PDT 24
Peak memory 200368 kb
Host smart-94b62072-b703-490b-9910-5cfa2f1dad11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216103619 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.1216103619
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.1656568577
Short name T124
Test name
Test status
Simulation time 256171804 ps
CPU time 1.58 seconds
Started Aug 05 05:59:13 PM PDT 24
Finished Aug 05 05:59:14 PM PDT 24
Peak memory 200648 kb
Host smart-a1b9706f-d513-413a-9aca-d33a26f5430a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656568577 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.1656568577
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.2388421342
Short name T68
Test name
Test status
Simulation time 157000876 ps
CPU time 2.9 seconds
Started Aug 05 05:59:14 PM PDT 24
Finished Aug 05 05:59:17 PM PDT 24
Peak memory 209020 kb
Host smart-0917b1c1-bed6-4a74-934b-212f7202e77e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388421342 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.2388421342
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2966313850
Short name T927
Test name
Test status
Simulation time 130403946 ps
CPU time 2.29 seconds
Started Aug 05 05:59:13 PM PDT 24
Finished Aug 05 05:59:16 PM PDT 24
Peak memory 200520 kb
Host smart-9ff00579-7f68-4785-b6eb-d92ef14d1b37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966313850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2966313850
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.3299392901
Short name T105
Test name
Test status
Simulation time 77384470 ps
CPU time 1.69 seconds
Started Aug 05 05:59:13 PM PDT 24
Finished Aug 05 05:59:14 PM PDT 24
Peak memory 200564 kb
Host smart-aec93502-dad7-4011-86cd-00a8d300e4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299392901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.clkmgr_tl_intg_err.3299392901
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.3760715943
Short name T918
Test name
Test status
Simulation time 26936585 ps
CPU time 0.69 seconds
Started Aug 05 06:00:08 PM PDT 24
Finished Aug 05 06:00:09 PM PDT 24
Peak memory 198984 kb
Host smart-0d019296-c7d3-4f3e-8ce3-d636598e5056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760715943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.3760715943
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1262381484
Short name T865
Test name
Test status
Simulation time 11223841 ps
CPU time 0.64 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198972 kb
Host smart-c1a7fe8b-1ecf-4956-aba4-b45d96b79cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262381484 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1262381484
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2797887001
Short name T823
Test name
Test status
Simulation time 17232076 ps
CPU time 0.66 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198972 kb
Host smart-411ad3ca-7fca-41da-82df-b92a3b4ad716
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797887001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.2797887001
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.3596556232
Short name T881
Test name
Test status
Simulation time 35185188 ps
CPU time 0.73 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 198968 kb
Host smart-c56eee89-75e4-4b7b-8beb-41d939105f9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596556232 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.3596556232
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.1014071257
Short name T849
Test name
Test status
Simulation time 28876601 ps
CPU time 0.71 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 198968 kb
Host smart-9639c258-4bfd-4ec0-9803-828b57adebf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014071257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.cl
kmgr_intr_test.1014071257
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.2699565109
Short name T888
Test name
Test status
Simulation time 15311746 ps
CPU time 0.66 seconds
Started Aug 05 06:00:07 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 199004 kb
Host smart-5b24c2ac-ba47-4b3b-ab8f-35beb240d442
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699565109 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.2699565109
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.4056783071
Short name T903
Test name
Test status
Simulation time 16476216 ps
CPU time 0.69 seconds
Started Aug 05 06:00:05 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198992 kb
Host smart-00ea54fa-f2a0-4c10-ad78-842c2042638e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056783071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.4056783071
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.2300309978
Short name T914
Test name
Test status
Simulation time 120279949 ps
CPU time 0.95 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 199040 kb
Host smart-774509b3-ec2a-459b-af17-6c6121c1308a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300309978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.2300309978
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.619119750
Short name T922
Test name
Test status
Simulation time 54738505 ps
CPU time 0.78 seconds
Started Aug 05 06:00:07 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 198984 kb
Host smart-20dfd969-3cb3-4da5-ba4f-8a34136ea9d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619119750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clk
mgr_intr_test.619119750
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.540699879
Short name T846
Test name
Test status
Simulation time 15197046 ps
CPU time 0.66 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 199172 kb
Host smart-3a57d374-5b70-4fc6-9d6c-c6f76bdc3c19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540699879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clk
mgr_intr_test.540699879
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3550860812
Short name T963
Test name
Test status
Simulation time 401269499 ps
CPU time 2.12 seconds
Started Aug 05 05:59:17 PM PDT 24
Finished Aug 05 05:59:19 PM PDT 24
Peak memory 200436 kb
Host smart-52162187-1954-4843-a2bb-800b914c32e3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550860812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3550860812
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.1852327085
Short name T949
Test name
Test status
Simulation time 2555926687 ps
CPU time 12.48 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 200568 kb
Host smart-303c4384-f0a0-4239-93bd-3d34100cd88b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852327085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.1852327085
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1463500638
Short name T898
Test name
Test status
Simulation time 72962076 ps
CPU time 0.97 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:26 PM PDT 24
Peak memory 200320 kb
Host smart-6b9c8ef6-74fb-4ee7-8358-72270e0e74ac
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463500638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1463500638
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.1757773384
Short name T866
Test name
Test status
Simulation time 22680316 ps
CPU time 0.87 seconds
Started Aug 05 05:59:24 PM PDT 24
Finished Aug 05 05:59:25 PM PDT 24
Peak memory 200324 kb
Host smart-22d682a2-7781-4172-a357-c06f2663c809
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757773384 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.1757773384
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.180208094
Short name T885
Test name
Test status
Simulation time 12696081 ps
CPU time 0.74 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:26 PM PDT 24
Peak memory 200288 kb
Host smart-dfff2b3b-0103-4979-a715-10b731a9171a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180208094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.c
lkmgr_csr_rw.180208094
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.383415072
Short name T834
Test name
Test status
Simulation time 104117948 ps
CPU time 0.85 seconds
Started Aug 05 05:59:20 PM PDT 24
Finished Aug 05 05:59:21 PM PDT 24
Peak memory 198972 kb
Host smart-0a0d6d2a-69d7-43b7-99cf-f09c7f72243e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383415072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkm
gr_intr_test.383415072
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.3655557685
Short name T953
Test name
Test status
Simulation time 181884515 ps
CPU time 1.69 seconds
Started Aug 05 05:59:18 PM PDT 24
Finished Aug 05 05:59:19 PM PDT 24
Peak memory 200612 kb
Host smart-30f8cf11-1e38-4bef-9e75-162286c761d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655557685 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.3655557685
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.4208388624
Short name T928
Test name
Test status
Simulation time 163537537 ps
CPU time 1.62 seconds
Started Aug 05 05:59:18 PM PDT 24
Finished Aug 05 05:59:20 PM PDT 24
Peak memory 200612 kb
Host smart-00dc76f1-4f47-4193-acaf-560f1b6b5034
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208388624 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.4208388624
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2984776868
Short name T122
Test name
Test status
Simulation time 217221921 ps
CPU time 2.84 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:28 PM PDT 24
Peak memory 208992 kb
Host smart-85efac88-41b3-42e2-8f0c-f7a18b09889a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984776868 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.2984776868
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1655335323
Short name T933
Test name
Test status
Simulation time 54257148 ps
CPU time 1.81 seconds
Started Aug 05 05:59:17 PM PDT 24
Finished Aug 05 05:59:19 PM PDT 24
Peak memory 200496 kb
Host smart-fac05de4-e887-4c86-8825-a9d57accfc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655335323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1655335323
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.1407935117
Short name T100
Test name
Test status
Simulation time 190215174 ps
CPU time 2.67 seconds
Started Aug 05 05:59:18 PM PDT 24
Finished Aug 05 05:59:21 PM PDT 24
Peak memory 200588 kb
Host smart-9c774c1a-96b5-4db0-8067-0e6a11453f1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407935117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.1407935117
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.1254786211
Short name T942
Test name
Test status
Simulation time 16244842 ps
CPU time 0.72 seconds
Started Aug 05 06:00:10 PM PDT 24
Finished Aug 05 06:00:11 PM PDT 24
Peak memory 199044 kb
Host smart-aa3e9e66-3d5b-4e35-a792-e229f07d9856
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254786211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.cl
kmgr_intr_test.1254786211
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.878067895
Short name T838
Test name
Test status
Simulation time 36790747 ps
CPU time 0.71 seconds
Started Aug 05 06:00:07 PM PDT 24
Finished Aug 05 06:00:08 PM PDT 24
Peak memory 198984 kb
Host smart-705fe507-463e-40f4-86f2-776a6f28365d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878067895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk
mgr_intr_test.878067895
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.537388673
Short name T833
Test name
Test status
Simulation time 37119734 ps
CPU time 0.71 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198980 kb
Host smart-49490e29-01a4-44f7-8184-f4a4addf4d5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537388673 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clk
mgr_intr_test.537388673
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.3854113041
Short name T960
Test name
Test status
Simulation time 38334023 ps
CPU time 0.74 seconds
Started Aug 05 06:00:11 PM PDT 24
Finished Aug 05 06:00:12 PM PDT 24
Peak memory 199040 kb
Host smart-93e22e1c-785b-4c7c-9284-305d3eadbfba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854113041 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.cl
kmgr_intr_test.3854113041
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.1311797530
Short name T912
Test name
Test status
Simulation time 26112140 ps
CPU time 0.69 seconds
Started Aug 05 06:00:06 PM PDT 24
Finished Aug 05 06:00:07 PM PDT 24
Peak memory 198964 kb
Host smart-32c7bba7-6876-4cc4-ab93-7bc7b399b326
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311797530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.1311797530
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.127816870
Short name T835
Test name
Test status
Simulation time 13941409 ps
CPU time 0.7 seconds
Started Aug 05 06:00:09 PM PDT 24
Finished Aug 05 06:00:10 PM PDT 24
Peak memory 198948 kb
Host smart-6d0e7031-893d-4618-9ff9-76c45b351be5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127816870 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clk
mgr_intr_test.127816870
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.1019164531
Short name T895
Test name
Test status
Simulation time 33345497 ps
CPU time 0.7 seconds
Started Aug 05 06:00:09 PM PDT 24
Finished Aug 05 06:00:10 PM PDT 24
Peak memory 198948 kb
Host smart-0ebf60b6-b374-4ae8-83cc-4fa8576ebca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019164531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.cl
kmgr_intr_test.1019164531
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.330739992
Short name T972
Test name
Test status
Simulation time 15340107 ps
CPU time 0.68 seconds
Started Aug 05 06:00:09 PM PDT 24
Finished Aug 05 06:00:10 PM PDT 24
Peak memory 198964 kb
Host smart-460d2a5c-ad10-491e-8d04-2994797d8796
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330739992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clk
mgr_intr_test.330739992
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.2752972347
Short name T946
Test name
Test status
Simulation time 22324249 ps
CPU time 0.73 seconds
Started Aug 05 06:00:13 PM PDT 24
Finished Aug 05 06:00:14 PM PDT 24
Peak memory 198964 kb
Host smart-98d149dc-c7bf-4600-ae58-b905d55b94a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752972347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.2752972347
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.969622247
Short name T862
Test name
Test status
Simulation time 12441784 ps
CPU time 0.72 seconds
Started Aug 05 06:00:12 PM PDT 24
Finished Aug 05 06:00:13 PM PDT 24
Peak memory 199032 kb
Host smart-3f08f5bc-1d49-414b-8160-aa8d5c53cc82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969622247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clk
mgr_intr_test.969622247
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1715250391
Short name T840
Test name
Test status
Simulation time 41166120 ps
CPU time 1.22 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:29 PM PDT 24
Peak memory 200448 kb
Host smart-7268f51a-06bf-48f2-8ce3-de508e3ee936
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715250391 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1715250391
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.4260476285
Short name T839
Test name
Test status
Simulation time 113892234 ps
CPU time 0.97 seconds
Started Aug 05 05:59:23 PM PDT 24
Finished Aug 05 05:59:24 PM PDT 24
Peak memory 200320 kb
Host smart-5a97922d-8d93-4f3e-ad20-4b5f3cd7af38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260476285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.4260476285
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.4294289216
Short name T932
Test name
Test status
Simulation time 32694499 ps
CPU time 0.71 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:26 PM PDT 24
Peak memory 198984 kb
Host smart-2965edae-4689-44fb-8de6-6f23551b994f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294289216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.4294289216
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.332966347
Short name T873
Test name
Test status
Simulation time 239003371 ps
CPU time 1.42 seconds
Started Aug 05 05:59:24 PM PDT 24
Finished Aug 05 05:59:26 PM PDT 24
Peak memory 200300 kb
Host smart-22475d67-2335-419e-a4bc-b508b13b3c3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332966347 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.clkmgr_same_csr_outstanding.332966347
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.729219495
Short name T131
Test name
Test status
Simulation time 167359984 ps
CPU time 2.83 seconds
Started Aug 05 05:59:24 PM PDT 24
Finished Aug 05 05:59:27 PM PDT 24
Peak memory 201048 kb
Host smart-ecdb4a95-9e88-415a-a802-207df4a97c2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729219495 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.729219495
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.3242843835
Short name T948
Test name
Test status
Simulation time 30760817 ps
CPU time 1.7 seconds
Started Aug 05 05:59:25 PM PDT 24
Finished Aug 05 05:59:27 PM PDT 24
Peak memory 200560 kb
Host smart-194546ba-6ed6-44c3-a03b-97d697f8eb4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242843835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.3242843835
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.1983441499
Short name T106
Test name
Test status
Simulation time 474992638 ps
CPU time 2.82 seconds
Started Aug 05 05:59:24 PM PDT 24
Finished Aug 05 05:59:27 PM PDT 24
Peak memory 200536 kb
Host smart-094502fb-b63c-40f1-a1a3-e4b98bb3fe94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983441499 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.clkmgr_tl_intg_err.1983441499
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.3394377157
Short name T926
Test name
Test status
Simulation time 45004088 ps
CPU time 1.25 seconds
Started Aug 05 05:59:32 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 200424 kb
Host smart-bf913622-0ef6-41b3-8f68-c3a6676ded03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394377157 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.3394377157
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.2463454804
Short name T847
Test name
Test status
Simulation time 18157612 ps
CPU time 0.86 seconds
Started Aug 05 05:59:30 PM PDT 24
Finished Aug 05 05:59:31 PM PDT 24
Peak memory 200264 kb
Host smart-868cecf9-a451-4d57-8043-a2d8896863a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463454804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
clkmgr_csr_rw.2463454804
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.2598509806
Short name T959
Test name
Test status
Simulation time 37165822 ps
CPU time 0.73 seconds
Started Aug 05 05:59:36 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 198960 kb
Host smart-76014ade-fd74-4edd-9065-8e26e7a97271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598509806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.2598509806
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1025557914
Short name T957
Test name
Test status
Simulation time 34565356 ps
CPU time 1.08 seconds
Started Aug 05 05:59:27 PM PDT 24
Finished Aug 05 05:59:28 PM PDT 24
Peak memory 200432 kb
Host smart-13988ea2-cb19-4b2f-8093-86c6792600fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025557914 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1025557914
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2302141163
Short name T60
Test name
Test status
Simulation time 91022315 ps
CPU time 1.16 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:29 PM PDT 24
Peak memory 200648 kb
Host smart-0a664c3d-8a77-4f1e-a1c9-ea41c5e10b19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302141163 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2302141163
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1421451419
Short name T57
Test name
Test status
Simulation time 481508067 ps
CPU time 3.85 seconds
Started Aug 05 05:59:31 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 208996 kb
Host smart-b972224a-dd2c-4a65-b90e-04cdba3f4639
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421451419 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1421451419
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.1687154714
Short name T920
Test name
Test status
Simulation time 53130975 ps
CPU time 1.69 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:29 PM PDT 24
Peak memory 200540 kb
Host smart-8b42eabe-ffbf-43f7-bcb7-0540b293d909
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687154714 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.1687154714
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.381033313
Short name T886
Test name
Test status
Simulation time 54345021 ps
CPU time 1.79 seconds
Started Aug 05 05:59:36 PM PDT 24
Finished Aug 05 05:59:38 PM PDT 24
Peak memory 200500 kb
Host smart-ca619045-565c-47a4-a893-7c5b26aa5735
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381033313 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.381033313
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1150547062
Short name T897
Test name
Test status
Simulation time 76337394 ps
CPU time 0.91 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:29 PM PDT 24
Peak memory 200384 kb
Host smart-18668532-c509-483a-95e5-5fa1ad6032cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150547062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.1150547062
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.902035371
Short name T915
Test name
Test status
Simulation time 37823761 ps
CPU time 0.72 seconds
Started Aug 05 05:59:30 PM PDT 24
Finished Aug 05 05:59:30 PM PDT 24
Peak memory 198980 kb
Host smart-4b840e45-b00e-40fe-99b4-2c41b6877b20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902035371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkm
gr_intr_test.902035371
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.4132759916
Short name T905
Test name
Test status
Simulation time 245398422 ps
CPU time 1.97 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:30 PM PDT 24
Peak memory 200716 kb
Host smart-7ac42e49-0e45-48c3-9420-56b16b620366
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132759916 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.4132759916
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.983253723
Short name T120
Test name
Test status
Simulation time 412315814 ps
CPU time 2.74 seconds
Started Aug 05 05:59:36 PM PDT 24
Finished Aug 05 05:59:39 PM PDT 24
Peak memory 209024 kb
Host smart-4d2d81c1-8729-4219-906f-168a3b6da6ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983253723 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 7.clkmgr_shadow_reg_errors.983253723
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.1911706094
Short name T63
Test name
Test status
Simulation time 472441400 ps
CPU time 3.89 seconds
Started Aug 05 05:59:36 PM PDT 24
Finished Aug 05 05:59:40 PM PDT 24
Peak memory 209048 kb
Host smart-0ee87e70-627f-4ca0-893d-1521d5f453eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911706094 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.1911706094
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.1685470422
Short name T924
Test name
Test status
Simulation time 268870963 ps
CPU time 2.43 seconds
Started Aug 05 05:59:29 PM PDT 24
Finished Aug 05 05:59:32 PM PDT 24
Peak memory 200548 kb
Host smart-5d95f9ea-3096-4166-9cf4-203acae47a58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685470422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.1685470422
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3778310062
Short name T99
Test name
Test status
Simulation time 173612491 ps
CPU time 1.93 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:30 PM PDT 24
Peak memory 200604 kb
Host smart-6752e02f-d664-442e-8d21-45a3cd319829
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778310062 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3778310062
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.3169321059
Short name T950
Test name
Test status
Simulation time 29468485 ps
CPU time 1.32 seconds
Started Aug 05 05:59:35 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 200700 kb
Host smart-ec583e49-53f1-4534-b746-d65dfab416d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169321059 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.3169321059
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.160097586
Short name T855
Test name
Test status
Simulation time 49567633 ps
CPU time 0.83 seconds
Started Aug 05 05:59:34 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 200328 kb
Host smart-3b9f42fe-ee68-4643-9e25-a0520f62b305
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160097586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.c
lkmgr_csr_rw.160097586
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.4098548706
Short name T878
Test name
Test status
Simulation time 34703339 ps
CPU time 0.72 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:29 PM PDT 24
Peak memory 198920 kb
Host smart-3aa5ed88-f8f9-4033-aa61-ab379b447756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098548706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_intr_test.4098548706
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2754723461
Short name T941
Test name
Test status
Simulation time 25572139 ps
CPU time 0.97 seconds
Started Aug 05 05:59:34 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 200384 kb
Host smart-af438d27-5224-4f9b-98d9-4bbc04f43a0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754723461 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.2754723461
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.228499131
Short name T128
Test name
Test status
Simulation time 527251103 ps
CPU time 2.56 seconds
Started Aug 05 05:59:29 PM PDT 24
Finished Aug 05 05:59:32 PM PDT 24
Peak memory 200628 kb
Host smart-8019ec79-146d-4b2f-b708-c4dc26c6a793
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228499131 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.clkmgr_shadow_reg_errors.228499131
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3071324377
Short name T66
Test name
Test status
Simulation time 114932918 ps
CPU time 2.62 seconds
Started Aug 05 05:59:28 PM PDT 24
Finished Aug 05 05:59:31 PM PDT 24
Peak memory 201176 kb
Host smart-d6103845-f85c-414b-9d93-9e265177dbd5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071324377 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3071324377
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.862462982
Short name T887
Test name
Test status
Simulation time 1447977734 ps
CPU time 5.64 seconds
Started Aug 05 05:59:30 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 200424 kb
Host smart-3671db6e-3eb8-47ae-ad8f-11f57b0a70a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862462982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_tl_errors.862462982
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.3766775536
Short name T108
Test name
Test status
Simulation time 98863327 ps
CPU time 2.54 seconds
Started Aug 05 05:59:29 PM PDT 24
Finished Aug 05 05:59:31 PM PDT 24
Peak memory 200604 kb
Host smart-762d6bb5-1db2-4597-b952-14b455f7b39b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766775536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.3766775536
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.19108412
Short name T940
Test name
Test status
Simulation time 20799390 ps
CPU time 0.88 seconds
Started Aug 05 05:59:34 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 200436 kb
Host smart-0a56d3d8-1f3c-4fd8-9514-1b6fd192b92f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19108412 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.19108412
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.2490368445
Short name T952
Test name
Test status
Simulation time 22203867 ps
CPU time 0.81 seconds
Started Aug 05 05:59:33 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 200356 kb
Host smart-a7b79fe7-0e6e-40c0-9111-3d72b4215594
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490368445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
clkmgr_csr_rw.2490368445
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.499704804
Short name T850
Test name
Test status
Simulation time 13096244 ps
CPU time 0.68 seconds
Started Aug 05 05:59:34 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 198956 kb
Host smart-131ffad7-9553-4c0e-80cb-1aad7338a370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499704804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkm
gr_intr_test.499704804
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.1510149633
Short name T891
Test name
Test status
Simulation time 279670963 ps
CPU time 2.02 seconds
Started Aug 05 05:59:37 PM PDT 24
Finished Aug 05 05:59:39 PM PDT 24
Peak memory 200592 kb
Host smart-f9860f33-8787-4b92-a4ce-6751b4687198
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510149633 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.1510149633
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2312605594
Short name T64
Test name
Test status
Simulation time 140900556 ps
CPU time 2.08 seconds
Started Aug 05 05:59:32 PM PDT 24
Finished Aug 05 05:59:34 PM PDT 24
Peak memory 200892 kb
Host smart-d533b387-e00d-4196-a3cf-64d401958aad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312605594 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.2312605594
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.4189233140
Short name T118
Test name
Test status
Simulation time 294395492 ps
CPU time 2.45 seconds
Started Aug 05 05:59:34 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 209008 kb
Host smart-6ab0212f-3dae-4fa8-9de7-e1921b30f4f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189233140 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.4189233140
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.4019890119
Short name T156
Test name
Test status
Simulation time 722838928 ps
CPU time 3.69 seconds
Started Aug 05 05:59:33 PM PDT 24
Finished Aug 05 05:59:37 PM PDT 24
Peak memory 200756 kb
Host smart-c91a3aef-db04-4078-bc37-8beaddcba241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019890119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.4019890119
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.1533257977
Short name T974
Test name
Test status
Simulation time 52052044 ps
CPU time 1.62 seconds
Started Aug 05 05:59:33 PM PDT 24
Finished Aug 05 05:59:35 PM PDT 24
Peak memory 200576 kb
Host smart-94f1e17d-3780-41f1-ba97-bfc82af0334a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533257977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.1533257977
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.2924986485
Short name T725
Test name
Test status
Simulation time 20165231 ps
CPU time 0.74 seconds
Started Aug 05 06:23:10 PM PDT 24
Finished Aug 05 06:23:10 PM PDT 24
Peak memory 201124 kb
Host smart-746e5cfd-2fa8-452b-b68d-c2ce3a0bfb59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924986485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.2924986485
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1701604145
Short name T798
Test name
Test status
Simulation time 49513528 ps
CPU time 0.9 seconds
Started Aug 05 06:23:04 PM PDT 24
Finished Aug 05 06:23:05 PM PDT 24
Peak memory 201072 kb
Host smart-06c8766f-54d9-4c3f-877f-dca8acd86a78
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701604145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1701604145
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.3830373415
Short name T41
Test name
Test status
Simulation time 32839077 ps
CPU time 0.74 seconds
Started Aug 05 06:23:03 PM PDT 24
Finished Aug 05 06:23:04 PM PDT 24
Peak memory 200292 kb
Host smart-a037195b-0867-465e-9ca1-34c58c34b10c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830373415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3830373415
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.1600722976
Short name T297
Test name
Test status
Simulation time 16932464 ps
CPU time 0.77 seconds
Started Aug 05 06:23:09 PM PDT 24
Finished Aug 05 06:23:10 PM PDT 24
Peak memory 201072 kb
Host smart-3a273fe5-8754-4e56-85d4-f0aaec9f3cd8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600722976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.1600722976
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.4126122921
Short name T213
Test name
Test status
Simulation time 61863099 ps
CPU time 0.95 seconds
Started Aug 05 06:22:56 PM PDT 24
Finished Aug 05 06:22:58 PM PDT 24
Peak memory 201020 kb
Host smart-cb80f1a0-1b5e-477a-947b-725d24b62cea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126122921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.4126122921
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.2417136895
Short name T674
Test name
Test status
Simulation time 1105835643 ps
CPU time 5.13 seconds
Started Aug 05 06:22:57 PM PDT 24
Finished Aug 05 06:23:03 PM PDT 24
Peak memory 201136 kb
Host smart-4e8ce897-d19c-4c47-ba90-5c2fbdd74443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417136895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.2417136895
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.3496821906
Short name T240
Test name
Test status
Simulation time 2296871112 ps
CPU time 16.28 seconds
Started Aug 05 06:22:58 PM PDT 24
Finished Aug 05 06:23:14 PM PDT 24
Peak memory 201468 kb
Host smart-05f9b1b6-8a83-4b08-b002-94ac3ba3dddf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496821906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.3496821906
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.2902630390
Short name T605
Test name
Test status
Simulation time 26129215 ps
CPU time 0.91 seconds
Started Aug 05 06:23:03 PM PDT 24
Finished Aug 05 06:23:05 PM PDT 24
Peak memory 201124 kb
Host smart-1db9e122-d987-4db8-a627-20fd95ccf1f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902630390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.2902630390
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3776928715
Short name T362
Test name
Test status
Simulation time 23729256 ps
CPU time 0.89 seconds
Started Aug 05 06:23:04 PM PDT 24
Finished Aug 05 06:23:06 PM PDT 24
Peak memory 201084 kb
Host smart-a27ab463-8096-4c46-bf0f-5896a0428b11
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776928715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3776928715
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.1243383174
Short name T237
Test name
Test status
Simulation time 89890486 ps
CPU time 1.1 seconds
Started Aug 05 06:23:04 PM PDT 24
Finished Aug 05 06:23:05 PM PDT 24
Peak memory 201088 kb
Host smart-ddd5fe49-0b98-46d8-973d-90cf87d4086e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243383174 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.1243383174
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.2166723297
Short name T431
Test name
Test status
Simulation time 38305694 ps
CPU time 0.81 seconds
Started Aug 05 06:22:57 PM PDT 24
Finished Aug 05 06:22:58 PM PDT 24
Peak memory 201112 kb
Host smart-13e7d7da-37c8-46e4-852b-99df6dcf53a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166723297 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2166723297
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3945411178
Short name T586
Test name
Test status
Simulation time 677007553 ps
CPU time 3.9 seconds
Started Aug 05 06:23:09 PM PDT 24
Finished Aug 05 06:23:13 PM PDT 24
Peak memory 201328 kb
Host smart-d86842c2-a0c1-41c6-8acc-fae5f0583318
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945411178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3945411178
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.3475359348
Short name T651
Test name
Test status
Simulation time 59736023 ps
CPU time 0.96 seconds
Started Aug 05 06:22:57 PM PDT 24
Finished Aug 05 06:22:58 PM PDT 24
Peak memory 201000 kb
Host smart-2c3f3324-7a79-4bcd-a25a-99489ff5f882
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475359348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3475359348
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.247808098
Short name T815
Test name
Test status
Simulation time 13322052572 ps
CPU time 50.23 seconds
Started Aug 05 06:23:09 PM PDT 24
Finished Aug 05 06:24:00 PM PDT 24
Peak memory 201492 kb
Host smart-12fb24eb-221b-4808-a328-8eed9a36c020
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247808098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.247808098
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.3179973445
Short name T442
Test name
Test status
Simulation time 133551083 ps
CPU time 1.42 seconds
Started Aug 05 06:23:03 PM PDT 24
Finished Aug 05 06:23:04 PM PDT 24
Peak memory 201072 kb
Host smart-3035780c-b87f-44ce-b363-acb005ce2691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179973445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.3179973445
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.2938821706
Short name T486
Test name
Test status
Simulation time 16473758 ps
CPU time 0.69 seconds
Started Aug 05 06:23:20 PM PDT 24
Finished Aug 05 06:23:21 PM PDT 24
Peak memory 201080 kb
Host smart-99b936f5-f842-4554-8112-02b8238a7de3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938821706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.2938821706
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3802578657
Short name T494
Test name
Test status
Simulation time 14305407 ps
CPU time 0.72 seconds
Started Aug 05 06:23:15 PM PDT 24
Finished Aug 05 06:23:16 PM PDT 24
Peak memory 201208 kb
Host smart-eb399ea8-1245-4d1a-9bb2-df00931df637
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802578657 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3802578657
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.957595175
Short name T339
Test name
Test status
Simulation time 17401497 ps
CPU time 0.73 seconds
Started Aug 05 06:23:16 PM PDT 24
Finished Aug 05 06:23:17 PM PDT 24
Peak memory 201016 kb
Host smart-97fe731b-a4dc-40ae-85d4-05b3a12155f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957595175 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.957595175
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3933510900
Short name T507
Test name
Test status
Simulation time 48955248 ps
CPU time 0.83 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201064 kb
Host smart-be16a277-ad16-44ff-acbf-5d58d763a079
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933510900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3933510900
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.2717472487
Short name T458
Test name
Test status
Simulation time 90596024 ps
CPU time 1.06 seconds
Started Aug 05 06:23:07 PM PDT 24
Finished Aug 05 06:23:09 PM PDT 24
Peak memory 201064 kb
Host smart-65b29a1d-0613-4fa4-a59a-f64b39f3cc9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717472487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.2717472487
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3776658364
Short name T554
Test name
Test status
Simulation time 338517370 ps
CPU time 2.14 seconds
Started Aug 05 06:23:15 PM PDT 24
Finished Aug 05 06:23:17 PM PDT 24
Peak memory 201116 kb
Host smart-5b8b20f3-8620-4d05-a0fe-f34f87fe0946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776658364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3776658364
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.3647223561
Short name T180
Test name
Test status
Simulation time 263876058 ps
CPU time 2 seconds
Started Aug 05 06:23:15 PM PDT 24
Finished Aug 05 06:23:17 PM PDT 24
Peak memory 201196 kb
Host smart-cd3e9437-0464-4275-802d-d9af6fa908c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647223561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_ti
meout.3647223561
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.590612809
Short name T333
Test name
Test status
Simulation time 34162577 ps
CPU time 0.9 seconds
Started Aug 05 06:23:16 PM PDT 24
Finished Aug 05 06:23:17 PM PDT 24
Peak memory 201084 kb
Host smart-5a74b22c-f862-47ad-9ece-9aa7eb55c2fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590612809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
.clkmgr_idle_intersig_mubi.590612809
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.791787387
Short name T565
Test name
Test status
Simulation time 60800054 ps
CPU time 0.91 seconds
Started Aug 05 06:23:14 PM PDT 24
Finished Aug 05 06:23:15 PM PDT 24
Peak memory 201056 kb
Host smart-e5999f35-52cc-4805-89d6-a582bb7b3c50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791787387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 1.clkmgr_lc_clk_byp_req_intersig_mubi.791787387
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3416630146
Short name T386
Test name
Test status
Simulation time 21460190 ps
CPU time 0.85 seconds
Started Aug 05 06:23:15 PM PDT 24
Finished Aug 05 06:23:16 PM PDT 24
Peak memory 201072 kb
Host smart-467dba55-3cdb-4fb6-8d05-fe8a2e3fe867
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416630146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.3416630146
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2856487852
Short name T406
Test name
Test status
Simulation time 18152317 ps
CPU time 0.81 seconds
Started Aug 05 06:23:16 PM PDT 24
Finished Aug 05 06:23:17 PM PDT 24
Peak memory 201052 kb
Host smart-221c27fd-5525-4c5c-8206-32d16f3aea95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856487852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2856487852
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.2504445168
Short name T148
Test name
Test status
Simulation time 1316533731 ps
CPU time 5.24 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:25 PM PDT 24
Peak memory 201276 kb
Host smart-c7221477-6c89-4211-a914-8696e952aed8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504445168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.2504445168
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.135210577
Short name T44
Test name
Test status
Simulation time 308660088 ps
CPU time 2.31 seconds
Started Aug 05 06:23:21 PM PDT 24
Finished Aug 05 06:23:23 PM PDT 24
Peak memory 216552 kb
Host smart-8178582d-aa9a-46b6-ae9a-c793f5a8b654
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135210577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr
_sec_cm.135210577
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2544737238
Short name T454
Test name
Test status
Simulation time 18562369 ps
CPU time 0.83 seconds
Started Aug 05 06:23:09 PM PDT 24
Finished Aug 05 06:23:10 PM PDT 24
Peak memory 201088 kb
Host smart-5fa72dc5-42a5-4a81-b861-b58082f87c71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544737238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2544737238
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.270763216
Short name T1
Test name
Test status
Simulation time 3577957368 ps
CPU time 18.52 seconds
Started Aug 05 06:23:20 PM PDT 24
Finished Aug 05 06:23:39 PM PDT 24
Peak memory 201460 kb
Host smart-1b456e70-028c-4e88-9d25-344fdb1a260c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270763216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.270763216
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2498742632
Short name T300
Test name
Test status
Simulation time 81520581 ps
CPU time 1.07 seconds
Started Aug 05 06:23:14 PM PDT 24
Finished Aug 05 06:23:15 PM PDT 24
Peak memory 201076 kb
Host smart-d0d7a712-1e89-4b47-9a71-020e8147766d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498742632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2498742632
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1236377462
Short name T618
Test name
Test status
Simulation time 59766756 ps
CPU time 0.84 seconds
Started Aug 05 06:24:21 PM PDT 24
Finished Aug 05 06:24:23 PM PDT 24
Peak memory 201112 kb
Host smart-c1cd710f-9e0b-45e3-b8d1-daf566542db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236377462 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1236377462
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.2681366187
Short name T421
Test name
Test status
Simulation time 22211996 ps
CPU time 0.83 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201084 kb
Host smart-e2f448e5-7d9f-4f21-8024-d675ed5e1e28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681366187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.2681366187
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.4187741331
Short name T410
Test name
Test status
Simulation time 33681844 ps
CPU time 0.73 seconds
Started Aug 05 06:24:12 PM PDT 24
Finished Aug 05 06:24:12 PM PDT 24
Peak memory 201028 kb
Host smart-a51ae27d-df22-4e26-ba1c-b80c60696a74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187741331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.4187741331
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.2989646467
Short name T707
Test name
Test status
Simulation time 53523669 ps
CPU time 1 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201084 kb
Host smart-c9b9f210-c96a-4b8b-a264-bb98d93368b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989646467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.2989646467
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.2495786070
Short name T617
Test name
Test status
Simulation time 76550268 ps
CPU time 1 seconds
Started Aug 05 06:24:13 PM PDT 24
Finished Aug 05 06:24:15 PM PDT 24
Peak memory 201088 kb
Host smart-75eee997-1ce9-4a00-8ba9-966168cb01a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495786070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.2495786070
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.695996417
Short name T598
Test name
Test status
Simulation time 315689196 ps
CPU time 2.95 seconds
Started Aug 05 06:24:14 PM PDT 24
Finished Aug 05 06:24:17 PM PDT 24
Peak memory 201132 kb
Host smart-1e27a24b-18f8-417e-9ebb-c1f0f9e7652e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695996417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.695996417
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3037481035
Short name T636
Test name
Test status
Simulation time 501137982 ps
CPU time 3 seconds
Started Aug 05 06:24:14 PM PDT 24
Finished Aug 05 06:24:17 PM PDT 24
Peak memory 201188 kb
Host smart-7e9824e9-4602-4ffa-a050-6e8ce23869da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037481035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3037481035
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.2700597363
Short name T392
Test name
Test status
Simulation time 47391001 ps
CPU time 0.91 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201092 kb
Host smart-e9b33e18-696e-41d8-8c23-cbefcf087a7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700597363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.2700597363
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2824071838
Short name T516
Test name
Test status
Simulation time 24472998 ps
CPU time 0.87 seconds
Started Aug 05 06:24:21 PM PDT 24
Finished Aug 05 06:24:22 PM PDT 24
Peak memory 201072 kb
Host smart-25c596b4-506c-4daf-9b03-efbc1ea771bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824071838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_ctrl_intersig_mubi.2824071838
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.647859413
Short name T23
Test name
Test status
Simulation time 27757035 ps
CPU time 0.75 seconds
Started Aug 05 06:24:11 PM PDT 24
Finished Aug 05 06:24:12 PM PDT 24
Peak memory 201064 kb
Host smart-0d86f797-99a5-4156-84fa-211704f185bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647859413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.647859413
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.3776605923
Short name T11
Test name
Test status
Simulation time 810955092 ps
CPU time 4.38 seconds
Started Aug 05 06:24:17 PM PDT 24
Finished Aug 05 06:24:21 PM PDT 24
Peak memory 201232 kb
Host smart-23af1f14-27eb-4958-a2fd-68174b0dddc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776605923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3776605923
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.559665029
Short name T138
Test name
Test status
Simulation time 36225747 ps
CPU time 0.92 seconds
Started Aug 05 06:24:12 PM PDT 24
Finished Aug 05 06:24:13 PM PDT 24
Peak memory 201092 kb
Host smart-e4f84c52-1ea6-450d-94df-d9d940706a59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559665029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.559665029
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.759498712
Short name T2
Test name
Test status
Simulation time 13114425898 ps
CPU time 46.34 seconds
Started Aug 05 06:24:17 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201360 kb
Host smart-d5d6ba69-e61f-492b-a007-c25ec6c6a1ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759498712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.759498712
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.387909734
Short name T75
Test name
Test status
Simulation time 385859094579 ps
CPU time 1650.1 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:51:49 PM PDT 24
Peak memory 217856 kb
Host smart-c1b6f027-7000-45b4-bdd0-05c6781614c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=387909734 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.387909734
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.2291170768
Short name T591
Test name
Test status
Simulation time 34754247 ps
CPU time 0.91 seconds
Started Aug 05 06:24:13 PM PDT 24
Finished Aug 05 06:24:14 PM PDT 24
Peak memory 201020 kb
Host smart-8150a51c-3d1f-49ad-9e98-71faa630cf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291170768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.2291170768
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.1635584203
Short name T756
Test name
Test status
Simulation time 21187857 ps
CPU time 0.75 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201084 kb
Host smart-5fbd78e8-383d-4401-905b-3e539297da2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635584203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clk
mgr_alert_test.1635584203
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.1252827904
Short name T369
Test name
Test status
Simulation time 49192715 ps
CPU time 0.98 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201076 kb
Host smart-2ebaa0c4-534c-4b67-a1d2-fb263fce1181
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252827904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.1252827904
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.3652842665
Short name T746
Test name
Test status
Simulation time 14376019 ps
CPU time 0.74 seconds
Started Aug 05 06:24:17 PM PDT 24
Finished Aug 05 06:24:18 PM PDT 24
Peak memory 200332 kb
Host smart-97ff9d91-745f-49f5-a9a5-120a87a54756
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652842665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.3652842665
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.1018591292
Short name T334
Test name
Test status
Simulation time 23949465 ps
CPU time 0.84 seconds
Started Aug 05 06:24:17 PM PDT 24
Finished Aug 05 06:24:18 PM PDT 24
Peak memory 201088 kb
Host smart-db96fa39-d2b5-4177-9b81-7982134f7c59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018591292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.1018591292
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.454257559
Short name T474
Test name
Test status
Simulation time 16268997 ps
CPU time 0.78 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201192 kb
Host smart-c9bc5a05-3653-4a77-9be5-f2666939ef7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454257559 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.454257559
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.1995598283
Short name T241
Test name
Test status
Simulation time 806081221 ps
CPU time 5.16 seconds
Started Aug 05 06:24:17 PM PDT 24
Finished Aug 05 06:24:22 PM PDT 24
Peak memory 201192 kb
Host smart-6f5a3969-afc0-4ca8-8eee-ab32631b12d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995598283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.1995598283
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.3619206358
Short name T269
Test name
Test status
Simulation time 1712167141 ps
CPU time 7.28 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:26 PM PDT 24
Peak memory 201192 kb
Host smart-f1504027-e454-4035-b6d1-7ba1dd76eb86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619206358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_t
imeout.3619206358
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.3507993960
Short name T311
Test name
Test status
Simulation time 32897441 ps
CPU time 0.8 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201080 kb
Host smart-5ac66c20-2351-40ea-bd9b-352b3d64b5fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507993960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_idle_intersig_mubi.3507993960
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.1788681667
Short name T577
Test name
Test status
Simulation time 144554144 ps
CPU time 1.25 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201084 kb
Host smart-533d5a4b-0156-4c46-8d49-61838c0bd9f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788681667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_clk_byp_req_intersig_mubi.1788681667
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1638902442
Short name T455
Test name
Test status
Simulation time 14196682 ps
CPU time 0.75 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201060 kb
Host smart-5f455482-b50a-4a48-a4ae-b254a40dd50a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638902442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1638902442
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.3557371614
Short name T301
Test name
Test status
Simulation time 50052420 ps
CPU time 0.88 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201072 kb
Host smart-ec66f1f1-77d3-4886-8d9f-afa0d8a08ba9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557371614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.3557371614
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.4234004076
Short name T305
Test name
Test status
Simulation time 31310423 ps
CPU time 0.86 seconds
Started Aug 05 06:24:19 PM PDT 24
Finished Aug 05 06:24:20 PM PDT 24
Peak memory 201068 kb
Host smart-7aa0d8af-eb44-4725-b745-dc4bd6bb59a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234004076 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.4234004076
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_trans.2692848864
Short name T479
Test name
Test status
Simulation time 34035554 ps
CPU time 1.03 seconds
Started Aug 05 06:24:21 PM PDT 24
Finished Aug 05 06:24:22 PM PDT 24
Peak memory 201096 kb
Host smart-7c4d919e-e6f1-422e-8e1b-ce386368fea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692848864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.2692848864
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2422665816
Short name T191
Test name
Test status
Simulation time 192494620 ps
CPU time 1.27 seconds
Started Aug 05 06:24:26 PM PDT 24
Finished Aug 05 06:24:27 PM PDT 24
Peak memory 201116 kb
Host smart-0a938b08-13f2-4b08-9ef2-f99d804622ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422665816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2422665816
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.2351370908
Short name T425
Test name
Test status
Simulation time 20717987 ps
CPU time 0.83 seconds
Started Aug 05 06:24:27 PM PDT 24
Finished Aug 05 06:24:28 PM PDT 24
Peak memory 201128 kb
Host smart-bb4fa8df-d244-4a9a-a93f-cd3eda802881
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351370908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.2351370908
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.1371314037
Short name T503
Test name
Test status
Simulation time 35817827 ps
CPU time 0.77 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 200328 kb
Host smart-3448a7ee-4c72-451b-8b88-4dfbf1c90403
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371314037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.1371314037
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.2880017545
Short name T320
Test name
Test status
Simulation time 47206770 ps
CPU time 0.85 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:23 PM PDT 24
Peak memory 201088 kb
Host smart-42137652-d1ca-4edf-a7e1-6af234db8d98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880017545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.2880017545
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.75685521
Short name T822
Test name
Test status
Simulation time 36316687 ps
CPU time 0.85 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 201076 kb
Host smart-02b95ea9-b017-4db7-873d-48ebca16d9a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75685521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.75685521
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.4221335444
Short name T783
Test name
Test status
Simulation time 1155983406 ps
CPU time 8.7 seconds
Started Aug 05 06:24:24 PM PDT 24
Finished Aug 05 06:24:33 PM PDT 24
Peak memory 201132 kb
Host smart-d5809f83-17eb-401b-acab-81afa391ea48
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221335444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.4221335444
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.535670497
Short name T814
Test name
Test status
Simulation time 2520082110 ps
CPU time 10.92 seconds
Started Aug 05 06:24:26 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201484 kb
Host smart-e33977e7-33b7-4495-91f0-deaec3f1a385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535670497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_ti
meout.535670497
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1590453580
Short name T469
Test name
Test status
Simulation time 89277112 ps
CPU time 0.95 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 201072 kb
Host smart-94dd0794-3c39-4f34-b6d1-268bce917975
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590453580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.1590453580
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.791974415
Short name T489
Test name
Test status
Simulation time 111167372 ps
CPU time 1.11 seconds
Started Aug 05 06:24:26 PM PDT 24
Finished Aug 05 06:24:28 PM PDT 24
Peak memory 201096 kb
Host smart-51639942-05f4-4155-9663-bb7dfe0ced64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791974415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.clkmgr_lc_clk_byp_req_intersig_mubi.791974415
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.4041311136
Short name T224
Test name
Test status
Simulation time 52281328 ps
CPU time 0.92 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201088 kb
Host smart-a0ed2bbc-d49c-48fc-90b5-995388e7a18c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041311136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.4041311136
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.319380572
Short name T791
Test name
Test status
Simulation time 12296314 ps
CPU time 0.74 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 201072 kb
Host smart-54a52c3a-9466-48b1-b72a-6033fa9a109b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319380572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.319380572
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.3925654324
Short name T681
Test name
Test status
Simulation time 631908905 ps
CPU time 2.98 seconds
Started Aug 05 06:24:25 PM PDT 24
Finished Aug 05 06:24:29 PM PDT 24
Peak memory 201236 kb
Host smart-c9f6cf17-7f78-47e9-80e9-7921c02c743a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925654324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.3925654324
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.546133596
Short name T137
Test name
Test status
Simulation time 76490871 ps
CPU time 1.01 seconds
Started Aug 05 06:24:18 PM PDT 24
Finished Aug 05 06:24:19 PM PDT 24
Peak memory 201028 kb
Host smart-f0de2c25-a479-4d4a-b963-56158d4e429b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546133596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.546133596
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.2640497224
Short name T222
Test name
Test status
Simulation time 7683178064 ps
CPU time 56.69 seconds
Started Aug 05 06:24:25 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201480 kb
Host smart-9fe85710-c2a6-443e-a493-69de40065314
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640497224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.2640497224
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.2706997003
Short name T422
Test name
Test status
Simulation time 46042874 ps
CPU time 0.95 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201092 kb
Host smart-30242631-c8c3-4bb5-8ee5-97d93c7422aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706997003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.2706997003
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.3031886853
Short name T555
Test name
Test status
Simulation time 17521007 ps
CPU time 0.8 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201128 kb
Host smart-d6fca768-36b7-4a4d-b554-0789fa768b1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031886853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.3031886853
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1948442707
Short name T205
Test name
Test status
Simulation time 21853160 ps
CPU time 0.83 seconds
Started Aug 05 06:24:29 PM PDT 24
Finished Aug 05 06:24:30 PM PDT 24
Peak memory 201060 kb
Host smart-68bb3a66-b73e-4647-b552-84413da31f21
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948442707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1948442707
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.2840059069
Short name T768
Test name
Test status
Simulation time 16379406 ps
CPU time 0.74 seconds
Started Aug 05 06:24:24 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 200996 kb
Host smart-fddc2d77-eb5d-4e4c-aba3-3d724252e3fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840059069 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.2840059069
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1836707372
Short name T752
Test name
Test status
Simulation time 250367223 ps
CPU time 1.57 seconds
Started Aug 05 06:24:29 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201064 kb
Host smart-8d4d67d2-0356-4632-83e9-f40fa4879c1a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836707372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1836707372
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.2454637202
Short name T202
Test name
Test status
Simulation time 27997294 ps
CPU time 0.81 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 201000 kb
Host smart-f32cca53-a252-45b2-8dbc-cbc42b7b83bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454637202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2454637202
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.1962430339
Short name T255
Test name
Test status
Simulation time 598687487 ps
CPU time 3.04 seconds
Started Aug 05 06:24:27 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201184 kb
Host smart-121bd0f0-f7f6-4ebf-8f9f-b06ae7c7cbdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962430339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.1962430339
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.4134316784
Short name T779
Test name
Test status
Simulation time 1367163819 ps
CPU time 5.76 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201192 kb
Host smart-1f481c1c-f48f-4773-9936-2882a80a0ff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134316784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.4134316784
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3483825567
Short name T771
Test name
Test status
Simulation time 31148514 ps
CPU time 0.96 seconds
Started Aug 05 06:24:24 PM PDT 24
Finished Aug 05 06:24:25 PM PDT 24
Peak memory 201088 kb
Host smart-a4d79ba2-9a3b-46e7-98c8-2b72fd7d5ecd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483825567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.3483825567
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2954681161
Short name T470
Test name
Test status
Simulation time 92189553 ps
CPU time 1 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201068 kb
Host smart-379244aa-8ace-4f73-8d58-407b8ab3a396
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954681161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.2954681161
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.1511782001
Short name T175
Test name
Test status
Simulation time 39741950 ps
CPU time 0.82 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201088 kb
Host smart-1c1184a0-eee7-4ad5-a0cc-9358a72114c8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511782001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_ctrl_intersig_mubi.1511782001
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1219386138
Short name T819
Test name
Test status
Simulation time 97323612 ps
CPU time 1 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201044 kb
Host smart-70923898-6bb7-459c-a4eb-baeacbc889c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219386138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1219386138
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.1653553838
Short name T451
Test name
Test status
Simulation time 1191113109 ps
CPU time 4.51 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:35 PM PDT 24
Peak memory 201312 kb
Host smart-22654e32-f0cc-4db5-9789-6946ca5377c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653553838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.1653553838
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.772980576
Short name T587
Test name
Test status
Simulation time 21836341 ps
CPU time 0.85 seconds
Started Aug 05 06:24:23 PM PDT 24
Finished Aug 05 06:24:24 PM PDT 24
Peak memory 201128 kb
Host smart-dc66dfaa-c223-4148-a338-db46532b94f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772980576 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.772980576
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.2580794715
Short name T677
Test name
Test status
Simulation time 2489671750 ps
CPU time 19 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:49 PM PDT 24
Peak memory 201476 kb
Host smart-c00d72e7-a9d4-45e3-bad1-85b62160f06a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580794715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.2580794715
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.494636268
Short name T70
Test name
Test status
Simulation time 333240376472 ps
CPU time 1236.4 seconds
Started Aug 05 06:24:28 PM PDT 24
Finished Aug 05 06:45:05 PM PDT 24
Peak memory 217964 kb
Host smart-e8543520-e3f1-419c-a951-65ca49b34a05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=494636268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.494636268
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.3812365246
Short name T20
Test name
Test status
Simulation time 29176358 ps
CPU time 0.89 seconds
Started Aug 05 06:24:26 PM PDT 24
Finished Aug 05 06:24:27 PM PDT 24
Peak memory 201120 kb
Host smart-bc969769-c447-429c-a3ea-99dc37fef1cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812365246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.3812365246
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.124636598
Short name T561
Test name
Test status
Simulation time 27421559 ps
CPU time 0.84 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201112 kb
Host smart-d2f0be8b-cecf-4386-9168-43079ce15e73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124636598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkm
gr_alert_test.124636598
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.1631946967
Short name T600
Test name
Test status
Simulation time 72954576 ps
CPU time 1.04 seconds
Started Aug 05 06:24:29 PM PDT 24
Finished Aug 05 06:24:30 PM PDT 24
Peak memory 201096 kb
Host smart-8777e8c8-e716-4f0e-a9fe-ba81c6f15212
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631946967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.1631946967
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.3665896218
Short name T601
Test name
Test status
Simulation time 40551086 ps
CPU time 0.74 seconds
Started Aug 05 06:24:29 PM PDT 24
Finished Aug 05 06:24:30 PM PDT 24
Peak memory 200996 kb
Host smart-1d6a24ab-f699-4697-be73-fa52e1418d2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665896218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.3665896218
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.837693161
Short name T391
Test name
Test status
Simulation time 19360251 ps
CPU time 0.78 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201108 kb
Host smart-0f1a4bb3-8f61-42a3-bf9e-ce18a2321b99
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837693161 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_div_intersig_mubi.837693161
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.1324819783
Short name T385
Test name
Test status
Simulation time 79421840 ps
CPU time 1.02 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201120 kb
Host smart-7bb9cda1-1253-487c-95a6-16b5d6d27d98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324819783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.1324819783
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.3482612133
Short name T347
Test name
Test status
Simulation time 542295266 ps
CPU time 2.59 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201136 kb
Host smart-61b1196f-efdb-49a8-afb6-db98637ab297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482612133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.3482612133
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.753816924
Short name T706
Test name
Test status
Simulation time 746234265 ps
CPU time 4.13 seconds
Started Aug 05 06:24:28 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201136 kb
Host smart-5fa3111e-2e37-4c34-ab17-ea76ba07d3aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753816924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_ti
meout.753816924
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.2106449632
Short name T647
Test name
Test status
Simulation time 26821162 ps
CPU time 0.93 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 201096 kb
Host smart-841c6833-6305-48ca-bf79-8a00d703059e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106449632 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.2106449632
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.2299604380
Short name T295
Test name
Test status
Simulation time 16937393 ps
CPU time 0.73 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201116 kb
Host smart-0084236a-0710-4a2b-a6e4-e588819819a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299604380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.2299604380
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.3199586476
Short name T258
Test name
Test status
Simulation time 15022481 ps
CPU time 0.72 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:31 PM PDT 24
Peak memory 200924 kb
Host smart-c3e5b286-8cec-45c4-b257-b318b78027a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199586476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_ctrl_intersig_mubi.3199586476
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.2442130000
Short name T583
Test name
Test status
Simulation time 40714643 ps
CPU time 0.8 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201112 kb
Host smart-7ea6457d-3a38-449b-9c0a-1ad2efd3be7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442130000 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.2442130000
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.2574402617
Short name T144
Test name
Test status
Simulation time 990989115 ps
CPU time 6.18 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201276 kb
Host smart-2245ef45-042c-4dfe-baee-3476e64dac6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574402617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2574402617
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.4235670877
Short name T380
Test name
Test status
Simulation time 14697789 ps
CPU time 0.82 seconds
Started Aug 05 06:24:28 PM PDT 24
Finished Aug 05 06:24:29 PM PDT 24
Peak memory 201032 kb
Host smart-8ef69fbd-a0b0-449b-9aa0-e0b4b74c4c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235670877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.4235670877
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.242751095
Short name T34
Test name
Test status
Simulation time 6516818763 ps
CPU time 47.6 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:25:19 PM PDT 24
Peak memory 201472 kb
Host smart-747d1b5c-baae-4771-8e1f-bc4bf10a18fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242751095 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.242751095
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all_with_rand_reset.1128752648
Short name T42
Test name
Test status
Simulation time 250073243396 ps
CPU time 1128.33 seconds
Started Aug 05 06:24:30 PM PDT 24
Finished Aug 05 06:43:19 PM PDT 24
Peak memory 213912 kb
Host smart-a6353f1b-3f48-4ef6-964f-e0b761b000a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1128752648 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.1128752648
Directory /workspace/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.clkmgr_trans.2558053936
Short name T590
Test name
Test status
Simulation time 20452195 ps
CPU time 0.88 seconds
Started Aug 05 06:24:31 PM PDT 24
Finished Aug 05 06:24:32 PM PDT 24
Peak memory 201076 kb
Host smart-94f95d66-0aac-4b4b-bf09-02faff342d02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558053936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.2558053936
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.1583756290
Short name T517
Test name
Test status
Simulation time 17884838 ps
CPU time 0.85 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:42 PM PDT 24
Peak memory 201104 kb
Host smart-b2c23a67-5421-4f41-b729-194251093d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583756290 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.1583756290
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.3134986768
Short name T92
Test name
Test status
Simulation time 19421024 ps
CPU time 0.82 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:36 PM PDT 24
Peak memory 201092 kb
Host smart-dcab1528-3a2c-4a68-bdc6-51eeaf47d04c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134986768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.3134986768
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.3294433164
Short name T559
Test name
Test status
Simulation time 16069829 ps
CPU time 0.72 seconds
Started Aug 05 06:24:45 PM PDT 24
Finished Aug 05 06:24:46 PM PDT 24
Peak memory 201036 kb
Host smart-55629ba5-fc6b-4138-8269-a669e7b08354
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294433164 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.3294433164
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.1148259028
Short name T703
Test name
Test status
Simulation time 70003708 ps
CPU time 0.99 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:36 PM PDT 24
Peak memory 201072 kb
Host smart-01c7315e-4fcc-4186-b7b5-be237af2a980
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148259028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_div_intersig_mubi.1148259028
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.790749510
Short name T402
Test name
Test status
Simulation time 43492505 ps
CPU time 0.81 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:42 PM PDT 24
Peak memory 201100 kb
Host smart-4a389a0a-a7ab-49a0-9ac7-9c89f6423129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790749510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.790749510
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.2820291635
Short name T809
Test name
Test status
Simulation time 2131647379 ps
CPU time 12.28 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201348 kb
Host smart-bd8e5a6d-31e5-4239-b935-d7974c964ee0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820291635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.2820291635
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.4046392417
Short name T755
Test name
Test status
Simulation time 1833819424 ps
CPU time 7.86 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:43 PM PDT 24
Peak memory 201192 kb
Host smart-d2cfb2d4-b162-47ad-ba8b-089c92852b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046392417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.4046392417
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.1619288635
Short name T497
Test name
Test status
Simulation time 54498757 ps
CPU time 0.87 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:51 PM PDT 24
Peak memory 201120 kb
Host smart-048442a6-75e8-4b0c-85d8-ee20eb2dd355
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619288635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_idle_intersig_mubi.1619288635
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.3884968223
Short name T142
Test name
Test status
Simulation time 92172771 ps
CPU time 1.07 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201052 kb
Host smart-9fa1fff2-2fa1-4182-beb7-c85cbc454f67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884968223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.3884968223
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3147469695
Short name T313
Test name
Test status
Simulation time 28659228 ps
CPU time 0.96 seconds
Started Aug 05 06:24:36 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201080 kb
Host smart-18886a5f-ee25-49bd-997b-602f62de3535
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147469695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_ctrl_intersig_mubi.3147469695
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.2703083849
Short name T708
Test name
Test status
Simulation time 41329145 ps
CPU time 0.92 seconds
Started Aug 05 06:24:37 PM PDT 24
Finished Aug 05 06:24:38 PM PDT 24
Peak memory 201184 kb
Host smart-90f53b90-77fe-4df6-91a8-08655db58a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703083849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2703083849
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.3426682415
Short name T627
Test name
Test status
Simulation time 315968983 ps
CPU time 1.82 seconds
Started Aug 05 06:24:45 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201120 kb
Host smart-b6572313-00ad-48d9-a6cb-2205780c6ce4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426682415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.3426682415
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.739757810
Short name T769
Test name
Test status
Simulation time 37403736 ps
CPU time 1.01 seconds
Started Aug 05 06:24:37 PM PDT 24
Finished Aug 05 06:24:38 PM PDT 24
Peak memory 201068 kb
Host smart-4a9e2801-ef52-470d-af92-8aa470a914d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739757810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.739757810
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.1937561493
Short name T694
Test name
Test status
Simulation time 48590566 ps
CPU time 1.07 seconds
Started Aug 05 06:24:36 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201040 kb
Host smart-144a87ad-4854-4810-ac06-003471110877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937561493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.1937561493
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_trans.3868808520
Short name T434
Test name
Test status
Simulation time 105564044 ps
CPU time 1.25 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201080 kb
Host smart-c0d03f38-7bcd-4665-b5f8-f8d7f4bd9960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868808520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.3868808520
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.1779613597
Short name T408
Test name
Test status
Simulation time 17530901 ps
CPU time 0.78 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:51 PM PDT 24
Peak memory 201116 kb
Host smart-cb14be78-0211-4453-8dad-ca3577ec9746
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779613597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clk
mgr_alert_test.1779613597
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1010326037
Short name T535
Test name
Test status
Simulation time 17949076 ps
CPU time 0.8 seconds
Started Aug 05 06:24:43 PM PDT 24
Finished Aug 05 06:24:44 PM PDT 24
Peak memory 201100 kb
Host smart-063aa608-28a5-43c1-92c2-24a82296baa0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010326037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.1010326037
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2604358837
Short name T695
Test name
Test status
Simulation time 32075151 ps
CPU time 0.77 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201032 kb
Host smart-32ff09ae-e0f5-4d30-a4a7-e385519006df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604358837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2604358837
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.2565590226
Short name T521
Test name
Test status
Simulation time 59011549 ps
CPU time 0.91 seconds
Started Aug 05 06:24:40 PM PDT 24
Finished Aug 05 06:24:41 PM PDT 24
Peak memory 201108 kb
Host smart-9450cca3-24ec-4ecf-a472-85574e74cf24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565590226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.2565590226
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.2914978809
Short name T456
Test name
Test status
Simulation time 71632019 ps
CPU time 1.05 seconds
Started Aug 05 06:24:36 PM PDT 24
Finished Aug 05 06:24:37 PM PDT 24
Peak memory 201108 kb
Host smart-5f5fef02-8a97-4554-9a4f-c8324689a4f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914978809 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.2914978809
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.4130670633
Short name T208
Test name
Test status
Simulation time 210725590 ps
CPU time 1.86 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:43 PM PDT 24
Peak memory 201168 kb
Host smart-02579e08-18df-49a3-b46d-84ae1cef8645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130670633 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.4130670633
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.941057765
Short name T252
Test name
Test status
Simulation time 499851131 ps
CPU time 4.3 seconds
Started Aug 05 06:24:36 PM PDT 24
Finished Aug 05 06:24:40 PM PDT 24
Peak memory 201192 kb
Host smart-23689776-a88c-4fd8-ba5f-2601047e645c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941057765 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_ti
meout.941057765
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2662698082
Short name T723
Test name
Test status
Simulation time 60626594 ps
CPU time 1.08 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:42 PM PDT 24
Peak memory 201076 kb
Host smart-eabb0152-6bad-413d-a6df-d8e477adbb81
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662698082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2662698082
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.469950843
Short name T709
Test name
Test status
Simulation time 32723690 ps
CPU time 0.85 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201124 kb
Host smart-b1c99965-ed85-4c5a-a52b-c79dccdd7769
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469950843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.clkmgr_lc_clk_byp_req_intersig_mubi.469950843
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.1082641553
Short name T579
Test name
Test status
Simulation time 59861255 ps
CPU time 0.89 seconds
Started Aug 05 06:24:40 PM PDT 24
Finished Aug 05 06:24:41 PM PDT 24
Peak memory 200996 kb
Host smart-5629a36d-c9d1-4885-b2d7-054fc2b3c8f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082641553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.1082641553
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.3315516569
Short name T530
Test name
Test status
Simulation time 23859606 ps
CPU time 0.75 seconds
Started Aug 05 06:24:35 PM PDT 24
Finished Aug 05 06:24:36 PM PDT 24
Peak memory 201076 kb
Host smart-5129b52a-c412-4248-bb1f-038b21ef5996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315516569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.3315516569
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.2526357705
Short name T659
Test name
Test status
Simulation time 914699104 ps
CPU time 3.83 seconds
Started Aug 05 06:24:40 PM PDT 24
Finished Aug 05 06:24:44 PM PDT 24
Peak memory 201252 kb
Host smart-834b63c8-0340-4291-b3f7-2480d5173e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526357705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.2526357705
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.2648231190
Short name T745
Test name
Test status
Simulation time 17912679 ps
CPU time 0.82 seconds
Started Aug 05 06:24:44 PM PDT 24
Finished Aug 05 06:24:45 PM PDT 24
Peak memory 201068 kb
Host smart-c74a25e9-355b-4ded-a842-a63503bcccac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648231190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.2648231190
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.3359188206
Short name T624
Test name
Test status
Simulation time 1378772257 ps
CPU time 6.13 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:47 PM PDT 24
Peak memory 201224 kb
Host smart-e785e80f-b4a5-4f90-9e0b-0b210cfe1f97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359188206 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.3359188206
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.349787530
Short name T472
Test name
Test status
Simulation time 86185434 ps
CPU time 1.07 seconds
Started Aug 05 06:24:42 PM PDT 24
Finished Aug 05 06:24:43 PM PDT 24
Peak memory 201032 kb
Host smart-2101d5b5-ad03-4ece-9c1b-181ab6d20eb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349787530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.349787530
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.3844827267
Short name T585
Test name
Test status
Simulation time 26898068 ps
CPU time 0.81 seconds
Started Aug 05 06:24:45 PM PDT 24
Finished Aug 05 06:24:46 PM PDT 24
Peak memory 201096 kb
Host smart-d6c2720c-230c-4d46-a9e9-ffad1d1f6915
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844827267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.3844827267
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.550371780
Short name T589
Test name
Test status
Simulation time 86940258 ps
CPU time 1.11 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201120 kb
Host smart-402e77ab-dd6f-4f2d-a197-2304c392b83b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550371780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.550371780
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.3958534485
Short name T796
Test name
Test status
Simulation time 19416522 ps
CPU time 0.72 seconds
Started Aug 05 06:24:46 PM PDT 24
Finished Aug 05 06:24:47 PM PDT 24
Peak memory 200280 kb
Host smart-029e459b-32c8-4d4c-b899-a60428d488b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958534485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.3958534485
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.2161536777
Short name T506
Test name
Test status
Simulation time 26238426 ps
CPU time 0.85 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201052 kb
Host smart-42fb2291-872b-4ac3-9461-3ce62995be2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161536777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_div_intersig_mubi.2161536777
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.2103932676
Short name T548
Test name
Test status
Simulation time 56332398 ps
CPU time 0.88 seconds
Started Aug 05 06:24:42 PM PDT 24
Finished Aug 05 06:24:43 PM PDT 24
Peak memory 201052 kb
Host smart-acbbc2c1-ec6d-44be-969f-2f6f0ab84e2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103932676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.2103932676
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3366178306
Short name T509
Test name
Test status
Simulation time 1757587683 ps
CPU time 13.73 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:25:05 PM PDT 24
Peak memory 201360 kb
Host smart-069d3651-12b1-40f5-911f-b9b37843f459
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366178306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3366178306
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.3083696286
Short name T643
Test name
Test status
Simulation time 1947335683 ps
CPU time 8.43 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:50 PM PDT 24
Peak memory 201332 kb
Host smart-7f588617-6eb8-4cb2-be6d-0af1b0e0ac16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083696286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.3083696286
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.2839231227
Short name T204
Test name
Test status
Simulation time 13256754 ps
CPU time 0.79 seconds
Started Aug 05 06:24:48 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201052 kb
Host smart-a5e6f185-203a-43d5-9db6-6831f76e454f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839231227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_idle_intersig_mubi.2839231227
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.4222985323
Short name T400
Test name
Test status
Simulation time 111831957 ps
CPU time 1.03 seconds
Started Aug 05 06:24:46 PM PDT 24
Finished Aug 05 06:24:47 PM PDT 24
Peak memory 201004 kb
Host smart-cfcfd828-32ae-4a4a-95fb-9c106ecfc2c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222985323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.4222985323
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.513533623
Short name T375
Test name
Test status
Simulation time 18085124 ps
CPU time 0.87 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:51 PM PDT 24
Peak memory 201060 kb
Host smart-8f65ba1b-96e4-4ce2-a701-8d743c8babb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513533623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.clkmgr_lc_ctrl_intersig_mubi.513533623
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1374843723
Short name T221
Test name
Test status
Simulation time 20782952 ps
CPU time 0.8 seconds
Started Aug 05 06:24:41 PM PDT 24
Finished Aug 05 06:24:42 PM PDT 24
Peak memory 201080 kb
Host smart-66d755b2-8474-496f-9e83-54c2d58706ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374843723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1374843723
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.2634306477
Short name T285
Test name
Test status
Simulation time 383409704 ps
CPU time 1.9 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201076 kb
Host smart-4ee16305-e1f3-4a70-820b-f3d350bc550e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634306477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.2634306477
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.3865943426
Short name T359
Test name
Test status
Simulation time 26213463 ps
CPU time 0.83 seconds
Started Aug 05 06:24:42 PM PDT 24
Finished Aug 05 06:24:43 PM PDT 24
Peak memory 201108 kb
Host smart-d59c64ed-821b-4fce-8996-8c071c39433d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865943426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3865943426
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.2378493567
Short name T750
Test name
Test status
Simulation time 7699692222 ps
CPU time 51.78 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201444 kb
Host smart-72611347-94df-4693-8317-899903528d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378493567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.2378493567
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.493616034
Short name T667
Test name
Test status
Simulation time 32928179 ps
CPU time 1.02 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201080 kb
Host smart-11fed116-73e7-448b-ad53-1c0fd62fe922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493616034 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.493616034
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.4180863683
Short name T808
Test name
Test status
Simulation time 51492198 ps
CPU time 0.86 seconds
Started Aug 05 06:24:54 PM PDT 24
Finished Aug 05 06:24:55 PM PDT 24
Peak memory 201092 kb
Host smart-aa59cccc-3c6c-4107-9b3f-1ede67248bdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180863683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clk
mgr_alert_test.4180863683
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.653007139
Short name T77
Test name
Test status
Simulation time 74678221 ps
CPU time 1 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201092 kb
Host smart-6db31bb0-906e-4545-af54-4fcaaaf03f7c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653007139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.653007139
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.2492544964
Short name T157
Test name
Test status
Simulation time 72334983 ps
CPU time 0.92 seconds
Started Aug 05 06:24:46 PM PDT 24
Finished Aug 05 06:24:47 PM PDT 24
Peak memory 200276 kb
Host smart-801fa837-84c0-4ca3-a6a9-825067172207
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492544964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2492544964
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.1429884640
Short name T415
Test name
Test status
Simulation time 70863686 ps
CPU time 0.9 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201064 kb
Host smart-30117e7c-f163-4607-8246-5036b3718ea4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429884640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.1429884640
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.2429095369
Short name T363
Test name
Test status
Simulation time 19254078 ps
CPU time 0.76 seconds
Started Aug 05 06:24:45 PM PDT 24
Finished Aug 05 06:24:46 PM PDT 24
Peak memory 200984 kb
Host smart-f614850e-3bfa-4549-94f1-62174595880a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429095369 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.2429095369
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.4294156187
Short name T568
Test name
Test status
Simulation time 920370387 ps
CPU time 7.49 seconds
Started Aug 05 06:24:46 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201132 kb
Host smart-3e9c4f1d-4d12-489b-9425-70cbef033f41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294156187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.4294156187
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.2318827479
Short name T344
Test name
Test status
Simulation time 980454740 ps
CPU time 5.23 seconds
Started Aug 05 06:24:48 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201192 kb
Host smart-e34f4086-82a7-4fd4-8f62-9b831ccfb3ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318827479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.2318827479
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.411298943
Short name T428
Test name
Test status
Simulation time 20393454 ps
CPU time 0.82 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201096 kb
Host smart-9f784fa3-5213-4c99-b56f-bf5450a8a65e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411298943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_idle_intersig_mubi.411298943
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.3244491589
Short name T263
Test name
Test status
Simulation time 33185251 ps
CPU time 0.91 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201072 kb
Host smart-59377a90-bdef-496f-ac7e-a619636e5b6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244491589 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.3244491589
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.2860991301
Short name T571
Test name
Test status
Simulation time 136653198 ps
CPU time 1.16 seconds
Started Aug 05 06:24:46 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201124 kb
Host smart-be4b7f01-d5d2-4582-be09-c82a86ea08af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860991301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.2860991301
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.1915491208
Short name T249
Test name
Test status
Simulation time 20255301 ps
CPU time 0.76 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201040 kb
Host smart-81a61b19-67f4-4d93-b4e9-00b0735e6574
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915491208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.1915491208
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.1940183877
Short name T573
Test name
Test status
Simulation time 1005052483 ps
CPU time 3.98 seconds
Started Aug 05 06:24:54 PM PDT 24
Finished Aug 05 06:24:58 PM PDT 24
Peak memory 201264 kb
Host smart-eeb503c4-7d9e-449d-b84b-0120d45dee60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940183877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.1940183877
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.497680182
Short name T564
Test name
Test status
Simulation time 21821668 ps
CPU time 0.87 seconds
Started Aug 05 06:24:48 PM PDT 24
Finished Aug 05 06:24:49 PM PDT 24
Peak memory 201044 kb
Host smart-b72fd00e-177f-40df-b715-28bd905fd272
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497680182 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.497680182
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.3210401700
Short name T602
Test name
Test status
Simulation time 7517968243 ps
CPU time 52.64 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 201452 kb
Host smart-51905d04-d1ee-4b20-afc2-fd659d013ab1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210401700 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_stress_all.3210401700
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.1881360580
Short name T668
Test name
Test status
Simulation time 23155244 ps
CPU time 0.89 seconds
Started Aug 05 06:24:47 PM PDT 24
Finished Aug 05 06:24:48 PM PDT 24
Peak memory 201072 kb
Host smart-4b100004-c17a-47ea-9b38-4cefa9b882c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881360580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1881360580
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.1427739853
Short name T799
Test name
Test status
Simulation time 15993619 ps
CPU time 0.76 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:24:59 PM PDT 24
Peak memory 201104 kb
Host smart-74a1661c-c147-4dd2-a269-98366b25447c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427739853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.1427739853
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.1174510905
Short name T728
Test name
Test status
Simulation time 19769488 ps
CPU time 0.84 seconds
Started Aug 05 06:24:54 PM PDT 24
Finished Aug 05 06:24:55 PM PDT 24
Peak memory 201080 kb
Host smart-503de776-ba23-4497-b530-f6ce319d0a7a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174510905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.1174510905
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.1609709418
Short name T159
Test name
Test status
Simulation time 24380337 ps
CPU time 0.74 seconds
Started Aug 05 06:24:52 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 200288 kb
Host smart-c969ecf8-038f-43a8-9cc9-4571b0f5a3ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609709418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.1609709418
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.2990946501
Short name T619
Test name
Test status
Simulation time 20180916 ps
CPU time 0.82 seconds
Started Aug 05 06:24:52 PM PDT 24
Finished Aug 05 06:24:53 PM PDT 24
Peak memory 201124 kb
Host smart-d30fb474-0f1e-4f6d-92b9-0c002b4727f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990946501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.2990946501
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.2248051706
Short name T389
Test name
Test status
Simulation time 17093865 ps
CPU time 0.75 seconds
Started Aug 05 06:24:54 PM PDT 24
Finished Aug 05 06:24:55 PM PDT 24
Peak memory 201072 kb
Host smart-6652d136-5ccb-49ef-80e5-f284d9a5332f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248051706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.2248051706
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3962412750
Short name T216
Test name
Test status
Simulation time 1997281282 ps
CPU time 15.74 seconds
Started Aug 05 06:24:52 PM PDT 24
Finished Aug 05 06:25:08 PM PDT 24
Peak memory 201376 kb
Host smart-f4feac48-d855-4b38-8479-36e52109819b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962412750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3962412750
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.2933595762
Short name T757
Test name
Test status
Simulation time 2299433737 ps
CPU time 12.49 seconds
Started Aug 05 06:24:53 PM PDT 24
Finished Aug 05 06:25:05 PM PDT 24
Peak memory 201404 kb
Host smart-94b2547e-52b8-4334-97dc-82c16b6b2bd7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933595762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.2933595762
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.4224695039
Short name T348
Test name
Test status
Simulation time 24578939 ps
CPU time 0.75 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201008 kb
Host smart-08738ef9-31c5-4792-88da-a1818428139b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224695039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.4224695039
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.3833872652
Short name T490
Test name
Test status
Simulation time 26223392 ps
CPU time 0.76 seconds
Started Aug 05 06:24:50 PM PDT 24
Finished Aug 05 06:24:51 PM PDT 24
Peak memory 200996 kb
Host smart-8dbe640e-d3fb-457a-bbb4-2bd7dfafc843
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833872652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.3833872652
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.938272115
Short name T416
Test name
Test status
Simulation time 78154629 ps
CPU time 1.03 seconds
Started Aug 05 06:24:55 PM PDT 24
Finished Aug 05 06:24:56 PM PDT 24
Peak memory 201072 kb
Host smart-b584552e-7ab5-4882-9af2-6e559e86f8a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938272115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 19.clkmgr_lc_ctrl_intersig_mubi.938272115
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1646571882
Short name T206
Test name
Test status
Simulation time 15169480 ps
CPU time 0.74 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201092 kb
Host smart-4a4123bc-52d4-4a56-adeb-e06f0ee550b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646571882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1646571882
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2920240542
Short name T143
Test name
Test status
Simulation time 524776448 ps
CPU time 2.16 seconds
Started Aug 05 06:24:54 PM PDT 24
Finished Aug 05 06:24:57 PM PDT 24
Peak memory 201092 kb
Host smart-4ce7c58f-8dc8-4969-b0b4-dc52d115518e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920240542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2920240542
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.1691791653
Short name T399
Test name
Test status
Simulation time 41769235 ps
CPU time 0.89 seconds
Started Aug 05 06:24:53 PM PDT 24
Finished Aug 05 06:24:54 PM PDT 24
Peak memory 201056 kb
Host smart-b37ae06c-b8be-4ce0-aff1-1ba47d337c09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691791653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1691791653
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.2621954622
Short name T14
Test name
Test status
Simulation time 375048985 ps
CPU time 3.7 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:25:01 PM PDT 24
Peak memory 201208 kb
Host smart-fb52ff8f-f10e-47f2-b5ed-db2441d12b99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621954622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.2621954622
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.1021005223
Short name T488
Test name
Test status
Simulation time 15272962 ps
CPU time 0.82 seconds
Started Aug 05 06:24:51 PM PDT 24
Finished Aug 05 06:24:52 PM PDT 24
Peak memory 201112 kb
Host smart-4839d353-9a15-4301-914d-9d9259dd5636
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021005223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.1021005223
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1718327617
Short name T518
Test name
Test status
Simulation time 80869536 ps
CPU time 1.19 seconds
Started Aug 05 06:23:26 PM PDT 24
Finished Aug 05 06:23:27 PM PDT 24
Peak memory 201088 kb
Host smart-c4f1885e-c562-4b38-b149-1ea1c595dd82
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718327617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1718327617
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.2671471887
Short name T784
Test name
Test status
Simulation time 13934494 ps
CPU time 0.71 seconds
Started Aug 05 06:23:20 PM PDT 24
Finished Aug 05 06:23:21 PM PDT 24
Peak memory 200272 kb
Host smart-ab1942ad-0278-4fe5-aed8-3d3fbab98be5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671471887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.2671471887
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.2823959339
Short name T770
Test name
Test status
Simulation time 17546796 ps
CPU time 0.78 seconds
Started Aug 05 06:23:24 PM PDT 24
Finished Aug 05 06:23:25 PM PDT 24
Peak memory 201040 kb
Host smart-0109f00a-3d72-494b-b50f-403b97064129
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823959339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_div_intersig_mubi.2823959339
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.145997415
Short name T318
Test name
Test status
Simulation time 25018014 ps
CPU time 0.96 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201072 kb
Host smart-d715d756-d9dc-4302-81b0-4e6151526ee9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145997415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.145997415
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.1982943796
Short name T508
Test name
Test status
Simulation time 1558064702 ps
CPU time 6.48 seconds
Started Aug 05 06:23:20 PM PDT 24
Finished Aug 05 06:23:27 PM PDT 24
Peak memory 201104 kb
Host smart-08aa4010-eddb-44a8-9f2f-3cfe2ecde506
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982943796 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.1982943796
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.1041303827
Short name T357
Test name
Test status
Simulation time 2062593594 ps
CPU time 10.81 seconds
Started Aug 05 06:23:21 PM PDT 24
Finished Aug 05 06:23:31 PM PDT 24
Peak memory 201388 kb
Host smart-4f2e4d63-19c6-4ebf-9274-f04b3963a065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041303827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.1041303827
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.861468617
Short name T358
Test name
Test status
Simulation time 116214750 ps
CPU time 1.2 seconds
Started Aug 05 06:23:17 PM PDT 24
Finished Aug 05 06:23:19 PM PDT 24
Peak memory 201072 kb
Host smart-ca5507ba-949b-442f-bf4b-025f17cb6cb5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861468617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_idle_intersig_mubi.861468617
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.1545755739
Short name T645
Test name
Test status
Simulation time 24564141 ps
CPU time 0.88 seconds
Started Aug 05 06:23:26 PM PDT 24
Finished Aug 05 06:23:27 PM PDT 24
Peak memory 201112 kb
Host smart-a9f68bb6-2522-47a5-87a6-1ed1087be38f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545755739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_clk_byp_req_intersig_mubi.1545755739
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.4187654941
Short name T536
Test name
Test status
Simulation time 28773139 ps
CPU time 0.85 seconds
Started Aug 05 06:23:25 PM PDT 24
Finished Aug 05 06:23:26 PM PDT 24
Peak memory 201112 kb
Host smart-f4745557-8ce7-4dc6-adba-06e7df440a72
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187654941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.4187654941
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.2569055411
Short name T629
Test name
Test status
Simulation time 46556308 ps
CPU time 0.86 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201092 kb
Host smart-432338c0-52a9-4a03-8fb5-fba55738bf67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569055411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.2569055411
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.641792242
Short name T690
Test name
Test status
Simulation time 910147275 ps
CPU time 4.96 seconds
Started Aug 05 06:23:24 PM PDT 24
Finished Aug 05 06:23:29 PM PDT 24
Peak memory 201304 kb
Host smart-78a87f6a-2c87-4530-bb30-f50721cce85b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641792242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.641792242
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.962371640
Short name T47
Test name
Test status
Simulation time 323055732 ps
CPU time 3.32 seconds
Started Aug 05 06:23:26 PM PDT 24
Finished Aug 05 06:23:29 PM PDT 24
Peak memory 217896 kb
Host smart-bd9c3b20-e6a0-4fe9-bad3-82f7ac905589
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962371640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr
_sec_cm.962371640
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.683836341
Short name T615
Test name
Test status
Simulation time 29065829 ps
CPU time 0.88 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201120 kb
Host smart-327f2776-d738-4595-a015-e324eb24fb49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683836341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.683836341
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.2146496018
Short name T368
Test name
Test status
Simulation time 2814642031 ps
CPU time 15.8 seconds
Started Aug 05 06:23:28 PM PDT 24
Finished Aug 05 06:23:44 PM PDT 24
Peak memory 201456 kb
Host smart-03500aa8-72c1-49f0-b064-a30c014f4ba9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146496018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.2146496018
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.3076241461
Short name T69
Test name
Test status
Simulation time 429455850269 ps
CPU time 1526.55 seconds
Started Aug 05 06:23:25 PM PDT 24
Finished Aug 05 06:48:51 PM PDT 24
Peak memory 217928 kb
Host smart-fdf99a42-4dc9-40fb-a07d-48761eadad32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3076241461 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.3076241461
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.clkmgr_trans.1723982159
Short name T387
Test name
Test status
Simulation time 43594783 ps
CPU time 1.01 seconds
Started Aug 05 06:23:19 PM PDT 24
Finished Aug 05 06:23:20 PM PDT 24
Peak memory 201044 kb
Host smart-a4b46f54-b9e7-4a19-86e0-f59bf5d643b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723982159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.1723982159
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.3807856649
Short name T662
Test name
Test status
Simulation time 26540783 ps
CPU time 0.75 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201076 kb
Host smart-dc701fd1-5605-43ad-b1ad-c19d9c2b62c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807856649 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.3807856649
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.478427241
Short name T219
Test name
Test status
Simulation time 25798809 ps
CPU time 0.87 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:00 PM PDT 24
Peak memory 201204 kb
Host smart-416d6e14-097d-4455-8dc3-4b3b6680e345
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478427241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.478427241
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1512551567
Short name T611
Test name
Test status
Simulation time 14924904 ps
CPU time 0.73 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:24:59 PM PDT 24
Peak memory 201012 kb
Host smart-7a7e12ca-ea81-4608-ade2-4e87fb7ebcb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512551567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1512551567
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.3362507653
Short name T606
Test name
Test status
Simulation time 29061998 ps
CPU time 0.9 seconds
Started Aug 05 06:24:57 PM PDT 24
Finished Aug 05 06:24:58 PM PDT 24
Peak memory 201088 kb
Host smart-cd040d96-98db-46bc-add1-0131c977d5e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362507653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.3362507653
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.1282975323
Short name T542
Test name
Test status
Simulation time 19797081 ps
CPU time 0.8 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:00 PM PDT 24
Peak memory 201056 kb
Host smart-6a875739-9a01-4965-ab3c-5b3db23d67de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282975323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1282975323
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.105062843
Short name T612
Test name
Test status
Simulation time 2024085609 ps
CPU time 9.04 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201328 kb
Host smart-59e436b5-9905-4d93-b56e-c0bf77873e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105062843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.105062843
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.38149480
Short name T551
Test name
Test status
Simulation time 845482512 ps
CPU time 3.51 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201132 kb
Host smart-71d74454-7b9b-49a1-86fe-58cd5edbb89b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38149480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_tim
eout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_tim
eout.38149480
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.3142340897
Short name T27
Test name
Test status
Simulation time 15710414 ps
CPU time 0.82 seconds
Started Aug 05 06:25:00 PM PDT 24
Finished Aug 05 06:25:01 PM PDT 24
Peak memory 201108 kb
Host smart-3206a304-fa53-4fd0-bf28-b21968838586
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142340897 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_idle_intersig_mubi.3142340897
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2233465531
Short name T381
Test name
Test status
Simulation time 21673945 ps
CPU time 0.82 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:00 PM PDT 24
Peak memory 201056 kb
Host smart-82a2c420-4878-49db-8d89-0bbb04586280
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233465531 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.2233465531
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.3775055088
Short name T251
Test name
Test status
Simulation time 54939962 ps
CPU time 0.87 seconds
Started Aug 05 06:25:01 PM PDT 24
Finished Aug 05 06:25:02 PM PDT 24
Peak memory 201080 kb
Host smart-6d1fac29-d1aa-4b3f-baf4-b2a84542cba2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775055088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_ctrl_intersig_mubi.3775055088
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.1544154378
Short name T372
Test name
Test status
Simulation time 48838741 ps
CPU time 0.89 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:00 PM PDT 24
Peak memory 201092 kb
Host smart-49eb59cc-cf48-436d-9dc9-1dfa8ac40a0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544154378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.1544154378
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.372500301
Short name T607
Test name
Test status
Simulation time 317640774 ps
CPU time 1.58 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:24:59 PM PDT 24
Peak memory 201084 kb
Host smart-f8de612b-5b83-489a-b735-2805dfa5a6e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372500301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.372500301
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.1214162561
Short name T328
Test name
Test status
Simulation time 21416022 ps
CPU time 0.88 seconds
Started Aug 05 06:24:58 PM PDT 24
Finished Aug 05 06:24:59 PM PDT 24
Peak memory 201032 kb
Host smart-a1b73ab6-870e-4b19-b939-1f812dff79bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214162561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.1214162561
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.2336745922
Short name T338
Test name
Test status
Simulation time 10564858880 ps
CPU time 41.96 seconds
Started Aug 05 06:24:57 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201340 kb
Host smart-9b52e795-f975-458b-aae5-7a489fb438fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336745922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.2336745922
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_trans.3550284981
Short name T401
Test name
Test status
Simulation time 95866228 ps
CPU time 1.26 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:04 PM PDT 24
Peak memory 201076 kb
Host smart-ff93eb70-432a-44d8-9778-80d2d9860c5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550284981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.3550284981
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1183307300
Short name T24
Test name
Test status
Simulation time 15166503 ps
CPU time 0.77 seconds
Started Aug 05 06:25:06 PM PDT 24
Finished Aug 05 06:25:07 PM PDT 24
Peak memory 201092 kb
Host smart-607ed4ce-f3f6-419d-b183-f525d46eeb5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183307300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1183307300
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.2445890556
Short name T96
Test name
Test status
Simulation time 38837487 ps
CPU time 0.94 seconds
Started Aug 05 06:25:05 PM PDT 24
Finished Aug 05 06:25:06 PM PDT 24
Peak memory 201100 kb
Host smart-f88fffe0-804b-4f1e-b06d-b7b6cb98c854
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445890556 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.2445890556
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.1797794081
Short name T185
Test name
Test status
Simulation time 77573335 ps
CPU time 1.04 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201092 kb
Host smart-0b1e46d9-2de1-4e46-8795-f81ab87a35b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797794081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_div_intersig_mubi.1797794081
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.1408044620
Short name T675
Test name
Test status
Simulation time 19626019 ps
CPU time 0.79 seconds
Started Aug 05 06:24:56 PM PDT 24
Finished Aug 05 06:24:57 PM PDT 24
Peak memory 201100 kb
Host smart-a6d8e159-3940-4ef7-801e-6f6a6f7511ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408044620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.1408044620
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.1723881003
Short name T13
Test name
Test status
Simulation time 1520249411 ps
CPU time 9.13 seconds
Started Aug 05 06:25:00 PM PDT 24
Finished Aug 05 06:25:09 PM PDT 24
Peak memory 201116 kb
Host smart-81f11551-5e98-4da9-b313-a43c01dafdbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723881003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.1723881003
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.519869515
Short name T238
Test name
Test status
Simulation time 1100531082 ps
CPU time 8.83 seconds
Started Aug 05 06:25:00 PM PDT 24
Finished Aug 05 06:25:09 PM PDT 24
Peak memory 201232 kb
Host smart-ce401990-8c4d-487a-97f8-63f616fe38c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519869515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_ti
meout.519869515
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.3869914581
Short name T682
Test name
Test status
Simulation time 70071034 ps
CPU time 0.99 seconds
Started Aug 05 06:25:05 PM PDT 24
Finished Aug 05 06:25:06 PM PDT 24
Peak memory 201144 kb
Host smart-424b9331-88b1-4dbb-9b66-cd704f9f930e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869914581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.3869914581
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.4104925418
Short name T638
Test name
Test status
Simulation time 37524097 ps
CPU time 0.82 seconds
Started Aug 05 06:25:03 PM PDT 24
Finished Aug 05 06:25:04 PM PDT 24
Peak memory 201076 kb
Host smart-deaa2129-e447-4b44-97af-a03bb79f20b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104925418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.4104925418
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3191436938
Short name T210
Test name
Test status
Simulation time 22984595 ps
CPU time 0.87 seconds
Started Aug 05 06:25:03 PM PDT 24
Finished Aug 05 06:25:04 PM PDT 24
Peak memory 201088 kb
Host smart-8cea1732-8373-4b96-8bdb-7a3c9cc31c65
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191436938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3191436938
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.4073779320
Short name T266
Test name
Test status
Simulation time 38225987 ps
CPU time 0.82 seconds
Started Aug 05 06:25:01 PM PDT 24
Finished Aug 05 06:25:02 PM PDT 24
Peak memory 201056 kb
Host smart-f318f1d9-d440-4a3e-94af-988d63303fea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073779320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.4073779320
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.2834571309
Short name T139
Test name
Test status
Simulation time 1682117274 ps
CPU time 6.14 seconds
Started Aug 05 06:25:05 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201260 kb
Host smart-119faf09-5d67-48cb-954b-ad0b6b6e3621
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834571309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.2834571309
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.153125769
Short name T594
Test name
Test status
Simulation time 23295160 ps
CPU time 0.89 seconds
Started Aug 05 06:24:59 PM PDT 24
Finished Aug 05 06:25:00 PM PDT 24
Peak memory 201080 kb
Host smart-e779ff32-91fa-41f4-b89c-9cb4334b8436
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153125769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.153125769
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.4021605977
Short name T525
Test name
Test status
Simulation time 2328604371 ps
CPU time 17.81 seconds
Started Aug 05 06:25:05 PM PDT 24
Finished Aug 05 06:25:23 PM PDT 24
Peak memory 201448 kb
Host smart-150cba29-662c-4801-8bd2-b0d6a9973a95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021605977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.4021605977
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.3153752541
Short name T635
Test name
Test status
Simulation time 33460899 ps
CPU time 0.88 seconds
Started Aug 05 06:25:01 PM PDT 24
Finished Aug 05 06:25:02 PM PDT 24
Peak memory 201076 kb
Host smart-7b1b3264-da91-4057-85c9-e77304a99cf9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153752541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.3153752541
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1660340501
Short name T284
Test name
Test status
Simulation time 15428689 ps
CPU time 0.74 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201080 kb
Host smart-abe524db-3068-413c-827d-f77f119476c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660340501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1660340501
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3394362217
Short name T473
Test name
Test status
Simulation time 40404259 ps
CPU time 0.78 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201072 kb
Host smart-11e74dc0-fa76-41a9-a140-c1e4c88a21e6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394362217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.3394362217
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.2138149890
Short name T162
Test name
Test status
Simulation time 44362496 ps
CPU time 0.76 seconds
Started Aug 05 06:25:04 PM PDT 24
Finished Aug 05 06:25:05 PM PDT 24
Peak memory 200272 kb
Host smart-3eae5114-6e86-4edf-930e-7d73dfae14b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138149890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.2138149890
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.808267787
Short name T197
Test name
Test status
Simulation time 21491200 ps
CPU time 0.89 seconds
Started Aug 05 06:25:13 PM PDT 24
Finished Aug 05 06:25:14 PM PDT 24
Peak memory 201060 kb
Host smart-56b59d2e-7bfa-40d7-bb11-a0a79c8516e9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808267787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_div_intersig_mubi.808267787
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.3716445348
Short name T218
Test name
Test status
Simulation time 26624221 ps
CPU time 0.81 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201056 kb
Host smart-50d1c9c7-8b0d-4fc2-8f98-178f953bdb9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716445348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.3716445348
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.492597874
Short name T405
Test name
Test status
Simulation time 1518664969 ps
CPU time 11.81 seconds
Started Aug 05 06:25:04 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201136 kb
Host smart-b1704c47-e7fd-473b-b422-c648c19bb267
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492597874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.492597874
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.380120925
Short name T82
Test name
Test status
Simulation time 632665617 ps
CPU time 3.45 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:06 PM PDT 24
Peak memory 201168 kb
Host smart-cc5af101-e167-4364-ab0d-0d76bfdd654a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380120925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.380120925
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.4278521798
Short name T666
Test name
Test status
Simulation time 40743034 ps
CPU time 0.84 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201056 kb
Host smart-2fbf34ad-fd02-406d-b3b1-c47325e66425
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278521798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_idle_intersig_mubi.4278521798
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.543360847
Short name T367
Test name
Test status
Simulation time 24098347 ps
CPU time 0.89 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201132 kb
Host smart-5efcfee9-8bb0-43a6-b440-e993741f7d21
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543360847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 22.clkmgr_lc_clk_byp_req_intersig_mubi.543360847
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.2838779993
Short name T557
Test name
Test status
Simulation time 82925586 ps
CPU time 0.96 seconds
Started Aug 05 06:25:12 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201108 kb
Host smart-a9165683-b5de-4170-b979-8352b1dfcd27
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838779993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.2838779993
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.3555755366
Short name T547
Test name
Test status
Simulation time 18681719 ps
CPU time 0.81 seconds
Started Aug 05 06:25:06 PM PDT 24
Finished Aug 05 06:25:07 PM PDT 24
Peak memory 201088 kb
Host smart-288b84fe-da9e-47cf-9395-bf7fad4f01da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555755366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.3555755366
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2944715438
Short name T345
Test name
Test status
Simulation time 1146347243 ps
CPU time 6.81 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:18 PM PDT 24
Peak memory 201264 kb
Host smart-13e8f75b-1e3e-4f29-925a-2922a3670178
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944715438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2944715438
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.2407350303
Short name T257
Test name
Test status
Simulation time 70430837 ps
CPU time 1.02 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201080 kb
Host smart-39eb6e2e-7ea1-435a-9988-a7ec383dd295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407350303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.2407350303
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.3075578005
Short name T736
Test name
Test status
Simulation time 9032984985 ps
CPU time 35.41 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:46 PM PDT 24
Peak memory 201412 kb
Host smart-7dd590ec-a4b6-407e-9d02-1cc365873be1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075578005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.3075578005
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all_with_rand_reset.2835301248
Short name T73
Test name
Test status
Simulation time 217625063468 ps
CPU time 1201.85 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:45:13 PM PDT 24
Peak memory 209764 kb
Host smart-c6b41cdd-c7e1-48bb-8d35-4815e6e7e544
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2835301248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.2835301248
Directory /workspace/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3520813453
Short name T152
Test name
Test status
Simulation time 34983317 ps
CPU time 1.03 seconds
Started Aug 05 06:25:02 PM PDT 24
Finished Aug 05 06:25:03 PM PDT 24
Peak memory 201128 kb
Host smart-c1a410c3-db5e-4b80-90d9-8604d53f97b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520813453 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3520813453
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1308883847
Short name T501
Test name
Test status
Simulation time 26082710 ps
CPU time 0.8 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201096 kb
Host smart-cebab67b-6d0b-4687-bdb0-24669171b1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308883847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1308883847
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.1081902852
Short name T526
Test name
Test status
Simulation time 83233268 ps
CPU time 1.04 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201060 kb
Host smart-a8837722-7726-43d5-9f99-c13e7b1495a6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081902852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.1081902852
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.3963566728
Short name T493
Test name
Test status
Simulation time 72542373 ps
CPU time 0.94 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 200332 kb
Host smart-a9680ce6-8db7-45e2-b7a5-a552276c1879
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963566728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.3963566728
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.1372118731
Short name T294
Test name
Test status
Simulation time 18881271 ps
CPU time 0.8 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201084 kb
Host smart-eb98b15f-962a-4909-bf76-be4b6784a762
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372118731 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.1372118731
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.2546635856
Short name T613
Test name
Test status
Simulation time 19787106 ps
CPU time 0.85 seconds
Started Aug 05 06:25:12 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201040 kb
Host smart-3a10afe8-df4e-47e8-af00-b1ad339c63d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546635856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.2546635856
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.2992944460
Short name T278
Test name
Test status
Simulation time 2484520420 ps
CPU time 14.3 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201380 kb
Host smart-9f547231-1269-409f-9d1f-b0f185e980ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992944460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2992944460
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.2104116074
Short name T261
Test name
Test status
Simulation time 501267103 ps
CPU time 3.06 seconds
Started Aug 05 06:25:09 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201204 kb
Host smart-9e7b91e2-2a2a-4878-95cd-51934e2d5c7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104116074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_t
imeout.2104116074
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.1598958909
Short name T398
Test name
Test status
Simulation time 54386229 ps
CPU time 0.9 seconds
Started Aug 05 06:25:09 PM PDT 24
Finished Aug 05 06:25:10 PM PDT 24
Peak memory 201080 kb
Host smart-31e451a9-f119-4a30-98f3-5b19ac53db74
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598958909 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.1598958909
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.161933749
Short name T654
Test name
Test status
Simulation time 20560287 ps
CPU time 0.86 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201048 kb
Host smart-71686aa3-05b8-449f-8b8a-cd5e01dab8ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161933749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_clk_byp_req_intersig_mubi.161933749
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.543045385
Short name T747
Test name
Test status
Simulation time 54560797 ps
CPU time 0.88 seconds
Started Aug 05 06:25:13 PM PDT 24
Finished Aug 05 06:25:14 PM PDT 24
Peak memory 201068 kb
Host smart-917c14a2-681a-4dc5-b9a3-b7f2d4a3b0b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543045385 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 23.clkmgr_lc_ctrl_intersig_mubi.543045385
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.1381475693
Short name T759
Test name
Test status
Simulation time 25430417 ps
CPU time 0.76 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:12 PM PDT 24
Peak memory 201052 kb
Host smart-b8f82120-784d-41c8-81cf-c75cbba01ea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381475693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.1381475693
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.1769812740
Short name T10
Test name
Test status
Simulation time 243161137 ps
CPU time 1.95 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201080 kb
Host smart-c860daa9-ab8d-4eb6-be3e-5dacc3c85abe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769812740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.1769812740
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.714785808
Short name T136
Test name
Test status
Simulation time 58861689 ps
CPU time 0.95 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201040 kb
Host smart-45f3d3bf-f50f-4aa9-88eb-496eea410524
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714785808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.714785808
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.1923259248
Short name T697
Test name
Test status
Simulation time 582409850 ps
CPU time 3.76 seconds
Started Aug 05 06:25:09 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201304 kb
Host smart-aa3177a7-1268-4ee0-890d-279cbde0fd98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923259248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.1923259248
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/default/23.clkmgr_trans.3807979105
Short name T426
Test name
Test status
Simulation time 62327591 ps
CPU time 1.09 seconds
Started Aug 05 06:25:09 PM PDT 24
Finished Aug 05 06:25:10 PM PDT 24
Peak memory 201064 kb
Host smart-675d4aca-7c93-4211-9ad0-176caea79aa3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807979105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3807979105
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.3825079754
Short name T201
Test name
Test status
Simulation time 25877156 ps
CPU time 0.82 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201204 kb
Host smart-cb6a2de3-70b9-42d2-9cca-4a1f29f2652a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825079754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clk
mgr_alert_test.3825079754
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.2556441852
Short name T764
Test name
Test status
Simulation time 54442983 ps
CPU time 0.85 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201068 kb
Host smart-68fe7c9a-f408-4245-8b56-0accbac44c6e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556441852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.2556441852
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2158956993
Short name T235
Test name
Test status
Simulation time 50332907 ps
CPU time 0.82 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 200324 kb
Host smart-b846e292-525a-4b5d-8a6a-f7e375c3aa98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158956993 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2158956993
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.3567379107
Short name T698
Test name
Test status
Simulation time 22709481 ps
CPU time 0.88 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 201080 kb
Host smart-1d9fe2d8-4bdc-4abb-a319-f0d771f2651b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567379107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_div_intersig_mubi.3567379107
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.2644333497
Short name T578
Test name
Test status
Simulation time 24713977 ps
CPU time 0.9 seconds
Started Aug 05 06:25:12 PM PDT 24
Finished Aug 05 06:25:13 PM PDT 24
Peak memory 201056 kb
Host smart-760af067-21a7-4a00-9bdb-8c7551dfefff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644333497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.2644333497
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.3932991873
Short name T232
Test name
Test status
Simulation time 1784013418 ps
CPU time 8.2 seconds
Started Aug 05 06:25:11 PM PDT 24
Finished Aug 05 06:25:20 PM PDT 24
Peak memory 201316 kb
Host smart-a7a7f60f-621f-4220-91fc-9d4bb1e63c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932991873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.3932991873
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.540619026
Short name T54
Test name
Test status
Simulation time 1945754508 ps
CPU time 8.33 seconds
Started Aug 05 06:25:12 PM PDT 24
Finished Aug 05 06:25:21 PM PDT 24
Peak memory 201200 kb
Host smart-8bbeaa30-3c2b-4e18-bf7b-bd5bc03b3d77
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540619026 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_ti
meout.540619026
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.2535806890
Short name T544
Test name
Test status
Simulation time 37824890 ps
CPU time 1.03 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 201064 kb
Host smart-da12951e-516a-40b6-9063-7ea7903d1782
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535806890 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.2535806890
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.1038923574
Short name T403
Test name
Test status
Simulation time 17451833 ps
CPU time 0.8 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201092 kb
Host smart-de4f180e-8ffa-49b1-a9f4-df3140e85265
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038923574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.1038923574
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2334669443
Short name T383
Test name
Test status
Simulation time 39380584 ps
CPU time 0.93 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201084 kb
Host smart-8262fe0c-c97b-4f70-9f7f-bdf592b7d456
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334669443 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.2334669443
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.360964501
Short name T427
Test name
Test status
Simulation time 46469489 ps
CPU time 0.84 seconds
Started Aug 05 06:25:09 PM PDT 24
Finished Aug 05 06:25:10 PM PDT 24
Peak memory 200956 kb
Host smart-c31719de-ff77-48bc-8ac9-def4e39a48ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360964501 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.360964501
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3650102445
Short name T149
Test name
Test status
Simulation time 530749086 ps
CPU time 3.4 seconds
Started Aug 05 06:25:20 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201284 kb
Host smart-c7172061-9b6f-493b-b5f5-46e3a92720cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650102445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3650102445
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.2506123974
Short name T153
Test name
Test status
Simulation time 31313757 ps
CPU time 0.89 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201048 kb
Host smart-6b25ca15-9bfb-461f-aaa8-8e7e20a97c9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506123974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2506123974
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_trans.1988346545
Short name T112
Test name
Test status
Simulation time 21099414 ps
CPU time 0.9 seconds
Started Aug 05 06:25:10 PM PDT 24
Finished Aug 05 06:25:11 PM PDT 24
Peak memory 201032 kb
Host smart-da3ee5a3-6903-4d39-9f64-50ad119954be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988346545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.1988346545
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.2747638106
Short name T274
Test name
Test status
Simulation time 22057739 ps
CPU time 0.74 seconds
Started Aug 05 06:25:22 PM PDT 24
Finished Aug 05 06:25:23 PM PDT 24
Peak memory 201136 kb
Host smart-dbb5c09d-e0a9-4aa1-9a7e-e01d79fe83ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747638106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.2747638106
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.845778073
Short name T655
Test name
Test status
Simulation time 47662982 ps
CPU time 0.93 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201108 kb
Host smart-f8b96e43-30a1-400a-9b66-b4d147894236
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845778073 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.845778073
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.3615759994
Short name T477
Test name
Test status
Simulation time 24321863 ps
CPU time 0.76 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201036 kb
Host smart-57d0ae9d-1e74-42f3-af2d-3aa50d56b01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615759994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3615759994
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.703370284
Short name T282
Test name
Test status
Simulation time 29422503 ps
CPU time 0.95 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201072 kb
Host smart-12a24e50-03b5-49c7-9393-53e6b450f18c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703370284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
5.clkmgr_div_intersig_mubi.703370284
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.4215833435
Short name T170
Test name
Test status
Simulation time 56765547 ps
CPU time 0.95 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:16 PM PDT 24
Peak memory 201056 kb
Host smart-340c8161-d9fa-4418-aee9-949eddf9d426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215833435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.4215833435
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3738512291
Short name T113
Test name
Test status
Simulation time 282950444 ps
CPU time 1.61 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 201180 kb
Host smart-d8c8abc8-312c-4afe-b2b1-0e2ed65301db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738512291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3738512291
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.1073208733
Short name T576
Test name
Test status
Simulation time 933033469 ps
CPU time 3.9 seconds
Started Aug 05 06:25:15 PM PDT 24
Finished Aug 05 06:25:19 PM PDT 24
Peak memory 201200 kb
Host smart-d743e31d-0754-40fe-a8d4-e78c0ab9a815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073208733 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.1073208733
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.3699118472
Short name T324
Test name
Test status
Simulation time 329961242 ps
CPU time 1.74 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:18 PM PDT 24
Peak memory 201084 kb
Host smart-52136fa2-f9fb-4db5-aba9-eff4e6d0628d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699118472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.3699118472
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1792505289
Short name T296
Test name
Test status
Simulation time 19636900 ps
CPU time 0.84 seconds
Started Aug 05 06:25:20 PM PDT 24
Finished Aug 05 06:25:21 PM PDT 24
Peak memory 201120 kb
Host smart-acad3452-4b4f-4c9f-bf04-45f705893774
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792505289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1792505289
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.359465108
Short name T22
Test name
Test status
Simulation time 29957232 ps
CPU time 0.8 seconds
Started Aug 05 06:25:14 PM PDT 24
Finished Aug 05 06:25:15 PM PDT 24
Peak memory 201080 kb
Host smart-9bd91dd8-4573-48c1-be7e-ee33240cd19a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359465108 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 25.clkmgr_lc_ctrl_intersig_mubi.359465108
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.123813033
Short name T277
Test name
Test status
Simulation time 28117439 ps
CPU time 0.82 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 201064 kb
Host smart-4ff3b5c8-656f-49d9-b25f-8e9b852d45f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123813033 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.123813033
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.3136531055
Short name T524
Test name
Test status
Simulation time 746127376 ps
CPU time 3.51 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201256 kb
Host smart-96426b10-f532-4c8d-949f-9cd112a08a11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136531055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3136531055
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.2562750605
Short name T195
Test name
Test status
Simulation time 44500108 ps
CPU time 0.89 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201068 kb
Host smart-c1e1a2bc-80b5-4676-a819-c8c6151ce9a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562750605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.2562750605
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.2224243396
Short name T632
Test name
Test status
Simulation time 4082343673 ps
CPU time 31.06 seconds
Started Aug 05 06:25:24 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 201432 kb
Host smart-fd9aa69f-836e-4624-8e2a-174d0095b7ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224243396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.2224243396
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.790986039
Short name T684
Test name
Test status
Simulation time 41907344 ps
CPU time 0.97 seconds
Started Aug 05 06:25:16 PM PDT 24
Finished Aug 05 06:25:17 PM PDT 24
Peak memory 201124 kb
Host smart-5f27eb8d-2de4-4ee4-98e0-defc0c651c91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790986039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.790986039
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.1568022179
Short name T722
Test name
Test status
Simulation time 79572012 ps
CPU time 0.93 seconds
Started Aug 05 06:25:23 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201108 kb
Host smart-2c0051aa-f281-4644-9288-3774273d1ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568022179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.1568022179
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.3527484183
Short name T433
Test name
Test status
Simulation time 81561555 ps
CPU time 0.98 seconds
Started Aug 05 06:25:20 PM PDT 24
Finished Aug 05 06:25:21 PM PDT 24
Peak memory 201080 kb
Host smart-35b3c855-2262-43a6-bcff-d3be80c77aef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527484183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.3527484183
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2724837496
Short name T650
Test name
Test status
Simulation time 31714280 ps
CPU time 0.72 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 200336 kb
Host smart-714b033d-d389-4ea1-9731-fce98fd25aa9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724837496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2724837496
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.3462105959
Short name T419
Test name
Test status
Simulation time 35289250 ps
CPU time 0.86 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201044 kb
Host smart-db88a9c4-62b9-4709-89ab-2b0d91cbb5e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462105959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.3462105959
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.3566126646
Short name T761
Test name
Test status
Simulation time 44822755 ps
CPU time 0.97 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201092 kb
Host smart-463b234f-8c23-49f1-836f-3f80aec10d4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566126646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3566126646
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.4162553574
Short name T217
Test name
Test status
Simulation time 1642134021 ps
CPU time 13.05 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201176 kb
Host smart-a122c616-deb9-41a1-8b1a-5c8d47eafba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162553574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.4162553574
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1919021936
Short name T496
Test name
Test status
Simulation time 1936774093 ps
CPU time 11.97 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201128 kb
Host smart-0ef5e3dd-fe56-4867-943a-7b5fe33a5974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919021936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1919021936
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.1411039414
Short name T444
Test name
Test status
Simulation time 30008330 ps
CPU time 0.99 seconds
Started Aug 05 06:25:24 PM PDT 24
Finished Aug 05 06:25:25 PM PDT 24
Peak memory 201112 kb
Host smart-e6ca73d1-8994-4c12-8e01-af94fc9fe32f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411039414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.1411039414
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.3331565224
Short name T49
Test name
Test status
Simulation time 38012532 ps
CPU time 0.89 seconds
Started Aug 05 06:25:31 PM PDT 24
Finished Aug 05 06:25:32 PM PDT 24
Peak memory 201080 kb
Host smart-77f762cc-ed79-4df7-9624-78734ab0383e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331565224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_clk_byp_req_intersig_mubi.3331565224
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2209101428
Short name T379
Test name
Test status
Simulation time 34952367 ps
CPU time 0.93 seconds
Started Aug 05 06:25:23 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201084 kb
Host smart-c2889819-aafa-401e-936c-4014f638b6fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209101428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.2209101428
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.2594474886
Short name T731
Test name
Test status
Simulation time 59048869 ps
CPU time 0.86 seconds
Started Aug 05 06:25:24 PM PDT 24
Finished Aug 05 06:25:25 PM PDT 24
Peak memory 201056 kb
Host smart-243aa03a-bc3d-4d72-af14-199ca5d82fb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594474886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.2594474886
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.1977547227
Short name T268
Test name
Test status
Simulation time 1163717292 ps
CPU time 6.27 seconds
Started Aug 05 06:25:31 PM PDT 24
Finished Aug 05 06:25:38 PM PDT 24
Peak memory 201284 kb
Host smart-f38b5556-3877-402a-8b0d-1b73dc275190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977547227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1977547227
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.3061968203
Short name T177
Test name
Test status
Simulation time 37203132 ps
CPU time 0.92 seconds
Started Aug 05 06:25:21 PM PDT 24
Finished Aug 05 06:25:22 PM PDT 24
Peak memory 201044 kb
Host smart-6028f1ea-7189-4438-9563-e94c77f01685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061968203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3061968203
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.1848921082
Short name T33
Test name
Test status
Simulation time 7104448076 ps
CPU time 50.28 seconds
Started Aug 05 06:25:25 PM PDT 24
Finished Aug 05 06:26:15 PM PDT 24
Peak memory 201488 kb
Host smart-87ddfed6-2a37-4238-860b-5fb71eea370a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848921082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.1848921082
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.1619993480
Short name T190
Test name
Test status
Simulation time 30250284 ps
CPU time 0.96 seconds
Started Aug 05 06:25:25 PM PDT 24
Finished Aug 05 06:25:26 PM PDT 24
Peak memory 201116 kb
Host smart-f8e0082c-6b4b-4b5f-821d-0c1fc06fda2f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619993480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.1619993480
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.762669005
Short name T776
Test name
Test status
Simulation time 112850706 ps
CPU time 1.1 seconds
Started Aug 05 06:25:26 PM PDT 24
Finished Aug 05 06:25:27 PM PDT 24
Peak memory 201120 kb
Host smart-200f66ce-5a12-49b0-88de-6b61ead30aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762669005 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkm
gr_alert_test.762669005
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.3212793507
Short name T633
Test name
Test status
Simulation time 15637571 ps
CPU time 0.72 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 200196 kb
Host smart-22442448-1033-4936-a2cb-38f9ccdfd1e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212793507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.3212793507
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3017007357
Short name T788
Test name
Test status
Simulation time 85594231 ps
CPU time 1.09 seconds
Started Aug 05 06:25:26 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201072 kb
Host smart-86490c46-fee9-4041-82eb-d203b99bf42f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017007357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3017007357
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.3086917801
Short name T302
Test name
Test status
Simulation time 45279780 ps
CPU time 0.94 seconds
Started Aug 05 06:25:23 PM PDT 24
Finished Aug 05 06:25:24 PM PDT 24
Peak memory 201072 kb
Host smart-ba5d3355-0fcb-4101-83ae-49c911027a3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086917801 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.3086917801
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1695269738
Short name T377
Test name
Test status
Simulation time 353898065 ps
CPU time 2.11 seconds
Started Aug 05 06:25:20 PM PDT 24
Finished Aug 05 06:25:23 PM PDT 24
Peak memory 201116 kb
Host smart-490ff8f1-3560-4414-af3a-166e889bdcef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695269738 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1695269738
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.1534996185
Short name T435
Test name
Test status
Simulation time 2279010269 ps
CPU time 9.84 seconds
Started Aug 05 06:25:23 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201460 kb
Host smart-589ca41a-b44f-4db9-b9fb-17f5d795381d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534996185 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.1534996185
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.656979305
Short name T171
Test name
Test status
Simulation time 75547297 ps
CPU time 1.07 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201124 kb
Host smart-56d8e00f-e77a-40e2-990d-ad426a68d754
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656979305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_idle_intersig_mubi.656979305
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.424015592
Short name T429
Test name
Test status
Simulation time 18226134 ps
CPU time 0.77 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 200424 kb
Host smart-a0880808-cd46-4839-878c-dcf5c0741708
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424015592 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_clk_byp_req_intersig_mubi.424015592
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.2283915358
Short name T696
Test name
Test status
Simulation time 99337694 ps
CPU time 1.18 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201120 kb
Host smart-f27f6d1e-418b-4e4b-b2f1-0cdb4beb044e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283915358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_ctrl_intersig_mubi.2283915358
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.2239890068
Short name T467
Test name
Test status
Simulation time 27265148 ps
CPU time 0.82 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201072 kb
Host smart-6d97a091-4801-4c51-8fb7-1cdf86c8fa28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239890068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.2239890068
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1714465459
Short name T665
Test name
Test status
Simulation time 1382468218 ps
CPU time 4.88 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201240 kb
Host smart-9ac35e94-97b1-40f1-ac40-9d04cb4d7838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714465459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1714465459
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.214367447
Short name T640
Test name
Test status
Simulation time 15361824 ps
CPU time 0.82 seconds
Started Aug 05 06:25:31 PM PDT 24
Finished Aug 05 06:25:32 PM PDT 24
Peak memory 201096 kb
Host smart-c40aef30-ecaa-4685-8c26-9e43832999ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214367447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.214367447
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.167299118
Short name T742
Test name
Test status
Simulation time 2519928606 ps
CPU time 19.86 seconds
Started Aug 05 06:25:29 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201448 kb
Host smart-f44f5652-85c6-4c53-acdd-ef7e16cdfefa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167299118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.167299118
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.3290357341
Short name T713
Test name
Test status
Simulation time 29718650097 ps
CPU time 217.15 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:29:09 PM PDT 24
Peak memory 216884 kb
Host smart-b604b860-d143-4be4-8cb3-0947ae2a9f7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3290357341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.3290357341
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.3374189951
Short name T271
Test name
Test status
Simulation time 17649931 ps
CPU time 0.87 seconds
Started Aug 05 06:25:25 PM PDT 24
Finished Aug 05 06:25:26 PM PDT 24
Peak memory 201140 kb
Host smart-4182d92d-ad42-4236-8dee-91cfc57202a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374189951 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.3374189951
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.4169759211
Short name T304
Test name
Test status
Simulation time 69942266 ps
CPU time 0.94 seconds
Started Aug 05 06:25:26 PM PDT 24
Finished Aug 05 06:25:27 PM PDT 24
Peak memory 201044 kb
Host smart-579c2a13-0770-4ea2-996b-1e66afe80ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169759211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.4169759211
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.4024944884
Short name T93
Test name
Test status
Simulation time 22322230 ps
CPU time 0.88 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201100 kb
Host smart-33d1fb39-edc0-4ec7-8db9-91b1cd30aa69
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024944884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_clk_handshake_intersig_mubi.4024944884
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.1394629862
Short name T337
Test name
Test status
Simulation time 14637467 ps
CPU time 0.73 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 200996 kb
Host smart-53bd2b24-c3e7-4891-9b0d-0f060e39aa0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394629862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1394629862
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.3423371495
Short name T669
Test name
Test status
Simulation time 42208673 ps
CPU time 0.81 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201052 kb
Host smart-c3d95a71-205e-4c96-9c1c-b8f9cbcff59a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423371495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_div_intersig_mubi.3423371495
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.1909201018
Short name T260
Test name
Test status
Simulation time 179038243 ps
CPU time 1.27 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201076 kb
Host smart-0c4cbe4e-cb10-4b47-80d7-92662c025aff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909201018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.1909201018
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.740317397
Short name T637
Test name
Test status
Simulation time 2306810492 ps
CPU time 8.17 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:36 PM PDT 24
Peak memory 201364 kb
Host smart-e35e2267-6d4b-4179-933a-5109976afa4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740317397 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.740317397
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.1401048798
Short name T245
Test name
Test status
Simulation time 1789833562 ps
CPU time 7.62 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:36 PM PDT 24
Peak memory 201172 kb
Host smart-26eb1401-0195-4af7-9105-7e209beaca4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401048798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_t
imeout.1401048798
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.4116269196
Short name T173
Test name
Test status
Simulation time 19337093 ps
CPU time 0.81 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201060 kb
Host smart-dfb5ed67-f6b2-4bce-a189-e09854f43eb4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116269196 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.4116269196
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.4074031510
Short name T804
Test name
Test status
Simulation time 23391303 ps
CPU time 0.87 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 200432 kb
Host smart-8c075392-7681-4da7-838f-6da8480317f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074031510 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.4074031510
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.3130133111
Short name T299
Test name
Test status
Simulation time 100405264 ps
CPU time 1.09 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 201076 kb
Host smart-1cd8721e-36dd-407f-8f66-52e9d94c281d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130133111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.3130133111
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.454500848
Short name T676
Test name
Test status
Simulation time 27071083 ps
CPU time 0.76 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 201052 kb
Host smart-c79b7a9e-f0b3-4cb7-a33d-9264eed1affb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454500848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.454500848
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.4036804219
Short name T256
Test name
Test status
Simulation time 101890626 ps
CPU time 1.18 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201044 kb
Host smart-b9688f49-1f22-4df7-a527-d26be1831b3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036804219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.4036804219
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.78748265
Short name T164
Test name
Test status
Simulation time 54622766 ps
CPU time 0.92 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201116 kb
Host smart-15aa6e8e-e1e4-43be-ab00-ad9b04984956
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78748265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.78748265
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.3010691016
Short name T40
Test name
Test status
Simulation time 6692502301 ps
CPU time 29.41 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:26:01 PM PDT 24
Peak memory 201452 kb
Host smart-dc9bbc3a-f2e2-46a1-b35f-3d67445dae9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010691016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.3010691016
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all_with_rand_reset.1257164984
Short name T72
Test name
Test status
Simulation time 86155234792 ps
CPU time 520.52 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:34:13 PM PDT 24
Peak memory 209784 kb
Host smart-4cfe599d-cdbf-4154-bb99-cc63f770e0ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1257164984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.1257164984
Directory /workspace/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.clkmgr_trans.1789765391
Short name T247
Test name
Test status
Simulation time 391733128 ps
CPU time 2.14 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:41 PM PDT 24
Peak memory 201116 kb
Host smart-a72ee5e7-773b-4e3a-b466-cae2a6d22646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789765391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1789765391
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.1236780173
Short name T787
Test name
Test status
Simulation time 37523790 ps
CPU time 0.81 seconds
Started Aug 05 06:25:33 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201100 kb
Host smart-96421576-39d2-43e2-b0dd-738353b8fc7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236780173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.1236780173
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.877932595
Short name T604
Test name
Test status
Simulation time 45801064 ps
CPU time 1.03 seconds
Started Aug 05 06:25:33 PM PDT 24
Finished Aug 05 06:25:35 PM PDT 24
Peak memory 201016 kb
Host smart-5cf7836f-3292-4ec7-bfdf-86bed24ed6af
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877932595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.877932595
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.433044470
Short name T440
Test name
Test status
Simulation time 45855975 ps
CPU time 0.8 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 200312 kb
Host smart-38dc13e4-946f-48fd-95c1-c8ff7e223075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433044470 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.433044470
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.764528451
Short name T176
Test name
Test status
Simulation time 49835520 ps
CPU time 0.87 seconds
Started Aug 05 06:25:33 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201064 kb
Host smart-861ab43c-120d-461c-98de-8c52260a8fb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764528451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_div_intersig_mubi.764528451
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.3143597296
Short name T51
Test name
Test status
Simulation time 14201527 ps
CPU time 0.72 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201024 kb
Host smart-1b486ab7-c22e-491c-bd64-2c6ec4a5133a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143597296 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3143597296
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2770077849
Short name T242
Test name
Test status
Simulation time 2254621749 ps
CPU time 11.6 seconds
Started Aug 05 06:25:25 PM PDT 24
Finished Aug 05 06:25:37 PM PDT 24
Peak memory 201412 kb
Host smart-7c5d6408-886b-4ab8-8d36-11be1b1fcd7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770077849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2770077849
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.4229750938
Short name T325
Test name
Test status
Simulation time 1411444752 ps
CPU time 6.08 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201164 kb
Host smart-fd047dea-f1c3-44e3-97c3-4d221b8f4c20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229750938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.4229750938
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.171950686
Short name T356
Test name
Test status
Simulation time 94974834 ps
CPU time 1.22 seconds
Started Aug 05 06:25:34 PM PDT 24
Finished Aug 05 06:25:35 PM PDT 24
Peak memory 201132 kb
Host smart-083d6adf-ecf6-42e7-9519-e41a983a46cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171950686 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
9.clkmgr_idle_intersig_mubi.171950686
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1438613710
Short name T50
Test name
Test status
Simulation time 24501309 ps
CPU time 0.87 seconds
Started Aug 05 06:25:34 PM PDT 24
Finished Aug 05 06:25:35 PM PDT 24
Peak memory 201116 kb
Host smart-a787b43d-c086-43f6-9652-03ce7850343d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438613710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.1438613710
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.4159033970
Short name T670
Test name
Test status
Simulation time 24935435 ps
CPU time 0.89 seconds
Started Aug 05 06:25:33 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201120 kb
Host smart-41ff6906-56da-4e03-b92f-9b97959f55f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159033970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_ctrl_intersig_mubi.4159033970
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.1055100655
Short name T378
Test name
Test status
Simulation time 42139808 ps
CPU time 0.8 seconds
Started Aug 05 06:25:29 PM PDT 24
Finished Aug 05 06:25:30 PM PDT 24
Peak memory 201104 kb
Host smart-f3c1656b-e92e-4303-84b4-910f6194977b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055100655 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1055100655
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.2929186308
Short name T374
Test name
Test status
Simulation time 1159516613 ps
CPU time 6.63 seconds
Started Aug 05 06:25:35 PM PDT 24
Finished Aug 05 06:25:42 PM PDT 24
Peak memory 201256 kb
Host smart-e68b540a-b31b-45cc-bdcb-db60ca9bd03b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929186308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2929186308
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.3231076786
Short name T680
Test name
Test status
Simulation time 19550076 ps
CPU time 0.83 seconds
Started Aug 05 06:25:27 PM PDT 24
Finished Aug 05 06:25:28 PM PDT 24
Peak memory 201000 kb
Host smart-f1ee5c41-b071-4199-982c-d094b7b34db1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231076786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3231076786
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.3563478446
Short name T460
Test name
Test status
Simulation time 3757128422 ps
CPU time 27.69 seconds
Started Aug 05 06:25:34 PM PDT 24
Finished Aug 05 06:26:02 PM PDT 24
Peak memory 201464 kb
Host smart-3eccb4f8-ff1a-4755-8cf4-4bd1b2f96553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563478446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.3563478446
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.1334947456
Short name T765
Test name
Test status
Simulation time 63384346 ps
CPU time 0.99 seconds
Started Aug 05 06:25:28 PM PDT 24
Finished Aug 05 06:25:29 PM PDT 24
Peak memory 201184 kb
Host smart-dc5b6b4a-c6f5-417b-960b-8ab43a42e312
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334947456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.1334947456
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.1448543324
Short name T246
Test name
Test status
Simulation time 14723206 ps
CPU time 0.73 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:42 PM PDT 24
Peak memory 201116 kb
Host smart-7e1adef7-7c7b-4675-874f-bb6c8861b735
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448543324 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.1448543324
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3534881665
Short name T352
Test name
Test status
Simulation time 13849419 ps
CPU time 0.77 seconds
Started Aug 05 06:23:32 PM PDT 24
Finished Aug 05 06:23:33 PM PDT 24
Peak memory 201084 kb
Host smart-80e3e854-6041-46ec-9ca8-8016afb3ea8d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534881665 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3534881665
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.2547799741
Short name T704
Test name
Test status
Simulation time 17365856 ps
CPU time 0.74 seconds
Started Aug 05 06:23:32 PM PDT 24
Finished Aug 05 06:23:33 PM PDT 24
Peak memory 201036 kb
Host smart-2d044c5c-ea99-44cb-9fe9-bac4e8bdaed2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547799741 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.2547799741
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.2525486227
Short name T443
Test name
Test status
Simulation time 53433105 ps
CPU time 0.94 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:31 PM PDT 24
Peak memory 201060 kb
Host smart-9d38e16a-ac82-4a79-9b52-f80d633ac395
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525486227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.2525486227
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.1818647254
Short name T178
Test name
Test status
Simulation time 23697647 ps
CPU time 0.85 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:31 PM PDT 24
Peak memory 201096 kb
Host smart-aa1f7cca-9af9-4b15-b405-fcd2db8559cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818647254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.1818647254
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.2930799433
Short name T562
Test name
Test status
Simulation time 1635708271 ps
CPU time 12.77 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:43 PM PDT 24
Peak memory 201184 kb
Host smart-0ff342a2-0332-4eb9-9695-8b68998838c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930799433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.2930799433
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.1291127331
Short name T504
Test name
Test status
Simulation time 2295670187 ps
CPU time 15.5 seconds
Started Aug 05 06:23:29 PM PDT 24
Finished Aug 05 06:23:45 PM PDT 24
Peak memory 201408 kb
Host smart-7eae5142-708a-44ff-84f7-728ac6e39803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291127331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.1291127331
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.4206660147
Short name T777
Test name
Test status
Simulation time 37590810 ps
CPU time 0.77 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:31 PM PDT 24
Peak memory 201072 kb
Host smart-df718d5c-ddfe-4368-a91e-093d7d7f5e6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206660147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.4206660147
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.206546905
Short name T449
Test name
Test status
Simulation time 51679084 ps
CPU time 0.92 seconds
Started Aug 05 06:23:29 PM PDT 24
Finished Aug 05 06:23:30 PM PDT 24
Peak memory 201068 kb
Host smart-9d963cd8-b8b0-4f7c-9a8c-da9961b9a35f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206546905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_clk_byp_req_intersig_mubi.206546905
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.319292560
Short name T717
Test name
Test status
Simulation time 54281787 ps
CPU time 0.96 seconds
Started Aug 05 06:23:33 PM PDT 24
Finished Aug 05 06:23:34 PM PDT 24
Peak memory 201080 kb
Host smart-b3616bf2-ec77-4522-90d5-7263140f904a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319292560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 3.clkmgr_lc_ctrl_intersig_mubi.319292560
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.1764841605
Short name T491
Test name
Test status
Simulation time 17253216 ps
CPU time 0.75 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:30 PM PDT 24
Peak memory 200984 kb
Host smart-eb9f5d3c-bcfe-4c22-b979-fa800f3f90fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764841605 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1764841605
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.1901435430
Short name T145
Test name
Test status
Simulation time 712454908 ps
CPU time 4.59 seconds
Started Aug 05 06:23:33 PM PDT 24
Finished Aug 05 06:23:38 PM PDT 24
Peak memory 201280 kb
Host smart-5c4f86b4-a50b-40d5-a45b-d0f248b4a331
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901435430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1901435430
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.2200811658
Short name T46
Test name
Test status
Simulation time 302014679 ps
CPU time 3.12 seconds
Started Aug 05 06:23:35 PM PDT 24
Finished Aug 05 06:23:38 PM PDT 24
Peak memory 217960 kb
Host smart-89782254-d894-4128-b08a-ef8553e8d676
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200811658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.2200811658
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2046934701
Short name T498
Test name
Test status
Simulation time 16058507 ps
CPU time 0.79 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:31 PM PDT 24
Peak memory 200932 kb
Host smart-e44bf74d-2fa5-4a02-b3d3-f277cd260f94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046934701 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2046934701
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.2124699193
Short name T466
Test name
Test status
Simulation time 21717649 ps
CPU time 0.81 seconds
Started Aug 05 06:23:35 PM PDT 24
Finished Aug 05 06:23:36 PM PDT 24
Peak memory 200960 kb
Host smart-f4acf872-56ea-4092-860a-7cafd5a75c32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124699193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.2124699193
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.3318385828
Short name T514
Test name
Test status
Simulation time 22855591 ps
CPU time 0.81 seconds
Started Aug 05 06:23:30 PM PDT 24
Finished Aug 05 06:23:30 PM PDT 24
Peak memory 201072 kb
Host smart-eb20c422-230a-481c-9c8a-ec7f44cc7f8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318385828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.3318385828
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1133962666
Short name T236
Test name
Test status
Simulation time 219656803 ps
CPU time 1.43 seconds
Started Aug 05 06:25:38 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201208 kb
Host smart-77506956-01ab-4a61-ab30-bfe68a712922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133962666 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1133962666
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.598292766
Short name T539
Test name
Test status
Simulation time 24250929 ps
CPU time 0.9 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201092 kb
Host smart-634983b5-a57b-4577-ba5f-819b84788f98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598292766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.598292766
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.205211287
Short name T628
Test name
Test status
Simulation time 28091170 ps
CPU time 0.78 seconds
Started Aug 05 06:25:34 PM PDT 24
Finished Aug 05 06:25:35 PM PDT 24
Peak memory 201036 kb
Host smart-74b7fa20-aa2d-4f95-9367-43bc6a152985
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205211287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.205211287
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.2481318924
Short name T811
Test name
Test status
Simulation time 163151831 ps
CPU time 1.32 seconds
Started Aug 05 06:25:37 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201020 kb
Host smart-6d77e8f7-f557-4e94-bc86-f6d07a675b66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481318924 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.2481318924
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.1475391629
Short name T563
Test name
Test status
Simulation time 15777267 ps
CPU time 0.73 seconds
Started Aug 05 06:25:34 PM PDT 24
Finished Aug 05 06:25:35 PM PDT 24
Peak memory 201004 kb
Host smart-1d5b451c-972f-4271-a847-64a232baf112
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475391629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.1475391629
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2340309135
Short name T189
Test name
Test status
Simulation time 2361029133 ps
CPU time 17.67 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:25:50 PM PDT 24
Peak memory 201344 kb
Host smart-46c414f5-d3b7-486a-8d78-329381d5b147
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340309135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2340309135
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.1385172529
Short name T510
Test name
Test status
Simulation time 2182022430 ps
CPU time 15.55 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201456 kb
Host smart-41bf9a6e-96a0-43d9-85a8-1e78a71bee9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385172529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.1385172529
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3799922266
Short name T658
Test name
Test status
Simulation time 60010775 ps
CPU time 0.9 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201052 kb
Host smart-6cc6eec5-5a82-4d54-9b3b-3e078ca30224
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799922266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3799922266
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.1839844679
Short name T411
Test name
Test status
Simulation time 19985803 ps
CPU time 0.77 seconds
Started Aug 05 06:25:37 PM PDT 24
Finished Aug 05 06:25:38 PM PDT 24
Peak memory 201072 kb
Host smart-30c0c21e-1f26-41db-9ec4-f1aa3790a7b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839844679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_clk_byp_req_intersig_mubi.1839844679
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3771398100
Short name T648
Test name
Test status
Simulation time 21991913 ps
CPU time 0.83 seconds
Started Aug 05 06:25:36 PM PDT 24
Finished Aug 05 06:25:38 PM PDT 24
Peak memory 201084 kb
Host smart-438fa016-ebd3-4682-b1de-78289724bdc5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771398100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.3771398100
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.1980275895
Short name T417
Test name
Test status
Simulation time 26084324 ps
CPU time 0.75 seconds
Started Aug 05 06:25:33 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201072 kb
Host smart-24d9f761-8b76-44fe-b07d-8fcfb6e0e159
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980275895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.1980275895
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.2533496483
Short name T622
Test name
Test status
Simulation time 812572051 ps
CPU time 3.87 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:51 PM PDT 24
Peak memory 201252 kb
Host smart-d45f7520-f1de-47b9-a322-74af7494998e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533496483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.2533496483
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.4290427201
Short name T424
Test name
Test status
Simulation time 95139554 ps
CPU time 1.12 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:25:34 PM PDT 24
Peak memory 201056 kb
Host smart-23a71358-0905-43d4-9b6a-203e6e46c103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290427201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.4290427201
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.930811787
Short name T631
Test name
Test status
Simulation time 10839335864 ps
CPU time 51.98 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:26:32 PM PDT 24
Peak memory 201480 kb
Host smart-01a8ccbd-11bc-4d7b-8927-892d0ce35818
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930811787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.930811787
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_trans.3154103300
Short name T88
Test name
Test status
Simulation time 82627816 ps
CPU time 1.05 seconds
Started Aug 05 06:25:32 PM PDT 24
Finished Aug 05 06:25:33 PM PDT 24
Peak memory 201076 kb
Host smart-35e82c4c-2b32-4a95-9cb5-16f2c49b817f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154103300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.3154103300
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.2373065039
Short name T540
Test name
Test status
Simulation time 38750753 ps
CPU time 0.83 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201108 kb
Host smart-60ae2300-453d-412e-9165-56a42dc3432c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373065039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.2373065039
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.2004253987
Short name T393
Test name
Test status
Simulation time 14197508 ps
CPU time 0.78 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201056 kb
Host smart-177e36f4-4859-44cf-a104-2fa1505df86e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004253987 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_clk_handshake_intersig_mubi.2004253987
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.1369908988
Short name T537
Test name
Test status
Simulation time 17322185 ps
CPU time 0.71 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 200272 kb
Host smart-08559a77-e73c-4120-8fd8-a7baa10590c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369908988 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.1369908988
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.393110703
Short name T588
Test name
Test status
Simulation time 22031933 ps
CPU time 0.84 seconds
Started Aug 05 06:25:38 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201104 kb
Host smart-44b9c5cf-1140-4056-9d7f-8d2cf76bf965
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393110703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_div_intersig_mubi.393110703
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.256206645
Short name T244
Test name
Test status
Simulation time 28509951 ps
CPU time 0.92 seconds
Started Aug 05 06:25:37 PM PDT 24
Finished Aug 05 06:25:38 PM PDT 24
Peak memory 201088 kb
Host smart-32430bd1-4241-4fb3-8595-3d1714dae673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256206645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.256206645
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.3242752850
Short name T17
Test name
Test status
Simulation time 1283971346 ps
CPU time 10.01 seconds
Started Aug 05 06:25:39 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201152 kb
Host smart-436e6c5d-44bf-459f-ba54-a0d2391e520d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242752850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3242752850
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.3534646180
Short name T712
Test name
Test status
Simulation time 1945082301 ps
CPU time 9.99 seconds
Started Aug 05 06:25:50 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201156 kb
Host smart-41aabb65-ee31-4c31-8243-c65792e6e16b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534646180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.3534646180
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1728156814
Short name T599
Test name
Test status
Simulation time 73352858 ps
CPU time 0.93 seconds
Started Aug 05 06:25:38 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201100 kb
Host smart-daeaf100-0e4e-49ec-a089-0c8bf75da668
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728156814 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1728156814
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.1728976065
Short name T646
Test name
Test status
Simulation time 13966149 ps
CPU time 0.73 seconds
Started Aug 05 06:25:40 PM PDT 24
Finished Aug 05 06:25:41 PM PDT 24
Peak memory 201092 kb
Host smart-f478df9d-7c4b-456b-b7ea-3f6807cf219a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728976065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.1728976065
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.721268690
Short name T346
Test name
Test status
Simulation time 30964398 ps
CPU time 0.8 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201044 kb
Host smart-168360a2-f19b-469f-bea2-b5e5d4f0cd43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721268690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 31.clkmgr_lc_ctrl_intersig_mubi.721268690
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.595565436
Short name T287
Test name
Test status
Simulation time 16927923 ps
CPU time 0.79 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201040 kb
Host smart-34a433e1-1193-4cce-bb6b-e16cb43d39f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595565436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.595565436
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.4153921085
Short name T760
Test name
Test status
Simulation time 377432582 ps
CPU time 1.92 seconds
Started Aug 05 06:25:37 PM PDT 24
Finished Aug 05 06:25:40 PM PDT 24
Peak memory 201124 kb
Host smart-fd2f7400-a8c3-4207-a148-abc23b7d5a65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153921085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.4153921085
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.2642019873
Short name T365
Test name
Test status
Simulation time 14873857 ps
CPU time 0.87 seconds
Started Aug 05 06:25:40 PM PDT 24
Finished Aug 05 06:25:41 PM PDT 24
Peak memory 201072 kb
Host smart-75c80b91-f7bd-4a12-842b-b9d81638d96d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642019873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.2642019873
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.865534539
Short name T134
Test name
Test status
Simulation time 2439274965 ps
CPU time 13.15 seconds
Started Aug 05 06:25:38 PM PDT 24
Finished Aug 05 06:25:51 PM PDT 24
Peak memory 201456 kb
Host smart-31a288af-9f33-4949-be64-1ba81401a808
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865534539 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.865534539
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.3676617097
Short name T773
Test name
Test status
Simulation time 56264911 ps
CPU time 1.11 seconds
Started Aug 05 06:25:41 PM PDT 24
Finished Aug 05 06:25:42 PM PDT 24
Peak memory 201068 kb
Host smart-7deb7bc4-a8b6-4ded-a07c-bd0271dcd6c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676617097 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.3676617097
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.2637463854
Short name T595
Test name
Test status
Simulation time 22309083 ps
CPU time 0.82 seconds
Started Aug 05 06:25:42 PM PDT 24
Finished Aug 05 06:25:43 PM PDT 24
Peak memory 201080 kb
Host smart-7f1a335e-86bf-449a-8726-af02a04d9062
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637463854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.2637463854
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.690922452
Short name T480
Test name
Test status
Simulation time 65389651 ps
CPU time 0.98 seconds
Started Aug 05 06:25:43 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 201084 kb
Host smart-e1daf2aa-4bd9-4749-8f65-0f63e83d6c0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690922452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_clk_handshake_intersig_mubi.690922452
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.355412441
Short name T546
Test name
Test status
Simulation time 40530462 ps
CPU time 0.75 seconds
Started Aug 05 06:25:43 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 200176 kb
Host smart-5c9c58c2-3cc1-4fa4-a3a4-71e18a96adea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355412441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.355412441
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.3505930845
Short name T673
Test name
Test status
Simulation time 23538337 ps
CPU time 0.91 seconds
Started Aug 05 06:25:44 PM PDT 24
Finished Aug 05 06:25:45 PM PDT 24
Peak memory 201060 kb
Host smart-424fd5db-2ba2-4b93-b867-03ff4ca73f83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505930845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.3505930845
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.4115238623
Short name T802
Test name
Test status
Simulation time 58275024 ps
CPU time 0.93 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 200984 kb
Host smart-8ed9e47a-95eb-475f-a735-39f2de0559e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115238623 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.4115238623
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.2318409049
Short name T464
Test name
Test status
Simulation time 559914597 ps
CPU time 4.65 seconds
Started Aug 05 06:25:37 PM PDT 24
Finished Aug 05 06:25:42 PM PDT 24
Peak memory 201180 kb
Host smart-ab393432-8a34-4783-947d-11477bb847a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318409049 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.2318409049
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.591976925
Short name T220
Test name
Test status
Simulation time 1001352115 ps
CPU time 4.57 seconds
Started Aug 05 06:25:43 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201192 kb
Host smart-a4242a70-2d6b-4d3e-87aa-b5725966ee3e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591976925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_ti
meout.591976925
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.2408646959
Short name T485
Test name
Test status
Simulation time 33378275 ps
CPU time 0.95 seconds
Started Aug 05 06:25:42 PM PDT 24
Finished Aug 05 06:25:43 PM PDT 24
Peak memory 201076 kb
Host smart-2605683d-d0a6-413b-b416-ff6a4478bab3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408646959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.2408646959
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.2962150601
Short name T388
Test name
Test status
Simulation time 47804081 ps
CPU time 0.92 seconds
Started Aug 05 06:25:42 PM PDT 24
Finished Aug 05 06:25:43 PM PDT 24
Peak memory 201088 kb
Host smart-e4c63efb-e294-490e-8427-036ef701f737
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962150601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_clk_byp_req_intersig_mubi.2962150601
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.976309959
Short name T523
Test name
Test status
Simulation time 20387095 ps
CPU time 0.84 seconds
Started Aug 05 06:25:42 PM PDT 24
Finished Aug 05 06:25:43 PM PDT 24
Peak memory 201056 kb
Host smart-db4667cb-d214-4623-861f-6cd05a9233c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976309959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_ctrl_intersig_mubi.976309959
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.1783569914
Short name T610
Test name
Test status
Simulation time 33899907 ps
CPU time 0.8 seconds
Started Aug 05 06:25:43 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 201128 kb
Host smart-ab7fbbb7-d6e3-417f-b5e0-257f0b86255e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783569914 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1783569914
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.350986582
Short name T459
Test name
Test status
Simulation time 1235909198 ps
CPU time 4.8 seconds
Started Aug 05 06:25:44 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201296 kb
Host smart-c20051ba-a458-40e8-87ff-fb4574deede0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350986582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.350986582
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.2191965170
Short name T738
Test name
Test status
Simulation time 61631686 ps
CPU time 0.95 seconds
Started Aug 05 06:25:38 PM PDT 24
Finished Aug 05 06:25:39 PM PDT 24
Peak memory 201032 kb
Host smart-6083bf82-512f-4cd8-99e9-9193cfe04c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191965170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.2191965170
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.4071169588
Short name T298
Test name
Test status
Simulation time 2530886584 ps
CPU time 18.63 seconds
Started Aug 05 06:25:42 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201412 kb
Host smart-f59a06f3-2d99-4650-b675-f03b5bac3686
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071169588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.4071169588
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_trans.214702338
Short name T279
Test name
Test status
Simulation time 144940048 ps
CPU time 1.39 seconds
Started Aug 05 06:25:43 PM PDT 24
Finished Aug 05 06:25:44 PM PDT 24
Peak memory 201092 kb
Host smart-896f4106-03fe-4f4e-8101-85f478b5dc61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214702338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.214702338
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.1699641173
Short name T55
Test name
Test status
Simulation time 21302098 ps
CPU time 0.8 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201080 kb
Host smart-d8bba617-9156-48ea-906c-913e9d3bd384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699641173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.1699641173
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3273957113
Short name T465
Test name
Test status
Simulation time 13644492 ps
CPU time 0.76 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201128 kb
Host smart-5c49ebfe-65db-44a9-9f85-28aeb0134465
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273957113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.3273957113
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.3704725610
Short name T762
Test name
Test status
Simulation time 13090836 ps
CPU time 0.69 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 200308 kb
Host smart-a96956db-1dfd-406f-9bb5-830a01a4489e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704725610 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.3704725610
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.4104070541
Short name T169
Test name
Test status
Simulation time 88396195 ps
CPU time 1.09 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:53 PM PDT 24
Peak memory 201088 kb
Host smart-20482352-0edc-41ef-a232-18aa37dc6239
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104070541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.4104070541
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.3625235767
Short name T570
Test name
Test status
Simulation time 1481569814 ps
CPU time 7.09 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:56 PM PDT 24
Peak memory 201148 kb
Host smart-375a69a3-6a8f-4a27-9ffe-02c60a5a2bc9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625235767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3625235767
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.623984818
Short name T592
Test name
Test status
Simulation time 2296885981 ps
CPU time 17.13 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201320 kb
Host smart-bfd36f8e-15f3-4f01-8fec-1c61c99b4e38
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623984818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_ti
meout.623984818
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.1211801964
Short name T172
Test name
Test status
Simulation time 37496999 ps
CPU time 1.08 seconds
Started Aug 05 06:25:46 PM PDT 24
Finished Aug 05 06:25:47 PM PDT 24
Peak memory 201048 kb
Host smart-60fe9c2d-a4b7-4567-9444-f7ad8e7aa860
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211801964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_idle_intersig_mubi.1211801964
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2180824213
Short name T331
Test name
Test status
Simulation time 22275950 ps
CPU time 0.82 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:53 PM PDT 24
Peak memory 201068 kb
Host smart-33fb408f-da07-400e-a439-143fe5469ce4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180824213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2180824213
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1935579828
Short name T639
Test name
Test status
Simulation time 102465370 ps
CPU time 1.04 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:25:50 PM PDT 24
Peak memory 201008 kb
Host smart-71d10fc3-2ef9-4439-ad2a-b68b942a2fa8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935579828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1935579828
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.4182331138
Short name T90
Test name
Test status
Simulation time 203275380 ps
CPU time 1.31 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201048 kb
Host smart-9fe48ad3-0814-4690-8bd2-c526fd9d3632
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182331138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.4182331138
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.2393887312
Short name T810
Test name
Test status
Simulation time 722627269 ps
CPU time 3.2 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:51 PM PDT 24
Peak memory 201316 kb
Host smart-bee499c6-2ec3-45c0-9a13-f9be2b2fbc03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393887312 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.2393887312
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.776734139
Short name T151
Test name
Test status
Simulation time 50772065 ps
CPU time 0.91 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201116 kb
Host smart-f8d879b3-8e0f-4201-bf2d-7d5d35494e5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776734139 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.776734139
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.79153791
Short name T309
Test name
Test status
Simulation time 108627711 ps
CPU time 1.17 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201084 kb
Host smart-bc5f68e7-3537-46fa-bb74-0611afb7b167
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79153791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_stress_all.79153791
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_trans.2981327138
Short name T78
Test name
Test status
Simulation time 17870643 ps
CPU time 0.8 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:25:50 PM PDT 24
Peak memory 201076 kb
Host smart-b200cb1c-3745-4049-8f21-acac41abf946
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981327138 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.2981327138
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1613220035
Short name T355
Test name
Test status
Simulation time 20461726 ps
CPU time 0.76 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201148 kb
Host smart-f49f67be-b1f8-4e48-9e3a-6b6f805b05c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613220035 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1613220035
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.2294704153
Short name T463
Test name
Test status
Simulation time 54741389 ps
CPU time 1.02 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:25:48 PM PDT 24
Peak memory 201096 kb
Host smart-689fa52b-c17b-4ee0-a2c9-e6e46d9175bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294704153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.2294704153
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.1420180082
Short name T528
Test name
Test status
Simulation time 19275225 ps
CPU time 0.74 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:25:50 PM PDT 24
Peak memory 200176 kb
Host smart-3c3b5304-b9f0-4b2a-85e7-781acfa417ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420180082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.1420180082
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.910982400
Short name T543
Test name
Test status
Simulation time 12086192 ps
CPU time 0.71 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:53 PM PDT 24
Peak memory 201076 kb
Host smart-d5462618-73aa-4d93-b71b-d73c59c7e4a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910982400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_div_intersig_mubi.910982400
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.40952980
Short name T354
Test name
Test status
Simulation time 90291916 ps
CPU time 1.11 seconds
Started Aug 05 06:25:51 PM PDT 24
Finished Aug 05 06:25:52 PM PDT 24
Peak memory 201044 kb
Host smart-81e5e65b-a420-4b4e-9d27-70023b814375
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40952980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.40952980
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.779171548
Short name T692
Test name
Test status
Simulation time 1635715242 ps
CPU time 12.48 seconds
Started Aug 05 06:25:47 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201164 kb
Host smart-83149ef5-0db9-4407-95bf-d324686f82a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779171548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.779171548
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.951697448
Short name T181
Test name
Test status
Simulation time 273957148 ps
CPU time 1.64 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:56 PM PDT 24
Peak memory 201204 kb
Host smart-56ff25c9-96ed-4f2e-b341-9495156d8094
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951697448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_ti
meout.951697448
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.2064265153
Short name T336
Test name
Test status
Simulation time 16348653 ps
CPU time 0.81 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201084 kb
Host smart-7b65509c-56af-4fb5-b078-2641e8316c5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064265153 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_idle_intersig_mubi.2064265153
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.1528513020
Short name T813
Test name
Test status
Simulation time 45512699 ps
CPU time 0.92 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201056 kb
Host smart-216c36dc-9a7c-40a7-b0c9-d5a679644f8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528513020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_clk_byp_req_intersig_mubi.1528513020
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.4268358247
Short name T763
Test name
Test status
Simulation time 41109032 ps
CPU time 0.96 seconds
Started Aug 05 06:25:50 PM PDT 24
Finished Aug 05 06:25:52 PM PDT 24
Peak memory 201052 kb
Host smart-a772a6be-8bda-4352-a9a1-7d435bc13581
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268358247 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.4268358247
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.3230774523
Short name T184
Test name
Test status
Simulation time 16767664 ps
CPU time 0.8 seconds
Started Aug 05 06:25:51 PM PDT 24
Finished Aug 05 06:25:52 PM PDT 24
Peak memory 201092 kb
Host smart-97806885-2f82-4dcb-98ef-aa00b648f7cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230774523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.3230774523
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.239091522
Short name T734
Test name
Test status
Simulation time 677401174 ps
CPU time 2.69 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:51 PM PDT 24
Peak memory 201252 kb
Host smart-f08e22c3-9e09-4856-868b-d030d46ec5e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239091522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.239091522
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.4064842219
Short name T575
Test name
Test status
Simulation time 30521758 ps
CPU time 0.95 seconds
Started Aug 05 06:25:49 PM PDT 24
Finished Aug 05 06:25:50 PM PDT 24
Peak memory 201096 kb
Host smart-53085e28-8bcc-4cf0-b214-b17cce311d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064842219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.4064842219
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.306526115
Short name T140
Test name
Test status
Simulation time 42866528 ps
CPU time 0.9 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201092 kb
Host smart-1ab75459-ce87-423d-8f91-643f56ede2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306526115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.306526115
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.1211046678
Short name T560
Test name
Test status
Simulation time 40286790 ps
CPU time 0.87 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201064 kb
Host smart-e08c4725-b10c-419a-b9dc-3e2e6f3b262d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211046678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1211046678
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.1240198235
Short name T608
Test name
Test status
Simulation time 16264660 ps
CPU time 0.83 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201080 kb
Host smart-5738aeb5-0d65-43d2-94c2-54e8fb5609c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240198235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.1240198235
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1977708579
Short name T533
Test name
Test status
Simulation time 64065389 ps
CPU time 0.98 seconds
Started Aug 05 06:25:57 PM PDT 24
Finished Aug 05 06:25:58 PM PDT 24
Peak memory 201080 kb
Host smart-6fa909d9-b790-4ae8-83ba-75b12b7d0d7e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977708579 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.1977708579
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.471563142
Short name T795
Test name
Test status
Simulation time 21628817 ps
CPU time 0.72 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 200312 kb
Host smart-b97f8c61-a93c-4168-a959-2c6f6c76dc27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471563142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.471563142
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.4288435467
Short name T423
Test name
Test status
Simulation time 144435735 ps
CPU time 1.23 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 201088 kb
Host smart-882fd2e6-3535-4303-80bf-1e08abb7ef36
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288435467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.4288435467
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.1023783121
Short name T623
Test name
Test status
Simulation time 74733911 ps
CPU time 1.03 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 200996 kb
Host smart-8f04d32d-373d-40cd-8667-aaa148fb281f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023783121 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1023783121
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2036019446
Short name T567
Test name
Test status
Simulation time 1521899915 ps
CPU time 12.09 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201128 kb
Host smart-9672b594-2079-4e27-b462-dc5b9cb76863
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036019446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2036019446
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.3601141198
Short name T685
Test name
Test status
Simulation time 1579820648 ps
CPU time 11.62 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 201236 kb
Host smart-804d17bd-6b2b-4336-a5db-0f4d6fb18d73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601141198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.3601141198
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.935045123
Short name T596
Test name
Test status
Simulation time 16965428 ps
CPU time 0.77 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:53 PM PDT 24
Peak memory 201080 kb
Host smart-447e46b8-e92f-4d49-a857-f9f34018dc62
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935045123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.clkmgr_idle_intersig_mubi.935045123
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3741615120
Short name T786
Test name
Test status
Simulation time 16681399 ps
CPU time 0.81 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:53 PM PDT 24
Peak memory 201104 kb
Host smart-87502d2c-373b-4ced-b597-0e0dab714d5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741615120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.3741615120
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1148199712
Short name T322
Test name
Test status
Simulation time 23089238 ps
CPU time 0.81 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 201080 kb
Host smart-d07931c0-a640-4d5f-93b7-76882c4e8837
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148199712 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.1148199712
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.943976767
Short name T30
Test name
Test status
Simulation time 20643292 ps
CPU time 0.78 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 201200 kb
Host smart-16b9a224-6a77-4bbe-b625-27d4527e8030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943976767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.943976767
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.2514887321
Short name T21
Test name
Test status
Simulation time 982730797 ps
CPU time 3.53 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:57 PM PDT 24
Peak memory 201080 kb
Host smart-52fcd886-4ee2-4fcc-a116-f78022170be5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514887321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2514887321
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.2347468746
Short name T715
Test name
Test status
Simulation time 62093462 ps
CPU time 0.94 seconds
Started Aug 05 06:25:48 PM PDT 24
Finished Aug 05 06:25:49 PM PDT 24
Peak memory 201080 kb
Host smart-c08ae463-4f64-48f9-a279-9521427d7eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347468746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2347468746
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.3907519348
Short name T200
Test name
Test status
Simulation time 5405023447 ps
CPU time 22.74 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:26:15 PM PDT 24
Peak memory 201436 kb
Host smart-452a5c4f-dc32-4a0a-8965-7d45a5b87578
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907519348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.3907519348
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.1514125258
Short name T74
Test name
Test status
Simulation time 35988750695 ps
CPU time 375.13 seconds
Started Aug 05 06:25:57 PM PDT 24
Finished Aug 05 06:32:13 PM PDT 24
Peak memory 209736 kb
Host smart-b8dd2687-f4cc-4fb6-950e-b9451c6a38c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1514125258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.1514125258
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1499340687
Short name T404
Test name
Test status
Simulation time 185207971 ps
CPU time 1.37 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201048 kb
Host smart-86b4411f-fceb-4d3b-8529-244c49ad0426
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499340687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1499340687
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.4037234248
Short name T529
Test name
Test status
Simulation time 36159866 ps
CPU time 0.81 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201084 kb
Host smart-f7fd007a-2770-45bf-be86-1c2ace36e751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037234248 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.4037234248
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.576835863
Short name T541
Test name
Test status
Simulation time 148314776 ps
CPU time 1.25 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201124 kb
Host smart-e120831f-a6b9-4a0d-847a-e157599bd1ec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576835863 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.576835863
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.3231957179
Short name T478
Test name
Test status
Simulation time 124477618 ps
CPU time 1.01 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 200276 kb
Host smart-fce47343-f6d3-4892-8c21-79e7d7b1d904
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231957179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.3231957179
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.874556891
Short name T492
Test name
Test status
Simulation time 151979247 ps
CPU time 1.21 seconds
Started Aug 05 06:25:59 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201096 kb
Host smart-ed66f041-7f68-4eaf-84af-2e7b1c04277e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874556891 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_div_intersig_mubi.874556891
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.885742580
Short name T283
Test name
Test status
Simulation time 23842952 ps
CPU time 0.89 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201076 kb
Host smart-47877f83-4735-43b8-93dc-55a66384799a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885742580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.885742580
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.3985269403
Short name T6
Test name
Test status
Simulation time 458266734 ps
CPU time 2.63 seconds
Started Aug 05 06:25:58 PM PDT 24
Finished Aug 05 06:26:01 PM PDT 24
Peak memory 201132 kb
Host smart-a9832b99-5027-41e3-a359-4a4a0fcd1e8f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985269403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.3985269403
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.2163960802
Short name T505
Test name
Test status
Simulation time 621215193 ps
CPU time 5.16 seconds
Started Aug 05 06:25:52 PM PDT 24
Finished Aug 05 06:25:58 PM PDT 24
Peak memory 201192 kb
Host smart-c4f595f6-33db-4159-b695-e6290fe627b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163960802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.2163960802
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.1408272827
Short name T448
Test name
Test status
Simulation time 26944234 ps
CPU time 0.78 seconds
Started Aug 05 06:26:03 PM PDT 24
Finished Aug 05 06:26:04 PM PDT 24
Peak memory 201076 kb
Host smart-467156bd-4132-4dbd-bb0e-3e95a1a69f0c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408272827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.1408272827
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.2968440786
Short name T280
Test name
Test status
Simulation time 24668023 ps
CPU time 0.88 seconds
Started Aug 05 06:25:57 PM PDT 24
Finished Aug 05 06:25:59 PM PDT 24
Peak memory 201076 kb
Host smart-6e9d2251-78bb-4b54-91f5-576727bde3a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968440786 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.2968440786
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3639837238
Short name T141
Test name
Test status
Simulation time 86609727 ps
CPU time 1.14 seconds
Started Aug 05 06:25:59 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201068 kb
Host smart-5051d40d-558d-42f7-b806-19e1b39277b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639837238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3639837238
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.17325075
Short name T183
Test name
Test status
Simulation time 17815767 ps
CPU time 0.79 seconds
Started Aug 05 06:25:54 PM PDT 24
Finished Aug 05 06:25:55 PM PDT 24
Peak memory 201076 kb
Host smart-54d9d1a9-76a4-4b10-b61d-837dcd1c3bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17325075 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.17325075
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.832527980
Short name T733
Test name
Test status
Simulation time 584494155 ps
CPU time 3.75 seconds
Started Aug 05 06:26:00 PM PDT 24
Finished Aug 05 06:26:04 PM PDT 24
Peak memory 201260 kb
Host smart-cfe388e0-b994-4f9c-9c51-8c023ee88f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832527980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.832527980
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.1115198319
Short name T370
Test name
Test status
Simulation time 21687729 ps
CPU time 0.82 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201056 kb
Host smart-7e243013-464f-4161-9fa1-aa0d48afbd44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115198319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.1115198319
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.52037006
Short name T233
Test name
Test status
Simulation time 8120973176 ps
CPU time 46.59 seconds
Started Aug 05 06:26:01 PM PDT 24
Finished Aug 05 06:26:48 PM PDT 24
Peak memory 201460 kb
Host smart-38036f01-8419-4451-9272-6b53374e117d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52037006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.clkmgr_stress_all.52037006
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_trans.1852501961
Short name T552
Test name
Test status
Simulation time 22436451 ps
CPU time 0.83 seconds
Started Aug 05 06:25:53 PM PDT 24
Finished Aug 05 06:25:54 PM PDT 24
Peak memory 201084 kb
Host smart-1f62e238-3309-468e-9a9d-84143d83952e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852501961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.1852501961
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.359928100
Short name T413
Test name
Test status
Simulation time 13493332 ps
CPU time 0.73 seconds
Started Aug 05 06:25:59 PM PDT 24
Finished Aug 05 06:26:00 PM PDT 24
Peak memory 201068 kb
Host smart-4492cbb9-5680-4fff-abd5-d77f3324cb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359928100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkm
gr_alert_test.359928100
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1043824716
Short name T502
Test name
Test status
Simulation time 45979706 ps
CPU time 0.83 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201084 kb
Host smart-c35ff639-9bca-4c30-816c-720b83860a44
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043824716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.1043824716
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.2721649331
Short name T705
Test name
Test status
Simulation time 16763389 ps
CPU time 0.75 seconds
Started Aug 05 06:26:00 PM PDT 24
Finished Aug 05 06:26:01 PM PDT 24
Peak memory 200328 kb
Host smart-d4e89b32-075b-40f4-962a-083cca2efc25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721649331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.2721649331
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.4275503512
Short name T341
Test name
Test status
Simulation time 30212536 ps
CPU time 0.86 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201064 kb
Host smart-8a945fe5-fdb3-4867-8cc4-1fc3de65869a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275503512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.4275503512
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.1753025535
Short name T740
Test name
Test status
Simulation time 14875309 ps
CPU time 0.76 seconds
Started Aug 05 06:26:01 PM PDT 24
Finished Aug 05 06:26:02 PM PDT 24
Peak memory 201064 kb
Host smart-7d139930-c009-4ff6-9829-d55e9fe5df4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753025535 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1753025535
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.4074296899
Short name T748
Test name
Test status
Simulation time 222793969 ps
CPU time 1.64 seconds
Started Aug 05 06:25:59 PM PDT 24
Finished Aug 05 06:26:01 PM PDT 24
Peak memory 201148 kb
Host smart-fc718fc4-c290-40d2-8c33-d4fa422ef22d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074296899 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.4074296899
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.3664822882
Short name T782
Test name
Test status
Simulation time 1352018146 ps
CPU time 5.76 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:12 PM PDT 24
Peak memory 201216 kb
Host smart-5bf50856-ddde-4136-825d-f456cc4eef39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664822882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.3664822882
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.2496808269
Short name T286
Test name
Test status
Simulation time 20698491 ps
CPU time 0.83 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201120 kb
Host smart-422e38ea-6d35-4520-b637-44251f75a13c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496808269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.2496808269
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.1234796430
Short name T556
Test name
Test status
Simulation time 26695584 ps
CPU time 0.79 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201100 kb
Host smart-0d335dcb-7488-425b-9734-f35cb77a2543
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234796430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.1234796430
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2279385060
Short name T620
Test name
Test status
Simulation time 98787887 ps
CPU time 1.02 seconds
Started Aug 05 06:25:58 PM PDT 24
Finished Aug 05 06:25:59 PM PDT 24
Peak memory 201052 kb
Host smart-d93daec9-2828-4fa7-8a79-04654729dde0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279385060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.2279385060
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.3901163937
Short name T532
Test name
Test status
Simulation time 13322357 ps
CPU time 0.72 seconds
Started Aug 05 06:25:58 PM PDT 24
Finished Aug 05 06:25:59 PM PDT 24
Peak memory 201072 kb
Host smart-68eb3f86-a492-4a29-a068-b31150e07ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901163937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3901163937
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1127009428
Short name T307
Test name
Test status
Simulation time 1164153045 ps
CPU time 6.37 seconds
Started Aug 05 06:25:58 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 201324 kb
Host smart-82fe38a5-fada-4743-9a47-31131c823865
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127009428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1127009428
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.1030664699
Short name T209
Test name
Test status
Simulation time 60926984 ps
CPU time 0.95 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201116 kb
Host smart-8c2f362f-f2c1-480d-8d0d-99b50e74488e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030664699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1030664699
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.3248191582
Short name T437
Test name
Test status
Simulation time 5866500586 ps
CPU time 43.98 seconds
Started Aug 05 06:25:59 PM PDT 24
Finished Aug 05 06:26:43 PM PDT 24
Peak memory 201488 kb
Host smart-68fe461e-0475-4fca-8175-63a0a6b369f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248191582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.3248191582
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/37.clkmgr_trans.1310688791
Short name T182
Test name
Test status
Simulation time 20694401 ps
CPU time 0.82 seconds
Started Aug 05 06:26:07 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201108 kb
Host smart-ae14ceda-aa5e-4e20-aedc-4cffb79b444c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310688791 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1310688791
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.3076754805
Short name T203
Test name
Test status
Simulation time 18378562 ps
CPU time 0.79 seconds
Started Aug 05 06:26:04 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 201008 kb
Host smart-0c678255-bbaf-4d18-b9a7-c355133c3ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076754805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.3076754805
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.1699372283
Short name T94
Test name
Test status
Simulation time 35649056 ps
CPU time 0.96 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201060 kb
Host smart-bceeec45-f3a5-400d-8928-f8a506e7a2d9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699372283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.1699372283
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.2451354342
Short name T812
Test name
Test status
Simulation time 13183246 ps
CPU time 0.69 seconds
Started Aug 05 06:26:04 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 200272 kb
Host smart-69030851-bede-4c55-a8e5-92115ff18faf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451354342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.2451354342
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.4039151194
Short name T376
Test name
Test status
Simulation time 24426488 ps
CPU time 0.85 seconds
Started Aug 05 06:26:04 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 201052 kb
Host smart-12ff58df-9d31-47a1-ab1b-f2f8db76e59f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039151194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_div_intersig_mubi.4039151194
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.3337893882
Short name T688
Test name
Test status
Simulation time 49937742 ps
CPU time 1.03 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201068 kb
Host smart-5b114894-8448-4148-b37c-f69300ab4bec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337893882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.3337893882
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1738739613
Short name T188
Test name
Test status
Simulation time 519772976 ps
CPU time 2.55 seconds
Started Aug 05 06:26:01 PM PDT 24
Finished Aug 05 06:26:04 PM PDT 24
Peak memory 201140 kb
Host smart-23c387e4-66e7-4e8c-9c76-9fab59cdaa5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738739613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1738739613
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.467414793
Short name T476
Test name
Test status
Simulation time 2127000657 ps
CPU time 7.35 seconds
Started Aug 05 06:26:01 PM PDT 24
Finished Aug 05 06:26:09 PM PDT 24
Peak memory 201392 kb
Host smart-dcdeb562-0604-4bff-ba9d-879f9ce580a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467414793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_ti
meout.467414793
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.839950803
Short name T462
Test name
Test status
Simulation time 45062329 ps
CPU time 0.98 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201064 kb
Host smart-6170ee9f-59b6-4d73-b6fc-e932df46bdb2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839950803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_idle_intersig_mubi.839950803
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.2323124938
Short name T678
Test name
Test status
Simulation time 40629877 ps
CPU time 0.88 seconds
Started Aug 05 06:26:04 PM PDT 24
Finished Aug 05 06:26:05 PM PDT 24
Peak memory 201080 kb
Host smart-9c43285f-e26f-490b-a226-f72dcb1a27e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323124938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_clk_byp_req_intersig_mubi.2323124938
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.2809981876
Short name T499
Test name
Test status
Simulation time 19706072 ps
CPU time 0.84 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201056 kb
Host smart-33036eff-6056-45d7-9754-ee21ec6d9f80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809981876 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 38.clkmgr_lc_ctrl_intersig_mubi.2809981876
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.1908266565
Short name T335
Test name
Test status
Simulation time 23800871 ps
CPU time 0.75 seconds
Started Aug 05 06:26:09 PM PDT 24
Finished Aug 05 06:26:10 PM PDT 24
Peak memory 201068 kb
Host smart-a7f00224-7ef1-41b4-bbfd-428296e1f23b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908266565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1908266565
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.3488386486
Short name T81
Test name
Test status
Simulation time 1046192511 ps
CPU time 4.88 seconds
Started Aug 05 06:26:03 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201308 kb
Host smart-e4b33b8b-4304-4da3-a9e5-87dfd6b9eda1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488386486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.3488386486
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.2697802478
Short name T511
Test name
Test status
Simulation time 111273917 ps
CPU time 1.16 seconds
Started Aug 05 06:26:02 PM PDT 24
Finished Aug 05 06:26:03 PM PDT 24
Peak memory 201096 kb
Host smart-a58f34d3-8e86-4dfa-bea7-19b8a0a4171c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697802478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.2697802478
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.1582096487
Short name T38
Test name
Test status
Simulation time 16966799029 ps
CPU time 54.12 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:27:00 PM PDT 24
Peak memory 201452 kb
Host smart-06c59e9c-9318-4d6a-9b0b-513f2051bb2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582096487 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.1582096487
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all_with_rand_reset.3751435176
Short name T71
Test name
Test status
Simulation time 202331101341 ps
CPU time 963.08 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:42:08 PM PDT 24
Peak memory 217956 kb
Host smart-e730ee46-d092-417c-b8dc-980d8b60646f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3751435176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3751435176
Directory /workspace/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.clkmgr_trans.174698465
Short name T253
Test name
Test status
Simulation time 89527152 ps
CPU time 1.3 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201008 kb
Host smart-be59677c-00fb-4faf-ad16-3df6aacd0190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174698465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.174698465
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.442878354
Short name T37
Test name
Test status
Simulation time 17378288 ps
CPU time 0.77 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:13 PM PDT 24
Peak memory 201064 kb
Host smart-6cb86528-ed7e-4068-82be-e233134b9cf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442878354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.442878354
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.1105767367
Short name T95
Test name
Test status
Simulation time 33677400 ps
CPU time 0.98 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201096 kb
Host smart-b7ee2594-7863-4677-a998-e4bd8b28fa1b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105767367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.1105767367
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.4014093316
Short name T158
Test name
Test status
Simulation time 14719126 ps
CPU time 0.73 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 200280 kb
Host smart-72eb062d-89d3-4c28-a006-ee2478577e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014093316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.4014093316
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2320201227
Short name T603
Test name
Test status
Simulation time 51914277 ps
CPU time 1.04 seconds
Started Aug 05 06:26:07 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201068 kb
Host smart-5911f318-9104-46ea-8b49-1c7c4abc3524
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320201227 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.2320201227
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.1450589418
Short name T306
Test name
Test status
Simulation time 76326716 ps
CPU time 1.09 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201076 kb
Host smart-72270209-e118-4b71-a014-bf529f967e25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450589418 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.1450589418
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.3581903351
Short name T366
Test name
Test status
Simulation time 436954258 ps
CPU time 3.88 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:09 PM PDT 24
Peak memory 201192 kb
Host smart-56393a57-e414-4978-b641-3c6bf5910d85
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581903351 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.3581903351
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.4213181169
Short name T785
Test name
Test status
Simulation time 2181583048 ps
CPU time 13.03 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201492 kb
Host smart-a0d08ab1-09ed-4824-802d-c2bc88ae2d0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213181169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.4213181169
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.3735684251
Short name T726
Test name
Test status
Simulation time 35403530 ps
CPU time 1.05 seconds
Started Aug 05 06:26:09 PM PDT 24
Finished Aug 05 06:26:10 PM PDT 24
Peak memory 201060 kb
Host smart-b8f8a511-0217-4005-bb63-9012f102a66d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735684251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.3735684251
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.1189474710
Short name T751
Test name
Test status
Simulation time 22919322 ps
CPU time 0.99 seconds
Started Aug 05 06:26:05 PM PDT 24
Finished Aug 05 06:26:06 PM PDT 24
Peak memory 201080 kb
Host smart-0f1bafb5-edaf-4801-8f32-e406d8897e64
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189474710 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_clk_byp_req_intersig_mubi.1189474710
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.3183860778
Short name T250
Test name
Test status
Simulation time 74317117 ps
CPU time 1.04 seconds
Started Aug 05 06:26:07 PM PDT 24
Finished Aug 05 06:26:08 PM PDT 24
Peak memory 201064 kb
Host smart-f04d31e0-a350-4acf-bcc3-609655e0a1e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183860778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.3183860778
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.2620473739
Short name T739
Test name
Test status
Simulation time 13248481 ps
CPU time 0.71 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201100 kb
Host smart-2a2f7069-533e-4869-979f-8fe8408c6021
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620473739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.2620473739
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1828330395
Short name T147
Test name
Test status
Simulation time 953066501 ps
CPU time 5.89 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:12 PM PDT 24
Peak memory 201280 kb
Host smart-46b86952-b8c9-46bb-9feb-c95b195e2c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828330395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1828330395
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.1982196742
Short name T484
Test name
Test status
Simulation time 70874006 ps
CPU time 0.99 seconds
Started Aug 05 06:26:03 PM PDT 24
Finished Aug 05 06:26:04 PM PDT 24
Peak memory 201120 kb
Host smart-1c678037-614c-4c35-aaf4-9788a88e2753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982196742 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1982196742
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.3946419177
Short name T234
Test name
Test status
Simulation time 7276047448 ps
CPU time 51.72 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:58 PM PDT 24
Peak memory 201460 kb
Host smart-96af105a-bf9d-4a77-bf14-59832bb92d92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946419177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.3946419177
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_trans.3812799159
Short name T566
Test name
Test status
Simulation time 26585864 ps
CPU time 0.76 seconds
Started Aug 05 06:26:06 PM PDT 24
Finished Aug 05 06:26:07 PM PDT 24
Peak memory 201096 kb
Host smart-7e3643bc-127c-409a-a6b0-88cbba676918
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812799159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.3812799159
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.3207700621
Short name T457
Test name
Test status
Simulation time 24009496 ps
CPU time 0.78 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:42 PM PDT 24
Peak memory 201100 kb
Host smart-62aaa8f7-5da1-4c1d-9122-375063db7c9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207700621 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.3207700621
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.533229751
Short name T89
Test name
Test status
Simulation time 17067781 ps
CPU time 0.77 seconds
Started Aug 05 06:23:39 PM PDT 24
Finished Aug 05 06:23:40 PM PDT 24
Peak memory 201084 kb
Host smart-cf57c0aa-3ae3-4533-8e49-29eaba78a7ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533229751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.533229751
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.2646248900
Short name T758
Test name
Test status
Simulation time 26618464 ps
CPU time 0.7 seconds
Started Aug 05 06:23:39 PM PDT 24
Finished Aug 05 06:23:40 PM PDT 24
Peak memory 200280 kb
Host smart-1f3b9959-acfa-4daa-9708-96d2c00d0e5b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646248900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.2646248900
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.2230803667
Short name T79
Test name
Test status
Simulation time 25791613 ps
CPU time 0.89 seconds
Started Aug 05 06:23:39 PM PDT 24
Finished Aug 05 06:23:40 PM PDT 24
Peak memory 201104 kb
Host smart-31d9467d-522a-42d3-90c6-74993533636f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230803667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.2230803667
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.2933758301
Short name T481
Test name
Test status
Simulation time 68758647 ps
CPU time 1.02 seconds
Started Aug 05 06:23:36 PM PDT 24
Finished Aug 05 06:23:37 PM PDT 24
Peak memory 201064 kb
Host smart-19799526-2e12-47ee-b202-bd18b1986eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933758301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.2933758301
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.1219221007
Short name T248
Test name
Test status
Simulation time 1643831629 ps
CPU time 13.58 seconds
Started Aug 05 06:23:37 PM PDT 24
Finished Aug 05 06:23:51 PM PDT 24
Peak memory 201184 kb
Host smart-78cb8be8-2590-4ad7-8b5c-c221817d10df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219221007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1219221007
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.395489295
Short name T316
Test name
Test status
Simulation time 1122062623 ps
CPU time 4.81 seconds
Started Aug 05 06:23:35 PM PDT 24
Finished Aug 05 06:23:40 PM PDT 24
Peak memory 201188 kb
Host smart-f5dc497d-7c18-46e3-a07a-fa53a2b7ca2e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395489295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_tim
eout.395489295
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.997124978
Short name T664
Test name
Test status
Simulation time 74219849 ps
CPU time 1.09 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:42 PM PDT 24
Peak memory 201088 kb
Host smart-e0c08dc7-4913-4d46-a208-8a27843cb9c7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997124978 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
.clkmgr_idle_intersig_mubi.997124978
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.1137929588
Short name T483
Test name
Test status
Simulation time 67317178 ps
CPU time 0.92 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:42 PM PDT 24
Peak memory 201100 kb
Host smart-8b6de038-d207-43a6-81d8-89a9276a0359
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137929588 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.1137929588
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.1115293750
Short name T741
Test name
Test status
Simulation time 102637863 ps
CPU time 1.07 seconds
Started Aug 05 06:23:42 PM PDT 24
Finished Aug 05 06:23:43 PM PDT 24
Peak memory 201120 kb
Host smart-a2de2c8a-6520-4ce0-a104-f055feba9fbb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115293750 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.1115293750
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.4070714737
Short name T290
Test name
Test status
Simulation time 22363245 ps
CPU time 0.74 seconds
Started Aug 05 06:23:38 PM PDT 24
Finished Aug 05 06:23:39 PM PDT 24
Peak memory 200976 kb
Host smart-2413527b-f599-4849-9c8f-a1904c0f5b9e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070714737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.4070714737
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.2652717116
Short name T31
Test name
Test status
Simulation time 1354552910 ps
CPU time 5.83 seconds
Started Aug 05 06:23:39 PM PDT 24
Finished Aug 05 06:23:45 PM PDT 24
Peak memory 201300 kb
Host smart-017782f7-66a5-4735-9da5-9c7169d81150
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652717116 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.2652717116
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.2992120653
Short name T45
Test name
Test status
Simulation time 316375123 ps
CPU time 3.38 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:44 PM PDT 24
Peak memory 221956 kb
Host smart-74c577f7-e01c-4f27-aef1-a99f271e12f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992120653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmg
r_sec_cm.2992120653
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.3158224540
Short name T446
Test name
Test status
Simulation time 17669689 ps
CPU time 0.81 seconds
Started Aug 05 06:23:41 PM PDT 24
Finished Aug 05 06:23:42 PM PDT 24
Peak memory 201112 kb
Host smart-11b131f8-c022-43df-b9d3-23d349ed2c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158224540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3158224540
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.3731957048
Short name T326
Test name
Test status
Simulation time 8194382342 ps
CPU time 60.03 seconds
Started Aug 05 06:23:40 PM PDT 24
Finished Aug 05 06:24:40 PM PDT 24
Peak memory 201472 kb
Host smart-067f9cff-9863-4991-8a20-ec8f8289ee2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731957048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.3731957048
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1542589855
Short name T800
Test name
Test status
Simulation time 29664145 ps
CPU time 0.99 seconds
Started Aug 05 06:23:36 PM PDT 24
Finished Aug 05 06:23:37 PM PDT 24
Peak memory 201092 kb
Host smart-34d95660-3889-4bfd-a87c-f81fa041d450
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542589855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1542589855
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1651364976
Short name T312
Test name
Test status
Simulation time 18443071 ps
CPU time 0.77 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 201080 kb
Host smart-e3118c21-7dcf-438b-9e57-0d854ddb6c18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651364976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1651364976
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4227606433
Short name T630
Test name
Test status
Simulation time 80759063 ps
CPU time 1.08 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201060 kb
Host smart-a1c04998-eb97-41f0-a5b8-8064debc962f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227606433 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.4227606433
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.491381399
Short name T789
Test name
Test status
Simulation time 15143719 ps
CPU time 0.72 seconds
Started Aug 05 06:26:11 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 201028 kb
Host smart-34092996-881d-49b3-865d-06208421884b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491381399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.491381399
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.396860945
Short name T818
Test name
Test status
Simulation time 25037630 ps
CPU time 0.89 seconds
Started Aug 05 06:26:09 PM PDT 24
Finished Aug 05 06:26:10 PM PDT 24
Peak memory 201084 kb
Host smart-86c84b0f-004b-4cea-9f0e-b0df24a6e079
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396860945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.396860945
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.3088417269
Short name T714
Test name
Test status
Simulation time 45619310 ps
CPU time 0.83 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 200976 kb
Host smart-5c933dc8-9337-44bf-8bd9-e59f74e1f4ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088417269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.3088417269
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.415458323
Short name T373
Test name
Test status
Simulation time 321198615 ps
CPU time 2.36 seconds
Started Aug 05 06:26:09 PM PDT 24
Finished Aug 05 06:26:12 PM PDT 24
Peak memory 201084 kb
Host smart-985a55f3-9403-4f33-8f3b-41e7fa53c482
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415458323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.415458323
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.1283541922
Short name T625
Test name
Test status
Simulation time 990202021 ps
CPU time 4.4 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:16 PM PDT 24
Peak memory 201232 kb
Host smart-81eece0b-e234-4cab-be61-80de8421cb49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283541922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_t
imeout.1283541922
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.2377989974
Short name T582
Test name
Test status
Simulation time 27313846 ps
CPU time 0.92 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201088 kb
Host smart-b954a6bd-a301-44b3-a2af-19bb34233f89
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377989974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.2377989974
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.3425357254
Short name T198
Test name
Test status
Simulation time 35972934 ps
CPU time 0.87 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:12 PM PDT 24
Peak memory 201140 kb
Host smart-ca03c1ea-6a2a-4717-8a20-bcfc533e663d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425357254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.3425357254
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.157869260
Short name T534
Test name
Test status
Simulation time 32261411 ps
CPU time 0.83 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:13 PM PDT 24
Peak memory 201124 kb
Host smart-f0038624-b33a-4155-826b-d84986e83e4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157869260 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 40.clkmgr_lc_ctrl_intersig_mubi.157869260
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.2512117457
Short name T329
Test name
Test status
Simulation time 134378905 ps
CPU time 1.11 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:12 PM PDT 24
Peak memory 201104 kb
Host smart-cdbe1a73-cca0-4b34-bd3d-811d4d6d4af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512117457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.2512117457
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.1507951723
Short name T146
Test name
Test status
Simulation time 151640449 ps
CPU time 1.39 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201080 kb
Host smart-1157f67f-47db-4032-9b8b-ecd5e0f40d75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507951723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.1507951723
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.2250897201
Short name T527
Test name
Test status
Simulation time 71241052 ps
CPU time 1.02 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201096 kb
Host smart-3e2370c5-752a-4cff-96bd-1fbb26710f72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250897201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2250897201
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.505072214
Short name T753
Test name
Test status
Simulation time 4418746388 ps
CPU time 16.07 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201484 kb
Host smart-0dc2bbe7-fbd2-4e96-a404-e5e0d7e566d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505072214 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.505072214
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.1956259659
Short name T652
Test name
Test status
Simulation time 15089632 ps
CPU time 0.72 seconds
Started Aug 05 06:26:15 PM PDT 24
Finished Aug 05 06:26:16 PM PDT 24
Peak memory 201092 kb
Host smart-0293f68d-824d-460f-9048-f990e408dbf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956259659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.1956259659
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.587911027
Short name T436
Test name
Test status
Simulation time 44141067 ps
CPU time 0.81 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:17 PM PDT 24
Peak memory 201076 kb
Host smart-7ea84f19-a013-44af-bb37-45db557c20e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587911027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkm
gr_alert_test.587911027
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.3341738757
Short name T97
Test name
Test status
Simulation time 18446687 ps
CPU time 0.81 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:17 PM PDT 24
Peak memory 201128 kb
Host smart-8d18568c-6393-4084-9777-7cee8f37342c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341738757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.3341738757
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.3508077707
Short name T160
Test name
Test status
Simulation time 18841302 ps
CPU time 0.74 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:13 PM PDT 24
Peak memory 200244 kb
Host smart-7d1d124e-b26d-4bdc-8cfd-801442d9e057
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508077707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.3508077707
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.2159126736
Short name T781
Test name
Test status
Simulation time 43089848 ps
CPU time 0.84 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201128 kb
Host smart-22fe81d4-f137-4792-b854-dfa5f18d08eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159126736 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_div_intersig_mubi.2159126736
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.4103638044
Short name T774
Test name
Test status
Simulation time 47190459 ps
CPU time 1 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 201060 kb
Host smart-61ef1f3b-ad6e-4502-baf9-57caf8c1f75a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103638044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.4103638044
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1393768012
Short name T259
Test name
Test status
Simulation time 1259432915 ps
CPU time 5.11 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:17 PM PDT 24
Peak memory 201128 kb
Host smart-8668edfd-14b7-42e6-b32e-dbc43993c685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393768012 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1393768012
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.3946059001
Short name T293
Test name
Test status
Simulation time 1893763853 ps
CPU time 6.31 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:20 PM PDT 24
Peak memory 201212 kb
Host smart-0bb7c0be-24d7-4654-a666-c2a0af774e9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946059001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_t
imeout.3946059001
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.1656144096
Short name T550
Test name
Test status
Simulation time 34198251 ps
CPU time 1.02 seconds
Started Aug 05 06:26:10 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 201164 kb
Host smart-b28ee39a-ac96-4aa9-a3f9-b37e83e70614
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656144096 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.1656144096
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3895566852
Short name T330
Test name
Test status
Simulation time 40128156 ps
CPU time 0.78 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201076 kb
Host smart-39eecac8-ca90-4860-9d96-d8e1085e211e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895566852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.3895566852
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.550343257
Short name T641
Test name
Test status
Simulation time 26112658 ps
CPU time 0.86 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:19 PM PDT 24
Peak memory 201084 kb
Host smart-3c54eace-9c7d-4977-a178-f15e3cc4d30f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550343257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 41.clkmgr_lc_ctrl_intersig_mubi.550343257
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3442795320
Short name T303
Test name
Test status
Simulation time 24880192 ps
CPU time 0.8 seconds
Started Aug 05 06:26:12 PM PDT 24
Finished Aug 05 06:26:13 PM PDT 24
Peak memory 201028 kb
Host smart-433de7b9-c95f-430e-9589-0f79eab37642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442795320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3442795320
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.156753240
Short name T683
Test name
Test status
Simulation time 609767502 ps
CPU time 3.87 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:22 PM PDT 24
Peak memory 201280 kb
Host smart-11ff2e2e-eebb-4dde-adb9-ee856999f5b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156753240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.156753240
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.1452482415
Short name T351
Test name
Test status
Simulation time 23921286 ps
CPU time 0.93 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201052 kb
Host smart-4be4f066-1421-47d9-b4ec-1c80cacaf471
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452482415 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.1452482415
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.2827168291
Short name T743
Test name
Test status
Simulation time 653198050 ps
CPU time 4.45 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:21 PM PDT 24
Peak memory 201168 kb
Host smart-c3b500b9-5edc-4956-860b-9e29a77ee6d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827168291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.2827168291
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1180436979
Short name T289
Test name
Test status
Simulation time 31091227 ps
CPU time 1.02 seconds
Started Aug 05 06:26:13 PM PDT 24
Finished Aug 05 06:26:14 PM PDT 24
Peak memory 201104 kb
Host smart-1478fac1-cdde-452b-b425-648dc994e01e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180436979 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1180436979
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.3830949342
Short name T214
Test name
Test status
Simulation time 35926289 ps
CPU time 0.8 seconds
Started Aug 05 06:26:15 PM PDT 24
Finished Aug 05 06:26:15 PM PDT 24
Peak memory 201100 kb
Host smart-b7cbc351-5223-491b-b582-a3efcb337fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830949342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.3830949342
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.1181451246
Short name T687
Test name
Test status
Simulation time 15210765 ps
CPU time 0.76 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:19 PM PDT 24
Peak memory 201128 kb
Host smart-d0cb9f36-d0c6-40dd-8d65-5d3f7e789aa0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181451246 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.1181451246
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.2023643541
Short name T702
Test name
Test status
Simulation time 35224097 ps
CPU time 0.73 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 200280 kb
Host smart-b8968caa-452d-4790-b950-00289ddfd8f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023643541 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2023643541
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.1299381938
Short name T319
Test name
Test status
Simulation time 29757295 ps
CPU time 0.91 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201080 kb
Host smart-6f81d3ad-4c95-4579-8db6-b94c8e24668f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299381938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.1299381938
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.1819680410
Short name T820
Test name
Test status
Simulation time 65433285 ps
CPU time 0.98 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:19 PM PDT 24
Peak memory 201080 kb
Host smart-fec909ba-254b-4b99-9a54-65a1d4d57920
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819680410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1819680410
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.1605461611
Short name T3
Test name
Test status
Simulation time 1882361195 ps
CPU time 14.12 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201296 kb
Host smart-a2ff7265-f03e-4e02-8d86-b6aed50361a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605461611 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1605461611
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.4030542768
Short name T270
Test name
Test status
Simulation time 1703990704 ps
CPU time 11.74 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201092 kb
Host smart-63194681-8104-4cfe-b58a-d3169cda7f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030542768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_t
imeout.4030542768
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.3756435821
Short name T447
Test name
Test status
Simulation time 19979022 ps
CPU time 0.82 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201016 kb
Host smart-fc123e97-3f55-4046-9b35-58c01af4f529
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756435821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_idle_intersig_mubi.3756435821
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.4263451851
Short name T179
Test name
Test status
Simulation time 113087862 ps
CPU time 1.07 seconds
Started Aug 05 06:26:15 PM PDT 24
Finished Aug 05 06:26:16 PM PDT 24
Peak memory 201068 kb
Host smart-7ca74744-ecd0-4cb6-a885-57d6338b4d8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263451851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.4263451851
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.3163113929
Short name T225
Test name
Test status
Simulation time 75514967 ps
CPU time 0.92 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201124 kb
Host smart-7b9aceb5-61ca-41d3-ad9d-5e0099309e67
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163113929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_ctrl_intersig_mubi.3163113929
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.3010004530
Short name T803
Test name
Test status
Simulation time 32957526 ps
CPU time 0.76 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201064 kb
Host smart-9a1218e2-b392-49d5-8cf0-74f49b96f32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010004530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3010004530
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.4275649879
Short name T730
Test name
Test status
Simulation time 17105308 ps
CPU time 0.84 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:19 PM PDT 24
Peak memory 201116 kb
Host smart-a2cd24f5-5e4b-4831-8f41-99bcacf5af71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275649879 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.4275649879
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.1892801798
Short name T806
Test name
Test status
Simulation time 5680116975 ps
CPU time 30.76 seconds
Started Aug 05 06:26:16 PM PDT 24
Finished Aug 05 06:26:46 PM PDT 24
Peak memory 201428 kb
Host smart-ae47a8da-9429-4004-8805-f6c7ec0adee7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892801798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.1892801798
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_trans.1652567530
Short name T520
Test name
Test status
Simulation time 50198764 ps
CPU time 0.87 seconds
Started Aug 05 06:26:14 PM PDT 24
Finished Aug 05 06:26:15 PM PDT 24
Peak memory 200976 kb
Host smart-22c6834a-3fd3-417c-8479-7e2ffc5c3941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652567530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1652567530
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.4153887651
Short name T821
Test name
Test status
Simulation time 52656422 ps
CPU time 0.85 seconds
Started Aug 05 06:26:23 PM PDT 24
Finished Aug 05 06:26:24 PM PDT 24
Peak memory 201092 kb
Host smart-3fe6e306-d0e7-41d4-b711-0aeaac86e4c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153887651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.4153887651
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3489686542
Short name T482
Test name
Test status
Simulation time 37816090 ps
CPU time 0.96 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201068 kb
Host smart-b1697136-fd52-4bcf-8016-63307f049b6b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489686542 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.3489686542
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.3463808946
Short name T807
Test name
Test status
Simulation time 14349219 ps
CPU time 0.71 seconds
Started Aug 05 06:26:19 PM PDT 24
Finished Aug 05 06:26:20 PM PDT 24
Peak memory 200276 kb
Host smart-57aa69e9-241d-4dfc-9af7-fa333e7646af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463808946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3463808946
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.2819411213
Short name T254
Test name
Test status
Simulation time 19621580 ps
CPU time 0.84 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 201128 kb
Host smart-32084662-c3af-48d0-a818-b3c66748f7a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819411213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.2819411213
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.2669757266
Short name T8
Test name
Test status
Simulation time 82001844 ps
CPU time 1.11 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:19 PM PDT 24
Peak memory 201068 kb
Host smart-52e3fe53-e5a3-46c6-b5c1-491ab7344b16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669757266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.2669757266
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.4195210677
Short name T291
Test name
Test status
Simulation time 2116374760 ps
CPU time 16.71 seconds
Started Aug 05 06:26:20 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 201360 kb
Host smart-53380b45-beea-42ce-a3b7-17e2f35d61e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195210677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.4195210677
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.3112268827
Short name T371
Test name
Test status
Simulation time 495913914 ps
CPU time 4.04 seconds
Started Aug 05 06:26:18 PM PDT 24
Finished Aug 05 06:26:22 PM PDT 24
Peak memory 201224 kb
Host smart-d11a3ae7-2b8e-4d56-915c-528172f32c18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112268827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.3112268827
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1261719602
Short name T816
Test name
Test status
Simulation time 199609534 ps
CPU time 1.51 seconds
Started Aug 05 06:26:19 PM PDT 24
Finished Aug 05 06:26:21 PM PDT 24
Peak memory 201068 kb
Host smart-122a1eb9-b0f5-4767-9774-772f4c0119c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261719602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1261719602
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.1052079718
Short name T227
Test name
Test status
Simulation time 14173200 ps
CPU time 0.76 seconds
Started Aug 05 06:26:23 PM PDT 24
Finished Aug 05 06:26:24 PM PDT 24
Peak memory 201072 kb
Host smart-a2cabe48-98e9-46fe-8541-c368df4ef9e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052079718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.1052079718
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.989802684
Short name T487
Test name
Test status
Simulation time 140530980 ps
CPU time 1.13 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201084 kb
Host smart-c2a5d300-7b7c-4555-8632-0a4a948db63a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989802684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.989802684
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.4076022792
Short name T735
Test name
Test status
Simulation time 44340147 ps
CPU time 0.84 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201072 kb
Host smart-71a7f794-5e3d-43df-8d33-7bbad1d7bdf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076022792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.4076022792
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.3591065343
Short name T420
Test name
Test status
Simulation time 1588582328 ps
CPU time 4.77 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:27 PM PDT 24
Peak memory 201264 kb
Host smart-5e0ace2d-448a-493d-a044-3dcafe52380f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591065343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.3591065343
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.3199585071
Short name T418
Test name
Test status
Simulation time 44732905 ps
CPU time 0.89 seconds
Started Aug 05 06:26:17 PM PDT 24
Finished Aug 05 06:26:18 PM PDT 24
Peak memory 201108 kb
Host smart-742810a3-fc0e-47a5-9764-3bb2af3a121c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199585071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3199585071
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1415811747
Short name T32
Test name
Test status
Simulation time 3656625446 ps
CPU time 27.35 seconds
Started Aug 05 06:26:20 PM PDT 24
Finished Aug 05 06:26:48 PM PDT 24
Peak memory 201484 kb
Host smart-b24e1110-b35f-44a4-8fc4-2c142a59e975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415811747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1415811747
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_trans.2881595578
Short name T275
Test name
Test status
Simulation time 71139152 ps
CPU time 0.96 seconds
Started Aug 05 06:26:15 PM PDT 24
Finished Aug 05 06:26:16 PM PDT 24
Peak memory 201024 kb
Host smart-1c21ef96-d422-4102-acc5-d88747a3099f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881595578 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2881595578
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1228748797
Short name T267
Test name
Test status
Simulation time 16751577 ps
CPU time 0.76 seconds
Started Aug 05 06:26:23 PM PDT 24
Finished Aug 05 06:26:24 PM PDT 24
Peak memory 201124 kb
Host smart-ff608529-dd00-4ea0-b8bc-b74dd743e23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228748797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1228748797
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1533256634
Short name T223
Test name
Test status
Simulation time 53739285 ps
CPU time 1.08 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:24 PM PDT 24
Peak memory 201064 kb
Host smart-ace61c60-fa0a-4813-a03b-ddfe51910c19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533256634 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_clk_handshake_intersig_mubi.1533256634
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.2158631234
Short name T471
Test name
Test status
Simulation time 51856757 ps
CPU time 0.84 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 200320 kb
Host smart-a3b7e8b7-c84f-412f-86a4-25157129f1c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158631234 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.2158631234
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.390700515
Short name T396
Test name
Test status
Simulation time 104246200 ps
CPU time 1.04 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201056 kb
Host smart-77cb9667-250f-42e3-bc7f-3371d57366f2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390700515 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_div_intersig_mubi.390700515
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.3293378221
Short name T315
Test name
Test status
Simulation time 19303449 ps
CPU time 0.86 seconds
Started Aug 05 06:26:26 PM PDT 24
Finished Aug 05 06:26:27 PM PDT 24
Peak memory 201032 kb
Host smart-f6eb066b-e76d-474b-b6cb-73382da1b36e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293378221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3293378221
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.2407994995
Short name T16
Test name
Test status
Simulation time 1050936441 ps
CPU time 6.48 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201180 kb
Host smart-b604f68b-9cc2-4190-a46b-9a80124c5414
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407994995 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.2407994995
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.1706331489
Short name T239
Test name
Test status
Simulation time 139712507 ps
CPU time 1.61 seconds
Started Aug 05 06:26:21 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201220 kb
Host smart-f88ac46c-0156-4e09-ba6d-07c6d70df4fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706331489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.1706331489
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.592091790
Short name T790
Test name
Test status
Simulation time 113606105 ps
CPU time 1.3 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201124 kb
Host smart-ab04af54-2ab3-47b1-81eb-813d7838ff69
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592091790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.592091790
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.3609360427
Short name T817
Test name
Test status
Simulation time 69935034 ps
CPU time 1.05 seconds
Started Aug 05 06:26:23 PM PDT 24
Finished Aug 05 06:26:24 PM PDT 24
Peak memory 201080 kb
Host smart-8aba278d-7a37-4b84-a34a-2bec95ed16eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609360427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.3609360427
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.2886341656
Short name T711
Test name
Test status
Simulation time 44810448 ps
CPU time 0.81 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201128 kb
Host smart-fd6f018a-e6fa-4893-9cb7-1d962684f137
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886341656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.2886341656
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.2393286045
Short name T614
Test name
Test status
Simulation time 64645439 ps
CPU time 0.85 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201056 kb
Host smart-9363b2a4-e3aa-4261-b48d-33ae55f001af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393286045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.2393286045
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.3361958343
Short name T661
Test name
Test status
Simulation time 828331818 ps
CPU time 4.73 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:34 PM PDT 24
Peak memory 201320 kb
Host smart-ef5caf59-d111-499c-a47e-94e8c0d6f386
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361958343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3361958343
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.1767216156
Short name T133
Test name
Test status
Simulation time 42097819 ps
CPU time 0.91 seconds
Started Aug 05 06:26:24 PM PDT 24
Finished Aug 05 06:26:25 PM PDT 24
Peak memory 201072 kb
Host smart-aceaf0e7-2e28-4d0d-9479-87437b332aad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767216156 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.1767216156
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.1380936748
Short name T716
Test name
Test status
Simulation time 2468203220 ps
CPU time 11.74 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:34 PM PDT 24
Peak memory 201412 kb
Host smart-df1963df-de95-4886-84dc-5ba77e2b6907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380936748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.1380936748
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_trans.1970170132
Short name T397
Test name
Test status
Simulation time 56016866 ps
CPU time 0.91 seconds
Started Aug 05 06:26:21 PM PDT 24
Finished Aug 05 06:26:22 PM PDT 24
Peak memory 201088 kb
Host smart-02c2c1a6-9d88-4a5b-ae36-dcb5c48d9e10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970170132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1970170132
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.3238245628
Short name T701
Test name
Test status
Simulation time 19952259 ps
CPU time 0.81 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201060 kb
Host smart-26d58285-4046-4547-85f8-ea12bbe521cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238245628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.3238245628
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.4093326937
Short name T453
Test name
Test status
Simulation time 66516303 ps
CPU time 0.99 seconds
Started Aug 05 06:26:33 PM PDT 24
Finished Aug 05 06:26:34 PM PDT 24
Peak memory 201088 kb
Host smart-0cd90ee5-cb9a-414a-8b31-865f00e41814
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093326937 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.4093326937
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.1793444282
Short name T407
Test name
Test status
Simulation time 25730792 ps
CPU time 0.7 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 200292 kb
Host smart-ae7ecead-3d53-49e6-801f-b6f13b90a2f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793444282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.1793444282
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.3637413732
Short name T35
Test name
Test status
Simulation time 43259353 ps
CPU time 0.81 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201084 kb
Host smart-dcf17915-787a-46ee-b133-0fe0a2af7c4d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637413732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.3637413732
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.1664271568
Short name T215
Test name
Test status
Simulation time 15610549 ps
CPU time 0.74 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201036 kb
Host smart-5684e1c0-df9d-4fb8-a866-006a0e4ab726
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664271568 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.1664271568
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.289012593
Short name T212
Test name
Test status
Simulation time 564438192 ps
CPU time 4.83 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:40 PM PDT 24
Peak memory 201160 kb
Host smart-c323ab59-b0ea-462f-ac49-e7732652ed54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289012593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.289012593
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.2562714777
Short name T468
Test name
Test status
Simulation time 1300409274 ps
CPU time 5.31 seconds
Started Aug 05 06:26:27 PM PDT 24
Finished Aug 05 06:26:32 PM PDT 24
Peak memory 201196 kb
Host smart-39d29939-5824-4f26-9808-a19d722dc08c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562714777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_t
imeout.2562714777
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.2152867931
Short name T174
Test name
Test status
Simulation time 121659063 ps
CPU time 1.23 seconds
Started Aug 05 06:26:27 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201104 kb
Host smart-9032d3d0-8b00-4cdf-98e7-5a7c6eaa9688
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152867931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_idle_intersig_mubi.2152867931
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.3844829450
Short name T323
Test name
Test status
Simulation time 19719332 ps
CPU time 0.86 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201088 kb
Host smart-588fe4fc-e3d1-406c-81c4-f3ceb7be27c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844829450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.3844829450
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3423333840
Short name T597
Test name
Test status
Simulation time 111634454 ps
CPU time 1.09 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 201096 kb
Host smart-a0a3dc36-2486-4cee-bcb9-ec104035e370
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423333840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.3423333840
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2976079208
Short name T801
Test name
Test status
Simulation time 20032875 ps
CPU time 0.81 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 200992 kb
Host smart-9eb29cf8-6c57-4bf9-85e1-a9799e65a19f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976079208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2976079208
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.406230690
Short name T754
Test name
Test status
Simulation time 1097450991 ps
CPU time 4.85 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:41 PM PDT 24
Peak memory 201280 kb
Host smart-b2732e7e-027a-4e48-9518-cb9304588df4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406230690 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.406230690
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.3699935985
Short name T778
Test name
Test status
Simulation time 25414697 ps
CPU time 0.89 seconds
Started Aug 05 06:26:22 PM PDT 24
Finished Aug 05 06:26:23 PM PDT 24
Peak memory 201080 kb
Host smart-92f74e49-4f50-4eb6-bea2-8d7010e09dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699935985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3699935985
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.2089073045
Short name T519
Test name
Test status
Simulation time 41594223 ps
CPU time 0.94 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201116 kb
Host smart-f1690c4e-22f5-47cb-9679-90605972abd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089073045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_stress_all.2089073045
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.1783104643
Short name T432
Test name
Test status
Simulation time 28872132 ps
CPU time 0.79 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201068 kb
Host smart-902824d1-be03-4af1-9e42-a06d6a0f0833
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783104643 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.1783104643
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.3599096347
Short name T572
Test name
Test status
Simulation time 56178446 ps
CPU time 0.84 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201088 kb
Host smart-3825714c-6fe6-44e8-95d6-077dfda1890d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599096347 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clk
mgr_alert_test.3599096347
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.131746912
Short name T538
Test name
Test status
Simulation time 71894047 ps
CPU time 1.09 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201140 kb
Host smart-9188c0ec-4e5d-4784-9e0d-d1dfacbad967
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131746912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.131746912
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.3670549420
Short name T25
Test name
Test status
Simulation time 21557705 ps
CPU time 0.72 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201000 kb
Host smart-2d383b30-d356-42da-966e-8c8270822b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670549420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.3670549420
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.2268408316
Short name T721
Test name
Test status
Simulation time 51689799 ps
CPU time 0.9 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201092 kb
Host smart-10824e8b-68d2-4ea5-84fc-17964c8b881b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268408316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_div_intersig_mubi.2268408316
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.2326606486
Short name T719
Test name
Test status
Simulation time 29030771 ps
CPU time 0.92 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:32 PM PDT 24
Peak memory 201076 kb
Host smart-dfba1929-c770-475d-9993-35edc61088a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326606486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.2326606486
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.702866037
Short name T441
Test name
Test status
Simulation time 1760209557 ps
CPU time 13.8 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:41 PM PDT 24
Peak memory 201136 kb
Host smart-1d1caaeb-b169-4923-83d2-4cf4cfba4d8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702866037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.702866037
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.3749585143
Short name T689
Test name
Test status
Simulation time 257305186 ps
CPU time 2.41 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 201196 kb
Host smart-f57d2423-12a0-4d42-bbf4-b8a892aff349
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749585143 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.3749585143
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.1168298111
Short name T700
Test name
Test status
Simulation time 64099130 ps
CPU time 0.93 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201132 kb
Host smart-2969a6f5-f072-4746-bc3b-885468fdb4ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168298111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_idle_intersig_mubi.1168298111
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.855540943
Short name T744
Test name
Test status
Simulation time 38718399 ps
CPU time 0.94 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201056 kb
Host smart-f57ff216-a391-4c74-aa7a-bd487b3cf53d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855540943 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_clk_byp_req_intersig_mubi.855540943
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.1078826043
Short name T657
Test name
Test status
Simulation time 20590952 ps
CPU time 0.83 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201012 kb
Host smart-5c1d5772-5853-41a5-b232-28508c851e09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078826043 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 46.clkmgr_lc_ctrl_intersig_mubi.1078826043
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.2037710456
Short name T660
Test name
Test status
Simulation time 16744219 ps
CPU time 0.83 seconds
Started Aug 05 06:26:31 PM PDT 24
Finished Aug 05 06:26:32 PM PDT 24
Peak memory 201100 kb
Host smart-3b1e86ef-02b8-4e44-8dfa-116a7773b7b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037710456 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.2037710456
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.451953653
Short name T310
Test name
Test status
Simulation time 1082518311 ps
CPU time 3.64 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:34 PM PDT 24
Peak memory 201268 kb
Host smart-c984874e-e475-42df-b9a5-cfb399cc3013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451953653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.451953653
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.4222263188
Short name T513
Test name
Test status
Simulation time 16065830 ps
CPU time 0.79 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 201100 kb
Host smart-1dd03689-824a-4996-8a71-11cffa820297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222263188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.4222263188
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.1217904929
Short name T132
Test name
Test status
Simulation time 7974515520 ps
CPU time 58.16 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:27:27 PM PDT 24
Peak memory 201456 kb
Host smart-60eaa20d-77d5-4ad1-88f1-c9fe8361e937
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217904929 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.1217904929
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.825799011
Short name T663
Test name
Test status
Simulation time 360539069359 ps
CPU time 1300.97 seconds
Started Aug 05 06:26:27 PM PDT 24
Finished Aug 05 06:48:08 PM PDT 24
Peak memory 217952 kb
Host smart-7c91fe44-aaec-4d70-83ee-2ed2b22e26fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=825799011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.825799011
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2540997454
Short name T230
Test name
Test status
Simulation time 45241285 ps
CPU time 0.93 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201096 kb
Host smart-251e9e61-2346-4fe9-9a69-390dcdabb33e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540997454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2540997454
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.3492622960
Short name T775
Test name
Test status
Simulation time 62473020 ps
CPU time 0.97 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201092 kb
Host smart-68fc6de7-4464-4804-a994-97b3f1a0db2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492622960 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.3492622960
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.1771505656
Short name T653
Test name
Test status
Simulation time 20937259 ps
CPU time 0.85 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 201088 kb
Host smart-d1965b5e-d547-47b9-9b6b-d75cead2a1a2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771505656 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.1771505656
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.1616325286
Short name T626
Test name
Test status
Simulation time 13251860 ps
CPU time 0.68 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 200992 kb
Host smart-b00a60bf-0e7f-4b6d-af01-90ba1f0469ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616325286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1616325286
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1318080761
Short name T52
Test name
Test status
Simulation time 61725792 ps
CPU time 0.91 seconds
Started Aug 05 06:26:32 PM PDT 24
Finished Aug 05 06:26:33 PM PDT 24
Peak memory 201088 kb
Host smart-a76add54-15d6-48db-8da9-78f3d773c97f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318080761 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.1318080761
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.1773732635
Short name T430
Test name
Test status
Simulation time 35603355 ps
CPU time 0.89 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:26:30 PM PDT 24
Peak memory 201048 kb
Host smart-5061993f-9763-4db7-9786-1be1fc63bae4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773732635 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.1773732635
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.3966577602
Short name T308
Test name
Test status
Simulation time 1517576593 ps
CPU time 11.8 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:40 PM PDT 24
Peak memory 201368 kb
Host smart-3815cbaf-31bf-4ac2-92a1-049fe40fb887
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966577602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3966577602
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.742853526
Short name T276
Test name
Test status
Simulation time 1348068711 ps
CPU time 5.78 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201192 kb
Host smart-ecddbf9a-8d2b-491c-8b78-cda5a31ff8bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742853526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_ti
meout.742853526
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.3291329253
Short name T569
Test name
Test status
Simulation time 24688326 ps
CPU time 0.9 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201088 kb
Host smart-714ae257-6a1c-41ff-abd9-be24041db3ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291329253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.3291329253
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.3635027852
Short name T794
Test name
Test status
Simulation time 17073886 ps
CPU time 0.92 seconds
Started Aug 05 06:26:30 PM PDT 24
Finished Aug 05 06:26:31 PM PDT 24
Peak memory 201088 kb
Host smart-21c67d30-13ed-45ab-9228-96e169ef13de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635027852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.3635027852
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.3598944933
Short name T621
Test name
Test status
Simulation time 152640643 ps
CPU time 1.17 seconds
Started Aug 05 06:26:32 PM PDT 24
Finished Aug 05 06:26:33 PM PDT 24
Peak memory 201080 kb
Host smart-9eec2444-37a6-4d62-b5fd-a75946b226fa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598944933 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_ctrl_intersig_mubi.3598944933
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.4102809404
Short name T231
Test name
Test status
Simulation time 22216700 ps
CPU time 0.76 seconds
Started Aug 05 06:26:28 PM PDT 24
Finished Aug 05 06:26:29 PM PDT 24
Peak memory 201100 kb
Host smart-090a4e98-8b46-4839-a689-fb7d5c573cbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102809404 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.4102809404
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.371225431
Short name T767
Test name
Test status
Simulation time 456461469 ps
CPU time 2.45 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:38 PM PDT 24
Peak memory 201280 kb
Host smart-6b3088e6-72a6-4a20-86f5-e6d78f7eab65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371225431 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.371225431
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.2634240653
Short name T699
Test name
Test status
Simulation time 78164673 ps
CPU time 1.02 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201076 kb
Host smart-bc811c2c-cfb6-40a3-815b-07e665777fee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634240653 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.2634240653
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.952761955
Short name T53
Test name
Test status
Simulation time 5325416053 ps
CPU time 40.06 seconds
Started Aug 05 06:26:29 PM PDT 24
Finished Aug 05 06:27:10 PM PDT 24
Peak memory 201456 kb
Host smart-ee4abe2d-3625-430a-b1ff-df327553d11c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952761955 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.952761955
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_trans.1659168749
Short name T581
Test name
Test status
Simulation time 23057153 ps
CPU time 0.85 seconds
Started Aug 05 06:26:32 PM PDT 24
Finished Aug 05 06:26:33 PM PDT 24
Peak memory 201076 kb
Host smart-b7c796bf-18d0-4dc0-af85-802b17422606
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659168749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1659168749
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.1803846580
Short name T724
Test name
Test status
Simulation time 35662193 ps
CPU time 0.82 seconds
Started Aug 05 06:26:42 PM PDT 24
Finished Aug 05 06:26:43 PM PDT 24
Peak memory 201096 kb
Host smart-9d18276a-c05f-4a68-9842-92bad4f269e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803846580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.1803846580
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1070899689
Short name T438
Test name
Test status
Simulation time 20924261 ps
CPU time 0.76 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201064 kb
Host smart-7f608601-cf4c-4c1f-97f3-9b24ba49e419
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070899689 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.1070899689
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.4032369920
Short name T161
Test name
Test status
Simulation time 16442966 ps
CPU time 0.74 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 200272 kb
Host smart-1cf41a87-e9ef-41a9-a8cc-54021d6b7968
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032369920 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.4032369920
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.2985673186
Short name T207
Test name
Test status
Simulation time 22484915 ps
CPU time 0.83 seconds
Started Aug 05 06:26:42 PM PDT 24
Finished Aug 05 06:26:43 PM PDT 24
Peak memory 201108 kb
Host smart-dd2e0277-78e8-4531-ba30-b6157e29fc73
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985673186 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.2985673186
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.4130009677
Short name T679
Test name
Test status
Simulation time 70057951 ps
CPU time 1.01 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201052 kb
Host smart-fafd46e7-8b35-4f2a-8972-fc8cabfc2a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130009677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.4130009677
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.1738934262
Short name T390
Test name
Test status
Simulation time 1643928237 ps
CPU time 9.77 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:45 PM PDT 24
Peak memory 201136 kb
Host smart-770938a5-c795-47fd-a615-756129c2e1aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738934262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.1738934262
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.1187237587
Short name T321
Test name
Test status
Simulation time 1945417531 ps
CPU time 10.68 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:47 PM PDT 24
Peak memory 201192 kb
Host smart-2c77a451-7b55-4fd3-ad66-347b8e4f6974
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187237587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_t
imeout.1187237587
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.3615578684
Short name T644
Test name
Test status
Simulation time 147563783 ps
CPU time 1.39 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201084 kb
Host smart-59f7c864-e2a3-4d02-906b-fecdec5b6e4f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615578684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.3615578684
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.3650436337
Short name T609
Test name
Test status
Simulation time 24945370 ps
CPU time 0.88 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201084 kb
Host smart-fdde7d3a-6ed5-4f82-ac80-d3a550f723e2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650436337 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_clk_byp_req_intersig_mubi.3650436337
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.44460300
Short name T780
Test name
Test status
Simulation time 17186193 ps
CPU time 0.77 seconds
Started Aug 05 06:26:33 PM PDT 24
Finished Aug 05 06:26:34 PM PDT 24
Peak memory 201092 kb
Host smart-a7615cfc-d1df-418a-ac57-263632f11523
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44460300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_lc_ctrl_intersig_mubi.44460300
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.3928873725
Short name T364
Test name
Test status
Simulation time 42063531 ps
CPU time 0.81 seconds
Started Aug 05 06:26:42 PM PDT 24
Finished Aug 05 06:26:43 PM PDT 24
Peak memory 201072 kb
Host smart-75f9f3fa-f7a9-44a1-b6a4-4709601b5a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928873725 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.3928873725
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.1939953889
Short name T4
Test name
Test status
Simulation time 427457276 ps
CPU time 2.67 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:38 PM PDT 24
Peak memory 201080 kb
Host smart-45d4798d-1b8c-44ab-9b23-ac1507b08510
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939953889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1939953889
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.327727356
Short name T475
Test name
Test status
Simulation time 16715588 ps
CPU time 0.82 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:36 PM PDT 24
Peak memory 201044 kb
Host smart-c840ccff-e194-4db1-91d4-cb98efa86921
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327727356 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.327727356
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.493741380
Short name T332
Test name
Test status
Simulation time 3329003037 ps
CPU time 21.79 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:55 PM PDT 24
Peak memory 201556 kb
Host smart-1f0971dd-9e48-40e4-888d-78df0a3a995f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493741380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.493741380
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.2626355699
Short name T445
Test name
Test status
Simulation time 28670351 ps
CPU time 0.95 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201096 kb
Host smart-fe27ff8c-93c9-42d5-8ba0-7ff30648eb6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626355699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2626355699
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1646537490
Short name T288
Test name
Test status
Simulation time 43232789 ps
CPU time 0.78 seconds
Started Aug 05 06:26:40 PM PDT 24
Finished Aug 05 06:26:41 PM PDT 24
Peak memory 201104 kb
Host smart-612cfc4f-ee12-4fec-b9ac-85e9a645d3e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646537490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1646537490
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.1189833319
Short name T558
Test name
Test status
Simulation time 44745940 ps
CPU time 0.91 seconds
Started Aug 05 06:26:43 PM PDT 24
Finished Aug 05 06:26:44 PM PDT 24
Peak memory 201080 kb
Host smart-cdcb29ae-237d-48d3-adfd-9c4702691fda
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189833319 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.1189833319
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.1549260136
Short name T163
Test name
Test status
Simulation time 48155195 ps
CPU time 0.77 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 200280 kb
Host smart-1cdc4aec-2427-4ef4-b11b-08f8c415b8df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549260136 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1549260136
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2316868307
Short name T264
Test name
Test status
Simulation time 22126994 ps
CPU time 0.74 seconds
Started Aug 05 06:26:40 PM PDT 24
Finished Aug 05 06:26:40 PM PDT 24
Peak memory 201072 kb
Host smart-8e94142e-afd9-46ee-91d2-6304c28438a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316868307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2316868307
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3283646354
Short name T317
Test name
Test status
Simulation time 16635240 ps
CPU time 0.8 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201004 kb
Host smart-94262fbe-9eba-4df6-b3f3-1d9cd63841c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283646354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3283646354
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.516673201
Short name T686
Test name
Test status
Simulation time 1421218414 ps
CPU time 6.58 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:40 PM PDT 24
Peak memory 201104 kb
Host smart-539e70f7-e66d-47c5-8377-faff25502443
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516673201 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.516673201
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.520963985
Short name T584
Test name
Test status
Simulation time 1697936641 ps
CPU time 12.44 seconds
Started Aug 05 06:26:38 PM PDT 24
Finished Aug 05 06:26:50 PM PDT 24
Peak memory 201196 kb
Host smart-e4c5529b-85ca-41fe-9a82-eb6968f8b858
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520963985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_ti
meout.520963985
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.2495522480
Short name T649
Test name
Test status
Simulation time 60809007 ps
CPU time 1.07 seconds
Started Aug 05 06:26:34 PM PDT 24
Finished Aug 05 06:26:35 PM PDT 24
Peak memory 201100 kb
Host smart-40b7be1d-b17c-4ba6-a5d8-5a24c95942a0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495522480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.2495522480
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2322445679
Short name T710
Test name
Test status
Simulation time 93200397 ps
CPU time 0.99 seconds
Started Aug 05 06:26:41 PM PDT 24
Finished Aug 05 06:26:42 PM PDT 24
Peak memory 201080 kb
Host smart-792627a3-776b-4759-89b3-e15f0e4be9c4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322445679 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.2322445679
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.3580769739
Short name T414
Test name
Test status
Simulation time 73261207 ps
CPU time 0.96 seconds
Started Aug 05 06:26:38 PM PDT 24
Finished Aug 05 06:26:39 PM PDT 24
Peak memory 201084 kb
Host smart-dad37cf6-e052-4346-ae15-0bd2b28b6fa0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580769739 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.3580769739
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.3664857411
Short name T515
Test name
Test status
Simulation time 20272214 ps
CPU time 0.8 seconds
Started Aug 05 06:26:36 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 201072 kb
Host smart-96d1223e-42bb-4621-afc7-5b49f18c8b32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664857411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.3664857411
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.1991967460
Short name T495
Test name
Test status
Simulation time 1361666360 ps
CPU time 6.32 seconds
Started Aug 05 06:26:40 PM PDT 24
Finished Aug 05 06:26:46 PM PDT 24
Peak memory 201280 kb
Host smart-e0a5f9e0-7372-45c6-884a-828ae0722c40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991967460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.1991967460
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.187566947
Short name T154
Test name
Test status
Simulation time 45709192 ps
CPU time 0.91 seconds
Started Aug 05 06:26:37 PM PDT 24
Finished Aug 05 06:26:38 PM PDT 24
Peak memory 201024 kb
Host smart-802e00a3-fce1-463f-9b99-f9b52876c3e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187566947 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.187566947
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.1348480858
Short name T691
Test name
Test status
Simulation time 4143945284 ps
CPU time 30.69 seconds
Started Aug 05 06:26:43 PM PDT 24
Finished Aug 05 06:27:13 PM PDT 24
Peak memory 201440 kb
Host smart-8695dee0-fd97-42a7-9de9-535803445446
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348480858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.1348480858
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.884984017
Short name T111
Test name
Test status
Simulation time 25198311 ps
CPU time 0.9 seconds
Started Aug 05 06:26:35 PM PDT 24
Finished Aug 05 06:26:37 PM PDT 24
Peak memory 201068 kb
Host smart-f36a5e4f-2f3a-4f2f-81dd-ce3e0d60235f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884984017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.884984017
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.3638495018
Short name T412
Test name
Test status
Simulation time 98623871 ps
CPU time 0.97 seconds
Started Aug 05 06:23:48 PM PDT 24
Finished Aug 05 06:23:49 PM PDT 24
Peak memory 201092 kb
Host smart-f6102d17-b696-4aef-88a6-432a2551e592
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638495018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.3638495018
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.396751278
Short name T91
Test name
Test status
Simulation time 27339088 ps
CPU time 0.94 seconds
Started Aug 05 06:23:46 PM PDT 24
Finished Aug 05 06:23:48 PM PDT 24
Peak memory 201084 kb
Host smart-5cf04516-15a6-4e4d-bb95-3aeda29e8acf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396751278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.396751278
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.1273931528
Short name T394
Test name
Test status
Simulation time 38613316 ps
CPU time 0.74 seconds
Started Aug 05 06:23:47 PM PDT 24
Finished Aug 05 06:23:48 PM PDT 24
Peak memory 200264 kb
Host smart-254f376e-e669-4f30-b1cd-e7f369302d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273931528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1273931528
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.3919792309
Short name T76
Test name
Test status
Simulation time 31009149 ps
CPU time 0.75 seconds
Started Aug 05 06:23:46 PM PDT 24
Finished Aug 05 06:23:47 PM PDT 24
Peak memory 201112 kb
Host smart-a641434b-8319-4d5a-8f0e-aec85e02b8e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919792309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.3919792309
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.1091997395
Short name T593
Test name
Test status
Simulation time 21800439 ps
CPU time 0.79 seconds
Started Aug 05 06:23:44 PM PDT 24
Finished Aug 05 06:23:45 PM PDT 24
Peak memory 201008 kb
Host smart-cb623199-6de4-4be8-af08-c477fb231216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091997395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.1091997395
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.970854747
Short name T292
Test name
Test status
Simulation time 1412429441 ps
CPU time 8.24 seconds
Started Aug 05 06:23:45 PM PDT 24
Finished Aug 05 06:23:54 PM PDT 24
Peak memory 201168 kb
Host smart-315dcfe1-de9b-4563-8a40-507c679a574e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970854747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.970854747
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.364635350
Short name T340
Test name
Test status
Simulation time 261042733 ps
CPU time 2.33 seconds
Started Aug 05 06:23:46 PM PDT 24
Finished Aug 05 06:23:48 PM PDT 24
Peak memory 201228 kb
Host smart-46ceb452-6fb1-4d6a-9f07-d04fa7860798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364635350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_tim
eout.364635350
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.3552284454
Short name T361
Test name
Test status
Simulation time 32063088 ps
CPU time 0.95 seconds
Started Aug 05 06:23:47 PM PDT 24
Finished Aug 05 06:23:48 PM PDT 24
Peak memory 201064 kb
Host smart-ee0911c3-816a-4820-a0e9-6b31287d3bfc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552284454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_idle_intersig_mubi.3552284454
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.2938448002
Short name T553
Test name
Test status
Simulation time 11781964 ps
CPU time 0.75 seconds
Started Aug 05 06:23:48 PM PDT 24
Finished Aug 05 06:23:49 PM PDT 24
Peak memory 201108 kb
Host smart-41f5ea83-5f9e-426b-9ddb-1dbc04d4658f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938448002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.2938448002
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.411131338
Short name T192
Test name
Test status
Simulation time 60189103 ps
CPU time 0.91 seconds
Started Aug 05 06:23:45 PM PDT 24
Finished Aug 05 06:23:46 PM PDT 24
Peak memory 201096 kb
Host smart-e27191e8-e308-4d7f-a6e0-bec93131fe2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411131338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_ctrl_intersig_mubi.411131338
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.3056936115
Short name T187
Test name
Test status
Simulation time 75582068 ps
CPU time 0.88 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201116 kb
Host smart-e838342a-7f67-44c2-b091-719d6717aa37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056936115 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.3056936115
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.3208238366
Short name T574
Test name
Test status
Simulation time 1083364203 ps
CPU time 6.28 seconds
Started Aug 05 06:23:50 PM PDT 24
Finished Aug 05 06:23:56 PM PDT 24
Peak memory 201320 kb
Host smart-2857be38-c9eb-4e2e-a24d-1d0da971c6f9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208238366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.3208238366
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.3742626797
Short name T135
Test name
Test status
Simulation time 81177569 ps
CPU time 1.03 seconds
Started Aug 05 06:23:40 PM PDT 24
Finished Aug 05 06:23:41 PM PDT 24
Peak memory 201108 kb
Host smart-be7f395e-9104-4df9-872d-78bfda61b9f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742626797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3742626797
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.864799923
Short name T737
Test name
Test status
Simulation time 194173471 ps
CPU time 2.26 seconds
Started Aug 05 06:23:48 PM PDT 24
Finished Aug 05 06:23:50 PM PDT 24
Peak memory 201240 kb
Host smart-9d2901e6-bf96-4627-be35-19f42e49f6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864799923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.864799923
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_trans.3738722802
Short name T26
Test name
Test status
Simulation time 17944149 ps
CPU time 0.75 seconds
Started Aug 05 06:23:47 PM PDT 24
Finished Aug 05 06:23:48 PM PDT 24
Peak memory 201108 kb
Host smart-af5cbf23-7235-4034-aa23-9d11334754c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738722802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.3738722802
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.394009327
Short name T634
Test name
Test status
Simulation time 59091085 ps
CPU time 0.85 seconds
Started Aug 05 06:23:50 PM PDT 24
Finished Aug 05 06:23:51 PM PDT 24
Peak memory 201056 kb
Host smart-75c27a91-1944-4776-bc89-0259263bc547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394009327 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmg
r_alert_test.394009327
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.1074767055
Short name T150
Test name
Test status
Simulation time 16251015 ps
CPU time 0.79 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201080 kb
Host smart-4b74fd64-7a1f-420d-ba08-2da540ae036f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074767055 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.1074767055
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2457558388
Short name T545
Test name
Test status
Simulation time 16316943 ps
CPU time 0.71 seconds
Started Aug 05 06:23:53 PM PDT 24
Finished Aug 05 06:23:53 PM PDT 24
Peak memory 200260 kb
Host smart-00adb8ce-a1c1-4b5f-8650-eaead19c3cca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457558388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2457558388
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.2219037856
Short name T720
Test name
Test status
Simulation time 22452259 ps
CPU time 0.76 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201108 kb
Host smart-abea8058-aacb-4d65-b590-02d171de34da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219037856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_div_intersig_mubi.2219037856
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.2327509086
Short name T28
Test name
Test status
Simulation time 21821097 ps
CPU time 0.78 seconds
Started Aug 05 06:23:52 PM PDT 24
Finished Aug 05 06:23:53 PM PDT 24
Peak memory 201044 kb
Host smart-16aebc6e-ae91-4ed8-bc53-c405154f52e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327509086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.2327509086
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.3460749430
Short name T797
Test name
Test status
Simulation time 348342292 ps
CPU time 2.14 seconds
Started Aug 05 06:23:52 PM PDT 24
Finished Aug 05 06:23:55 PM PDT 24
Peak memory 201096 kb
Host smart-07d40c6f-2e4e-41e2-9bbc-981ba17592b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460749430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.3460749430
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.417047877
Short name T48
Test name
Test status
Simulation time 495491698 ps
CPU time 4.27 seconds
Started Aug 05 06:23:50 PM PDT 24
Finished Aug 05 06:23:54 PM PDT 24
Peak memory 201192 kb
Host smart-c26727d0-34d5-4291-8a87-6c77dc955d46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417047877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_tim
eout.417047877
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.750141986
Short name T766
Test name
Test status
Simulation time 80403769 ps
CPU time 1.03 seconds
Started Aug 05 06:23:55 PM PDT 24
Finished Aug 05 06:23:56 PM PDT 24
Peak memory 201104 kb
Host smart-2f647c22-e7be-4754-b5aa-5ba5711a5a83
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750141986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_idle_intersig_mubi.750141986
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.1564987203
Short name T452
Test name
Test status
Simulation time 20958965 ps
CPU time 0.82 seconds
Started Aug 05 06:23:52 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201076 kb
Host smart-eb00b6b2-46a6-4a11-8533-4501b1bef07e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564987203 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.1564987203
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.3542402305
Short name T168
Test name
Test status
Simulation time 18430905 ps
CPU time 0.82 seconds
Started Aug 05 06:23:55 PM PDT 24
Finished Aug 05 06:23:56 PM PDT 24
Peak memory 201108 kb
Host smart-4a51656d-8afa-4f26-bdeb-ee5a616033bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542402305 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.3542402305
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.4136975293
Short name T805
Test name
Test status
Simulation time 25280044 ps
CPU time 0.79 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201104 kb
Host smart-6943af00-fce6-428f-ba75-51bad393416c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136975293 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.4136975293
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3868373877
Short name T512
Test name
Test status
Simulation time 1366186832 ps
CPU time 4.97 seconds
Started Aug 05 06:23:55 PM PDT 24
Finished Aug 05 06:24:00 PM PDT 24
Peak memory 201300 kb
Host smart-2ef72d66-7c7a-4c84-aa12-7e3583a92841
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868373877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3868373877
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.1931183911
Short name T772
Test name
Test status
Simulation time 65256942 ps
CPU time 0.97 seconds
Started Aug 05 06:23:46 PM PDT 24
Finished Aug 05 06:23:47 PM PDT 24
Peak memory 201072 kb
Host smart-2311f45e-1aa6-4a28-9cb0-564008fa2321
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931183911 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1931183911
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.1965965674
Short name T349
Test name
Test status
Simulation time 1060505458 ps
CPU time 5.33 seconds
Started Aug 05 06:23:50 PM PDT 24
Finished Aug 05 06:23:55 PM PDT 24
Peak memory 201224 kb
Host smart-c31ea1d8-d1ee-4521-bae6-78e2f68dc78a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965965674 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.1965965674
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all_with_rand_reset.2440219053
Short name T155
Test name
Test status
Simulation time 82384836293 ps
CPU time 519.7 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:32:31 PM PDT 24
Peak memory 209776 kb
Host smart-2c153537-96f6-4275-8120-2235c9fcf4f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2440219053 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2440219053
Directory /workspace/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1419094760
Short name T439
Test name
Test status
Simulation time 29951228 ps
CPU time 0.94 seconds
Started Aug 05 06:23:51 PM PDT 24
Finished Aug 05 06:23:52 PM PDT 24
Peak memory 201136 kb
Host smart-915b2204-653b-42ca-93d7-d6eee7e665d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419094760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1419094760
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.846484007
Short name T360
Test name
Test status
Simulation time 49936834 ps
CPU time 0.88 seconds
Started Aug 05 06:23:55 PM PDT 24
Finished Aug 05 06:23:56 PM PDT 24
Peak memory 201084 kb
Host smart-dab90ced-2cf4-4400-bf54-6bc0516454e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846484007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmg
r_alert_test.846484007
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1786538877
Short name T549
Test name
Test status
Simulation time 21486891 ps
CPU time 0.82 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:23:59 PM PDT 24
Peak memory 201076 kb
Host smart-df3c88c9-14cb-4a7e-8110-9371cb0a0836
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786538877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1786538877
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.749118368
Short name T522
Test name
Test status
Simulation time 166701898 ps
CPU time 1.04 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:23:58 PM PDT 24
Peak memory 200272 kb
Host smart-98696d05-4a16-4727-8550-5ed4c7277385
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749118368 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.749118368
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1795368162
Short name T656
Test name
Test status
Simulation time 32180541 ps
CPU time 0.74 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:23:59 PM PDT 24
Peak memory 201052 kb
Host smart-21b03564-8172-4b1b-91e8-c86845b30920
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795368162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1795368162
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.445030199
Short name T693
Test name
Test status
Simulation time 27035349 ps
CPU time 0.94 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:23:58 PM PDT 24
Peak memory 201088 kb
Host smart-f5e1e8dd-fc7a-4e38-9bd3-6043747800b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445030199 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.445030199
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.826101521
Short name T243
Test name
Test status
Simulation time 798871136 ps
CPU time 7.22 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:24:05 PM PDT 24
Peak memory 201132 kb
Host smart-70de2b5b-14c2-4816-9e2b-dbffc90f2b76
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826101521 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.826101521
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.1006985925
Short name T729
Test name
Test status
Simulation time 155991613 ps
CPU time 1.34 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:23:58 PM PDT 24
Peak memory 201152 kb
Host smart-c14be027-ab3f-426b-9ce9-1a65a8abbd3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006985925 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.1006985925
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.1676100364
Short name T461
Test name
Test status
Simulation time 18787603 ps
CPU time 0.83 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:23:58 PM PDT 24
Peak memory 201068 kb
Host smart-98ef1b96-9cda-4c60-b802-64a13c669517
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676100364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.1676100364
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1257925132
Short name T194
Test name
Test status
Simulation time 70815037 ps
CPU time 1 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:23:58 PM PDT 24
Peak memory 201096 kb
Host smart-9d1e7e1e-5abf-47e8-99f5-c72f1f5b9478
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257925132 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.1257925132
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.2620051743
Short name T193
Test name
Test status
Simulation time 76706300 ps
CPU time 1.04 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:23:59 PM PDT 24
Peak memory 201044 kb
Host smart-ebf801db-c194-4d5c-935b-51dd6ee2ecf8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620051743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_ctrl_intersig_mubi.2620051743
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.3725173029
Short name T732
Test name
Test status
Simulation time 20480497 ps
CPU time 0.84 seconds
Started Aug 05 06:23:56 PM PDT 24
Finished Aug 05 06:23:57 PM PDT 24
Peak memory 201192 kb
Host smart-8b04cdaf-1fa9-4982-a85b-1f803f029eb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725173029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3725173029
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.130274900
Short name T262
Test name
Test status
Simulation time 767828643 ps
CPU time 3.1 seconds
Started Aug 05 06:23:57 PM PDT 24
Finished Aug 05 06:24:00 PM PDT 24
Peak memory 201264 kb
Host smart-886a7df9-7925-4718-b45f-4dc651e45424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130274900 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.130274900
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.67668577
Short name T199
Test name
Test status
Simulation time 15932206 ps
CPU time 0.78 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:23:59 PM PDT 24
Peak memory 201024 kb
Host smart-f6b195e0-cc4f-48c1-9eb2-4b4017312d8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67668577 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.67668577
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.2891080064
Short name T382
Test name
Test status
Simulation time 11790670685 ps
CPU time 82.85 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:25:21 PM PDT 24
Peak memory 201456 kb
Host smart-5b06577b-7d8d-4f0b-a41a-279485de8434
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891080064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.2891080064
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.1747869045
Short name T450
Test name
Test status
Simulation time 56793046 ps
CPU time 0.88 seconds
Started Aug 05 06:23:58 PM PDT 24
Finished Aug 05 06:23:59 PM PDT 24
Peak memory 201096 kb
Host smart-08941ec1-887a-4246-8eda-613b3b76bc26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747869045 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.1747869045
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.768506485
Short name T580
Test name
Test status
Simulation time 46442699 ps
CPU time 0.79 seconds
Started Aug 05 06:24:08 PM PDT 24
Finished Aug 05 06:24:09 PM PDT 24
Peak memory 201084 kb
Host smart-2eb3bd0f-d430-4748-917d-557a6a346540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768506485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmg
r_alert_test.768506485
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.3467757816
Short name T395
Test name
Test status
Simulation time 55943669 ps
CPU time 0.92 seconds
Started Aug 05 06:24:04 PM PDT 24
Finished Aug 05 06:24:05 PM PDT 24
Peak memory 201072 kb
Host smart-f193f514-9a11-4f58-8110-8abb396b5444
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467757816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.3467757816
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.2748680334
Short name T749
Test name
Test status
Simulation time 42387420 ps
CPU time 0.78 seconds
Started Aug 05 06:24:05 PM PDT 24
Finished Aug 05 06:24:05 PM PDT 24
Peak memory 200260 kb
Host smart-69416b57-9f8c-4a00-9bb8-b51f11ce222a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748680334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.2748680334
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.1968500522
Short name T793
Test name
Test status
Simulation time 16685996 ps
CPU time 0.78 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:03 PM PDT 24
Peak memory 201052 kb
Host smart-a4599d8e-6302-4359-be60-385e4c22b364
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968500522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.1968500522
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.4199498894
Short name T211
Test name
Test status
Simulation time 73767089 ps
CPU time 1 seconds
Started Aug 05 06:24:03 PM PDT 24
Finished Aug 05 06:24:04 PM PDT 24
Peak memory 201104 kb
Host smart-b10865ef-34a8-49d1-a01f-44371c29fee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199498894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.4199498894
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.1622301446
Short name T18
Test name
Test status
Simulation time 1782926327 ps
CPU time 8.94 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:11 PM PDT 24
Peak memory 201120 kb
Host smart-263bc997-2980-4386-8199-cb77a100cd00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622301446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.1622301446
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.291296379
Short name T186
Test name
Test status
Simulation time 2322145203 ps
CPU time 9.42 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:12 PM PDT 24
Peak memory 201456 kb
Host smart-e085f43a-78df-4622-80e0-977823bffe42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291296379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_tim
eout.291296379
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.941197572
Short name T343
Test name
Test status
Simulation time 29606441 ps
CPU time 0.97 seconds
Started Aug 05 06:24:04 PM PDT 24
Finished Aug 05 06:24:05 PM PDT 24
Peak memory 201052 kb
Host smart-a2088a95-55ef-4dc3-af2c-83330e190982
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941197572 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.clkmgr_idle_intersig_mubi.941197572
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.1235742291
Short name T229
Test name
Test status
Simulation time 20817646 ps
CPU time 0.83 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:03 PM PDT 24
Peak memory 201088 kb
Host smart-a27a2a1a-a072-42d6-8b27-76b1b97e653e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235742291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.1235742291
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.930670841
Short name T500
Test name
Test status
Simulation time 76099394 ps
CPU time 0.94 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:03 PM PDT 24
Peak memory 201112 kb
Host smart-bfe3a2f6-a7e0-451e-93bc-e0aade6d024c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930670841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.clkmgr_lc_ctrl_intersig_mubi.930670841
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.2353197806
Short name T226
Test name
Test status
Simulation time 52727743 ps
CPU time 0.88 seconds
Started Aug 05 06:24:01 PM PDT 24
Finished Aug 05 06:24:02 PM PDT 24
Peak memory 201004 kb
Host smart-c18d8d5d-c62c-469f-8f66-eac1c7cfe1a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353197806 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.2353197806
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1692201563
Short name T531
Test name
Test status
Simulation time 1702904578 ps
CPU time 6.05 seconds
Started Aug 05 06:24:00 PM PDT 24
Finished Aug 05 06:24:07 PM PDT 24
Peak memory 201292 kb
Host smart-d3ca541d-6fd7-400f-9c52-f7a50362ea72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692201563 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1692201563
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.371288584
Short name T409
Test name
Test status
Simulation time 23607722 ps
CPU time 0.86 seconds
Started Aug 05 06:23:56 PM PDT 24
Finished Aug 05 06:23:57 PM PDT 24
Peak memory 201076 kb
Host smart-d0ca1fb4-03c1-478c-a97c-baff2d213a4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371288584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.371288584
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.4143752144
Short name T718
Test name
Test status
Simulation time 16677726063 ps
CPU time 124.21 seconds
Started Aug 05 06:24:07 PM PDT 24
Finished Aug 05 06:26:11 PM PDT 24
Peak memory 201472 kb
Host smart-e537ee06-cf09-40f9-a7d2-446cc0b5bf06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143752144 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.4143752144
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.1641759399
Short name T273
Test name
Test status
Simulation time 49702249 ps
CPU time 1 seconds
Started Aug 05 06:24:02 PM PDT 24
Finished Aug 05 06:24:03 PM PDT 24
Peak memory 201080 kb
Host smart-77ed01b0-b8e0-4f57-bb80-6a89d386e3ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641759399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.1641759399
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.3695602208
Short name T228
Test name
Test status
Simulation time 53013199 ps
CPU time 0.88 seconds
Started Aug 05 06:24:11 PM PDT 24
Finished Aug 05 06:24:12 PM PDT 24
Peak memory 201092 kb
Host smart-82e2c3d8-f88f-4224-a28f-371f7b2aa756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695602208 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.3695602208
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.4180404748
Short name T272
Test name
Test status
Simulation time 26096991 ps
CPU time 0.91 seconds
Started Aug 05 06:24:09 PM PDT 24
Finished Aug 05 06:24:10 PM PDT 24
Peak memory 201096 kb
Host smart-42a476ef-f9ed-46a7-8e33-bf8792b8bab6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180404748 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.4180404748
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.1337393881
Short name T384
Test name
Test status
Simulation time 38410332 ps
CPU time 0.75 seconds
Started Aug 05 06:24:08 PM PDT 24
Finished Aug 05 06:24:09 PM PDT 24
Peak memory 200928 kb
Host smart-7acbfefe-18a8-4ce5-862b-129d01e7c90d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337393881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.1337393881
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.2651732122
Short name T672
Test name
Test status
Simulation time 35102162 ps
CPU time 0.8 seconds
Started Aug 05 06:24:12 PM PDT 24
Finished Aug 05 06:24:13 PM PDT 24
Peak memory 201008 kb
Host smart-91256b24-b6be-4f14-92c0-11f6f6f0d821
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651732122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.2651732122
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.2058285981
Short name T342
Test name
Test status
Simulation time 30784596 ps
CPU time 0.81 seconds
Started Aug 05 06:24:08 PM PDT 24
Finished Aug 05 06:24:09 PM PDT 24
Peak memory 201072 kb
Host smart-d37c541c-40a1-48f7-8ffd-ce4812e157f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058285981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.2058285981
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.1464697355
Short name T29
Test name
Test status
Simulation time 202725603 ps
CPU time 1.6 seconds
Started Aug 05 06:24:09 PM PDT 24
Finished Aug 05 06:24:10 PM PDT 24
Peak memory 201152 kb
Host smart-1512b297-1dff-478e-b936-bbdb22c48791
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464697355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.1464697355
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.1541470664
Short name T353
Test name
Test status
Simulation time 1726891766 ps
CPU time 5.5 seconds
Started Aug 05 06:24:07 PM PDT 24
Finished Aug 05 06:24:13 PM PDT 24
Peak memory 201196 kb
Host smart-cca7560a-7cf4-4719-95a1-70a51aa6ff8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541470664 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_ti
meout.1541470664
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.2242846547
Short name T265
Test name
Test status
Simulation time 80637075 ps
CPU time 1.13 seconds
Started Aug 05 06:24:09 PM PDT 24
Finished Aug 05 06:24:10 PM PDT 24
Peak memory 201036 kb
Host smart-50daffd6-d2f8-42bf-a75a-b7713b4c5dba
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242846547 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.2242846547
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.1453207403
Short name T727
Test name
Test status
Simulation time 15220729 ps
CPU time 0.75 seconds
Started Aug 05 06:24:07 PM PDT 24
Finished Aug 05 06:24:08 PM PDT 24
Peak memory 201084 kb
Host smart-f880fd57-2e7d-4c5a-a1bb-fbfb2497edf8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453207403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_clk_byp_req_intersig_mubi.1453207403
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.1020065787
Short name T281
Test name
Test status
Simulation time 112227428 ps
CPU time 1.15 seconds
Started Aug 05 06:24:10 PM PDT 24
Finished Aug 05 06:24:11 PM PDT 24
Peak memory 201088 kb
Host smart-81f6cd05-d9c5-4c46-98ac-a386c1770ba1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020065787 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.1020065787
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.1825092591
Short name T671
Test name
Test status
Simulation time 40904503 ps
CPU time 0.79 seconds
Started Aug 05 06:24:08 PM PDT 24
Finished Aug 05 06:24:08 PM PDT 24
Peak memory 201104 kb
Host smart-e3f774eb-6540-48c9-9cc5-2b489d7a5e4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825092591 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.1825092591
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.1889328044
Short name T792
Test name
Test status
Simulation time 182232554 ps
CPU time 1.64 seconds
Started Aug 05 06:24:15 PM PDT 24
Finished Aug 05 06:24:17 PM PDT 24
Peak memory 201116 kb
Host smart-d525f611-e46b-4ca4-8960-c7e108f50c53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889328044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1889328044
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.2963296901
Short name T196
Test name
Test status
Simulation time 22293519 ps
CPU time 0.88 seconds
Started Aug 05 06:24:09 PM PDT 24
Finished Aug 05 06:24:10 PM PDT 24
Peak memory 201072 kb
Host smart-5bf9cc4e-074d-458c-81d8-83e6031a6254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963296901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.2963296901
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.1202880424
Short name T350
Test name
Test status
Simulation time 2844333734 ps
CPU time 20.58 seconds
Started Aug 05 06:24:12 PM PDT 24
Finished Aug 05 06:24:33 PM PDT 24
Peak memory 201460 kb
Host smart-81abc83b-373c-4195-a235-33e99366cef9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202880424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.1202880424
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all_with_rand_reset.1178649792
Short name T616
Test name
Test status
Simulation time 17687898463 ps
CPU time 263.68 seconds
Started Aug 05 06:24:14 PM PDT 24
Finished Aug 05 06:28:37 PM PDT 24
Peak memory 215544 kb
Host smart-71a5b7dd-ce4f-4c1d-84fd-b6aede1803da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1178649792 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.1178649792
Directory /workspace/9.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.clkmgr_trans.3468492472
Short name T642
Test name
Test status
Simulation time 13345737 ps
CPU time 0.74 seconds
Started Aug 05 06:24:07 PM PDT 24
Finished Aug 05 06:24:08 PM PDT 24
Peak memory 201108 kb
Host smart-360b7e0b-7884-4d4e-89f4-7beabd016b59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468492472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.3468492472
Directory /workspace/9.clkmgr_trans/latest
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