Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143631652 1 T5 100076 T1 188449 T6 2840
auto[1] 260728 1 T1 1268 T6 668 T2 17104


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143597462 1 T5 100076 T1 188490 T6 3180
auto[1] 294918 1 T1 866 T6 328 T2 13340


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 143554732 1 T5 100076 T1 188469 T6 2676
auto[1] 337648 1 T1 1072 T6 832 T2 18068


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 132352468 1 T5 100076 T1 187805 T6 2012
auto[1] 11539912 1 T1 7716 T6 1496 T2 56084


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 93761054 1 T5 100052 T1 173642 T6 3478
auto[1] 50131326 1 T5 24 T1 149342 T6 30


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 83659664 1 T5 100052 T1 172951 T6 1488
auto[0] auto[0] auto[0] auto[0] auto[1] 48431732 1 T5 24 T1 148304 T6 30
auto[0] auto[0] auto[0] auto[1] auto[0] 18640 1 T6 50 T2 1290 T20 10
auto[0] auto[0] auto[0] auto[1] auto[1] 4866 1 T1 22 T2 374 T3 164
auto[0] auto[0] auto[1] auto[0] auto[0] 9688614 1 T1 5986 T6 970 T2 35642
auto[0] auto[0] auto[1] auto[0] auto[1] 1625734 1 T1 466 T2 3572 T18 194
auto[0] auto[0] auto[1] auto[1] auto[0] 29568 1 T1 112 T6 122 T2 2640
auto[0] auto[0] auto[1] auto[1] auto[1] 7988 1 T1 18 T2 630 T128 6
auto[0] auto[1] auto[0] auto[0] auto[0] 53376 1 T2 406 T3 120 T129 20
auto[0] auto[1] auto[0] auto[0] auto[1] 1328 1 T2 30 T18 8 T81 8
auto[0] auto[1] auto[0] auto[1] auto[0] 7410 1 T2 740 T3 74 T9 124
auto[0] auto[1] auto[0] auto[1] auto[1] 1946 1 T2 48 T174 56 T25 74
auto[0] auto[1] auto[1] auto[0] auto[0] 6728 1 T1 38 T6 16 T2 784
auto[0] auto[1] auto[1] auto[0] auto[1] 1698 1 T1 22 T2 80 T82 16
auto[0] auto[1] auto[1] auto[1] auto[0] 12160 1 T1 90 T2 870 T81 46
auto[0] auto[1] auto[1] auto[1] auto[1] 3280 1 T1 118 T2 62 T3 78
auto[1] auto[0] auto[0] auto[0] auto[0] 34816 1 T1 12 T6 44 T2 1170
auto[1] auto[0] auto[0] auto[0] auto[1] 2282 1 T1 10 T2 100 T81 8
auto[1] auto[0] auto[0] auto[1] auto[0] 21390 1 T6 214 T2 1568 T20 54
auto[1] auto[0] auto[0] auto[1] auto[1] 5460 1 T1 112 T2 166 T3 124
auto[1] auto[0] auto[1] auto[0] auto[0] 17614 1 T1 56 T6 160 T2 1472
auto[1] auto[0] auto[1] auto[0] auto[1] 5166 1 T1 6 T2 436 T81 18
auto[1] auto[0] auto[1] auto[1] auto[0] 34910 1 T1 196 T6 102 T2 2316
auto[1] auto[0] auto[1] auto[1] auto[1] 9018 1 T1 82 T2 520 T117 78
auto[1] auto[1] auto[0] auto[0] auto[0] 65188 1 T1 18 T6 70 T2 1232
auto[1] auto[1] auto[0] auto[0] auto[1] 3384 1 T1 10 T2 238 T18 10
auto[1] auto[1] auto[0] auto[1] auto[0] 33634 1 T6 116 T2 1298 T3 600
auto[1] auto[1] auto[0] auto[1] auto[1] 7352 1 T1 44 T2 492 T128 60
auto[1] auto[1] auto[1] auto[0] auto[0] 27272 1 T1 26 T6 62 T2 2300
auto[1] auto[1] auto[1] auto[0] auto[1] 7056 1 T1 26 T2 670 T18 8
auto[1] auto[1] auto[1] auto[1] auto[0] 50070 1 T1 372 T6 64 T2 3244
auto[1] auto[1] auto[1] auto[1] auto[1] 13036 1 T1 102 T2 846 T128 38

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