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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 979
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T802 /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2023984545 Aug 07 05:03:19 PM PDT 24 Aug 07 05:03:21 PM PDT 24 23994883 ps
T803 /workspace/coverage/default/21.clkmgr_extclk.53316027 Aug 07 05:02:57 PM PDT 24 Aug 07 05:02:58 PM PDT 24 28625876 ps
T804 /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1242777567 Aug 07 05:02:22 PM PDT 24 Aug 07 05:02:22 PM PDT 24 39154516 ps
T805 /workspace/coverage/default/47.clkmgr_peri.2265126922 Aug 07 05:03:58 PM PDT 24 Aug 07 05:03:59 PM PDT 24 15195674 ps
T806 /workspace/coverage/default/15.clkmgr_extclk.3723216638 Aug 07 05:03:59 PM PDT 24 Aug 07 05:04:00 PM PDT 24 41328924 ps
T807 /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3022329584 Aug 07 05:03:48 PM PDT 24 Aug 07 05:12:07 PM PDT 24 26925804589 ps
T808 /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2274128652 Aug 07 05:02:42 PM PDT 24 Aug 07 05:02:43 PM PDT 24 29204766 ps
T809 /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.264271596 Aug 07 05:03:02 PM PDT 24 Aug 07 05:03:03 PM PDT 24 52976267 ps
T810 /workspace/coverage/default/11.clkmgr_trans.3318987205 Aug 07 05:02:30 PM PDT 24 Aug 07 05:02:32 PM PDT 24 294015379 ps
T811 /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.911449040 Aug 07 05:02:43 PM PDT 24 Aug 07 05:02:44 PM PDT 24 25301640 ps
T812 /workspace/coverage/default/36.clkmgr_regwen.3844583405 Aug 07 05:03:25 PM PDT 24 Aug 07 05:03:29 PM PDT 24 676677327 ps
T813 /workspace/coverage/default/28.clkmgr_extclk.456363512 Aug 07 05:03:14 PM PDT 24 Aug 07 05:03:15 PM PDT 24 55284613 ps
T814 /workspace/coverage/default/48.clkmgr_peri.1275820969 Aug 07 05:03:46 PM PDT 24 Aug 07 05:03:47 PM PDT 24 23039120 ps
T815 /workspace/coverage/default/9.clkmgr_frequency_timeout.821028704 Aug 07 05:02:19 PM PDT 24 Aug 07 05:02:24 PM PDT 24 1035853843 ps
T816 /workspace/coverage/default/22.clkmgr_alert_test.1844707338 Aug 07 05:02:56 PM PDT 24 Aug 07 05:02:57 PM PDT 24 61846366 ps
T817 /workspace/coverage/default/17.clkmgr_smoke.1831671963 Aug 07 05:02:38 PM PDT 24 Aug 07 05:02:39 PM PDT 24 19644829 ps
T818 /workspace/coverage/default/16.clkmgr_smoke.1578958555 Aug 07 05:02:33 PM PDT 24 Aug 07 05:02:34 PM PDT 24 21528187 ps
T819 /workspace/coverage/default/42.clkmgr_frequency_timeout.906770414 Aug 07 05:03:47 PM PDT 24 Aug 07 05:03:55 PM PDT 24 2075211842 ps
T820 /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.2868728435 Aug 07 05:02:36 PM PDT 24 Aug 07 05:02:37 PM PDT 24 21804320 ps
T821 /workspace/coverage/default/26.clkmgr_smoke.3663843847 Aug 07 05:03:14 PM PDT 24 Aug 07 05:03:15 PM PDT 24 46666828 ps
T822 /workspace/coverage/default/48.clkmgr_div_intersig_mubi.4111789645 Aug 07 05:03:47 PM PDT 24 Aug 07 05:03:48 PM PDT 24 15365132 ps
T823 /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1093432595 Aug 07 05:02:58 PM PDT 24 Aug 07 05:02:58 PM PDT 24 14880943 ps
T824 /workspace/coverage/default/17.clkmgr_stress_all.283131450 Aug 07 05:02:38 PM PDT 24 Aug 07 05:03:03 PM PDT 24 3820615060 ps
T825 /workspace/coverage/default/27.clkmgr_clk_status.2075744265 Aug 07 05:03:04 PM PDT 24 Aug 07 05:03:05 PM PDT 24 13001715 ps
T826 /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3562649065 Aug 07 06:54:33 PM PDT 24 Aug 07 06:54:34 PM PDT 24 12341851 ps
T60 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4173876716 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:30 PM PDT 24 71968471 ps
T118 /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1127114813 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:53 PM PDT 24 38401948 ps
T827 /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2933220758 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:40 PM PDT 24 118414850 ps
T89 /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.152462198 Aug 07 06:54:35 PM PDT 24 Aug 07 06:54:36 PM PDT 24 16749860 ps
T196 /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3615248400 Aug 07 06:54:48 PM PDT 24 Aug 07 06:54:50 PM PDT 24 40251141 ps
T828 /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1464733478 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:08 PM PDT 24 22769350 ps
T197 /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1955906093 Aug 07 06:54:33 PM PDT 24 Aug 07 06:54:34 PM PDT 24 22940224 ps
T90 /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2876144787 Aug 07 06:54:46 PM PDT 24 Aug 07 06:54:48 PM PDT 24 127282297 ps
T91 /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1250372150 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:55 PM PDT 24 18494814 ps
T110 /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.751034867 Aug 07 06:55:09 PM PDT 24 Aug 07 06:55:13 PM PDT 24 586725706 ps
T92 /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4033111789 Aug 07 06:54:57 PM PDT 24 Aug 07 06:54:58 PM PDT 24 54699413 ps
T61 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.222458859 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:56 PM PDT 24 226682447 ps
T829 /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.342868438 Aug 07 06:55:14 PM PDT 24 Aug 07 06:55:15 PM PDT 24 18182343 ps
T830 /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3707975874 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:03 PM PDT 24 38428303 ps
T62 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3037511560 Aug 07 06:54:57 PM PDT 24 Aug 07 06:55:00 PM PDT 24 337932864 ps
T93 /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.707693556 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:36 PM PDT 24 153254599 ps
T831 /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.140136523 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:37 PM PDT 24 1014543403 ps
T832 /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3835490311 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:54 PM PDT 24 22951099 ps
T833 /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2712283764 Aug 07 06:55:13 PM PDT 24 Aug 07 06:55:14 PM PDT 24 17961300 ps
T65 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.555154362 Aug 07 06:54:29 PM PDT 24 Aug 07 06:54:32 PM PDT 24 260068633 ps
T834 /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3482260128 Aug 07 06:55:06 PM PDT 24 Aug 07 06:55:07 PM PDT 24 80952140 ps
T835 /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2869643474 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:49 PM PDT 24 129577811 ps
T836 /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3097212275 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:29 PM PDT 24 21350629 ps
T837 /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1799678627 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:53 PM PDT 24 11562718 ps
T94 /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1518192681 Aug 07 06:55:09 PM PDT 24 Aug 07 06:55:11 PM PDT 24 36878810 ps
T838 /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3477613211 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:44 PM PDT 24 57175942 ps
T63 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1380109820 Aug 07 06:54:39 PM PDT 24 Aug 07 06:54:42 PM PDT 24 428031016 ps
T839 /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.738559218 Aug 07 06:55:15 PM PDT 24 Aug 07 06:55:16 PM PDT 24 39274563 ps
T840 /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2833934724 Aug 07 06:55:12 PM PDT 24 Aug 07 06:55:13 PM PDT 24 11698937 ps
T841 /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2225332692 Aug 07 06:55:12 PM PDT 24 Aug 07 06:55:13 PM PDT 24 11743332 ps
T111 /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3504794396 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:40 PM PDT 24 77499854 ps
T842 /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.649849986 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:44 PM PDT 24 14070757 ps
T843 /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1794968366 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:03 PM PDT 24 12776724 ps
T844 /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.403853188 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:33 PM PDT 24 93363776 ps
T845 /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3260688088 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:04 PM PDT 24 36629323 ps
T66 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.375033110 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:52 PM PDT 24 188985975 ps
T846 /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3370602339 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:38 PM PDT 24 20519919 ps
T847 /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1085910256 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:34 PM PDT 24 19864983 ps
T848 /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.4083057133 Aug 07 06:54:42 PM PDT 24 Aug 07 06:54:44 PM PDT 24 191449262 ps
T112 /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3638007910 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:45 PM PDT 24 108318179 ps
T849 /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.349972405 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:30 PM PDT 24 88288679 ps
T850 /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3012528800 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:54 PM PDT 24 57386323 ps
T851 /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2059414477 Aug 07 06:54:57 PM PDT 24 Aug 07 06:55:01 PM PDT 24 532309906 ps
T852 /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3817760555 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:29 PM PDT 24 44780612 ps
T853 /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3071476133 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:55 PM PDT 24 33058688 ps
T854 /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2457910582 Aug 07 06:55:15 PM PDT 24 Aug 07 06:55:16 PM PDT 24 25560849 ps
T855 /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.154492303 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:56 PM PDT 24 72779593 ps
T856 /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3185887615 Aug 07 06:55:14 PM PDT 24 Aug 07 06:55:14 PM PDT 24 20573758 ps
T64 /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2195365798 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:29 PM PDT 24 157055884 ps
T120 /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.650660221 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:33 PM PDT 24 82171387 ps
T857 /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1480363931 Aug 07 06:55:05 PM PDT 24 Aug 07 06:55:06 PM PDT 24 24628835 ps
T67 /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.4182815800 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:29 PM PDT 24 122288188 ps
T858 /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1695958303 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:35 PM PDT 24 110084446 ps
T859 /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2110449696 Aug 07 06:54:58 PM PDT 24 Aug 07 06:54:58 PM PDT 24 38242565 ps
T123 /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.823427474 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:56 PM PDT 24 189850695 ps
T136 /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2232737621 Aug 07 06:54:36 PM PDT 24 Aug 07 06:54:38 PM PDT 24 253579279 ps
T860 /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.134922719 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:30 PM PDT 24 102422379 ps
T70 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.627570542 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:57 PM PDT 24 89695744 ps
T861 /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.310898269 Aug 07 06:55:13 PM PDT 24 Aug 07 06:55:14 PM PDT 24 15477769 ps
T862 /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2279297467 Aug 07 06:54:57 PM PDT 24 Aug 07 06:54:58 PM PDT 24 74347065 ps
T863 /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1030866166 Aug 07 06:54:36 PM PDT 24 Aug 07 06:54:37 PM PDT 24 26460129 ps
T864 /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3548317908 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:48 PM PDT 24 64194681 ps
T865 /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3349627016 Aug 07 06:55:08 PM PDT 24 Aug 07 06:55:09 PM PDT 24 113642982 ps
T866 /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3568146286 Aug 07 06:55:11 PM PDT 24 Aug 07 06:55:11 PM PDT 24 19200093 ps
T867 /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.778315790 Aug 07 06:54:48 PM PDT 24 Aug 07 06:54:49 PM PDT 24 127423609 ps
T68 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3385267178 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:04 PM PDT 24 261771621 ps
T868 /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3884142077 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:44 PM PDT 24 56232221 ps
T869 /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2088514825 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:48 PM PDT 24 39258571 ps
T870 /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1583403281 Aug 07 06:54:42 PM PDT 24 Aug 07 06:54:44 PM PDT 24 126050547 ps
T871 /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2346410776 Aug 07 06:54:29 PM PDT 24 Aug 07 06:54:30 PM PDT 24 43929412 ps
T872 /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3763435713 Aug 07 06:54:22 PM PDT 24 Aug 07 06:54:23 PM PDT 24 12013280 ps
T873 /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1225080402 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:08 PM PDT 24 18825133 ps
T874 /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1489558692 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:38 PM PDT 24 14041685 ps
T875 /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1608647754 Aug 07 06:55:00 PM PDT 24 Aug 07 06:55:02 PM PDT 24 253340353 ps
T69 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2134297706 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:10 PM PDT 24 432118944 ps
T876 /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1273361949 Aug 07 06:54:33 PM PDT 24 Aug 07 06:54:34 PM PDT 24 19440555 ps
T877 /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1727502728 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:36 PM PDT 24 31552495 ps
T121 /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2992514015 Aug 07 06:54:59 PM PDT 24 Aug 07 06:55:02 PM PDT 24 134911814 ps
T878 /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.72458384 Aug 07 06:55:12 PM PDT 24 Aug 07 06:55:13 PM PDT 24 13091741 ps
T879 /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3181087767 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:35 PM PDT 24 77592851 ps
T880 /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.256820094 Aug 07 06:55:15 PM PDT 24 Aug 07 06:55:15 PM PDT 24 12371237 ps
T881 /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4255609897 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:30 PM PDT 24 53975506 ps
T114 /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2267882808 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:50 PM PDT 24 113361475 ps
T139 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2058533178 Aug 07 06:54:42 PM PDT 24 Aug 07 06:54:44 PM PDT 24 76473686 ps
T882 /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1672786151 Aug 07 06:54:39 PM PDT 24 Aug 07 06:54:39 PM PDT 24 38837067 ps
T216 /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.926204106 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:37 PM PDT 24 190895235 ps
T883 /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3670567077 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:09 PM PDT 24 125214473 ps
T884 /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3109211954 Aug 07 06:54:51 PM PDT 24 Aug 07 06:54:52 PM PDT 24 18854481 ps
T885 /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2997931302 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:53 PM PDT 24 34476632 ps
T886 /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1514873226 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:39 PM PDT 24 98347153 ps
T887 /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2776837456 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:39 PM PDT 24 97364156 ps
T888 /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3800213126 Aug 07 06:54:26 PM PDT 24 Aug 07 06:54:28 PM PDT 24 68151761 ps
T71 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3376978265 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:35 PM PDT 24 405293024 ps
T72 /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3902434185 Aug 07 06:54:45 PM PDT 24 Aug 07 06:54:47 PM PDT 24 107841628 ps
T889 /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.291584230 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:44 PM PDT 24 17045377 ps
T890 /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3862071628 Aug 07 06:55:15 PM PDT 24 Aug 07 06:55:15 PM PDT 24 12264172 ps
T891 /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1204869803 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:08 PM PDT 24 18267700 ps
T141 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4128816147 Aug 07 06:54:22 PM PDT 24 Aug 07 06:54:25 PM PDT 24 181469352 ps
T892 /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.575473427 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:56 PM PDT 24 78399602 ps
T893 /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.118238266 Aug 07 06:55:01 PM PDT 24 Aug 07 06:55:02 PM PDT 24 28969771 ps
T147 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1868792346 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:52 PM PDT 24 62843267 ps
T894 /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4153242535 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:49 PM PDT 24 168369216 ps
T217 /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1457530255 Aug 07 06:54:51 PM PDT 24 Aug 07 06:54:53 PM PDT 24 96616032 ps
T895 /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.282489892 Aug 07 06:54:56 PM PDT 24 Aug 07 06:54:57 PM PDT 24 27309926 ps
T148 /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2330360815 Aug 07 06:54:33 PM PDT 24 Aug 07 06:54:35 PM PDT 24 104848680 ps
T115 /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2593264403 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:35 PM PDT 24 235205470 ps
T896 /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2059980941 Aug 07 06:54:46 PM PDT 24 Aug 07 06:54:47 PM PDT 24 33801848 ps
T142 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2923856390 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:04 PM PDT 24 115700564 ps
T897 /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1787651304 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:45 PM PDT 24 34623188 ps
T898 /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3204119192 Aug 07 06:54:45 PM PDT 24 Aug 07 06:54:47 PM PDT 24 29809880 ps
T899 /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.849063379 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:48 PM PDT 24 15125000 ps
T900 /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3549216528 Aug 07 06:55:03 PM PDT 24 Aug 07 06:55:05 PM PDT 24 111678724 ps
T901 /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3964950915 Aug 07 06:55:20 PM PDT 24 Aug 07 06:55:21 PM PDT 24 25615272 ps
T902 /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.232936512 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:36 PM PDT 24 104607800 ps
T903 /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.66278251 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:54 PM PDT 24 127658345 ps
T904 /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2677747476 Aug 07 06:55:14 PM PDT 24 Aug 07 06:55:15 PM PDT 24 79305621 ps
T905 /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2292675926 Aug 07 06:54:30 PM PDT 24 Aug 07 06:54:32 PM PDT 24 29751012 ps
T906 /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1408654135 Aug 07 06:54:57 PM PDT 24 Aug 07 06:54:58 PM PDT 24 49894128 ps
T907 /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1859072040 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:08 PM PDT 24 42700653 ps
T908 /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2091003532 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:36 PM PDT 24 330117797 ps
T909 /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2413247732 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:03 PM PDT 24 34916652 ps
T910 /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2924493941 Aug 07 06:55:13 PM PDT 24 Aug 07 06:55:14 PM PDT 24 31351814 ps
T911 /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1968298622 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:36 PM PDT 24 138046551 ps
T912 /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1357458363 Aug 07 06:55:06 PM PDT 24 Aug 07 06:55:08 PM PDT 24 81204615 ps
T913 /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1636846323 Aug 07 06:55:02 PM PDT 24 Aug 07 06:55:04 PM PDT 24 100681703 ps
T137 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2502563470 Aug 07 06:55:06 PM PDT 24 Aug 07 06:55:08 PM PDT 24 232937891 ps
T143 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3323724250 Aug 07 06:54:45 PM PDT 24 Aug 07 06:54:47 PM PDT 24 143577224 ps
T149 /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4272682367 Aug 07 06:54:42 PM PDT 24 Aug 07 06:54:44 PM PDT 24 141472582 ps
T914 /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1456051566 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:29 PM PDT 24 14715591 ps
T140 /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4118958396 Aug 07 06:55:03 PM PDT 24 Aug 07 06:55:05 PM PDT 24 95693156 ps
T915 /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.4048029893 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:52 PM PDT 24 33921995 ps
T116 /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.40815797 Aug 07 06:55:08 PM PDT 24 Aug 07 06:55:12 PM PDT 24 609477710 ps
T916 /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3361313031 Aug 07 06:54:32 PM PDT 24 Aug 07 06:54:40 PM PDT 24 422551204 ps
T917 /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2571703020 Aug 07 06:54:27 PM PDT 24 Aug 07 06:54:30 PM PDT 24 342717222 ps
T918 /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1839449434 Aug 07 06:54:43 PM PDT 24 Aug 07 06:54:44 PM PDT 24 50278004 ps
T919 /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.211078238 Aug 07 06:54:23 PM PDT 24 Aug 07 06:54:26 PM PDT 24 298240732 ps
T920 /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1475307683 Aug 07 06:54:59 PM PDT 24 Aug 07 06:55:00 PM PDT 24 34460074 ps
T921 /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1201613923 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:39 PM PDT 24 54778639 ps
T922 /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1263286628 Aug 07 06:55:11 PM PDT 24 Aug 07 06:55:12 PM PDT 24 11654220 ps
T150 /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2705751221 Aug 07 06:55:10 PM PDT 24 Aug 07 06:55:11 PM PDT 24 95114669 ps
T923 /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3190993827 Aug 07 06:55:14 PM PDT 24 Aug 07 06:55:15 PM PDT 24 13890420 ps
T924 /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3245359250 Aug 07 06:54:29 PM PDT 24 Aug 07 06:54:30 PM PDT 24 36238390 ps
T925 /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1287337988 Aug 07 06:54:57 PM PDT 24 Aug 07 06:54:58 PM PDT 24 78204919 ps
T926 /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3472697461 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:54 PM PDT 24 455835512 ps
T144 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3110109097 Aug 07 06:54:34 PM PDT 24 Aug 07 06:54:35 PM PDT 24 50623703 ps
T138 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2812679169 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:48 PM PDT 24 71034453 ps
T927 /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4204280003 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:40 PM PDT 24 64328760 ps
T928 /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1289424594 Aug 07 06:54:57 PM PDT 24 Aug 07 06:54:58 PM PDT 24 29706138 ps
T929 /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2098373453 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:54 PM PDT 24 202600880 ps
T930 /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3374405531 Aug 07 06:55:03 PM PDT 24 Aug 07 06:55:04 PM PDT 24 45041209 ps
T931 /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.777383372 Aug 07 06:55:09 PM PDT 24 Aug 07 06:55:10 PM PDT 24 73664619 ps
T932 /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3266665113 Aug 07 06:55:05 PM PDT 24 Aug 07 06:55:06 PM PDT 24 156278492 ps
T933 /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4046702196 Aug 07 06:54:24 PM PDT 24 Aug 07 06:54:26 PM PDT 24 134161411 ps
T934 /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2800007410 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:54 PM PDT 24 103886375 ps
T935 /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2742955660 Aug 07 06:55:13 PM PDT 24 Aug 07 06:55:14 PM PDT 24 33377009 ps
T936 /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3414280677 Aug 07 06:55:10 PM PDT 24 Aug 07 06:55:10 PM PDT 24 19956963 ps
T937 /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1161321670 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:57 PM PDT 24 490348498 ps
T938 /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3461254207 Aug 07 06:55:12 PM PDT 24 Aug 07 06:55:13 PM PDT 24 25400199 ps
T939 /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3735171626 Aug 07 06:55:10 PM PDT 24 Aug 07 06:55:14 PM PDT 24 162656516 ps
T940 /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2976464323 Aug 07 06:54:36 PM PDT 24 Aug 07 06:54:41 PM PDT 24 479609187 ps
T941 /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3048956554 Aug 07 06:55:11 PM PDT 24 Aug 07 06:55:12 PM PDT 24 19536293 ps
T942 /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.720005400 Aug 07 06:54:47 PM PDT 24 Aug 07 06:54:48 PM PDT 24 21932911 ps
T943 /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1459701391 Aug 07 06:54:33 PM PDT 24 Aug 07 06:54:34 PM PDT 24 42143266 ps
T944 /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.217670762 Aug 07 06:55:08 PM PDT 24 Aug 07 06:55:08 PM PDT 24 15101925 ps
T945 /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2199579001 Aug 07 06:54:48 PM PDT 24 Aug 07 06:54:50 PM PDT 24 50143731 ps
T946 /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1918786235 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:39 PM PDT 24 37970300 ps
T124 /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2118045759 Aug 07 06:54:42 PM PDT 24 Aug 07 06:54:44 PM PDT 24 315527289 ps
T947 /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2489567072 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:54 PM PDT 24 306135094 ps
T948 /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2890665577 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:52 PM PDT 24 219076498 ps
T949 /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2178534155 Aug 07 06:55:04 PM PDT 24 Aug 07 06:55:06 PM PDT 24 237687478 ps
T950 /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2273204263 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:38 PM PDT 24 23949757 ps
T951 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3471963104 Aug 07 06:55:01 PM PDT 24 Aug 07 06:55:03 PM PDT 24 151681272 ps
T952 /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1634016303 Aug 07 06:54:35 PM PDT 24 Aug 07 06:54:37 PM PDT 24 111299772 ps
T953 /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.277305379 Aug 07 06:54:28 PM PDT 24 Aug 07 06:54:45 PM PDT 24 4084830505 ps
T954 /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2439238194 Aug 07 06:55:20 PM PDT 24 Aug 07 06:55:21 PM PDT 24 12866689 ps
T955 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1418193485 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:41 PM PDT 24 304310018 ps
T956 /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4044130948 Aug 07 06:54:22 PM PDT 24 Aug 07 06:54:24 PM PDT 24 74108660 ps
T957 /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3561846610 Aug 07 06:54:52 PM PDT 24 Aug 07 06:54:54 PM PDT 24 138577426 ps
T958 /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3553830553 Aug 07 06:55:01 PM PDT 24 Aug 07 06:55:03 PM PDT 24 136420955 ps
T119 /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4149664263 Aug 07 06:54:53 PM PDT 24 Aug 07 06:54:54 PM PDT 24 59744299 ps
T959 /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2421559713 Aug 07 06:55:06 PM PDT 24 Aug 07 06:55:07 PM PDT 24 48585317 ps
T960 /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3398257802 Aug 07 06:54:40 PM PDT 24 Aug 07 06:54:45 PM PDT 24 481488035 ps
T961 /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.12930782 Aug 07 06:54:38 PM PDT 24 Aug 07 06:54:40 PM PDT 24 121364837 ps
T962 /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1169944205 Aug 07 06:54:26 PM PDT 24 Aug 07 06:54:27 PM PDT 24 30183045 ps
T963 /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1343168099 Aug 07 06:55:07 PM PDT 24 Aug 07 06:55:08 PM PDT 24 67240191 ps
T122 /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2812653427 Aug 07 06:54:59 PM PDT 24 Aug 07 06:55:02 PM PDT 24 287963527 ps
T964 /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.544411691 Aug 07 06:55:19 PM PDT 24 Aug 07 06:55:20 PM PDT 24 28265563 ps
T145 /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2320487307 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:38 PM PDT 24 46826105 ps
T965 /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2787359719 Aug 07 06:55:00 PM PDT 24 Aug 07 06:55:02 PM PDT 24 67476841 ps
T966 /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1383638852 Aug 07 06:54:37 PM PDT 24 Aug 07 06:54:40 PM PDT 24 233387708 ps
T146 /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1923477457 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:53 PM PDT 24 263488289 ps
T967 /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1015489967 Aug 07 06:55:15 PM PDT 24 Aug 07 06:55:16 PM PDT 24 20189787 ps
T968 /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.4009325465 Aug 07 06:54:50 PM PDT 24 Aug 07 06:54:52 PM PDT 24 121967411 ps
T969 /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3569882399 Aug 07 06:54:59 PM PDT 24 Aug 07 06:55:01 PM PDT 24 120987463 ps
T970 /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4104346574 Aug 07 06:54:57 PM PDT 24 Aug 07 06:55:02 PM PDT 24 998221242 ps
T971 /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1466060751 Aug 07 06:54:36 PM PDT 24 Aug 07 06:54:37 PM PDT 24 41630061 ps
T972 /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1250065021 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:54 PM PDT 24 12627341 ps
T973 /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1775048652 Aug 07 06:54:58 PM PDT 24 Aug 07 06:54:59 PM PDT 24 28515594 ps
T974 /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2476176463 Aug 07 06:55:14 PM PDT 24 Aug 07 06:55:15 PM PDT 24 38293965 ps
T975 /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2961104908 Aug 07 06:55:20 PM PDT 24 Aug 07 06:55:21 PM PDT 24 30969661 ps
T976 /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1120480877 Aug 07 06:55:12 PM PDT 24 Aug 07 06:55:13 PM PDT 24 39273888 ps
T977 /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2247885157 Aug 07 06:55:09 PM PDT 24 Aug 07 06:55:10 PM PDT 24 40217559 ps
T978 /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3123315597 Aug 07 06:54:29 PM PDT 24 Aug 07 06:54:30 PM PDT 24 77321009 ps
T979 /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1598603429 Aug 07 06:54:54 PM PDT 24 Aug 07 06:54:55 PM PDT 24 53209992 ps

Test location /workspace/coverage/default/35.clkmgr_stress_all_with_rand_reset.140204476
Short name T2
Test name
Test status
Simulation time 94667386874 ps
CPU time 884.63 seconds
Started Aug 07 05:03:22 PM PDT 24
Finished Aug 07 05:18:07 PM PDT 24
Peak memory 217956 kb
Host smart-0f986c89-c4a6-4e11-94f3-df7102c3a97d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=140204476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.140204476
Directory /workspace/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.clkmgr_frequency_timeout.163252289
Short name T28
Test name
Test status
Simulation time 2205677298 ps
CPU time 9.08 seconds
Started Aug 07 05:03:54 PM PDT 24
Finished Aug 07 05:04:03 PM PDT 24
Peak memory 201388 kb
Host smart-2b039eec-34ba-44c9-812f-52257d37eb35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163252289 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_ti
meout.163252289
Directory /workspace/48.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3037511560
Short name T62
Test name
Test status
Simulation time 337932864 ps
CPU time 2.96 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:55:00 PM PDT 24
Peak memory 209124 kb
Host smart-cf0a1179-7ab6-4520-908f-7181a77069e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037511560 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.3037511560
Directory /workspace/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.clkmgr_regwen.3367480670
Short name T4
Test name
Test status
Simulation time 1274539877 ps
CPU time 6.64 seconds
Started Aug 07 05:03:12 PM PDT 24
Finished Aug 07 05:03:18 PM PDT 24
Peak memory 201312 kb
Host smart-999c66b7-bd96-48f0-82cb-fd60341f29c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367480670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.3367480670
Directory /workspace/24.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_clk_status.4253523977
Short name T170
Test name
Test status
Simulation time 21478326 ps
CPU time 0.72 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201052 kb
Host smart-d01efb09-6598-425c-acb3-42b70bf0cb9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253523977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.4253523977
Directory /workspace/11.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_sec_cm.3444207553
Short name T49
Test name
Test status
Simulation time 663125747 ps
CPU time 3.37 seconds
Started Aug 07 05:02:11 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 220548 kb
Host smart-4d4f60c3-c2c6-42d8-83d6-01a926842a24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444207553 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmg
r_sec_cm.3444207553
Directory /workspace/3.clkmgr_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.375033110
Short name T66
Test name
Test status
Simulation time 188985975 ps
CPU time 1.69 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 200692 kb
Host smart-0aa437f5-ded6-4577-85c6-25d5d2aa3d49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375033110 -assert nopostproc +UVM_TESTNAME=clkmgr_base
_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.clkmgr_shadow_reg_errors.375033110
Directory /workspace/11.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.clkmgr_stress_all.2779385371
Short name T1
Test name
Test status
Simulation time 9729441535 ps
CPU time 71.07 seconds
Started Aug 07 05:03:28 PM PDT 24
Finished Aug 07 05:04:39 PM PDT 24
Peak memory 201424 kb
Host smart-aee8c70e-82a8-4c7f-a073-5070e67d4ff5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779385371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_stress_all.2779385371
Directory /workspace/37.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_idle_intersig_mubi.4209657205
Short name T245
Test name
Test status
Simulation time 42432481 ps
CPU time 0.97 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 201000 kb
Host smart-baae808b-1488-469e-91b5-e8e9f768cbfc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209657205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_idle_intersig_mubi.4209657205
Directory /workspace/0.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_intg_err.823427474
Short name T123
Test name
Test status
Simulation time 189850695 ps
CPU time 2.92 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:56 PM PDT 24
Peak memory 200568 kb
Host smart-8b930555-ec60-4a2d-baeb-8aea74a0122d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823427474 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.clkmgr_tl_intg_err.823427474
Directory /workspace/13.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.clkmgr_sec_cm.1224982022
Short name T38
Test name
Test status
Simulation time 569608066 ps
CPU time 5.34 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:04 PM PDT 24
Peak memory 217852 kb
Host smart-08e068c2-a059-48c3-912c-b09b2f781c98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224982022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmg
r_sec_cm.1224982022
Directory /workspace/1.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/13.clkmgr_alert_test.3268382244
Short name T30
Test name
Test status
Simulation time 21023427 ps
CPU time 0.76 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201068 kb
Host smart-cece204c-c268-425e-8c78-eb056a9d2949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268382244 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clk
mgr_alert_test.3268382244
Directory /workspace/13.clkmgr_alert_test/latest

Test location /workspace/coverage/default/13.clkmgr_regwen.2180245603
Short name T7
Test name
Test status
Simulation time 651563858 ps
CPU time 3.57 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 201256 kb
Host smart-19112d6b-b4c1-483a-a17e-0734a2b7a94a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180245603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.2180245603
Directory /workspace/13.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.82657519
Short name T87
Test name
Test status
Simulation time 60077964 ps
CPU time 0.99 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201048 kb
Host smart-27ea7145-c896-4bcb-bfa7-6b8a9c235255
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82657519 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
2.clkmgr_clk_handshake_intersig_mubi.82657519
Directory /workspace/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_rw.152462198
Short name T89
Test name
Test status
Simulation time 16749860 ps
CPU time 0.79 seconds
Started Aug 07 06:54:35 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200308 kb
Host smart-abf02afe-593a-4d0f-b88f-2bdfbc57a797
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152462198 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.c
lkmgr_csr_rw.152462198
Directory /workspace/1.clkmgr_csr_rw/latest

Test location /workspace/coverage/default/23.clkmgr_stress_all.4031794407
Short name T152
Test name
Test status
Simulation time 8279124420 ps
CPU time 43.65 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:03:39 PM PDT 24
Peak memory 201432 kb
Host smart-d33746b3-ecf4-45ee-893e-87316686e9ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031794407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_stress_all.4031794407
Directory /workspace/23.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.4128816147
Short name T141
Test name
Test status
Simulation time 181469352 ps
CPU time 2.05 seconds
Started Aug 07 06:54:22 PM PDT 24
Finished Aug 07 06:54:25 PM PDT 24
Peak memory 200872 kb
Host smart-1ae76d90-bb6d-43ea-bdec-2ebeaa69e84c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128816147 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 0.clkmgr_shadow_reg_errors.4128816147
Directory /workspace/0.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.clkmgr_div_intersig_mubi.3580146444
Short name T131
Test name
Test status
Simulation time 37817905 ps
CPU time 0.81 seconds
Started Aug 07 05:02:05 PM PDT 24
Finished Aug 07 05:02:06 PM PDT 24
Peak memory 201084 kb
Host smart-05ef663f-f8af-482b-8f98-bd66ef8e6b5d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580146444 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_div_intersig_mubi.3580146444
Directory /workspace/1.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_regwen.1833850113
Short name T183
Test name
Test status
Simulation time 920410025 ps
CPU time 3.87 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 201264 kb
Host smart-f9c4e27b-4a9c-4ba8-bb3a-88fb37e6a161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833850113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_regwen.1833850113
Directory /workspace/39.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.3145668181
Short name T102
Test name
Test status
Simulation time 24725500 ps
CPU time 0.88 seconds
Started Aug 07 05:02:53 PM PDT 24
Finished Aug 07 05:02:54 PM PDT 24
Peak memory 201104 kb
Host smart-2210d317-fbf8-4337-9f5c-2aa2850407e5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145668181 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_clk_handshake_intersig_mubi.3145668181
Directory /workspace/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.2320487307
Short name T145
Test name
Test status
Simulation time 46826105 ps
CPU time 1.17 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 200728 kb
Host smart-50185fe9-519a-40f3-9a60-53c68366c836
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320487307 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 6.clkmgr_shadow_reg_errors.2320487307
Directory /workspace/6.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_intg_err.2992514015
Short name T121
Test name
Test status
Simulation time 134911814 ps
CPU time 2.37 seconds
Started Aug 07 06:54:59 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 200636 kb
Host smart-36a46a8b-407c-43d7-9aa0-5a58049c08b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992514015 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.clkmgr_tl_intg_err.2992514015
Directory /workspace/14.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.2195365798
Short name T64
Test name
Test status
Simulation time 157055884 ps
CPU time 1.4 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:29 PM PDT 24
Peak memory 200608 kb
Host smart-0de5a5be-2fa6-4252-af41-d3f70c49a64d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195365798 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 1.clkmgr_shadow_reg_errors.2195365798
Directory /workspace/1.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_intg_err.40815797
Short name T116
Test name
Test status
Simulation time 609477710 ps
CPU time 3.64 seconds
Started Aug 07 06:55:08 PM PDT 24
Finished Aug 07 06:55:12 PM PDT 24
Peak memory 200664 kb
Host smart-23777f8c-25aa-401e-8689-4b6a9e5aa280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40815797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.clkmgr_tl_intg_err.40815797
Directory /workspace/18.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.clkmgr_stress_all.574087448
Short name T33
Test name
Test status
Simulation time 7433633544 ps
CPU time 30.27 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:04:02 PM PDT 24
Peak memory 201444 kb
Host smart-52c79374-76fa-411a-b5ee-e2f7237238d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574087448 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_stress_all.574087448
Directory /workspace/41.clkmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_aliasing.2571703020
Short name T917
Test name
Test status
Simulation time 342717222 ps
CPU time 2.19 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200640 kb
Host smart-eb5449b3-bc73-4275-9f79-38510d6e02c0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571703020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_aliasing.2571703020
Directory /workspace/0.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.140136523
Short name T831
Test name
Test status
Simulation time 1014543403 ps
CPU time 9.35 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:37 PM PDT 24
Peak memory 200528 kb
Host smart-e8ef9173-5f4a-4fed-bc55-23c60456c807
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140136523 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_csr_bit_bash.140136523
Directory /workspace/0.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.1456051566
Short name T914
Test name
Test status
Simulation time 14715591 ps
CPU time 0.75 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:29 PM PDT 24
Peak memory 200396 kb
Host smart-6d576f20-7810-4e4b-a9e2-0902ece0ff05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456051566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.clkmgr_csr_hw_reset.1456051566
Directory /workspace/0.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.3097212275
Short name T836
Test name
Test status
Simulation time 21350629 ps
CPU time 1.03 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:29 PM PDT 24
Peak memory 200508 kb
Host smart-65bf12b2-326b-49a3-bb3c-6073edbe6d9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097212275 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.3097212275
Directory /workspace/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_csr_rw.3817760555
Short name T852
Test name
Test status
Simulation time 44780612 ps
CPU time 0.8 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:29 PM PDT 24
Peak memory 200352 kb
Host smart-c56e97f3-5f61-46d5-9f75-272175a4aa73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817760555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
clkmgr_csr_rw.3817760555
Directory /workspace/0.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_intr_test.3763435713
Short name T872
Test name
Test status
Simulation time 12013280 ps
CPU time 0.66 seconds
Started Aug 07 06:54:22 PM PDT 24
Finished Aug 07 06:54:23 PM PDT 24
Peak memory 198928 kb
Host smart-1d0152ab-a2e1-4408-bb49-1868a30bfc0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763435713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_intr_test.3763435713
Directory /workspace/0.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.3245359250
Short name T924
Test name
Test status
Simulation time 36238390 ps
CPU time 1.27 seconds
Started Aug 07 06:54:29 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200604 kb
Host smart-8b591ed8-8c3d-4d28-93eb-04c5a8cb6dae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245359250 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.clkmgr_same_csr_outstanding.3245359250
Directory /workspace/0.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.4046702196
Short name T933
Test name
Test status
Simulation time 134161411 ps
CPU time 2.02 seconds
Started Aug 07 06:54:24 PM PDT 24
Finished Aug 07 06:54:26 PM PDT 24
Peak memory 209052 kb
Host smart-85dfdbb9-da92-4f96-905f-dcb52bef8a4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046702196 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.4046702196
Directory /workspace/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_errors.4044130948
Short name T956
Test name
Test status
Simulation time 74108660 ps
CPU time 2.06 seconds
Started Aug 07 06:54:22 PM PDT 24
Finished Aug 07 06:54:24 PM PDT 24
Peak memory 200616 kb
Host smart-8508dfa0-deba-4e40-9107-b5962bb5b076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044130948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clk
mgr_tl_errors.4044130948
Directory /workspace/0.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.clkmgr_tl_intg_err.211078238
Short name T919
Test name
Test status
Simulation time 298240732 ps
CPU time 3.1 seconds
Started Aug 07 06:54:23 PM PDT 24
Finished Aug 07 06:54:26 PM PDT 24
Peak memory 200612 kb
Host smart-8674d901-bdf6-4523-88a0-80e6547a3c64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211078238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_tl_intg_err.211078238
Directory /workspace/0.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_aliasing.3800213126
Short name T888
Test name
Test status
Simulation time 68151761 ps
CPU time 1.86 seconds
Started Aug 07 06:54:26 PM PDT 24
Finished Aug 07 06:54:28 PM PDT 24
Peak memory 200668 kb
Host smart-a4f18b85-fbcb-4213-88fb-54f789350440
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800213126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_aliasing.3800213126
Directory /workspace/1.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.277305379
Short name T953
Test name
Test status
Simulation time 4084830505 ps
CPU time 16.87 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:45 PM PDT 24
Peak memory 200664 kb
Host smart-85e05365-2c70-491e-88b1-421240e33d62
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277305379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_csr_bit_bash.277305379
Directory /workspace/1.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.2346410776
Short name T871
Test name
Test status
Simulation time 43929412 ps
CPU time 0.82 seconds
Started Aug 07 06:54:29 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200272 kb
Host smart-00adeb64-c7fe-4bb8-9ebe-a32447c544f1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346410776 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.clkmgr_csr_hw_reset.2346410776
Directory /workspace/1.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.134922719
Short name T860
Test name
Test status
Simulation time 102422379 ps
CPU time 1.12 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200508 kb
Host smart-91815128-eca7-4236-9558-39f28a2129ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134922719 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.134922719
Directory /workspace/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_intr_test.1169944205
Short name T962
Test name
Test status
Simulation time 30183045 ps
CPU time 0.69 seconds
Started Aug 07 06:54:26 PM PDT 24
Finished Aug 07 06:54:27 PM PDT 24
Peak memory 199012 kb
Host smart-b66bbef9-0612-47b5-b24b-90ce89d3bc5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169944205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_intr_test.1169944205
Directory /workspace/1.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.4255609897
Short name T881
Test name
Test status
Simulation time 53975506 ps
CPU time 1.09 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200456 kb
Host smart-39440cb0-9b91-43c6-ad03-a31a6e25fd60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255609897 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.clkmgr_same_csr_outstanding.4255609897
Directory /workspace/1.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.555154362
Short name T65
Test name
Test status
Simulation time 260068633 ps
CPU time 2.85 seconds
Started Aug 07 06:54:29 PM PDT 24
Finished Aug 07 06:54:32 PM PDT 24
Peak memory 201188 kb
Host smart-848ebe10-5d43-4288-b525-d0bc949701c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555154362 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.555154362
Directory /workspace/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_errors.2292675926
Short name T905
Test name
Test status
Simulation time 29751012 ps
CPU time 1.55 seconds
Started Aug 07 06:54:30 PM PDT 24
Finished Aug 07 06:54:32 PM PDT 24
Peak memory 200624 kb
Host smart-29696255-ba2a-4a36-a137-f2cb858998a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292675926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clk
mgr_tl_errors.2292675926
Directory /workspace/1.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.clkmgr_tl_intg_err.3123315597
Short name T978
Test name
Test status
Simulation time 77321009 ps
CPU time 1.75 seconds
Started Aug 07 06:54:29 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200596 kb
Host smart-c566fb5c-ec9b-4d77-9545-374e0c90e5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123315597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.clkmgr_tl_intg_err.3123315597
Directory /workspace/1.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2869643474
Short name T835
Test name
Test status
Simulation time 129577811 ps
CPU time 1.54 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:49 PM PDT 24
Peak memory 200484 kb
Host smart-0bb66768-0922-4ae6-bc72-f503e3117b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869643474 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_mem_rw_with_rand_reset.2869643474
Directory /workspace/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_csr_rw.3109211954
Short name T884
Test name
Test status
Simulation time 18854481 ps
CPU time 0.83 seconds
Started Aug 07 06:54:51 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 199380 kb
Host smart-d76df24e-580b-4d85-a68c-bea341085bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109211954 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.clkmgr_csr_rw.3109211954
Directory /workspace/10.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_intr_test.849063379
Short name T899
Test name
Test status
Simulation time 15125000 ps
CPU time 0.69 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 199000 kb
Host smart-6e125113-3cba-45a2-a406-ff6411c8fca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849063379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clk
mgr_intr_test.849063379
Directory /workspace/10.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.2997931302
Short name T885
Test name
Test status
Simulation time 34476632 ps
CPU time 1.06 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:53 PM PDT 24
Peak memory 200392 kb
Host smart-aef466eb-435c-4398-bbb3-00a142f95ba0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997931302 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 10.clkmgr_same_csr_outstanding.2997931302
Directory /workspace/10.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2890665577
Short name T948
Test name
Test status
Simulation time 219076498 ps
CPU time 1.79 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 200688 kb
Host smart-7c179b3f-2642-4bb9-9e7b-6987c5a0553b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890665577 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 10.clkmgr_shadow_reg_errors.2890665577
Directory /workspace/10.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.1868792346
Short name T147
Test name
Test status
Simulation time 62843267 ps
CPU time 1.54 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 199816 kb
Host smart-e400775c-6132-4a70-a138-546196b90a96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868792346 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.1868792346
Directory /workspace/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_errors.4009325465
Short name T968
Test name
Test status
Simulation time 121967411 ps
CPU time 1.68 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 200148 kb
Host smart-d8c18d87-1c1c-4f95-aee2-1535787a366a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009325465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.cl
kmgr_tl_errors.4009325465
Directory /workspace/10.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1457530255
Short name T217
Test name
Test status
Simulation time 96616032 ps
CPU time 2.39 seconds
Started Aug 07 06:54:51 PM PDT 24
Finished Aug 07 06:54:53 PM PDT 24
Peak memory 199592 kb
Host smart-db36bd95-414a-4df3-9fd2-075812184987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457530255 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.clkmgr_tl_intg_err.1457530255
Directory /workspace/10.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.3835490311
Short name T832
Test name
Test status
Simulation time 22951099 ps
CPU time 1.14 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200480 kb
Host smart-9f5800c9-c8e6-4f04-b109-690e4d790692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835490311 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_mem_rw_with_rand_reset.3835490311
Directory /workspace/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_csr_rw.1598603429
Short name T979
Test name
Test status
Simulation time 53209992 ps
CPU time 0.87 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:55 PM PDT 24
Peak memory 200396 kb
Host smart-f31479e9-6863-4d45-a6ed-ff30e92aa9b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598603429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.clkmgr_csr_rw.1598603429
Directory /workspace/11.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_intr_test.1250065021
Short name T972
Test name
Test status
Simulation time 12627341 ps
CPU time 0.74 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 199104 kb
Host smart-472e1805-faa3-4759-a371-de8bd3282e6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250065021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_intr_test.1250065021
Directory /workspace/11.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2489567072
Short name T947
Test name
Test status
Simulation time 306135094 ps
CPU time 2.04 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200556 kb
Host smart-377d194c-07e6-4dbb-adb5-d866a742e8c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489567072 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 11.clkmgr_same_csr_outstanding.2489567072
Directory /workspace/11.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3472697461
Short name T926
Test name
Test status
Simulation time 455835512 ps
CPU time 3.58 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 209124 kb
Host smart-80a16fa8-a98e-44d0-85d3-5ed739c6be5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472697461 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.3472697461
Directory /workspace/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_errors.4048029893
Short name T915
Test name
Test status
Simulation time 33921995 ps
CPU time 1.89 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:52 PM PDT 24
Peak memory 200564 kb
Host smart-0420f02e-03a2-4b04-a5e0-d82a02260e8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048029893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.cl
kmgr_tl_errors.4048029893
Directory /workspace/11.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.clkmgr_tl_intg_err.4149664263
Short name T119
Test name
Test status
Simulation time 59744299 ps
CPU time 1.56 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200588 kb
Host smart-c1e60230-fc6c-491a-ac2d-3deb622c092f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149664263 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.clkmgr_tl_intg_err.4149664263
Directory /workspace/11.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.1127114813
Short name T118
Test name
Test status
Simulation time 38401948 ps
CPU time 1.33 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:53 PM PDT 24
Peak memory 200520 kb
Host smart-612299b2-7158-438a-adc8-2e2830acaec5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127114813 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_mem_rw_with_rand_reset.1127114813
Directory /workspace/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_csr_rw.3012528800
Short name T850
Test name
Test status
Simulation time 57386323 ps
CPU time 0.86 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200400 kb
Host smart-34bb62be-922b-4bc2-b44e-fb7d75e7e775
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012528800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.clkmgr_csr_rw.3012528800
Directory /workspace/12.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_intr_test.1799678627
Short name T837
Test name
Test status
Simulation time 11562718 ps
CPU time 0.67 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:53 PM PDT 24
Peak memory 199016 kb
Host smart-feb39e77-8f91-4083-9780-2ea6296a3315
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799678627 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_intr_test.1799678627
Directory /workspace/12.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.3561846610
Short name T957
Test name
Test status
Simulation time 138577426 ps
CPU time 1.37 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200452 kb
Host smart-76ff97c6-a1f9-49d3-bbd5-cc81cf0ec03b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561846610 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 12.clkmgr_same_csr_outstanding.3561846610
Directory /workspace/12.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2098373453
Short name T929
Test name
Test status
Simulation time 202600880 ps
CPU time 1.41 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200704 kb
Host smart-f9e08db1-5d33-4fe6-86ad-1db2073f143f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098373453 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 12.clkmgr_shadow_reg_errors.2098373453
Directory /workspace/12.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.627570542
Short name T70
Test name
Test status
Simulation time 89695744 ps
CPU time 2.38 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:57 PM PDT 24
Peak memory 209008 kb
Host smart-60c915b7-126d-4eeb-9710-aa87dceb9457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627570542 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.627570542
Directory /workspace/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_errors.1161321670
Short name T937
Test name
Test status
Simulation time 490348498 ps
CPU time 4 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:57 PM PDT 24
Peak memory 200608 kb
Host smart-001cb16c-8ae3-4e19-b8ed-af10e7681798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161321670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.cl
kmgr_tl_errors.1161321670
Directory /workspace/12.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.clkmgr_tl_intg_err.66278251
Short name T903
Test name
Test status
Simulation time 127658345 ps
CPU time 1.73 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200616 kb
Host smart-1e41e7b0-d735-46e5-b197-605bb96069b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66278251 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.clkmgr_tl_intg_err.66278251
Directory /workspace/12.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.282489892
Short name T895
Test name
Test status
Simulation time 27309926 ps
CPU time 1.24 seconds
Started Aug 07 06:54:56 PM PDT 24
Finished Aug 07 06:54:57 PM PDT 24
Peak memory 200436 kb
Host smart-d02affee-5da6-44ea-8944-6026dff6ea5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282489892 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_mem_rw_with_rand_reset.282489892
Directory /workspace/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_csr_rw.1250372150
Short name T91
Test name
Test status
Simulation time 18494814 ps
CPU time 0.87 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:55 PM PDT 24
Peak memory 200480 kb
Host smart-de82adda-f179-4c71-b564-6f6fe526b81b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250372150 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.clkmgr_csr_rw.1250372150
Directory /workspace/13.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_intr_test.3071476133
Short name T853
Test name
Test status
Simulation time 33058688 ps
CPU time 0.7 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:55 PM PDT 24
Peak memory 199008 kb
Host smart-5089efeb-73d9-4559-9f6e-48f8ee45f5bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071476133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.cl
kmgr_intr_test.3071476133
Directory /workspace/13.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.575473427
Short name T892
Test name
Test status
Simulation time 78399602 ps
CPU time 1.31 seconds
Started Aug 07 06:54:54 PM PDT 24
Finished Aug 07 06:54:56 PM PDT 24
Peak memory 200572 kb
Host smart-c43d7b79-22a2-4e6d-a96e-0e135faaff2d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575473427 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 13.clkmgr_same_csr_outstanding.575473427
Directory /workspace/13.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.2787359719
Short name T965
Test name
Test status
Simulation time 67476841 ps
CPU time 1.3 seconds
Started Aug 07 06:55:00 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 199648 kb
Host smart-7ebe21a8-e064-41d8-9b98-ebf609463a81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787359719 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 13.clkmgr_shadow_reg_errors.2787359719
Directory /workspace/13.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.222458859
Short name T61
Test name
Test status
Simulation time 226682447 ps
CPU time 3.16 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:56 PM PDT 24
Peak memory 209068 kb
Host smart-211fa161-40cf-4068-bfc7-b50f99f81110
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222458859 -assert nopostproc +UVM_TESTNAME
=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.222458859
Directory /workspace/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.clkmgr_tl_errors.154492303
Short name T855
Test name
Test status
Simulation time 72779593 ps
CPU time 2.46 seconds
Started Aug 07 06:54:53 PM PDT 24
Finished Aug 07 06:54:56 PM PDT 24
Peak memory 200576 kb
Host smart-47e2be72-e17d-41de-91d9-a8849e93d4db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154492303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clk
mgr_tl_errors.154492303
Directory /workspace/13.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.1289424594
Short name T928
Test name
Test status
Simulation time 29706138 ps
CPU time 1.13 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 200512 kb
Host smart-808ec341-3bb3-4920-acfe-75618892238e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289424594 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_mem_rw_with_rand_reset.1289424594
Directory /workspace/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_csr_rw.1408654135
Short name T906
Test name
Test status
Simulation time 49894128 ps
CPU time 0.9 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 200404 kb
Host smart-96c6c68a-fa96-486f-8ec4-904ddb52f723
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408654135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.clkmgr_csr_rw.1408654135
Directory /workspace/14.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_intr_test.2110449696
Short name T859
Test name
Test status
Simulation time 38242565 ps
CPU time 0.72 seconds
Started Aug 07 06:54:58 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 199004 kb
Host smart-a3261c8f-31ab-4315-91f0-84849ad0ef5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110449696 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_intr_test.2110449696
Directory /workspace/14.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.1287337988
Short name T925
Test name
Test status
Simulation time 78204919 ps
CPU time 1.05 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 200436 kb
Host smart-f4bf3e8f-6242-43ba-8183-73d1aef7b9c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287337988 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 14.clkmgr_same_csr_outstanding.1287337988
Directory /workspace/14.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.3471963104
Short name T951
Test name
Test status
Simulation time 151681272 ps
CPU time 1.44 seconds
Started Aug 07 06:55:01 PM PDT 24
Finished Aug 07 06:55:03 PM PDT 24
Peak memory 200676 kb
Host smart-a0a10f52-047e-4f04-8d95-5a2582ce9ac7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471963104 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 14.clkmgr_shadow_reg_errors.3471963104
Directory /workspace/14.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4104346574
Short name T970
Test name
Test status
Simulation time 998221242 ps
CPU time 5.11 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 217152 kb
Host smart-47d0d89a-5717-4ef4-877f-99f9d02eee57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104346574 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.4104346574
Directory /workspace/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.clkmgr_tl_errors.2059414477
Short name T851
Test name
Test status
Simulation time 532309906 ps
CPU time 4.09 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:55:01 PM PDT 24
Peak memory 200684 kb
Host smart-06f74324-1659-4b1e-bbd9-b127e7f098ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059414477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.cl
kmgr_tl_errors.2059414477
Directory /workspace/14.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.1775048652
Short name T973
Test name
Test status
Simulation time 28515594 ps
CPU time 0.96 seconds
Started Aug 07 06:54:58 PM PDT 24
Finished Aug 07 06:54:59 PM PDT 24
Peak memory 200380 kb
Host smart-c91e0caf-6249-47a0-ad01-926a73e293f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775048652 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_mem_rw_with_rand_reset.1775048652
Directory /workspace/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_csr_rw.1475307683
Short name T920
Test name
Test status
Simulation time 34460074 ps
CPU time 0.77 seconds
Started Aug 07 06:54:59 PM PDT 24
Finished Aug 07 06:55:00 PM PDT 24
Peak memory 200284 kb
Host smart-9a7f4db7-5fcf-484e-b9fd-97adc795193d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475307683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.clkmgr_csr_rw.1475307683
Directory /workspace/15.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_intr_test.2279297467
Short name T862
Test name
Test status
Simulation time 74347065 ps
CPU time 0.8 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 199008 kb
Host smart-ae837a23-55b0-4b70-bbcf-d1c2ddcb997b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279297467 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_intr_test.2279297467
Directory /workspace/15.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.4033111789
Short name T92
Test name
Test status
Simulation time 54699413 ps
CPU time 1.08 seconds
Started Aug 07 06:54:57 PM PDT 24
Finished Aug 07 06:54:58 PM PDT 24
Peak memory 200428 kb
Host smart-811da4a1-8826-4837-8695-222d9ac53a1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033111789 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 15.clkmgr_same_csr_outstanding.4033111789
Directory /workspace/15.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.3569882399
Short name T969
Test name
Test status
Simulation time 120987463 ps
CPU time 1.41 seconds
Started Aug 07 06:54:59 PM PDT 24
Finished Aug 07 06:55:01 PM PDT 24
Peak memory 200660 kb
Host smart-cbb4f04b-6fdc-4506-8c73-322439081376
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569882399 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 15.clkmgr_shadow_reg_errors.3569882399
Directory /workspace/15.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_errors.1608647754
Short name T875
Test name
Test status
Simulation time 253340353 ps
CPU time 2.7 seconds
Started Aug 07 06:55:00 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 200596 kb
Host smart-e27b3a0c-26fd-4026-a675-94ff90c661d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608647754 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.cl
kmgr_tl_errors.1608647754
Directory /workspace/15.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.clkmgr_tl_intg_err.2812653427
Short name T122
Test name
Test status
Simulation time 287963527 ps
CPU time 3.24 seconds
Started Aug 07 06:54:59 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 200644 kb
Host smart-ef8b0c3f-da17-480d-ba5f-022192fca617
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812653427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.clkmgr_tl_intg_err.2812653427
Directory /workspace/15.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3260688088
Short name T845
Test name
Test status
Simulation time 36629323 ps
CPU time 1.89 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:04 PM PDT 24
Peak memory 200676 kb
Host smart-d896c119-834a-45d7-976e-de6a08f0fc63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260688088 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_mem_rw_with_rand_reset.3260688088
Directory /workspace/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_csr_rw.3266665113
Short name T932
Test name
Test status
Simulation time 156278492 ps
CPU time 1.16 seconds
Started Aug 07 06:55:05 PM PDT 24
Finished Aug 07 06:55:06 PM PDT 24
Peak memory 200408 kb
Host smart-16d486f0-a672-4fc1-b5c0-8b75febef9be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266665113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.clkmgr_csr_rw.3266665113
Directory /workspace/16.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_intr_test.3707975874
Short name T830
Test name
Test status
Simulation time 38428303 ps
CPU time 0.72 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:03 PM PDT 24
Peak memory 199008 kb
Host smart-44b7f366-3b05-469b-b757-27e6c4fc7f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707975874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_intr_test.3707975874
Directory /workspace/16.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1480363931
Short name T857
Test name
Test status
Simulation time 24628835 ps
CPU time 1.05 seconds
Started Aug 07 06:55:05 PM PDT 24
Finished Aug 07 06:55:06 PM PDT 24
Peak memory 200412 kb
Host smart-3c50b9b7-7670-4bc7-b075-e9db2976d6fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480363931 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 16.clkmgr_same_csr_outstanding.1480363931
Directory /workspace/16.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.2923856390
Short name T142
Test name
Test status
Simulation time 115700564 ps
CPU time 1.89 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:04 PM PDT 24
Peak memory 200900 kb
Host smart-a9ba1bb3-bf2a-4048-b4ca-7365b2b4372b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923856390 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 16.clkmgr_shadow_reg_errors.2923856390
Directory /workspace/16.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.3553830553
Short name T958
Test name
Test status
Simulation time 136420955 ps
CPU time 1.86 seconds
Started Aug 07 06:55:01 PM PDT 24
Finished Aug 07 06:55:03 PM PDT 24
Peak memory 209048 kb
Host smart-dd427e39-cd0c-40c0-9d2f-e1f88908f2bc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553830553 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.3553830553
Directory /workspace/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_errors.2178534155
Short name T949
Test name
Test status
Simulation time 237687478 ps
CPU time 2.54 seconds
Started Aug 07 06:55:04 PM PDT 24
Finished Aug 07 06:55:06 PM PDT 24
Peak memory 200600 kb
Host smart-de42d21c-a316-44f4-b983-43e561553baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178534155 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.cl
kmgr_tl_errors.2178534155
Directory /workspace/16.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.clkmgr_tl_intg_err.1636846323
Short name T913
Test name
Test status
Simulation time 100681703 ps
CPU time 1.75 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:04 PM PDT 24
Peak memory 200592 kb
Host smart-d1545d52-a219-4589-8b84-34580ead9b89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636846323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.clkmgr_tl_intg_err.1636846323
Directory /workspace/16.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.3374405531
Short name T930
Test name
Test status
Simulation time 45041209 ps
CPU time 1.48 seconds
Started Aug 07 06:55:03 PM PDT 24
Finished Aug 07 06:55:04 PM PDT 24
Peak memory 200644 kb
Host smart-852f9f41-46c6-4dc4-96d0-e85b86ac2f69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374405531 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_mem_rw_with_rand_reset.3374405531
Directory /workspace/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_csr_rw.118238266
Short name T893
Test name
Test status
Simulation time 28969771 ps
CPU time 0.9 seconds
Started Aug 07 06:55:01 PM PDT 24
Finished Aug 07 06:55:02 PM PDT 24
Peak memory 200444 kb
Host smart-ed0d639b-7f27-4abe-a1a5-6803a8a4f4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118238266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
clkmgr_csr_rw.118238266
Directory /workspace/17.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_intr_test.1794968366
Short name T843
Test name
Test status
Simulation time 12776724 ps
CPU time 0.67 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:03 PM PDT 24
Peak memory 199020 kb
Host smart-1c7ffb80-f475-492a-b508-827e94cc7684
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794968366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_intr_test.1794968366
Directory /workspace/17.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.2413247732
Short name T909
Test name
Test status
Simulation time 34916652 ps
CPU time 1.08 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:03 PM PDT 24
Peak memory 200408 kb
Host smart-88493958-6163-4188-a467-082e6fbf02fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413247732 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 17.clkmgr_same_csr_outstanding.2413247732
Directory /workspace/17.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3385267178
Short name T68
Test name
Test status
Simulation time 261771621 ps
CPU time 1.78 seconds
Started Aug 07 06:55:02 PM PDT 24
Finished Aug 07 06:55:04 PM PDT 24
Peak memory 200616 kb
Host smart-81ca2ef1-2ee1-4948-b8f2-6b6ae0b52294
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385267178 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 17.clkmgr_shadow_reg_errors.3385267178
Directory /workspace/17.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.4118958396
Short name T140
Test name
Test status
Simulation time 95693156 ps
CPU time 2.31 seconds
Started Aug 07 06:55:03 PM PDT 24
Finished Aug 07 06:55:05 PM PDT 24
Peak memory 210140 kb
Host smart-88fdea5d-9b06-4344-8939-1b040e14118c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118958396 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.4118958396
Directory /workspace/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_errors.3549216528
Short name T900
Test name
Test status
Simulation time 111678724 ps
CPU time 2.03 seconds
Started Aug 07 06:55:03 PM PDT 24
Finished Aug 07 06:55:05 PM PDT 24
Peak memory 200580 kb
Host smart-65b9dd3c-7cc2-4cd7-9bd5-09c2e9cdedda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549216528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.cl
kmgr_tl_errors.3549216528
Directory /workspace/17.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.clkmgr_tl_intg_err.1357458363
Short name T912
Test name
Test status
Simulation time 81204615 ps
CPU time 1.65 seconds
Started Aug 07 06:55:06 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 200620 kb
Host smart-301df8ae-d664-4756-98c2-9858dc537b74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357458363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.clkmgr_tl_intg_err.1357458363
Directory /workspace/17.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.3482260128
Short name T834
Test name
Test status
Simulation time 80952140 ps
CPU time 1.09 seconds
Started Aug 07 06:55:06 PM PDT 24
Finished Aug 07 06:55:07 PM PDT 24
Peak memory 200444 kb
Host smart-3a1424d2-9707-495d-9d4f-c5c05f2f38d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482260128 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_mem_rw_with_rand_reset.3482260128
Directory /workspace/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_csr_rw.1225080402
Short name T873
Test name
Test status
Simulation time 18825133 ps
CPU time 0.79 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 200408 kb
Host smart-3377382a-efb3-4076-8494-d7464d96074f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225080402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.clkmgr_csr_rw.1225080402
Directory /workspace/18.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_intr_test.1464733478
Short name T828
Test name
Test status
Simulation time 22769350 ps
CPU time 0.72 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 199008 kb
Host smart-d539e855-e2a3-452a-852b-4fd9cdb61c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464733478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_intr_test.1464733478
Directory /workspace/18.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.1518192681
Short name T94
Test name
Test status
Simulation time 36878810 ps
CPU time 1.05 seconds
Started Aug 07 06:55:09 PM PDT 24
Finished Aug 07 06:55:11 PM PDT 24
Peak memory 200408 kb
Host smart-e8c55bca-d6e8-48dc-bd91-95e092402d34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518192681 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 18.clkmgr_same_csr_outstanding.1518192681
Directory /workspace/18.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.2502563470
Short name T137
Test name
Test status
Simulation time 232937891 ps
CPU time 2.01 seconds
Started Aug 07 06:55:06 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 200824 kb
Host smart-e41e2760-5b80-4541-a6ab-e98970e05b59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502563470 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 18.clkmgr_shadow_reg_errors.2502563470
Directory /workspace/18.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.3735171626
Short name T939
Test name
Test status
Simulation time 162656516 ps
CPU time 3.03 seconds
Started Aug 07 06:55:10 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 210044 kb
Host smart-c6ca999e-03b3-415b-b4c6-5ef1f36e1252
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735171626 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.3735171626
Directory /workspace/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.clkmgr_tl_errors.3670567077
Short name T883
Test name
Test status
Simulation time 125214473 ps
CPU time 2.77 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:09 PM PDT 24
Peak memory 200508 kb
Host smart-31c873b8-e0b5-453e-a164-3f06942e00a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670567077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.cl
kmgr_tl_errors.3670567077
Directory /workspace/18.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.1343168099
Short name T963
Test name
Test status
Simulation time 67240191 ps
CPU time 1.02 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 200516 kb
Host smart-06c8063e-8455-4fe4-bdfd-aaaabbd311b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343168099 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_mem_rw_with_rand_reset.1343168099
Directory /workspace/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_csr_rw.217670762
Short name T944
Test name
Test status
Simulation time 15101925 ps
CPU time 0.77 seconds
Started Aug 07 06:55:08 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 200416 kb
Host smart-249d7a84-d401-442f-a203-09c8cd2e252b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217670762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
clkmgr_csr_rw.217670762
Directory /workspace/19.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_intr_test.2247885157
Short name T977
Test name
Test status
Simulation time 40217559 ps
CPU time 0.73 seconds
Started Aug 07 06:55:09 PM PDT 24
Finished Aug 07 06:55:10 PM PDT 24
Peak memory 199056 kb
Host smart-5c7ba853-4c22-436a-9f68-380d5b1ed826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247885157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.cl
kmgr_intr_test.2247885157
Directory /workspace/19.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.2421559713
Short name T959
Test name
Test status
Simulation time 48585317 ps
CPU time 1.37 seconds
Started Aug 07 06:55:06 PM PDT 24
Finished Aug 07 06:55:07 PM PDT 24
Peak memory 200632 kb
Host smart-8576e158-b1ef-435b-9c35-4c00bd07fc8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421559713 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 19.clkmgr_same_csr_outstanding.2421559713
Directory /workspace/19.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.2705751221
Short name T150
Test name
Test status
Simulation time 95114669 ps
CPU time 1.42 seconds
Started Aug 07 06:55:10 PM PDT 24
Finished Aug 07 06:55:11 PM PDT 24
Peak memory 200692 kb
Host smart-31692bc3-7d70-4d86-997f-a66b97f930d7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705751221 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 19.clkmgr_shadow_reg_errors.2705751221
Directory /workspace/19.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.2134297706
Short name T69
Test name
Test status
Simulation time 432118944 ps
CPU time 3.65 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:10 PM PDT 24
Peak memory 209056 kb
Host smart-24bcc4f6-5e84-4aa0-aa0a-d4bbd4845113
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134297706 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.2134297706
Directory /workspace/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_errors.777383372
Short name T931
Test name
Test status
Simulation time 73664619 ps
CPU time 1.42 seconds
Started Aug 07 06:55:09 PM PDT 24
Finished Aug 07 06:55:10 PM PDT 24
Peak memory 200612 kb
Host smart-b084bd9e-64c4-4b26-91f7-fa1ea982fdbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777383372 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clk
mgr_tl_errors.777383372
Directory /workspace/19.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.clkmgr_tl_intg_err.751034867
Short name T110
Test name
Test status
Simulation time 586725706 ps
CPU time 3.49 seconds
Started Aug 07 06:55:09 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 200608 kb
Host smart-c1da61d1-a3ff-48c7-8413-6dd97b06c75e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751034867 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 19.clkmgr_tl_intg_err.751034867
Directory /workspace/19.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_aliasing.1968298622
Short name T911
Test name
Test status
Simulation time 138046551 ps
CPU time 1.52 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200420 kb
Host smart-54283298-b455-4fa0-9e18-71a3a61cf988
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968298622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_aliasing.1968298622
Directory /workspace/2.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3361313031
Short name T916
Test name
Test status
Simulation time 422551204 ps
CPU time 7.6 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 200580 kb
Host smart-13ca600a-8709-4ac4-9f54-7b085d3ba6d9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361313031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.clkmgr_csr_bit_bash.3361313031
Directory /workspace/2.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.403853188
Short name T844
Test name
Test status
Simulation time 93363776 ps
CPU time 1.01 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:33 PM PDT 24
Peak memory 200388 kb
Host smart-dd871d7d-bdba-4398-863f-f855bcaf4e1d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403853188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_csr_hw_reset.403853188
Directory /workspace/2.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3181087767
Short name T879
Test name
Test status
Simulation time 77592851 ps
CPU time 1.37 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200544 kb
Host smart-8b86475e-5daf-4a98-861b-28240870c534
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181087767 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3181087767
Directory /workspace/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_csr_rw.1955906093
Short name T197
Test name
Test status
Simulation time 22940224 ps
CPU time 0.86 seconds
Started Aug 07 06:54:33 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 200424 kb
Host smart-add93a3c-28a0-443f-b972-91c63df9be42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955906093 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
clkmgr_csr_rw.1955906093
Directory /workspace/2.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_intr_test.3562649065
Short name T826
Test name
Test status
Simulation time 12341851 ps
CPU time 0.7 seconds
Started Aug 07 06:54:33 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 199040 kb
Host smart-bd5986f7-1e62-43d3-8eaa-e2e7a1f2a1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562649065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clk
mgr_intr_test.3562649065
Directory /workspace/2.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.707693556
Short name T93
Test name
Test status
Simulation time 153254599 ps
CPU time 1.7 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200632 kb
Host smart-a6db9b86-f232-47d2-9ef8-df62dee66d33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707693556 -assert nopostproc +UVM_TESTNAME=clkmgr_b
ase_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.clkmgr_same_csr_outstanding.707693556
Directory /workspace/2.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.4182815800
Short name T67
Test name
Test status
Simulation time 122288188 ps
CPU time 2.18 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:29 PM PDT 24
Peak memory 200840 kb
Host smart-50077b20-4e14-4197-8970-0455d4a06caa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182815800 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 2.clkmgr_shadow_reg_errors.4182815800
Directory /workspace/2.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.4173876716
Short name T60
Test name
Test status
Simulation time 71968471 ps
CPU time 1.68 seconds
Started Aug 07 06:54:28 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 208944 kb
Host smart-874e1b14-7c1a-4d8e-bb4d-7a8496210c03
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173876716 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.4173876716
Directory /workspace/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_errors.349972405
Short name T849
Test name
Test status
Simulation time 88288679 ps
CPU time 2.48 seconds
Started Aug 07 06:54:27 PM PDT 24
Finished Aug 07 06:54:30 PM PDT 24
Peak memory 200680 kb
Host smart-42007483-be1a-487f-b0ea-ffccd666ccac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349972405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkm
gr_tl_errors.349972405
Directory /workspace/2.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.clkmgr_tl_intg_err.650660221
Short name T120
Test name
Test status
Simulation time 82171387 ps
CPU time 1.62 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:33 PM PDT 24
Peak memory 200568 kb
Host smart-28a15ef8-0621-46c9-a96f-35febf60703a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650660221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_tl_intg_err.650660221
Directory /workspace/2.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.clkmgr_intr_test.3414280677
Short name T936
Test name
Test status
Simulation time 19956963 ps
CPU time 0.68 seconds
Started Aug 07 06:55:10 PM PDT 24
Finished Aug 07 06:55:10 PM PDT 24
Peak memory 199040 kb
Host smart-1163ea58-7431-46ae-b814-bbf9fe01e019
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414280677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.cl
kmgr_intr_test.3414280677
Directory /workspace/20.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.clkmgr_intr_test.1859072040
Short name T907
Test name
Test status
Simulation time 42700653 ps
CPU time 0.76 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 199064 kb
Host smart-12dbbb35-e7f7-452e-8f17-56318618e70e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859072040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.cl
kmgr_intr_test.1859072040
Directory /workspace/21.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.clkmgr_intr_test.1204869803
Short name T891
Test name
Test status
Simulation time 18267700 ps
CPU time 0.68 seconds
Started Aug 07 06:55:07 PM PDT 24
Finished Aug 07 06:55:08 PM PDT 24
Peak memory 199032 kb
Host smart-44a2d4ae-9c90-46a7-b1a0-2d3370c1e71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204869803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.cl
kmgr_intr_test.1204869803
Directory /workspace/22.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.clkmgr_intr_test.3349627016
Short name T865
Test name
Test status
Simulation time 113642982 ps
CPU time 0.9 seconds
Started Aug 07 06:55:08 PM PDT 24
Finished Aug 07 06:55:09 PM PDT 24
Peak memory 199008 kb
Host smart-6b489454-e88b-456a-8c6b-6f0c346b6518
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349627016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.cl
kmgr_intr_test.3349627016
Directory /workspace/23.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.clkmgr_intr_test.1015489967
Short name T967
Test name
Test status
Simulation time 20189787 ps
CPU time 0.68 seconds
Started Aug 07 06:55:15 PM PDT 24
Finished Aug 07 06:55:16 PM PDT 24
Peak memory 199088 kb
Host smart-fc21b4bd-46c7-4f60-9f47-c14d7550e222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015489967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.cl
kmgr_intr_test.1015489967
Directory /workspace/24.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.clkmgr_intr_test.2225332692
Short name T841
Test name
Test status
Simulation time 11743332 ps
CPU time 0.67 seconds
Started Aug 07 06:55:12 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 198980 kb
Host smart-ff6c1dcf-5dbe-4b36-8f04-d790b82647ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225332692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.cl
kmgr_intr_test.2225332692
Directory /workspace/25.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.clkmgr_intr_test.738559218
Short name T839
Test name
Test status
Simulation time 39274563 ps
CPU time 0.7 seconds
Started Aug 07 06:55:15 PM PDT 24
Finished Aug 07 06:55:16 PM PDT 24
Peak memory 199036 kb
Host smart-8cd5dc4b-aa5f-4679-9c64-8f5c5d3507b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738559218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clk
mgr_intr_test.738559218
Directory /workspace/26.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.clkmgr_intr_test.3461254207
Short name T938
Test name
Test status
Simulation time 25400199 ps
CPU time 0.69 seconds
Started Aug 07 06:55:12 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 199012 kb
Host smart-ddafda6e-efc2-40f6-a1ee-5797d6263261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461254207 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.cl
kmgr_intr_test.3461254207
Directory /workspace/27.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.clkmgr_intr_test.2712283764
Short name T833
Test name
Test status
Simulation time 17961300 ps
CPU time 0.68 seconds
Started Aug 07 06:55:13 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 199080 kb
Host smart-345ee1a0-f86b-40ee-864b-4e83e815ce5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712283764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.cl
kmgr_intr_test.2712283764
Directory /workspace/28.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.clkmgr_intr_test.3964950915
Short name T901
Test name
Test status
Simulation time 25615272 ps
CPU time 0.69 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:21 PM PDT 24
Peak memory 199000 kb
Host smart-2762ffc0-06c7-445a-8490-d7ef5e57873b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964950915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.cl
kmgr_intr_test.3964950915
Directory /workspace/29.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_aliasing.1727502728
Short name T877
Test name
Test status
Simulation time 31552495 ps
CPU time 1.11 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200440 kb
Host smart-ef92a689-62fb-44b9-9d6a-5a2fc8a034f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727502728 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_aliasing.1727502728
Directory /workspace/3.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.2976464323
Short name T940
Test name
Test status
Simulation time 479609187 ps
CPU time 4.96 seconds
Started Aug 07 06:54:36 PM PDT 24
Finished Aug 07 06:54:41 PM PDT 24
Peak memory 200624 kb
Host smart-fd353cc5-17d3-445f-a504-cfc3658eb2b1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976464323 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_bit_bash.2976464323
Directory /workspace/3.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1634016303
Short name T952
Test name
Test status
Simulation time 111299772 ps
CPU time 0.97 seconds
Started Aug 07 06:54:35 PM PDT 24
Finished Aug 07 06:54:37 PM PDT 24
Peak memory 200412 kb
Host smart-43200d66-a66a-43ee-a1b8-c57661d5681d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634016303 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.clkmgr_csr_hw_reset.1634016303
Directory /workspace/3.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.232936512
Short name T902
Test name
Test status
Simulation time 104607800 ps
CPU time 1.23 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200528 kb
Host smart-4b5eefe6-de99-49ac-9276-aef269fcb940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232936512 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove
rage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.232936512
Directory /workspace/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_csr_rw.1459701391
Short name T943
Test name
Test status
Simulation time 42143266 ps
CPU time 0.87 seconds
Started Aug 07 06:54:33 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 200408 kb
Host smart-19190e27-f2f6-4e73-bc9c-c00c33e4c22a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459701391 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
clkmgr_csr_rw.1459701391
Directory /workspace/3.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_intr_test.1273361949
Short name T876
Test name
Test status
Simulation time 19440555 ps
CPU time 0.67 seconds
Started Aug 07 06:54:33 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 199136 kb
Host smart-d89a938f-762b-42d0-9116-7bf787bd9dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273361949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_intr_test.1273361949
Directory /workspace/3.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1695958303
Short name T858
Test name
Test status
Simulation time 110084446 ps
CPU time 1.38 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200664 kb
Host smart-7b676489-7ca1-45a5-8ca6-e60519d9b90c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695958303 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.clkmgr_same_csr_outstanding.1695958303
Directory /workspace/3.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3110109097
Short name T144
Test name
Test status
Simulation time 50623703 ps
CPU time 1.2 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200680 kb
Host smart-4e3f7a28-bef5-4643-a249-51173fdae5d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110109097 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 3.clkmgr_shadow_reg_errors.3110109097
Directory /workspace/3.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.1383638852
Short name T966
Test name
Test status
Simulation time 233387708 ps
CPU time 3.05 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 209092 kb
Host smart-22571b79-034f-4494-a35b-a5b16ae79dd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383638852 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.1383638852
Directory /workspace/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_errors.2091003532
Short name T908
Test name
Test status
Simulation time 330117797 ps
CPU time 3.39 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:36 PM PDT 24
Peak memory 200600 kb
Host smart-742d9450-c9fd-4101-bb32-e3886d1041fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091003532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clk
mgr_tl_errors.2091003532
Directory /workspace/3.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.clkmgr_tl_intg_err.926204106
Short name T216
Test name
Test status
Simulation time 190895235 ps
CPU time 1.96 seconds
Started Aug 07 06:54:34 PM PDT 24
Finished Aug 07 06:54:37 PM PDT 24
Peak memory 200596 kb
Host smart-a21f6553-f060-4983-8960-e494921f94ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926204106 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_tl_intg_err.926204106
Directory /workspace/3.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.clkmgr_intr_test.2742955660
Short name T935
Test name
Test status
Simulation time 33377009 ps
CPU time 0.7 seconds
Started Aug 07 06:55:13 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 199024 kb
Host smart-fdd6c1f7-1fb8-4eb7-833d-80af32418528
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742955660 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.cl
kmgr_intr_test.2742955660
Directory /workspace/30.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.clkmgr_intr_test.1263286628
Short name T922
Test name
Test status
Simulation time 11654220 ps
CPU time 0.66 seconds
Started Aug 07 06:55:11 PM PDT 24
Finished Aug 07 06:55:12 PM PDT 24
Peak memory 199008 kb
Host smart-73dec20b-6891-4860-b81b-df8110f35a78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263286628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.cl
kmgr_intr_test.1263286628
Directory /workspace/31.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.clkmgr_intr_test.2439238194
Short name T954
Test name
Test status
Simulation time 12866689 ps
CPU time 0.72 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:21 PM PDT 24
Peak memory 198872 kb
Host smart-7c030913-7b78-4b22-aeac-94dd278d916e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439238194 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.cl
kmgr_intr_test.2439238194
Directory /workspace/32.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.clkmgr_intr_test.2833934724
Short name T840
Test name
Test status
Simulation time 11698937 ps
CPU time 0.64 seconds
Started Aug 07 06:55:12 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 199000 kb
Host smart-6a5127f9-9454-4479-818c-ecac399c074c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833934724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.cl
kmgr_intr_test.2833934724
Directory /workspace/33.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.clkmgr_intr_test.72458384
Short name T878
Test name
Test status
Simulation time 13091741 ps
CPU time 0.74 seconds
Started Aug 07 06:55:12 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 199012 kb
Host smart-98ea8126-6547-4ba6-97a1-c1652edbdde1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72458384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ
=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkm
gr_intr_test.72458384
Directory /workspace/34.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.clkmgr_intr_test.3862071628
Short name T890
Test name
Test status
Simulation time 12264172 ps
CPU time 0.65 seconds
Started Aug 07 06:55:15 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 199140 kb
Host smart-99d3dd84-2323-481e-a586-534f9e01312c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862071628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.cl
kmgr_intr_test.3862071628
Directory /workspace/35.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.clkmgr_intr_test.3190993827
Short name T923
Test name
Test status
Simulation time 13890420 ps
CPU time 0.68 seconds
Started Aug 07 06:55:14 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 199060 kb
Host smart-983ddd4e-ad05-4fb3-a494-8a54b7db42a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190993827 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.cl
kmgr_intr_test.3190993827
Directory /workspace/36.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.clkmgr_intr_test.1120480877
Short name T976
Test name
Test status
Simulation time 39273888 ps
CPU time 0.75 seconds
Started Aug 07 06:55:12 PM PDT 24
Finished Aug 07 06:55:13 PM PDT 24
Peak memory 198996 kb
Host smart-f320e547-9bb7-4ef5-aff9-1d79b188702d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120480877 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.cl
kmgr_intr_test.1120480877
Directory /workspace/37.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.clkmgr_intr_test.2457910582
Short name T854
Test name
Test status
Simulation time 25560849 ps
CPU time 0.67 seconds
Started Aug 07 06:55:15 PM PDT 24
Finished Aug 07 06:55:16 PM PDT 24
Peak memory 198988 kb
Host smart-7738d9bd-5e60-4014-af3f-d46342889af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457910582 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.cl
kmgr_intr_test.2457910582
Directory /workspace/38.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.clkmgr_intr_test.2961104908
Short name T975
Test name
Test status
Simulation time 30969661 ps
CPU time 0.77 seconds
Started Aug 07 06:55:20 PM PDT 24
Finished Aug 07 06:55:21 PM PDT 24
Peak memory 198940 kb
Host smart-776eccd8-66af-4d8b-b247-f8ddf26763b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961104908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.cl
kmgr_intr_test.2961104908
Directory /workspace/39.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_aliasing.3884142077
Short name T868
Test name
Test status
Simulation time 56232221 ps
CPU time 1.68 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200524 kb
Host smart-90882d07-0448-42e5-8cc8-b2dcf10dcc84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884142077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_aliasing.3884142077
Directory /workspace/4.clkmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.3398257802
Short name T960
Test name
Test status
Simulation time 481488035 ps
CPU time 4.93 seconds
Started Aug 07 06:54:40 PM PDT 24
Finished Aug 07 06:54:45 PM PDT 24
Peak memory 200568 kb
Host smart-68c91971-c229-4b74-8eab-04451dc64874
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398257802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_bit_bash.3398257802
Directory /workspace/4.clkmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.1030866166
Short name T863
Test name
Test status
Simulation time 26460129 ps
CPU time 0.81 seconds
Started Aug 07 06:54:36 PM PDT 24
Finished Aug 07 06:54:37 PM PDT 24
Peak memory 200432 kb
Host smart-baffea09-e07a-4d0f-89f5-87eba3f61ba0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030866166 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.clkmgr_csr_hw_reset.1030866166
Directory /workspace/4.clkmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.3477613211
Short name T838
Test name
Test status
Simulation time 57175942 ps
CPU time 1.34 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200436 kb
Host smart-e596b858-40c2-4ded-92cd-3a0ec2e2684b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477613211 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.3477613211
Directory /workspace/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_csr_rw.1918786235
Short name T946
Test name
Test status
Simulation time 37970300 ps
CPU time 0.83 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:39 PM PDT 24
Peak memory 200352 kb
Host smart-d80fb1b4-ee2e-4191-88fe-3ce5282e345b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918786235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
clkmgr_csr_rw.1918786235
Directory /workspace/4.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_intr_test.1466060751
Short name T971
Test name
Test status
Simulation time 41630061 ps
CPU time 0.72 seconds
Started Aug 07 06:54:36 PM PDT 24
Finished Aug 07 06:54:37 PM PDT 24
Peak memory 199100 kb
Host smart-32b2618c-90e0-4b44-9c35-cfdfe693a3e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466060751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_intr_test.1466060751
Directory /workspace/4.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.1201613923
Short name T921
Test name
Test status
Simulation time 54778639 ps
CPU time 1.3 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:39 PM PDT 24
Peak memory 200656 kb
Host smart-b655e08c-4842-48bf-a9ad-cc718915f0a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201613923 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.clkmgr_same_csr_outstanding.1201613923
Directory /workspace/4.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.2330360815
Short name T148
Test name
Test status
Simulation time 104848680 ps
CPU time 1.8 seconds
Started Aug 07 06:54:33 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200928 kb
Host smart-f7d77c98-08a7-4204-a0c2-6d3f7eedf460
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330360815 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 4.clkmgr_shadow_reg_errors.2330360815
Directory /workspace/4.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.3376978265
Short name T71
Test name
Test status
Simulation time 405293024 ps
CPU time 2.5 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200952 kb
Host smart-5d504175-eedb-469d-b618-6fd6145e762f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376978265 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.3376978265
Directory /workspace/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_errors.1085910256
Short name T847
Test name
Test status
Simulation time 19864983 ps
CPU time 1.14 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:34 PM PDT 24
Peak memory 200408 kb
Host smart-813418b9-a414-4247-a91b-06ed2dd7abbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085910256 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clk
mgr_tl_errors.1085910256
Directory /workspace/4.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2593264403
Short name T115
Test name
Test status
Simulation time 235205470 ps
CPU time 2.51 seconds
Started Aug 07 06:54:32 PM PDT 24
Finished Aug 07 06:54:35 PM PDT 24
Peak memory 200600 kb
Host smart-e8eb36c9-24c8-418b-a426-ebb18f55ad58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593264403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.clkmgr_tl_intg_err.2593264403
Directory /workspace/4.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.clkmgr_intr_test.256820094
Short name T880
Test name
Test status
Simulation time 12371237 ps
CPU time 0.68 seconds
Started Aug 07 06:55:15 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 199032 kb
Host smart-459d3cbd-fe7e-4b12-85a5-738036ea016c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256820094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clk
mgr_intr_test.256820094
Directory /workspace/40.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.clkmgr_intr_test.544411691
Short name T964
Test name
Test status
Simulation time 28265563 ps
CPU time 0.69 seconds
Started Aug 07 06:55:19 PM PDT 24
Finished Aug 07 06:55:20 PM PDT 24
Peak memory 199020 kb
Host smart-92064fc8-2465-40ae-bff6-e336283ea9d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544411691 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clk
mgr_intr_test.544411691
Directory /workspace/41.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.clkmgr_intr_test.3568146286
Short name T866
Test name
Test status
Simulation time 19200093 ps
CPU time 0.67 seconds
Started Aug 07 06:55:11 PM PDT 24
Finished Aug 07 06:55:11 PM PDT 24
Peak memory 198920 kb
Host smart-f095ecc7-88dd-4f1e-b38d-0c88eafa714f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568146286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.cl
kmgr_intr_test.3568146286
Directory /workspace/42.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.clkmgr_intr_test.342868438
Short name T829
Test name
Test status
Simulation time 18182343 ps
CPU time 0.69 seconds
Started Aug 07 06:55:14 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 199064 kb
Host smart-6e5cdc86-ce48-4c32-a6fb-0f7221a2c439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342868438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clk
mgr_intr_test.342868438
Directory /workspace/43.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.clkmgr_intr_test.3048956554
Short name T941
Test name
Test status
Simulation time 19536293 ps
CPU time 0.66 seconds
Started Aug 07 06:55:11 PM PDT 24
Finished Aug 07 06:55:12 PM PDT 24
Peak memory 199080 kb
Host smart-67854a2c-b4fd-4a68-ba0d-840802c7a110
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048956554 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.cl
kmgr_intr_test.3048956554
Directory /workspace/44.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.clkmgr_intr_test.2476176463
Short name T974
Test name
Test status
Simulation time 38293965 ps
CPU time 0.73 seconds
Started Aug 07 06:55:14 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 199080 kb
Host smart-9c2c9a4a-01ff-4b4a-8b7b-d2457d170222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476176463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.cl
kmgr_intr_test.2476176463
Directory /workspace/45.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.clkmgr_intr_test.310898269
Short name T861
Test name
Test status
Simulation time 15477769 ps
CPU time 0.72 seconds
Started Aug 07 06:55:13 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 199040 kb
Host smart-84d637a2-e3e6-4165-9b3b-e040f7dc2eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310898269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clk
mgr_intr_test.310898269
Directory /workspace/46.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.clkmgr_intr_test.2924493941
Short name T910
Test name
Test status
Simulation time 31351814 ps
CPU time 0.69 seconds
Started Aug 07 06:55:13 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 199104 kb
Host smart-3047e591-a1d6-44bc-be3c-931b37e8f99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924493941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.cl
kmgr_intr_test.2924493941
Directory /workspace/47.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.clkmgr_intr_test.3185887615
Short name T856
Test name
Test status
Simulation time 20573758 ps
CPU time 0.69 seconds
Started Aug 07 06:55:14 PM PDT 24
Finished Aug 07 06:55:14 PM PDT 24
Peak memory 198952 kb
Host smart-51131c4a-5c9c-48ac-a33a-19f2f2f9afd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185887615 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.cl
kmgr_intr_test.3185887615
Directory /workspace/48.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.clkmgr_intr_test.2677747476
Short name T904
Test name
Test status
Simulation time 79305621 ps
CPU time 0.79 seconds
Started Aug 07 06:55:14 PM PDT 24
Finished Aug 07 06:55:15 PM PDT 24
Peak memory 198880 kb
Host smart-34985b22-6158-4a0b-909f-49f30c6fc743
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677747476 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.cl
kmgr_intr_test.2677747476
Directory /workspace/49.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.1787651304
Short name T897
Test name
Test status
Simulation time 34623188 ps
CPU time 1.94 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:45 PM PDT 24
Peak memory 200524 kb
Host smart-881aa3d7-374a-4189-862f-e72a8026bb16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787651304 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_mem_rw_with_rand_reset.1787651304
Directory /workspace/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_csr_rw.1489558692
Short name T874
Test name
Test status
Simulation time 14041685 ps
CPU time 0.83 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 200428 kb
Host smart-bffc0f64-2db8-44e1-8bbc-646b142da8e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489558692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
clkmgr_csr_rw.1489558692
Directory /workspace/5.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_intr_test.3370602339
Short name T846
Test name
Test status
Simulation time 20519919 ps
CPU time 0.68 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 199060 kb
Host smart-dcdd508a-7aca-43ad-9f52-0996ba4c4659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370602339 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_intr_test.3370602339
Directory /workspace/5.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.2273204263
Short name T950
Test name
Test status
Simulation time 23949757 ps
CPU time 0.92 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 200436 kb
Host smart-6d7871d5-acf0-4e98-8cc3-4efa899b0062
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273204263 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.clkmgr_same_csr_outstanding.2273204263
Directory /workspace/5.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.1380109820
Short name T63
Test name
Test status
Simulation time 428031016 ps
CPU time 2.71 seconds
Started Aug 07 06:54:39 PM PDT 24
Finished Aug 07 06:54:42 PM PDT 24
Peak memory 217232 kb
Host smart-323c275a-8783-4550-b27c-03477506003b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380109820 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 5.clkmgr_shadow_reg_errors.1380109820
Directory /workspace/5.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.2232737621
Short name T136
Test name
Test status
Simulation time 253579279 ps
CPU time 2.58 seconds
Started Aug 07 06:54:36 PM PDT 24
Finished Aug 07 06:54:38 PM PDT 24
Peak memory 209120 kb
Host smart-00a68d2c-9ebe-4c15-bfa7-7c5281305db4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232737621 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.2232737621
Directory /workspace/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_errors.2933220758
Short name T827
Test name
Test status
Simulation time 118414850 ps
CPU time 2.37 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 200636 kb
Host smart-075f2be2-7084-43d2-be05-f05151ec9b25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933220758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clk
mgr_tl_errors.2933220758
Directory /workspace/5.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.clkmgr_tl_intg_err.12930782
Short name T961
Test name
Test status
Simulation time 121364837 ps
CPU time 1.8 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 200616 kb
Host smart-8289c036-ed2e-4cd4-abab-60c8f68ffd03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930782 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 5.clkmgr_tl_intg_err.12930782
Directory /workspace/5.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.2776837456
Short name T887
Test name
Test status
Simulation time 97364156 ps
CPU time 1.2 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:39 PM PDT 24
Peak memory 200472 kb
Host smart-2295d88b-bcf1-43a9-a28b-f20a48d7e893
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776837456 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_mem_rw_with_rand_reset.2776837456
Directory /workspace/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_csr_rw.649849986
Short name T842
Test name
Test status
Simulation time 14070757 ps
CPU time 0.77 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200268 kb
Host smart-7d6a3c0c-867a-421b-b8e0-77f7bdb68fe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649849986 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.c
lkmgr_csr_rw.649849986
Directory /workspace/6.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_intr_test.1672786151
Short name T882
Test name
Test status
Simulation time 38837067 ps
CPU time 0.73 seconds
Started Aug 07 06:54:39 PM PDT 24
Finished Aug 07 06:54:39 PM PDT 24
Peak memory 199032 kb
Host smart-f7c39c61-fc4d-4bb1-b589-d6ad3c8132e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672786151 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_intr_test.1672786151
Directory /workspace/6.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1514873226
Short name T886
Test name
Test status
Simulation time 98347153 ps
CPU time 1.38 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:39 PM PDT 24
Peak memory 200668 kb
Host smart-df82bb1f-e847-4093-902f-cdbae010abe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514873226 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.clkmgr_same_csr_outstanding.1514873226
Directory /workspace/6.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1418193485
Short name T955
Test name
Test status
Simulation time 304310018 ps
CPU time 3.34 seconds
Started Aug 07 06:54:37 PM PDT 24
Finished Aug 07 06:54:41 PM PDT 24
Peak memory 201080 kb
Host smart-28a58974-5e76-4950-8be7-704ec12a13d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418193485 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1418193485
Directory /workspace/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_errors.4204280003
Short name T927
Test name
Test status
Simulation time 64328760 ps
CPU time 1.45 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 200424 kb
Host smart-f4d5c1ff-d3bb-4805-b039-055894ce899a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204280003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clk
mgr_tl_errors.4204280003
Directory /workspace/6.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3504794396
Short name T111
Test name
Test status
Simulation time 77499854 ps
CPU time 1.85 seconds
Started Aug 07 06:54:38 PM PDT 24
Finished Aug 07 06:54:40 PM PDT 24
Peak memory 200660 kb
Host smart-b5d43492-547e-4b5e-a78b-e267163f6b02
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504794396 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.clkmgr_tl_intg_err.3504794396
Directory /workspace/6.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.1583403281
Short name T870
Test name
Test status
Simulation time 126050547 ps
CPU time 1.57 seconds
Started Aug 07 06:54:42 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200492 kb
Host smart-b582ce4f-c14d-4eb7-9f51-093221792113
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583403281 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_mem_rw_with_rand_reset.1583403281
Directory /workspace/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_csr_rw.1839449434
Short name T918
Test name
Test status
Simulation time 50278004 ps
CPU time 0.87 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200396 kb
Host smart-0e8cc6ef-50bf-4ef4-b8f3-e806fbdb94a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839449434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
clkmgr_csr_rw.1839449434
Directory /workspace/7.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_intr_test.2059980941
Short name T896
Test name
Test status
Simulation time 33801848 ps
CPU time 0.71 seconds
Started Aug 07 06:54:46 PM PDT 24
Finished Aug 07 06:54:47 PM PDT 24
Peak memory 199016 kb
Host smart-72080541-2daf-4578-a273-64460982717c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059980941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_intr_test.2059980941
Directory /workspace/7.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.2876144787
Short name T90
Test name
Test status
Simulation time 127282297 ps
CPU time 1.24 seconds
Started Aug 07 06:54:46 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 200452 kb
Host smart-1aa4bbdf-7e7a-4bfb-b38a-e86bbb022317
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876144787 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.clkmgr_same_csr_outstanding.2876144787
Directory /workspace/7.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.2058533178
Short name T139
Test name
Test status
Simulation time 76473686 ps
CPU time 1.36 seconds
Started Aug 07 06:54:42 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200696 kb
Host smart-e9dbb32a-f26c-4614-8b52-dfd9b19c1c4f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058533178 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 7.clkmgr_shadow_reg_errors.2058533178
Directory /workspace/7.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.3902434185
Short name T72
Test name
Test status
Simulation time 107841628 ps
CPU time 2.71 seconds
Started Aug 07 06:54:45 PM PDT 24
Finished Aug 07 06:54:47 PM PDT 24
Peak memory 201040 kb
Host smart-257c7856-e0e5-4b2d-aa65-7d69c82ad755
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902434185 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.3902434185
Directory /workspace/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_errors.4083057133
Short name T848
Test name
Test status
Simulation time 191449262 ps
CPU time 2.19 seconds
Started Aug 07 06:54:42 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200632 kb
Host smart-233a6962-adfa-4aed-8746-8a56d131e9d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083057133 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clk
mgr_tl_errors.4083057133
Directory /workspace/7.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.clkmgr_tl_intg_err.3638007910
Short name T112
Test name
Test status
Simulation time 108318179 ps
CPU time 1.93 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:45 PM PDT 24
Peak memory 200636 kb
Host smart-2df13a93-cada-4507-84e3-bb9fc5981b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638007910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.clkmgr_tl_intg_err.3638007910
Directory /workspace/7.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.2199579001
Short name T945
Test name
Test status
Simulation time 50143731 ps
CPU time 1.15 seconds
Started Aug 07 06:54:48 PM PDT 24
Finished Aug 07 06:54:50 PM PDT 24
Peak memory 200556 kb
Host smart-7e4c4ff3-a468-461b-bb24-1baa073582b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199579001 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_mem_rw_with_rand_reset.2199579001
Directory /workspace/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_csr_rw.778315790
Short name T867
Test name
Test status
Simulation time 127423609 ps
CPU time 1.07 seconds
Started Aug 07 06:54:48 PM PDT 24
Finished Aug 07 06:54:49 PM PDT 24
Peak memory 200356 kb
Host smart-a4ec1eb3-f00f-407d-8150-3e05d998859a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778315790 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.c
lkmgr_csr_rw.778315790
Directory /workspace/8.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_intr_test.291584230
Short name T889
Test name
Test status
Simulation time 17045377 ps
CPU time 0.68 seconds
Started Aug 07 06:54:43 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 199032 kb
Host smart-392104c8-f007-4bab-8a88-f6fff580c6c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291584230 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SE
Q=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkm
gr_intr_test.291584230
Directory /workspace/8.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.3548317908
Short name T864
Test name
Test status
Simulation time 64194681 ps
CPU time 1.34 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 200600 kb
Host smart-e5091aea-bb19-4b01-9f54-31d5107b884f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548317908 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.clkmgr_same_csr_outstanding.3548317908
Directory /workspace/8.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.4272682367
Short name T149
Test name
Test status
Simulation time 141472582 ps
CPU time 2.27 seconds
Started Aug 07 06:54:42 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 209060 kb
Host smart-4c18adff-659a-43da-acd7-07835a85179f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272682367 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 8.clkmgr_shadow_reg_errors.4272682367
Directory /workspace/8.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.3323724250
Short name T143
Test name
Test status
Simulation time 143577224 ps
CPU time 2.7 seconds
Started Aug 07 06:54:45 PM PDT 24
Finished Aug 07 06:54:47 PM PDT 24
Peak memory 209116 kb
Host smart-6d99bcea-c3c4-48bf-ba1e-f9b9f5e29f73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323724250 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.3323724250
Directory /workspace/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_errors.3204119192
Short name T898
Test name
Test status
Simulation time 29809880 ps
CPU time 1.7 seconds
Started Aug 07 06:54:45 PM PDT 24
Finished Aug 07 06:54:47 PM PDT 24
Peak memory 200644 kb
Host smart-426a8ee1-e988-4429-82c6-60141bb0fc63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204119192 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clk
mgr_tl_errors.3204119192
Directory /workspace/8.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.clkmgr_tl_intg_err.2118045759
Short name T124
Test name
Test status
Simulation time 315527289 ps
CPU time 2.15 seconds
Started Aug 07 06:54:42 PM PDT 24
Finished Aug 07 06:54:44 PM PDT 24
Peak memory 200636 kb
Host smart-8315ae5a-c0d2-4f96-9853-4161e61dd872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118045759 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.clkmgr_tl_intg_err.2118045759
Directory /workspace/8.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3615248400
Short name T196
Test name
Test status
Simulation time 40251141 ps
CPU time 1.25 seconds
Started Aug 07 06:54:48 PM PDT 24
Finished Aug 07 06:54:50 PM PDT 24
Peak memory 200488 kb
Host smart-d38074cc-30b9-41f6-b515-b52506692283
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615248400 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov
erage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_mem_rw_with_rand_reset.3615248400
Directory /workspace/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_csr_rw.720005400
Short name T942
Test name
Test status
Simulation time 21932911 ps
CPU time 0.82 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 200468 kb
Host smart-df89cc26-51ff-4c96-bd2f-20ff4cdeebf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720005400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST
_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.c
lkmgr_csr_rw.720005400
Directory /workspace/9.clkmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_intr_test.2088514825
Short name T869
Test name
Test status
Simulation time 39258571 ps
CPU time 0.74 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 199016 kb
Host smart-12638963-860d-4aef-8014-5f154ebb9253
User root
Command /workspace/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088514825 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_intr_test.2088514825
Directory /workspace/9.clkmgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.4153242535
Short name T894
Test name
Test status
Simulation time 168369216 ps
CPU time 1.62 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:49 PM PDT 24
Peak memory 200448 kb
Host smart-c2ccc25e-eb26-485f-8969-5fbe41682a5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153242535 -assert nopostproc +UVM_TESTNAME=clkmgr_
base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.clkmgr_same_csr_outstanding.4153242535
Directory /workspace/9.clkmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.2812679169
Short name T138
Test name
Test status
Simulation time 71034453 ps
CPU time 1.4 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:48 PM PDT 24
Peak memory 200728 kb
Host smart-4965f8cc-53ea-4991-93b8-6411e142d042
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI
TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812679169 -assert nopostproc +UVM_TESTNAME=clkmgr_bas
e_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n
ull -cm_name 9.clkmgr_shadow_reg_errors.2812679169
Directory /workspace/9.clkmgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.1923477457
Short name T146
Test name
Test status
Simulation time 263488289 ps
CPU time 2.86 seconds
Started Aug 07 06:54:50 PM PDT 24
Finished Aug 07 06:54:53 PM PDT 24
Peak memory 217204 kb
Host smart-79f525ea-22a7-445e-809c-661e5bb13eb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923477457 -assert nopostproc +UVM_TESTNAM
E=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.1923477457
Directory /workspace/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_errors.2800007410
Short name T934
Test name
Test status
Simulation time 103886375 ps
CPU time 1.89 seconds
Started Aug 07 06:54:52 PM PDT 24
Finished Aug 07 06:54:54 PM PDT 24
Peak memory 200620 kb
Host smart-3a20ace5-fa5d-4486-b3c5-e152c59354b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800007410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_S
EQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clk
mgr_tl_errors.2800007410
Directory /workspace/9.clkmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.clkmgr_tl_intg_err.2267882808
Short name T114
Test name
Test status
Simulation time 113361475 ps
CPU time 2.43 seconds
Started Aug 07 06:54:47 PM PDT 24
Finished Aug 07 06:54:50 PM PDT 24
Peak memory 200600 kb
Host smart-d23562aa-0739-480b-8a4e-0bc206d9c8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267882808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.clkmgr_tl_intg_err.2267882808
Directory /workspace/9.clkmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.clkmgr_alert_test.2651332916
Short name T327
Test name
Test status
Simulation time 43354351 ps
CPU time 0.8 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:56 PM PDT 24
Peak memory 200964 kb
Host smart-e2a799fd-9501-4537-9261-44d3da21be32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651332916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkm
gr_alert_test.2651332916
Directory /workspace/0.clkmgr_alert_test/latest

Test location /workspace/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.1335663896
Short name T684
Test name
Test status
Simulation time 25128685 ps
CPU time 0.93 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200988 kb
Host smart-7a29ee6c-f264-4825-aade-f93381bfc0a9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335663896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_clk_handshake_intersig_mubi.1335663896
Directory /workspace/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_clk_status.2349170805
Short name T468
Test name
Test status
Simulation time 25467273 ps
CPU time 0.71 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200292 kb
Host smart-ac0d08c3-410f-4b73-9777-611a276b115e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349170805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.2349170805
Directory /workspace/0.clkmgr_clk_status/latest

Test location /workspace/coverage/default/0.clkmgr_div_intersig_mubi.2832622065
Short name T295
Test name
Test status
Simulation time 20892729 ps
CPU time 0.83 seconds
Started Aug 07 05:01:58 PM PDT 24
Finished Aug 07 05:01:58 PM PDT 24
Peak memory 201072 kb
Host smart-8deb760a-750e-414a-b7a1-0bab770170e8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832622065 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_div_intersig_mubi.2832622065
Directory /workspace/0.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_extclk.603225723
Short name T420
Test name
Test status
Simulation time 21139316 ps
CPU time 0.84 seconds
Started Aug 07 05:01:56 PM PDT 24
Finished Aug 07 05:01:57 PM PDT 24
Peak memory 200992 kb
Host smart-d02d9206-fa20-4342-a467-36701267e9c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603225723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.603225723
Directory /workspace/0.clkmgr_extclk/latest

Test location /workspace/coverage/default/0.clkmgr_frequency.3158238959
Short name T26
Test name
Test status
Simulation time 1523637914 ps
CPU time 12.08 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:12 PM PDT 24
Peak memory 201160 kb
Host smart-f8b13aed-7bbe-45cd-9e01-e857de679ea1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158238959 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.3158238959
Directory /workspace/0.clkmgr_frequency/latest

Test location /workspace/coverage/default/0.clkmgr_frequency_timeout.2156112169
Short name T84
Test name
Test status
Simulation time 975458919 ps
CPU time 7.69 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201232 kb
Host smart-491233c1-4692-4cad-ab9b-ceae3d1e492a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156112169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_ti
meout.2156112169
Directory /workspace/0.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.3153989101
Short name T328
Test name
Test status
Simulation time 45085515 ps
CPU time 0.9 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201076 kb
Host smart-6f0db8ba-4a10-41d5-86de-bd9891070b19
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153989101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_clk_byp_req_intersig_mubi.3153989101
Directory /workspace/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2787619257
Short name T556
Test name
Test status
Simulation time 60208659 ps
CPU time 0.92 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201076 kb
Host smart-89f593da-72be-43b3-a7e5-a0396b725c3c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787619257 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 0.clkmgr_lc_ctrl_intersig_mubi.2787619257
Directory /workspace/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/0.clkmgr_peri.2453679480
Short name T555
Test name
Test status
Simulation time 20273792 ps
CPU time 0.82 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:56 PM PDT 24
Peak memory 200984 kb
Host smart-68eb5fd8-d547-43a3-a2d3-26d9ed99fd07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453679480 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.2453679480
Directory /workspace/0.clkmgr_peri/latest

Test location /workspace/coverage/default/0.clkmgr_regwen.3365572003
Short name T125
Test name
Test status
Simulation time 1260749153 ps
CPU time 4.77 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:02:00 PM PDT 24
Peak memory 201240 kb
Host smart-da1dcc37-39eb-41d0-bc9a-601bd8470ab3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365572003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3365572003
Directory /workspace/0.clkmgr_regwen/latest

Test location /workspace/coverage/default/0.clkmgr_sec_cm.570281173
Short name T50
Test name
Test status
Simulation time 1009296923 ps
CPU time 4.4 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:02:00 PM PDT 24
Peak memory 216604 kb
Host smart-10c60f26-2088-4097-8c10-e1f9ee41d884
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570281173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr
_sec_cm.570281173
Directory /workspace/0.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/0.clkmgr_smoke.1546143956
Short name T465
Test name
Test status
Simulation time 40526176 ps
CPU time 0.9 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 201068 kb
Host smart-5dcb86f4-d3b1-4305-8f34-599e0407d356
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546143956 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.1546143956
Directory /workspace/0.clkmgr_smoke/latest

Test location /workspace/coverage/default/0.clkmgr_stress_all.1433343028
Short name T496
Test name
Test status
Simulation time 6997403000 ps
CPU time 36.44 seconds
Started Aug 07 05:01:58 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201324 kb
Host smart-68372464-08e1-4edb-a9d4-02595922e099
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433343028 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.clkmgr_stress_all.1433343028
Directory /workspace/0.clkmgr_stress_all/latest

Test location /workspace/coverage/default/0.clkmgr_trans.2987417307
Short name T687
Test name
Test status
Simulation time 30936162 ps
CPU time 0.86 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:56 PM PDT 24
Peak memory 201080 kb
Host smart-adbcc478-7d58-4d82-b4b5-5bc232a81cbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987417307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.2987417307
Directory /workspace/0.clkmgr_trans/latest

Test location /workspace/coverage/default/1.clkmgr_alert_test.3835681536
Short name T509
Test name
Test status
Simulation time 131096374 ps
CPU time 1.07 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:00 PM PDT 24
Peak memory 201096 kb
Host smart-b6b49742-0571-47de-be4f-0669e830ae6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835681536 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkm
gr_alert_test.3835681536
Directory /workspace/1.clkmgr_alert_test/latest

Test location /workspace/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.3283966613
Short name T447
Test name
Test status
Simulation time 123180775 ps
CPU time 1.01 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:00 PM PDT 24
Peak memory 201016 kb
Host smart-1f02c7c7-b921-47b5-8cd3-c6198153ff8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283966613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_clk_handshake_intersig_mubi.3283966613
Directory /workspace/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_clk_status.4065923723
Short name T528
Test name
Test status
Simulation time 88074602 ps
CPU time 0.92 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 200268 kb
Host smart-e58f3180-f3e5-4ea6-ac9a-d6fe0b169714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065923723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.4065923723
Directory /workspace/1.clkmgr_clk_status/latest

Test location /workspace/coverage/default/1.clkmgr_extclk.2028305711
Short name T595
Test name
Test status
Simulation time 49403029 ps
CPU time 0.83 seconds
Started Aug 07 05:01:55 PM PDT 24
Finished Aug 07 05:01:56 PM PDT 24
Peak memory 201104 kb
Host smart-756c0e2e-da59-4567-b4dd-8b8fd93de9ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028305711 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.2028305711
Directory /workspace/1.clkmgr_extclk/latest

Test location /workspace/coverage/default/1.clkmgr_frequency.3322340482
Short name T649
Test name
Test status
Simulation time 1042535477 ps
CPU time 7.91 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 201016 kb
Host smart-49139f11-d721-47e5-9b28-ea6d6d51b75d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322340482 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.3322340482
Directory /workspace/1.clkmgr_frequency/latest

Test location /workspace/coverage/default/1.clkmgr_frequency_timeout.296183667
Short name T693
Test name
Test status
Simulation time 874354246 ps
CPU time 4.32 seconds
Started Aug 07 05:01:54 PM PDT 24
Finished Aug 07 05:01:59 PM PDT 24
Peak memory 201132 kb
Host smart-393e891f-3ffc-4962-b9ea-a110626189ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296183667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_tim
eout.296183667
Directory /workspace/1.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/1.clkmgr_idle_intersig_mubi.2817816587
Short name T261
Test name
Test status
Simulation time 42644042 ps
CPU time 1.05 seconds
Started Aug 07 05:02:05 PM PDT 24
Finished Aug 07 05:02:06 PM PDT 24
Peak memory 201140 kb
Host smart-5449fa24-316f-4b0d-afcb-852328e645c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817816587 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_idle_intersig_mubi.2817816587
Directory /workspace/1.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.3655090241
Short name T545
Test name
Test status
Simulation time 48551292 ps
CPU time 0.86 seconds
Started Aug 07 05:02:04 PM PDT 24
Finished Aug 07 05:02:05 PM PDT 24
Peak memory 201076 kb
Host smart-33bf8b66-f32e-4f95-abda-422917db2765
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655090241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_clk_byp_req_intersig_mubi.3655090241
Directory /workspace/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.2816002463
Short name T667
Test name
Test status
Simulation time 61566444 ps
CPU time 0.96 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 201040 kb
Host smart-2571b890-93c7-4bcd-b0e1-acaeb98d8a51
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816002463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 1.clkmgr_lc_ctrl_intersig_mubi.2816002463
Directory /workspace/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/1.clkmgr_peri.2923676254
Short name T80
Test name
Test status
Simulation time 62249274 ps
CPU time 0.94 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 201088 kb
Host smart-248a20ad-be21-4fe2-9e79-6becaa0d227f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923676254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2923676254
Directory /workspace/1.clkmgr_peri/latest

Test location /workspace/coverage/default/1.clkmgr_regwen.1744482529
Short name T179
Test name
Test status
Simulation time 467956903 ps
CPU time 3.15 seconds
Started Aug 07 05:02:03 PM PDT 24
Finished Aug 07 05:02:07 PM PDT 24
Peak memory 201096 kb
Host smart-dc992595-f3da-4108-bb46-5e87b460aade
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744482529 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1744482529
Directory /workspace/1.clkmgr_regwen/latest

Test location /workspace/coverage/default/1.clkmgr_smoke.2650405583
Short name T201
Test name
Test status
Simulation time 25254923 ps
CPU time 0.86 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 201064 kb
Host smart-3418eb2c-f79c-4b17-952b-e50f6ba6302c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650405583 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.2650405583
Directory /workspace/1.clkmgr_smoke/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all.449585896
Short name T236
Test name
Test status
Simulation time 102249717 ps
CPU time 1.08 seconds
Started Aug 07 05:02:03 PM PDT 24
Finished Aug 07 05:02:04 PM PDT 24
Peak memory 201080 kb
Host smart-30967585-1d4d-4630-bf28-ec85bd20ab0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449585896 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.clkmgr_stress_all.449585896
Directory /workspace/1.clkmgr_stress_all/latest

Test location /workspace/coverage/default/1.clkmgr_stress_all_with_rand_reset.3580995620
Short name T75
Test name
Test status
Simulation time 362336201320 ps
CPU time 1478.07 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:26:38 PM PDT 24
Peak memory 209756 kb
Host smart-85878585-1afb-4247-91eb-751852dbb5fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3580995620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3580995620
Directory /workspace/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.clkmgr_trans.2652330840
Short name T775
Test name
Test status
Simulation time 98676597 ps
CPU time 1.19 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:04 PM PDT 24
Peak memory 201120 kb
Host smart-debc9cfa-5889-4dc4-b8c0-6ad7541b14b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652330840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.2652330840
Directory /workspace/1.clkmgr_trans/latest

Test location /workspace/coverage/default/10.clkmgr_alert_test.1729124074
Short name T415
Test name
Test status
Simulation time 15100042 ps
CPU time 0.7 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201064 kb
Host smart-22cd2aa9-167d-427e-8c0d-a93defe70a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729124074 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clk
mgr_alert_test.1729124074
Directory /workspace/10.clkmgr_alert_test/latest

Test location /workspace/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.1726099071
Short name T449
Test name
Test status
Simulation time 25398164 ps
CPU time 0.98 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201048 kb
Host smart-0e223274-a184-48c0-8f28-62ca2a9f4792
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726099071 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_clk_handshake_intersig_mubi.1726099071
Directory /workspace/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_clk_status.1405798135
Short name T793
Test name
Test status
Simulation time 40203194 ps
CPU time 0.74 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 200944 kb
Host smart-42cc2c0a-935c-4fb0-a5ec-d2b57e8f5de0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405798135 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.1405798135
Directory /workspace/10.clkmgr_clk_status/latest

Test location /workspace/coverage/default/10.clkmgr_div_intersig_mubi.1198489226
Short name T165
Test name
Test status
Simulation time 46103437 ps
CPU time 0.88 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201132 kb
Host smart-07644583-79e3-4e45-9851-6fd9fb7ffad0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198489226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_div_intersig_mubi.1198489226
Directory /workspace/10.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_extclk.954746760
Short name T373
Test name
Test status
Simulation time 48401495 ps
CPU time 0.82 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 201028 kb
Host smart-1c0326af-382e-44f8-b214-5443437678b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954746760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.954746760
Directory /workspace/10.clkmgr_extclk/latest

Test location /workspace/coverage/default/10.clkmgr_frequency.1775381944
Short name T366
Test name
Test status
Simulation time 1516569378 ps
CPU time 11.37 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:40 PM PDT 24
Peak memory 201124 kb
Host smart-b183a0ae-1f22-433a-9978-f3a9de9457b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775381944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.1775381944
Directory /workspace/10.clkmgr_frequency/latest

Test location /workspace/coverage/default/10.clkmgr_frequency_timeout.3275650446
Short name T259
Test name
Test status
Simulation time 1712269083 ps
CPU time 7.04 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201112 kb
Host smart-b3b9fd40-0c7d-45fb-9548-cd61ac8f3981
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275650446 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_t
imeout.3275650446
Directory /workspace/10.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/10.clkmgr_idle_intersig_mubi.168827099
Short name T304
Test name
Test status
Simulation time 27766984 ps
CPU time 0.93 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201092 kb
Host smart-36d59eb2-76da-4718-b6e2-5ecb1f9ce20d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168827099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.clkmgr_idle_intersig_mubi.168827099
Directory /workspace/10.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1373087973
Short name T227
Test name
Test status
Simulation time 18977922 ps
CPU time 0.85 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201040 kb
Host smart-2914a4c3-e973-48de-9543-e58c382128b1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373087973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 10.clkmgr_lc_clk_byp_req_intersig_mubi.1373087973
Directory /workspace/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.12624854
Short name T258
Test name
Test status
Simulation time 28597301 ps
CPU time 0.84 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201092 kb
Host smart-d8048ce5-e76a-44ce-9f1e-08e7c265f186
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12624854 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_lc_ctrl_intersig_mubi.12624854
Directory /workspace/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/10.clkmgr_peri.953850245
Short name T274
Test name
Test status
Simulation time 15193034 ps
CPU time 0.73 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 201012 kb
Host smart-0ffd7bcc-857f-4318-876f-95390ba98297
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953850245 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.953850245
Directory /workspace/10.clkmgr_peri/latest

Test location /workspace/coverage/default/10.clkmgr_regwen.1656988253
Short name T600
Test name
Test status
Simulation time 110610364 ps
CPU time 1.05 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 200960 kb
Host smart-42c452aa-b644-40f9-bdb7-18878d7cf3ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656988253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.1656988253
Directory /workspace/10.clkmgr_regwen/latest

Test location /workspace/coverage/default/10.clkmgr_smoke.2763877286
Short name T455
Test name
Test status
Simulation time 15115519 ps
CPU time 0.76 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201056 kb
Host smart-0d662866-90f8-4e24-aabf-e137debada6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763877286 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.2763877286
Directory /workspace/10.clkmgr_smoke/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all.540032495
Short name T530
Test name
Test status
Simulation time 7513541517 ps
CPU time 31.33 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201504 kb
Host smart-1fb9be98-f225-4927-b8e6-4c464dfcd23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540032495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.clkmgr_stress_all.540032495
Directory /workspace/10.clkmgr_stress_all/latest

Test location /workspace/coverage/default/10.clkmgr_stress_all_with_rand_reset.1088066797
Short name T9
Test name
Test status
Simulation time 94870151917 ps
CPU time 575.4 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:12:04 PM PDT 24
Peak memory 209716 kb
Host smart-e03958e0-00d1-4848-b545-7f373957edfa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1088066797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.1088066797
Directory /workspace/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.clkmgr_trans.1903462353
Short name T223
Test name
Test status
Simulation time 31718820 ps
CPU time 0.98 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201056 kb
Host smart-b3c6fb75-8a6d-4a99-9407-edb689f92704
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903462353 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.1903462353
Directory /workspace/10.clkmgr_trans/latest

Test location /workspace/coverage/default/11.clkmgr_alert_test.446849379
Short name T682
Test name
Test status
Simulation time 32071024 ps
CPU time 0.78 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 200980 kb
Host smart-bd1e0bf7-5bd6-459c-b2f9-7e5c1c37a3f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446849379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkm
gr_alert_test.446849379
Directory /workspace/11.clkmgr_alert_test/latest

Test location /workspace/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2818103292
Short name T395
Test name
Test status
Simulation time 23633822 ps
CPU time 0.89 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201104 kb
Host smart-0a957c71-c4ff-4172-8dda-ec56b1aff401
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818103292 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_clk_handshake_intersig_mubi.2818103292
Directory /workspace/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_div_intersig_mubi.4158709091
Short name T623
Test name
Test status
Simulation time 21556190 ps
CPU time 0.86 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201112 kb
Host smart-9a5ec151-4194-4950-a916-0dfc5175f903
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158709091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_div_intersig_mubi.4158709091
Directory /workspace/11.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_extclk.2256204036
Short name T374
Test name
Test status
Simulation time 61354842 ps
CPU time 0.91 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 201028 kb
Host smart-11f8b195-768b-456d-9da8-fd00baee9891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256204036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.2256204036
Directory /workspace/11.clkmgr_extclk/latest

Test location /workspace/coverage/default/11.clkmgr_frequency.4090942145
Short name T356
Test name
Test status
Simulation time 1107393414 ps
CPU time 5.4 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201148 kb
Host smart-0f10a20d-61e4-4484-ae96-820193dace7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090942145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.4090942145
Directory /workspace/11.clkmgr_frequency/latest

Test location /workspace/coverage/default/11.clkmgr_frequency_timeout.972944630
Short name T668
Test name
Test status
Simulation time 1224938215 ps
CPU time 6.43 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201180 kb
Host smart-41b26428-982c-42c8-a2a4-72ce9dbc7dac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972944630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_ti
meout.972944630
Directory /workspace/11.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/11.clkmgr_idle_intersig_mubi.963888282
Short name T42
Test name
Test status
Simulation time 22931698 ps
CPU time 0.74 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201088 kb
Host smart-80932c75-8261-4912-8cbc-4f908c41b15d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963888282 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.clkmgr_idle_intersig_mubi.963888282
Directory /workspace/11.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.59358295
Short name T458
Test name
Test status
Simulation time 21179704 ps
CPU time 0.77 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201084 kb
Host smart-4c5e7027-51b1-4382-8225-531d6c4558d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59358295 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_lc_clk_byp_req_intersig_mubi.59358295
Directory /workspace/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.1115959403
Short name T402
Test name
Test status
Simulation time 22649783 ps
CPU time 0.82 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 201084 kb
Host smart-7c3cc394-2bab-4cbe-b068-6e4a394530f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115959403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 11.clkmgr_lc_ctrl_intersig_mubi.1115959403
Directory /workspace/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/11.clkmgr_peri.1099896225
Short name T589
Test name
Test status
Simulation time 23939809 ps
CPU time 0.74 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 200220 kb
Host smart-3328c4de-8b48-43e2-a756-d2bafa000a13
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099896225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.1099896225
Directory /workspace/11.clkmgr_peri/latest

Test location /workspace/coverage/default/11.clkmgr_regwen.2769800275
Short name T703
Test name
Test status
Simulation time 1528962453 ps
CPU time 5.26 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201252 kb
Host smart-5dd7f5f7-4dd7-4612-8610-765ce8514484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769800275 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2769800275
Directory /workspace/11.clkmgr_regwen/latest

Test location /workspace/coverage/default/11.clkmgr_smoke.3549821085
Short name T412
Test name
Test status
Simulation time 26089996 ps
CPU time 0.87 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201032 kb
Host smart-2b8cfdfe-6509-4d65-8dc4-10686d68f8b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549821085 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.3549821085
Directory /workspace/11.clkmgr_smoke/latest

Test location /workspace/coverage/default/11.clkmgr_stress_all.4158182564
Short name T518
Test name
Test status
Simulation time 11169843251 ps
CPU time 81.86 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201480 kb
Host smart-f7c30241-3a2e-475e-8a01-de7a967c6ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158182564 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.clkmgr_stress_all.4158182564
Directory /workspace/11.clkmgr_stress_all/latest

Test location /workspace/coverage/default/11.clkmgr_trans.3318987205
Short name T810
Test name
Test status
Simulation time 294015379 ps
CPU time 1.87 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201052 kb
Host smart-f67d6f77-d6c2-4d39-9660-ff75cf6df5df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318987205 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.3318987205
Directory /workspace/11.clkmgr_trans/latest

Test location /workspace/coverage/default/12.clkmgr_alert_test.2535785641
Short name T406
Test name
Test status
Simulation time 26235820 ps
CPU time 0.75 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201052 kb
Host smart-74741720-3ff4-4b27-a9d8-44e4077ed1b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535785641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clk
mgr_alert_test.2535785641
Directory /workspace/12.clkmgr_alert_test/latest

Test location /workspace/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.3322646980
Short name T107
Test name
Test status
Simulation time 79539071 ps
CPU time 1.07 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201092 kb
Host smart-c51bdcdf-f7df-479d-bb48-cf96322e644c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322646980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_clk_handshake_intersig_mubi.3322646980
Directory /workspace/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_clk_status.3484117952
Short name T57
Test name
Test status
Simulation time 34880522 ps
CPU time 0.78 seconds
Started Aug 07 05:02:33 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 200280 kb
Host smart-8dfec3ab-f82c-4715-a074-a545ec66d28e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484117952 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.3484117952
Directory /workspace/12.clkmgr_clk_status/latest

Test location /workspace/coverage/default/12.clkmgr_div_intersig_mubi.1137671274
Short name T663
Test name
Test status
Simulation time 44839267 ps
CPU time 0.99 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 200960 kb
Host smart-34d7cfc1-407c-4a99-a3e7-27e709f055ee
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137671274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_div_intersig_mubi.1137671274
Directory /workspace/12.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_extclk.3383407278
Short name T268
Test name
Test status
Simulation time 74757993 ps
CPU time 1.08 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201076 kb
Host smart-aa2c720f-4458-4a13-956e-fec6bf177bc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383407278 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.3383407278
Directory /workspace/12.clkmgr_extclk/latest

Test location /workspace/coverage/default/12.clkmgr_frequency.1263531744
Short name T440
Test name
Test status
Simulation time 1650940664 ps
CPU time 9.51 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201160 kb
Host smart-97411bfa-e4c4-43fa-9dae-e287acf96fd6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263531744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.1263531744
Directory /workspace/12.clkmgr_frequency/latest

Test location /workspace/coverage/default/12.clkmgr_frequency_timeout.2257822565
Short name T88
Test name
Test status
Simulation time 1218937382 ps
CPU time 6.77 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 200364 kb
Host smart-9def5abc-459e-4861-ad97-a119e533c1f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257822565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_t
imeout.2257822565
Directory /workspace/12.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/12.clkmgr_idle_intersig_mubi.1449550118
Short name T220
Test name
Test status
Simulation time 34231026 ps
CPU time 0.98 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201060 kb
Host smart-7698e759-af7d-484c-bc84-cf6b24dc5ff9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449550118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_idle_intersig_mubi.1449550118
Directory /workspace/12.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.1294827183
Short name T640
Test name
Test status
Simulation time 24051508 ps
CPU time 0.86 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201040 kb
Host smart-4cf6d9b8-498f-4b8f-8bb0-7845af88150a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294827183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_clk_byp_req_intersig_mubi.1294827183
Directory /workspace/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.2768876291
Short name T749
Test name
Test status
Simulation time 188275250 ps
CPU time 1.23 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 201016 kb
Host smart-0ba191ed-bb65-46cf-9aaa-de95d9eb74e1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768876291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 12.clkmgr_lc_ctrl_intersig_mubi.2768876291
Directory /workspace/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/12.clkmgr_peri.464955842
Short name T571
Test name
Test status
Simulation time 20825723 ps
CPU time 0.72 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 200244 kb
Host smart-ff54a714-dbfa-4390-b4d0-a1d7a8830522
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464955842 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.464955842
Directory /workspace/12.clkmgr_peri/latest

Test location /workspace/coverage/default/12.clkmgr_regwen.733755658
Short name T681
Test name
Test status
Simulation time 168965155 ps
CPU time 1.55 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201060 kb
Host smart-ac2d4817-82dd-438d-902d-343a7aa3a304
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733755658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.733755658
Directory /workspace/12.clkmgr_regwen/latest

Test location /workspace/coverage/default/12.clkmgr_smoke.1195586125
Short name T633
Test name
Test status
Simulation time 60123301 ps
CPU time 0.97 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 201056 kb
Host smart-7088e7db-9971-403f-a3f1-5e7540b474d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195586125 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1195586125
Directory /workspace/12.clkmgr_smoke/latest

Test location /workspace/coverage/default/12.clkmgr_stress_all.2774382044
Short name T777
Test name
Test status
Simulation time 6861718430 ps
CPU time 48 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201456 kb
Host smart-a4b4285e-7383-4669-bf46-b5c5c941e0fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774382044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.clkmgr_stress_all.2774382044
Directory /workspace/12.clkmgr_stress_all/latest

Test location /workspace/coverage/default/12.clkmgr_trans.1863783804
Short name T451
Test name
Test status
Simulation time 126680983 ps
CPU time 1.04 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 200964 kb
Host smart-4b30a0e3-b9f9-4827-9bad-712eaf93d74a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863783804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.1863783804
Directory /workspace/12.clkmgr_trans/latest

Test location /workspace/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.1809901183
Short name T117
Test name
Test status
Simulation time 43358926 ps
CPU time 0.86 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201056 kb
Host smart-12dc1e44-1b85-4e03-a828-b3c484135f8c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809901183 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_clk_handshake_intersig_mubi.1809901183
Directory /workspace/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_clk_status.3439735492
Short name T544
Test name
Test status
Simulation time 42001454 ps
CPU time 0.83 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 200260 kb
Host smart-b3d2677a-f839-47fd-9619-37140945e7bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439735492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.3439735492
Directory /workspace/13.clkmgr_clk_status/latest

Test location /workspace/coverage/default/13.clkmgr_div_intersig_mubi.1089028221
Short name T357
Test name
Test status
Simulation time 16666222 ps
CPU time 0.75 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201088 kb
Host smart-9b697b11-181b-45eb-8592-d677fd621274
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089028221 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_div_intersig_mubi.1089028221
Directory /workspace/13.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_extclk.3868247522
Short name T58
Test name
Test status
Simulation time 16214485 ps
CPU time 0.81 seconds
Started Aug 07 05:02:29 PM PDT 24
Finished Aug 07 05:02:30 PM PDT 24
Peak memory 201084 kb
Host smart-cd966cc4-dfc4-46ed-a4e9-8e0ac8b07127
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868247522 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.3868247522
Directory /workspace/13.clkmgr_extclk/latest

Test location /workspace/coverage/default/13.clkmgr_frequency.2993896840
Short name T376
Test name
Test status
Simulation time 457822501 ps
CPU time 2.59 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201056 kb
Host smart-5d5778d4-847d-4589-a7f0-73bfb56120b5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993896840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.2993896840
Directory /workspace/13.clkmgr_frequency/latest

Test location /workspace/coverage/default/13.clkmgr_frequency_timeout.3041254177
Short name T742
Test name
Test status
Simulation time 1847927299 ps
CPU time 6.1 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:34 PM PDT 24
Peak memory 201228 kb
Host smart-b2edcd3f-cb70-40cf-8d66-c301825dc48a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041254177 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_t
imeout.3041254177
Directory /workspace/13.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/13.clkmgr_idle_intersig_mubi.3709094473
Short name T759
Test name
Test status
Simulation time 36880181 ps
CPU time 1.03 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 201060 kb
Host smart-584c7931-5ce8-4b43-9d5f-30bffa49bd5b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709094473 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_idle_intersig_mubi.3709094473
Directory /workspace/13.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.1784530838
Short name T608
Test name
Test status
Simulation time 40514029 ps
CPU time 0.81 seconds
Started Aug 07 05:02:30 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 200988 kb
Host smart-530730bd-b8d2-40e1-ba1b-41ca73747b6c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784530838 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 13.clkmgr_lc_clk_byp_req_intersig_mubi.1784530838
Directory /workspace/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.829220367
Short name T730
Test name
Test status
Simulation time 53752724 ps
CPU time 0.81 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 200996 kb
Host smart-f4380ca4-7222-40b7-9756-b628cc49c1ff
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829220367 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.clkmgr_lc_ctrl_intersig_mubi.829220367
Directory /workspace/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/13.clkmgr_peri.1003982926
Short name T334
Test name
Test status
Simulation time 16679117 ps
CPU time 0.75 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201068 kb
Host smart-4d821b97-cfa2-432c-9b93-09dcaae79a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003982926 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.1003982926
Directory /workspace/13.clkmgr_peri/latest

Test location /workspace/coverage/default/13.clkmgr_smoke.1763930242
Short name T763
Test name
Test status
Simulation time 111675533 ps
CPU time 1.17 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:34 PM PDT 24
Peak memory 201044 kb
Host smart-a3a40734-d2da-45aa-906c-1491a834773d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763930242 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.1763930242
Directory /workspace/13.clkmgr_smoke/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all.1817356774
Short name T273
Test name
Test status
Simulation time 9400407750 ps
CPU time 68.8 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201464 kb
Host smart-09a7e306-fdbd-44c2-81be-f39c916d0337
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817356774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.clkmgr_stress_all.1817356774
Directory /workspace/13.clkmgr_stress_all/latest

Test location /workspace/coverage/default/13.clkmgr_stress_all_with_rand_reset.1107848472
Short name T629
Test name
Test status
Simulation time 48945988589 ps
CPU time 530.04 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:11:22 PM PDT 24
Peak memory 217904 kb
Host smart-3d6826e1-b2bf-4400-8a47-8d78328d75f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1107848472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.1107848472
Directory /workspace/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.clkmgr_trans.2758503752
Short name T97
Test name
Test status
Simulation time 226136307 ps
CPU time 1.53 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201080 kb
Host smart-aea19c95-1d8b-4fd5-a897-7b95042a1f91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758503752 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.2758503752
Directory /workspace/13.clkmgr_trans/latest

Test location /workspace/coverage/default/14.clkmgr_alert_test.3511239202
Short name T652
Test name
Test status
Simulation time 25943716 ps
CPU time 0.81 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201076 kb
Host smart-114bb924-90c4-49b5-8b7d-16247e4b39f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511239202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clk
mgr_alert_test.3511239202
Directory /workspace/14.clkmgr_alert_test/latest

Test location /workspace/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.2458405099
Short name T187
Test name
Test status
Simulation time 93346348 ps
CPU time 1.04 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 201148 kb
Host smart-f2cff41f-4262-4e9c-84e6-de0084eb140c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458405099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_clk_handshake_intersig_mubi.2458405099
Directory /workspace/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_clk_status.1157970953
Short name T635
Test name
Test status
Simulation time 13949574 ps
CPU time 0.7 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 200220 kb
Host smart-5d27e136-0e67-4432-ac51-62c4b5daa2ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157970953 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.1157970953
Directory /workspace/14.clkmgr_clk_status/latest

Test location /workspace/coverage/default/14.clkmgr_div_intersig_mubi.307652862
Short name T602
Test name
Test status
Simulation time 23420125 ps
CPU time 0.79 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 201124 kb
Host smart-be47d394-19d7-4b5b-a2df-4aecc3aa3c98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307652862 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.clkmgr_div_intersig_mubi.307652862
Directory /workspace/14.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_extclk.3142516170
Short name T479
Test name
Test status
Simulation time 25038003 ps
CPU time 0.87 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 201004 kb
Host smart-7dc43c40-b05d-4454-90db-ebbaf963339c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142516170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.3142516170
Directory /workspace/14.clkmgr_extclk/latest

Test location /workspace/coverage/default/14.clkmgr_frequency.1279780707
Short name T587
Test name
Test status
Simulation time 2362131880 ps
CPU time 18.1 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:02:51 PM PDT 24
Peak memory 201420 kb
Host smart-566328eb-aebc-4324-9d24-52a7d8e16e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279780707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.1279780707
Directory /workspace/14.clkmgr_frequency/latest

Test location /workspace/coverage/default/14.clkmgr_frequency_timeout.4265267810
Short name T583
Test name
Test status
Simulation time 2071148104 ps
CPU time 10.34 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:47 PM PDT 24
Peak memory 201392 kb
Host smart-6dd1d76d-b165-463e-b522-0f1a550d04de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265267810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_t
imeout.4265267810
Directory /workspace/14.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/14.clkmgr_idle_intersig_mubi.3076912321
Short name T314
Test name
Test status
Simulation time 95853902 ps
CPU time 1.15 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201108 kb
Host smart-1106791c-7238-48f4-84f4-f37af13d95c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076912321 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_idle_intersig_mubi.3076912321
Directory /workspace/14.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.1994101159
Short name T186
Test name
Test status
Simulation time 108374225 ps
CPU time 1.09 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 201080 kb
Host smart-d2f01f1e-f050-4dcd-b601-106f0c2a765f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994101159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 14.clkmgr_lc_clk_byp_req_intersig_mubi.1994101159
Directory /workspace/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.638832764
Short name T546
Test name
Test status
Simulation time 55395360 ps
CPU time 0.91 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201076 kb
Host smart-31650e7c-8a31-4b6e-ba4f-8c98d271ba6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638832764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.clkmgr_lc_ctrl_intersig_mubi.638832764
Directory /workspace/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/14.clkmgr_peri.903028975
Short name T255
Test name
Test status
Simulation time 12871832 ps
CPU time 0.74 seconds
Started Aug 07 05:02:31 PM PDT 24
Finished Aug 07 05:02:32 PM PDT 24
Peak memory 201056 kb
Host smart-4a7dd525-f76b-42a0-a72b-162df53b9c78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903028975 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.903028975
Directory /workspace/14.clkmgr_peri/latest

Test location /workspace/coverage/default/14.clkmgr_regwen.2970618849
Short name T572
Test name
Test status
Simulation time 1238518753 ps
CPU time 6.71 seconds
Started Aug 07 05:02:33 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201248 kb
Host smart-01d37728-1869-45bf-a481-5ec637e25ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970618849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2970618849
Directory /workspace/14.clkmgr_regwen/latest

Test location /workspace/coverage/default/14.clkmgr_smoke.1189484274
Short name T160
Test name
Test status
Simulation time 78599463 ps
CPU time 1.03 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201048 kb
Host smart-61823684-3c6e-4d86-b3ef-fe3c8c0e88ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189484274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1189484274
Directory /workspace/14.clkmgr_smoke/latest

Test location /workspace/coverage/default/14.clkmgr_stress_all.2418142386
Short name T537
Test name
Test status
Simulation time 9973788758 ps
CPU time 43.39 seconds
Started Aug 07 05:02:32 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201472 kb
Host smart-769e9c12-7dae-4098-9f28-9e1d4a20b613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418142386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.clkmgr_stress_all.2418142386
Directory /workspace/14.clkmgr_stress_all/latest

Test location /workspace/coverage/default/14.clkmgr_trans.4266130441
Short name T773
Test name
Test status
Simulation time 44002558 ps
CPU time 0.93 seconds
Started Aug 07 05:02:28 PM PDT 24
Finished Aug 07 05:02:29 PM PDT 24
Peak memory 201052 kb
Host smart-537301a0-8267-46a9-9a78-f553c5a60e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266130441 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.4266130441
Directory /workspace/14.clkmgr_trans/latest

Test location /workspace/coverage/default/15.clkmgr_alert_test.2751894030
Short name T31
Test name
Test status
Simulation time 21000033 ps
CPU time 0.78 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 201140 kb
Host smart-097e82b8-9ee1-486f-8fd0-66819ad97b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751894030 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clk
mgr_alert_test.2751894030
Directory /workspace/15.clkmgr_alert_test/latest

Test location /workspace/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.431987886
Short name T467
Test name
Test status
Simulation time 77688987 ps
CPU time 1.01 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201128 kb
Host smart-372aeaf4-f302-4d38-b539-8b60f8853257
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431987886 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_clk_handshake_intersig_mubi.431987886
Directory /workspace/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_clk_status.2687372283
Short name T707
Test name
Test status
Simulation time 44251585 ps
CPU time 0.81 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 200292 kb
Host smart-d3ca0e14-b1ec-4d4a-b355-7408def73b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687372283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.2687372283
Directory /workspace/15.clkmgr_clk_status/latest

Test location /workspace/coverage/default/15.clkmgr_div_intersig_mubi.384769848
Short name T190
Test name
Test status
Simulation time 188232349 ps
CPU time 1.27 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201040 kb
Host smart-1fafec77-60da-4841-82df-4f106172e410
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384769848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_div_intersig_mubi.384769848
Directory /workspace/15.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_extclk.3723216638
Short name T806
Test name
Test status
Simulation time 41328924 ps
CPU time 0.94 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 200996 kb
Host smart-5a16bbdd-6035-4bec-b9fa-5325ed8fc947
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723216638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3723216638
Directory /workspace/15.clkmgr_extclk/latest

Test location /workspace/coverage/default/15.clkmgr_frequency.89706249
Short name T672
Test name
Test status
Simulation time 1277916529 ps
CPU time 10.3 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:45 PM PDT 24
Peak memory 201024 kb
Host smart-4a140e68-13bc-41a6-99ff-a932ec64992c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89706249 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.89706249
Directory /workspace/15.clkmgr_frequency/latest

Test location /workspace/coverage/default/15.clkmgr_frequency_timeout.3788310672
Short name T235
Test name
Test status
Simulation time 2755589187 ps
CPU time 9.21 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201468 kb
Host smart-632d2dbc-1525-4a79-b093-44ff441e90ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788310672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_t
imeout.3788310672
Directory /workspace/15.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/15.clkmgr_idle_intersig_mubi.951707622
Short name T677
Test name
Test status
Simulation time 114114792 ps
CPU time 1.25 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 200944 kb
Host smart-6d8da06f-bcb2-4eef-8560-481e79090f09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951707622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
5.clkmgr_idle_intersig_mubi.951707622
Directory /workspace/15.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.1658956111
Short name T163
Test name
Test status
Simulation time 92536608 ps
CPU time 1.1 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201108 kb
Host smart-04961a2c-2a3a-486c-958f-602a9eecad1d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658956111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 15.clkmgr_lc_clk_byp_req_intersig_mubi.1658956111
Directory /workspace/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.92950105
Short name T233
Test name
Test status
Simulation time 31583278 ps
CPU time 0.95 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201092 kb
Host smart-f55e652f-1f05-464f-8230-e8d6b6db93c1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92950105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_lc_ctrl_intersig_mubi.92950105
Directory /workspace/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/15.clkmgr_peri.1469688934
Short name T83
Test name
Test status
Simulation time 15962631 ps
CPU time 0.73 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 200960 kb
Host smart-d046d52e-a6dd-41b6-ab3f-87f3289e9877
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469688934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.1469688934
Directory /workspace/15.clkmgr_peri/latest

Test location /workspace/coverage/default/15.clkmgr_regwen.1947672020
Short name T634
Test name
Test status
Simulation time 223035873 ps
CPU time 1.77 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 201084 kb
Host smart-0abf7d6c-cbf4-4b20-a91f-42335fbf3d87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947672020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.1947672020
Directory /workspace/15.clkmgr_regwen/latest

Test location /workspace/coverage/default/15.clkmgr_smoke.1949920654
Short name T557
Test name
Test status
Simulation time 18767578 ps
CPU time 0.8 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 200920 kb
Host smart-4cbbca42-9ed5-4965-9f1c-4398bb2caacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949920654 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1949920654
Directory /workspace/15.clkmgr_smoke/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all.100954565
Short name T688
Test name
Test status
Simulation time 3909303576 ps
CPU time 28.26 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201376 kb
Host smart-c9eca1c9-ad99-41de-9e5a-90e4dec9b609
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100954565 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.clkmgr_stress_all.100954565
Directory /workspace/15.clkmgr_stress_all/latest

Test location /workspace/coverage/default/15.clkmgr_stress_all_with_rand_reset.3831265228
Short name T74
Test name
Test status
Simulation time 44327655938 ps
CPU time 249.58 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:06:43 PM PDT 24
Peak memory 217908 kb
Host smart-a44e16ac-19eb-4625-a07a-b0e185247f5d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3831265228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.3831265228
Directory /workspace/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.clkmgr_trans.184112413
Short name T462
Test name
Test status
Simulation time 44310663 ps
CPU time 0.95 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 201104 kb
Host smart-57e55389-ff03-4ab0-80fe-fd3d61f75c88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184112413 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.184112413
Directory /workspace/15.clkmgr_trans/latest

Test location /workspace/coverage/default/16.clkmgr_alert_test.849055042
Short name T785
Test name
Test status
Simulation time 19130370 ps
CPU time 0.83 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201084 kb
Host smart-191d8c4d-9abc-4822-823b-521ddb4b2c32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849055042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkm
gr_alert_test.849055042
Directory /workspace/16.clkmgr_alert_test/latest

Test location /workspace/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.1991837086
Short name T47
Test name
Test status
Simulation time 52800044 ps
CPU time 0.9 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 200996 kb
Host smart-86e6dce9-43d4-455b-ae62-e104bc159935
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991837086 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_clk_handshake_intersig_mubi.1991837086
Directory /workspace/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_clk_status.2107368128
Short name T438
Test name
Test status
Simulation time 22520015 ps
CPU time 0.74 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201028 kb
Host smart-43fd343a-0070-474c-8ae7-bf08b2b09683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107368128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.2107368128
Directory /workspace/16.clkmgr_clk_status/latest

Test location /workspace/coverage/default/16.clkmgr_div_intersig_mubi.1685387460
Short name T246
Test name
Test status
Simulation time 108793278 ps
CPU time 1.15 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201116 kb
Host smart-cf6021aa-7f12-4910-8b83-2c0421daeea2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685387460 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_div_intersig_mubi.1685387460
Directory /workspace/16.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_extclk.742620749
Short name T229
Test name
Test status
Simulation time 14752196 ps
CPU time 0.73 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201048 kb
Host smart-0dd8dc3e-56d2-4b60-aae6-6b495443552b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742620749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.742620749
Directory /workspace/16.clkmgr_extclk/latest

Test location /workspace/coverage/default/16.clkmgr_frequency.245297651
Short name T611
Test name
Test status
Simulation time 915868453 ps
CPU time 7.34 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:48 PM PDT 24
Peak memory 201100 kb
Host smart-55942baf-99bb-433d-a4dc-7ffd03019ef2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245297651 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.245297651
Directory /workspace/16.clkmgr_frequency/latest

Test location /workspace/coverage/default/16.clkmgr_frequency_timeout.2730705841
Short name T554
Test name
Test status
Simulation time 2062122274 ps
CPU time 14.08 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:49 PM PDT 24
Peak memory 201420 kb
Host smart-49054865-aabd-496a-be1b-6037e43073b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730705841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_t
imeout.2730705841
Directory /workspace/16.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/16.clkmgr_idle_intersig_mubi.2871640299
Short name T708
Test name
Test status
Simulation time 141748711 ps
CPU time 1.33 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201092 kb
Host smart-d16dfac7-ef9e-4c3c-8ac5-3166fc05d27d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871640299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_idle_intersig_mubi.2871640299
Directory /workspace/16.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.1359281974
Short name T570
Test name
Test status
Simulation time 16711669 ps
CPU time 0.76 seconds
Started Aug 07 05:02:35 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201040 kb
Host smart-823d77be-079f-4c76-9a5d-aca45f3749f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359281974 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_clk_byp_req_intersig_mubi.1359281974
Directory /workspace/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.2868728435
Short name T820
Test name
Test status
Simulation time 21804320 ps
CPU time 0.85 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:37 PM PDT 24
Peak memory 201152 kb
Host smart-717ec036-6b75-4c1f-9f3d-42f56b454be8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868728435 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 16.clkmgr_lc_ctrl_intersig_mubi.2868728435
Directory /workspace/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/16.clkmgr_peri.4177903341
Short name T343
Test name
Test status
Simulation time 17205173 ps
CPU time 0.72 seconds
Started Aug 07 05:02:39 PM PDT 24
Finished Aug 07 05:02:40 PM PDT 24
Peak memory 201028 kb
Host smart-9a4f8a8b-a88e-43bd-8cda-a6a04c378dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177903341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.4177903341
Directory /workspace/16.clkmgr_peri/latest

Test location /workspace/coverage/default/16.clkmgr_regwen.955163370
Short name T8
Test name
Test status
Simulation time 616351412 ps
CPU time 4.05 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:42 PM PDT 24
Peak memory 201328 kb
Host smart-12ce855d-4f09-4206-819d-3e013799bcfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955163370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.955163370
Directory /workspace/16.clkmgr_regwen/latest

Test location /workspace/coverage/default/16.clkmgr_smoke.1578958555
Short name T818
Test name
Test status
Simulation time 21528187 ps
CPU time 0.87 seconds
Started Aug 07 05:02:33 PM PDT 24
Finished Aug 07 05:02:34 PM PDT 24
Peak memory 201004 kb
Host smart-55e0b9d4-0961-4672-a1a1-90c38d6434e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578958555 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.1578958555
Directory /workspace/16.clkmgr_smoke/latest

Test location /workspace/coverage/default/16.clkmgr_stress_all.849192882
Short name T770
Test name
Test status
Simulation time 3102747683 ps
CPU time 17.11 seconds
Started Aug 07 05:02:46 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201324 kb
Host smart-7bfe7ea6-4bc9-4120-8cb3-b0abff25fe6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849192882 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.clkmgr_stress_all.849192882
Directory /workspace/16.clkmgr_stress_all/latest

Test location /workspace/coverage/default/16.clkmgr_trans.3331275548
Short name T609
Test name
Test status
Simulation time 256557868 ps
CPU time 1.66 seconds
Started Aug 07 05:02:34 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201076 kb
Host smart-44362d04-908c-4e17-bcbe-1db88e28173f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331275548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.3331275548
Directory /workspace/16.clkmgr_trans/latest

Test location /workspace/coverage/default/17.clkmgr_alert_test.2523741945
Short name T774
Test name
Test status
Simulation time 20960024 ps
CPU time 0.84 seconds
Started Aug 07 05:02:41 PM PDT 24
Finished Aug 07 05:02:42 PM PDT 24
Peak memory 201076 kb
Host smart-af84d4c5-0398-4d9b-8c13-4f82dc8bb52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523741945 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clk
mgr_alert_test.2523741945
Directory /workspace/17.clkmgr_alert_test/latest

Test location /workspace/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2872043399
Short name T540
Test name
Test status
Simulation time 65790157 ps
CPU time 0.86 seconds
Started Aug 07 05:02:39 PM PDT 24
Finished Aug 07 05:02:40 PM PDT 24
Peak memory 201116 kb
Host smart-d96488fb-352a-468a-8c34-a38ff40921b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872043399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_clk_handshake_intersig_mubi.2872043399
Directory /workspace/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_clk_status.2144134326
Short name T768
Test name
Test status
Simulation time 47768895 ps
CPU time 0.77 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 201012 kb
Host smart-0ed1b08b-9a3a-4490-b207-88f90d5f852d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144134326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.2144134326
Directory /workspace/17.clkmgr_clk_status/latest

Test location /workspace/coverage/default/17.clkmgr_div_intersig_mubi.827627762
Short name T309
Test name
Test status
Simulation time 54425904 ps
CPU time 0.88 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 201048 kb
Host smart-6b227883-60b8-46c0-a8eb-59d651b96380
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827627762 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_div_intersig_mubi.827627762
Directory /workspace/17.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_extclk.3858978497
Short name T234
Test name
Test status
Simulation time 69157320 ps
CPU time 1.03 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201052 kb
Host smart-69357074-8b75-4081-b3ec-b784fc5e0002
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858978497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.3858978497
Directory /workspace/17.clkmgr_extclk/latest

Test location /workspace/coverage/default/17.clkmgr_frequency.3922553803
Short name T591
Test name
Test status
Simulation time 561041270 ps
CPU time 3.77 seconds
Started Aug 07 05:02:39 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201068 kb
Host smart-27eda486-67bf-46dd-b1f4-df0630cc6f2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922553803 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.3922553803
Directory /workspace/17.clkmgr_frequency/latest

Test location /workspace/coverage/default/17.clkmgr_frequency_timeout.2993070533
Short name T5
Test name
Test status
Simulation time 501670519 ps
CPU time 4.28 seconds
Started Aug 07 05:02:36 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 201204 kb
Host smart-eed77a46-9b40-4c0e-a0c2-085f62ed4ced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993070533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_t
imeout.2993070533
Directory /workspace/17.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/17.clkmgr_idle_intersig_mubi.946948320
Short name T213
Test name
Test status
Simulation time 419057718 ps
CPU time 2.02 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 201040 kb
Host smart-d0077116-7920-4b1f-aac0-0e23f2fe6e38
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946948320 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.clkmgr_idle_intersig_mubi.946948320
Directory /workspace/17.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.3889870893
Short name T695
Test name
Test status
Simulation time 24340325 ps
CPU time 0.89 seconds
Started Aug 07 05:04:00 PM PDT 24
Finished Aug 07 05:04:01 PM PDT 24
Peak memory 200992 kb
Host smart-af0df9f3-3c34-4098-b876-42f50e2fb46e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889870893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_clk_byp_req_intersig_mubi.3889870893
Directory /workspace/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.2127967370
Short name T244
Test name
Test status
Simulation time 73653170 ps
CPU time 1.04 seconds
Started Aug 07 05:02:41 PM PDT 24
Finished Aug 07 05:02:42 PM PDT 24
Peak memory 201080 kb
Host smart-475852c0-9488-4623-8d83-8f8056b10430
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127967370 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 17.clkmgr_lc_ctrl_intersig_mubi.2127967370
Directory /workspace/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/17.clkmgr_peri.1812590744
Short name T716
Test name
Test status
Simulation time 16042520 ps
CPU time 0.75 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201092 kb
Host smart-d30a76ab-f3d4-4d3b-ad95-baeb015f32de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812590744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.1812590744
Directory /workspace/17.clkmgr_peri/latest

Test location /workspace/coverage/default/17.clkmgr_regwen.1241371985
Short name T219
Test name
Test status
Simulation time 642948945 ps
CPU time 3.08 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:40 PM PDT 24
Peak memory 201300 kb
Host smart-c941e8bd-b6c1-4d83-96a6-e3933fa533b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241371985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1241371985
Directory /workspace/17.clkmgr_regwen/latest

Test location /workspace/coverage/default/17.clkmgr_smoke.1831671963
Short name T817
Test name
Test status
Simulation time 19644829 ps
CPU time 0.84 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 200936 kb
Host smart-1eb38c79-ace5-4745-b6a3-16611e345ebd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831671963 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.1831671963
Directory /workspace/17.clkmgr_smoke/latest

Test location /workspace/coverage/default/17.clkmgr_stress_all.283131450
Short name T824
Test name
Test status
Simulation time 3820615060 ps
CPU time 25.17 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201348 kb
Host smart-075e8bea-1cb9-4919-aeb6-2541c3b143d1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283131450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.clkmgr_stress_all.283131450
Directory /workspace/17.clkmgr_stress_all/latest

Test location /workspace/coverage/default/17.clkmgr_trans.1766078054
Short name T297
Test name
Test status
Simulation time 31837439 ps
CPU time 1.04 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201012 kb
Host smart-131e3296-31ed-4a0b-b34b-a8fba2fde3a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766078054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.1766078054
Directory /workspace/17.clkmgr_trans/latest

Test location /workspace/coverage/default/18.clkmgr_alert_test.575294089
Short name T285
Test name
Test status
Simulation time 97824557 ps
CPU time 1.04 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201020 kb
Host smart-6ecee00d-8fe3-4b17-9a4b-437b8a9efd32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575294089 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkm
gr_alert_test.575294089
Directory /workspace/18.clkmgr_alert_test/latest

Test location /workspace/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.2528420994
Short name T647
Test name
Test status
Simulation time 26619106 ps
CPU time 0.91 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 201148 kb
Host smart-7dd5ef4d-5044-4730-92cf-f8a0ed0fd08f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528420994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_clk_handshake_intersig_mubi.2528420994
Directory /workspace/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_clk_status.1734056834
Short name T725
Test name
Test status
Simulation time 17171356 ps
CPU time 0.73 seconds
Started Aug 07 05:02:37 PM PDT 24
Finished Aug 07 05:02:38 PM PDT 24
Peak memory 200292 kb
Host smart-2bf00064-a2c0-422f-a822-df970cb22b40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734056834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.1734056834
Directory /workspace/18.clkmgr_clk_status/latest

Test location /workspace/coverage/default/18.clkmgr_div_intersig_mubi.3196001527
Short name T443
Test name
Test status
Simulation time 20562048 ps
CPU time 0.9 seconds
Started Aug 07 05:02:39 PM PDT 24
Finished Aug 07 05:02:40 PM PDT 24
Peak memory 201112 kb
Host smart-fa326ca8-79b6-48fb-8038-a8177426d409
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196001527 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_div_intersig_mubi.3196001527
Directory /workspace/18.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_extclk.3289202072
Short name T322
Test name
Test status
Simulation time 47556821 ps
CPU time 0.83 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 200904 kb
Host smart-e2607806-45fa-43c8-9b2a-c71b398b1e1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289202072 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.3289202072
Directory /workspace/18.clkmgr_extclk/latest

Test location /workspace/coverage/default/18.clkmgr_frequency.1669525216
Short name T534
Test name
Test status
Simulation time 1397524921 ps
CPU time 5.51 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201176 kb
Host smart-3eb7e4c8-2f73-4279-91a4-48dbfdf50754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669525216 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1669525216
Directory /workspace/18.clkmgr_frequency/latest

Test location /workspace/coverage/default/18.clkmgr_frequency_timeout.2431353775
Short name T325
Test name
Test status
Simulation time 2231366478 ps
CPU time 9.03 seconds
Started Aug 07 05:02:44 PM PDT 24
Finished Aug 07 05:02:53 PM PDT 24
Peak memory 201448 kb
Host smart-3d2f2f7d-5ecd-43fa-96c1-0b024d92b168
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431353775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_t
imeout.2431353775
Directory /workspace/18.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/18.clkmgr_idle_intersig_mubi.1963381068
Short name T221
Test name
Test status
Simulation time 17650195 ps
CPU time 0.77 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 201132 kb
Host smart-9ca3a5b2-7f46-4e5b-bb9f-ef43b30a8451
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963381068 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.clkmgr_idle_intersig_mubi.1963381068
Directory /workspace/18.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2685569866
Short name T252
Test name
Test status
Simulation time 19347809 ps
CPU time 0.82 seconds
Started Aug 07 05:02:44 PM PDT 24
Finished Aug 07 05:02:45 PM PDT 24
Peak memory 201048 kb
Host smart-b2b7bea8-9ee3-4568-919e-547938e948bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685569866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_clk_byp_req_intersig_mubi.2685569866
Directory /workspace/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.4075745512
Short name T99
Test name
Test status
Simulation time 15879330 ps
CPU time 0.77 seconds
Started Aug 07 05:03:43 PM PDT 24
Finished Aug 07 05:03:44 PM PDT 24
Peak memory 201108 kb
Host smart-9b749d92-9c7a-4596-acab-cc4ac79eca01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075745512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 18.clkmgr_lc_ctrl_intersig_mubi.4075745512
Directory /workspace/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/18.clkmgr_peri.832594313
Short name T753
Test name
Test status
Simulation time 91185491 ps
CPU time 0.96 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201092 kb
Host smart-2d9e6824-796b-414a-ad5f-c8efe173cd5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832594313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.832594313
Directory /workspace/18.clkmgr_peri/latest

Test location /workspace/coverage/default/18.clkmgr_regwen.2989985905
Short name T185
Test name
Test status
Simulation time 1135474315 ps
CPU time 4.58 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:48 PM PDT 24
Peak memory 201268 kb
Host smart-232cd7ff-01a4-45af-b37d-0a9d925d957c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989985905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2989985905
Directory /workspace/18.clkmgr_regwen/latest

Test location /workspace/coverage/default/18.clkmgr_smoke.580507939
Short name T626
Test name
Test status
Simulation time 126208899 ps
CPU time 1.2 seconds
Started Aug 07 05:02:38 PM PDT 24
Finished Aug 07 05:02:39 PM PDT 24
Peak memory 200968 kb
Host smart-d009bd2a-9723-4271-98fe-79d0d7d2b04e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580507939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.580507939
Directory /workspace/18.clkmgr_smoke/latest

Test location /workspace/coverage/default/18.clkmgr_stress_all.51454483
Short name T159
Test name
Test status
Simulation time 6930549192 ps
CPU time 37.53 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201320 kb
Host smart-702390b4-3020-4ca8-bd06-b134e3ba86b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51454483 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.clkmgr_stress_all.51454483
Directory /workspace/18.clkmgr_stress_all/latest

Test location /workspace/coverage/default/18.clkmgr_trans.810532050
Short name T96
Test name
Test status
Simulation time 30924907 ps
CPU time 1.04 seconds
Started Aug 07 05:02:41 PM PDT 24
Finished Aug 07 05:02:42 PM PDT 24
Peak memory 201020 kb
Host smart-bbd92e8d-aa94-46bb-9da0-e45c48815852
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810532050 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.810532050
Directory /workspace/18.clkmgr_trans/latest

Test location /workspace/coverage/default/19.clkmgr_alert_test.1042797187
Short name T243
Test name
Test status
Simulation time 14955068 ps
CPU time 0.75 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201056 kb
Host smart-cd22c54b-fff2-4457-b9e9-ec5e06eb7d0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042797187 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clk
mgr_alert_test.1042797187
Directory /workspace/19.clkmgr_alert_test/latest

Test location /workspace/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.3698891884
Short name T615
Test name
Test status
Simulation time 100618175 ps
CPU time 1.18 seconds
Started Aug 07 05:02:50 PM PDT 24
Finished Aug 07 05:02:52 PM PDT 24
Peak memory 201104 kb
Host smart-c5b841d1-8f41-4136-b6af-4ad8e17deff2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698891884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_clk_handshake_intersig_mubi.3698891884
Directory /workspace/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_clk_status.3685695663
Short name T665
Test name
Test status
Simulation time 16941277 ps
CPU time 0.73 seconds
Started Aug 07 05:02:44 PM PDT 24
Finished Aug 07 05:02:45 PM PDT 24
Peak memory 200280 kb
Host smart-77fef268-d74c-4a6b-ba0d-6700b0c845a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685695663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.3685695663
Directory /workspace/19.clkmgr_clk_status/latest

Test location /workspace/coverage/default/19.clkmgr_div_intersig_mubi.3179907120
Short name T463
Test name
Test status
Simulation time 85239047 ps
CPU time 1.08 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201120 kb
Host smart-09bab833-5208-4ebf-a059-1a0779ade516
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179907120 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_div_intersig_mubi.3179907120
Directory /workspace/19.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_extclk.3191406970
Short name T51
Test name
Test status
Simulation time 25224617 ps
CPU time 0.9 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 200996 kb
Host smart-853775a0-fad3-429f-9d7d-4678b34db7df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191406970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.3191406970
Directory /workspace/19.clkmgr_extclk/latest

Test location /workspace/coverage/default/19.clkmgr_frequency.3581381865
Short name T676
Test name
Test status
Simulation time 1611618908 ps
CPU time 7.51 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:51 PM PDT 24
Peak memory 201156 kb
Host smart-dd407825-0fd6-4e59-a4e4-7c005f116901
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581381865 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.3581381865
Directory /workspace/19.clkmgr_frequency/latest

Test location /workspace/coverage/default/19.clkmgr_frequency_timeout.3441581226
Short name T29
Test name
Test status
Simulation time 2179783482 ps
CPU time 15.8 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 201476 kb
Host smart-d18546a0-c7e5-455d-b54f-89f87da6992c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441581226 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_t
imeout.3441581226
Directory /workspace/19.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/19.clkmgr_idle_intersig_mubi.2274128652
Short name T808
Test name
Test status
Simulation time 29204766 ps
CPU time 0.84 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201100 kb
Host smart-2b752784-b4e3-4ce9-bcee-3135d16ff3e7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274128652 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_idle_intersig_mubi.2274128652
Directory /workspace/19.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.2258080962
Short name T469
Test name
Test status
Simulation time 75340050 ps
CPU time 1.05 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:02:52 PM PDT 24
Peak memory 201068 kb
Host smart-5a05cfa6-522c-480d-946a-820a5ef17fe3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258080962 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_clk_byp_req_intersig_mubi.2258080962
Directory /workspace/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2615836703
Short name T472
Test name
Test status
Simulation time 17288142 ps
CPU time 0.76 seconds
Started Aug 07 05:02:49 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 201096 kb
Host smart-d57ee43d-e1ab-4472-b84e-c0f0ccd29743
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615836703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 19.clkmgr_lc_ctrl_intersig_mubi.2615836703
Directory /workspace/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/19.clkmgr_peri.1089659810
Short name T429
Test name
Test status
Simulation time 22208066 ps
CPU time 0.75 seconds
Started Aug 07 05:02:40 PM PDT 24
Finished Aug 07 05:02:41 PM PDT 24
Peak memory 201124 kb
Host smart-4ce0ee56-bfea-4d16-b109-994dc96c1e33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089659810 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1089659810
Directory /workspace/19.clkmgr_peri/latest

Test location /workspace/coverage/default/19.clkmgr_regwen.2033198492
Short name T113
Test name
Test status
Simulation time 618390700 ps
CPU time 2.71 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:46 PM PDT 24
Peak memory 201232 kb
Host smart-9266e68e-722f-4efe-bda8-d455e1406a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033198492 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.2033198492
Directory /workspace/19.clkmgr_regwen/latest

Test location /workspace/coverage/default/19.clkmgr_smoke.3681133272
Short name T133
Test name
Test status
Simulation time 27413764 ps
CPU time 0.88 seconds
Started Aug 07 05:04:07 PM PDT 24
Finished Aug 07 05:04:09 PM PDT 24
Peak memory 201072 kb
Host smart-cfb4be12-324a-46d8-86df-6dbb22256940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681133272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.3681133272
Directory /workspace/19.clkmgr_smoke/latest

Test location /workspace/coverage/default/19.clkmgr_stress_all.1125080818
Short name T423
Test name
Test status
Simulation time 6631049328 ps
CPU time 28.63 seconds
Started Aug 07 05:02:41 PM PDT 24
Finished Aug 07 05:03:10 PM PDT 24
Peak memory 201388 kb
Host smart-7a7068b5-7713-4a66-a1d1-a47ba80b0247
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125080818 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.clkmgr_stress_all.1125080818
Directory /workspace/19.clkmgr_stress_all/latest

Test location /workspace/coverage/default/19.clkmgr_trans.4077677848
Short name T401
Test name
Test status
Simulation time 32288449 ps
CPU time 0.92 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 200972 kb
Host smart-bd564aea-b938-40b8-8c67-aec3abe5b051
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077677848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.4077677848
Directory /workspace/19.clkmgr_trans/latest

Test location /workspace/coverage/default/2.clkmgr_alert_test.2486118751
Short name T662
Test name
Test status
Simulation time 17355302 ps
CPU time 0.75 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201056 kb
Host smart-4a2545aa-2fc9-4d47-aaca-cb9fb1bd4257
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486118751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkm
gr_alert_test.2486118751
Directory /workspace/2.clkmgr_alert_test/latest

Test location /workspace/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.1424639944
Short name T651
Test name
Test status
Simulation time 23662843 ps
CPU time 0.8 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 201116 kb
Host smart-66ed908e-4d51-4d85-925b-161d108f96cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424639944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_clk_handshake_intersig_mubi.1424639944
Directory /workspace/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_clk_status.1775249695
Short name T761
Test name
Test status
Simulation time 17788114 ps
CPU time 0.76 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 200220 kb
Host smart-adf2c12d-e781-4664-9c6e-b9553e569e0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775249695 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.1775249695
Directory /workspace/2.clkmgr_clk_status/latest

Test location /workspace/coverage/default/2.clkmgr_div_intersig_mubi.900144931
Short name T166
Test name
Test status
Simulation time 16018877 ps
CPU time 0.81 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201000 kb
Host smart-78d4367c-d620-44fb-87e7-11ec9a3997ef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900144931 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
.clkmgr_div_intersig_mubi.900144931
Directory /workspace/2.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_extclk.1213945585
Short name T172
Test name
Test status
Simulation time 51865432 ps
CPU time 0.86 seconds
Started Aug 07 05:02:00 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 201020 kb
Host smart-2c66ff9a-5ba8-4122-a5b6-ca0665eb10f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213945585 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.1213945585
Directory /workspace/2.clkmgr_extclk/latest

Test location /workspace/coverage/default/2.clkmgr_frequency.3621309375
Short name T387
Test name
Test status
Simulation time 1274470639 ps
CPU time 10.22 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:33 PM PDT 24
Peak memory 201144 kb
Host smart-70bc93d2-ffcc-469c-bd6a-3265a5262948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621309375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3621309375
Directory /workspace/2.clkmgr_frequency/latest

Test location /workspace/coverage/default/2.clkmgr_frequency_timeout.1269659966
Short name T266
Test name
Test status
Simulation time 2203236522 ps
CPU time 9.44 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:09 PM PDT 24
Peak memory 201472 kb
Host smart-078aa330-b748-4139-b710-7f537360b26c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269659966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_ti
meout.1269659966
Directory /workspace/2.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/2.clkmgr_idle_intersig_mubi.1898281756
Short name T341
Test name
Test status
Simulation time 28307964 ps
CPU time 0.93 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201112 kb
Host smart-372099c9-fc1f-4ac0-9abf-74ee6221ea57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898281756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_idle_intersig_mubi.1898281756
Directory /workspace/2.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.50165218
Short name T421
Test name
Test status
Simulation time 15981339 ps
CPU time 0.8 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 201056 kb
Host smart-81cf880a-88ef-47dd-8515-04f8f0e2e950
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50165218 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_lc_clk_byp_req_intersig_mubi.50165218
Directory /workspace/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.1257260406
Short name T560
Test name
Test status
Simulation time 48962082 ps
CPU time 0.88 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 200972 kb
Host smart-87b5e175-d947-46f3-97e3-59f60b78ea35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257260406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 2.clkmgr_lc_ctrl_intersig_mubi.1257260406
Directory /workspace/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/2.clkmgr_peri.1492991225
Short name T302
Test name
Test status
Simulation time 31170393 ps
CPU time 0.78 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 201012 kb
Host smart-fb5598eb-2697-4112-93f6-e59fd97d884a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492991225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1492991225
Directory /workspace/2.clkmgr_peri/latest

Test location /workspace/coverage/default/2.clkmgr_regwen.3551046486
Short name T758
Test name
Test status
Simulation time 86039159 ps
CPU time 1.04 seconds
Started Aug 07 05:02:04 PM PDT 24
Finished Aug 07 05:02:05 PM PDT 24
Peak memory 201084 kb
Host smart-f97fa249-a205-479b-8908-4b31a415efb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551046486 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.3551046486
Directory /workspace/2.clkmgr_regwen/latest

Test location /workspace/coverage/default/2.clkmgr_sec_cm.3245916767
Short name T37
Test name
Test status
Simulation time 142052185 ps
CPU time 1.99 seconds
Started Aug 07 05:01:59 PM PDT 24
Finished Aug 07 05:02:01 PM PDT 24
Peak memory 216444 kb
Host smart-395347d5-42cf-41d6-b340-6f5c76c090ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245916767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmg
r_sec_cm.3245916767
Directory /workspace/2.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/2.clkmgr_smoke.3055889715
Short name T358
Test name
Test status
Simulation time 31511605 ps
CPU time 0.88 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:02:02 PM PDT 24
Peak memory 201084 kb
Host smart-8fa23104-c7fc-4ce9-933a-305e29894a5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055889715 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.3055889715
Directory /workspace/2.clkmgr_smoke/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all.1380417946
Short name T312
Test name
Test status
Simulation time 4121317676 ps
CPU time 18.49 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201420 kb
Host smart-8386baed-b8cd-4437-b856-6b24fa5f86cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380417946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.clkmgr_stress_all.1380417946
Directory /workspace/2.clkmgr_stress_all/latest

Test location /workspace/coverage/default/2.clkmgr_stress_all_with_rand_reset.1072693345
Short name T182
Test name
Test status
Simulation time 124822090303 ps
CPU time 701.15 seconds
Started Aug 07 05:02:01 PM PDT 24
Finished Aug 07 05:13:42 PM PDT 24
Peak memory 217908 kb
Host smart-189fc1ce-a502-4eb1-b273-76a5a21908c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1072693345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.1072693345
Directory /workspace/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.clkmgr_trans.787950856
Short name T396
Test name
Test status
Simulation time 30212519 ps
CPU time 0.96 seconds
Started Aug 07 05:02:02 PM PDT 24
Finished Aug 07 05:02:03 PM PDT 24
Peak memory 201072 kb
Host smart-44573128-b1f6-48b2-80a3-743ae2aec32d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787950856 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.787950856
Directory /workspace/2.clkmgr_trans/latest

Test location /workspace/coverage/default/20.clkmgr_alert_test.2211970067
Short name T338
Test name
Test status
Simulation time 15792738 ps
CPU time 0.77 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201020 kb
Host smart-97d84e18-7429-4f5e-bbbb-f0290435c1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211970067 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clk
mgr_alert_test.2211970067
Directory /workspace/20.clkmgr_alert_test/latest

Test location /workspace/coverage/default/20.clkmgr_clk_status.1973520769
Short name T353
Test name
Test status
Simulation time 36494778 ps
CPU time 0.75 seconds
Started Aug 07 05:02:49 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 200264 kb
Host smart-935f47ba-bfd0-4f83-9a7a-326f341c150e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973520769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.1973520769
Directory /workspace/20.clkmgr_clk_status/latest

Test location /workspace/coverage/default/20.clkmgr_div_intersig_mubi.1166606472
Short name T410
Test name
Test status
Simulation time 29981625 ps
CPU time 0.91 seconds
Started Aug 07 05:02:49 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 201084 kb
Host smart-4f88b146-932e-4acf-bebc-d0407c03a62d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166606472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_div_intersig_mubi.1166606472
Directory /workspace/20.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_extclk.3448298872
Short name T378
Test name
Test status
Simulation time 33680692 ps
CPU time 0.93 seconds
Started Aug 07 05:02:42 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201040 kb
Host smart-ff151fdd-d498-4b5f-b4b8-180389dec5c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448298872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.3448298872
Directory /workspace/20.clkmgr_extclk/latest

Test location /workspace/coverage/default/20.clkmgr_frequency.1389413077
Short name T444
Test name
Test status
Simulation time 2008124492 ps
CPU time 11.15 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201384 kb
Host smart-8415a1e9-7346-4084-8b81-900de097b462
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389413077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.1389413077
Directory /workspace/20.clkmgr_frequency/latest

Test location /workspace/coverage/default/20.clkmgr_frequency_timeout.850219584
Short name T52
Test name
Test status
Simulation time 2180487957 ps
CPU time 15.58 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:04:14 PM PDT 24
Peak memory 201316 kb
Host smart-dbef753b-138d-4c61-99c0-05aba9aaf573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850219584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_ti
meout.850219584
Directory /workspace/20.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/20.clkmgr_idle_intersig_mubi.279925149
Short name T249
Test name
Test status
Simulation time 24886208 ps
CPU time 0.89 seconds
Started Aug 07 05:02:47 PM PDT 24
Finished Aug 07 05:02:48 PM PDT 24
Peak memory 201092 kb
Host smart-8715d1e9-7504-49ca-9f7c-f4d8cdbbd1f0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279925149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.clkmgr_idle_intersig_mubi.279925149
Directory /workspace/20.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.1397113141
Short name T81
Test name
Test status
Simulation time 21826989 ps
CPU time 0.86 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201080 kb
Host smart-25e38251-fb23-489a-941d-792f837581bf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397113141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 20.clkmgr_lc_clk_byp_req_intersig_mubi.1397113141
Directory /workspace/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.911449040
Short name T811
Test name
Test status
Simulation time 25301640 ps
CPU time 0.86 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 200972 kb
Host smart-ee6098d4-c0b0-4465-a3df-5b8544ced88f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911449040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 20.clkmgr_lc_ctrl_intersig_mubi.911449040
Directory /workspace/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/20.clkmgr_peri.221823171
Short name T426
Test name
Test status
Simulation time 16910003 ps
CPU time 0.73 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201056 kb
Host smart-d7be2e2b-5aad-4dbb-b431-49478f578311
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221823171 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.221823171
Directory /workspace/20.clkmgr_peri/latest

Test location /workspace/coverage/default/20.clkmgr_regwen.1429508784
Short name T624
Test name
Test status
Simulation time 1969246756 ps
CPU time 6.68 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 201244 kb
Host smart-8c4b8f23-6c24-47cf-8cfe-f01366d6b7ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429508784 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1429508784
Directory /workspace/20.clkmgr_regwen/latest

Test location /workspace/coverage/default/20.clkmgr_smoke.3048939452
Short name T483
Test name
Test status
Simulation time 17223043 ps
CPU time 0.8 seconds
Started Aug 07 05:02:43 PM PDT 24
Finished Aug 07 05:02:44 PM PDT 24
Peak memory 201056 kb
Host smart-8b89626d-da36-4d54-9d06-b5e5561d008a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048939452 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.3048939452
Directory /workspace/20.clkmgr_smoke/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all.4063925498
Short name T795
Test name
Test status
Simulation time 5318166949 ps
CPU time 29.59 seconds
Started Aug 07 05:02:44 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201368 kb
Host smart-b836f896-a436-404f-9e64-152d1cf8a997
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063925498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.clkmgr_stress_all.4063925498
Directory /workspace/20.clkmgr_stress_all/latest

Test location /workspace/coverage/default/20.clkmgr_stress_all_with_rand_reset.3742996617
Short name T76
Test name
Test status
Simulation time 104872692464 ps
CPU time 710.93 seconds
Started Aug 07 05:02:48 PM PDT 24
Finished Aug 07 05:14:39 PM PDT 24
Peak memory 217888 kb
Host smart-6f52d639-4347-491a-88bb-c50784e02a09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3742996617 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3742996617
Directory /workspace/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.clkmgr_trans.2674938737
Short name T627
Test name
Test status
Simulation time 71184442 ps
CPU time 0.98 seconds
Started Aug 07 05:02:45 PM PDT 24
Finished Aug 07 05:02:46 PM PDT 24
Peak memory 201032 kb
Host smart-9378d200-0520-4ef8-9ad3-f57a910d133b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674938737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.2674938737
Directory /workspace/20.clkmgr_trans/latest

Test location /workspace/coverage/default/21.clkmgr_alert_test.1090714545
Short name T370
Test name
Test status
Simulation time 22117837 ps
CPU time 0.71 seconds
Started Aug 07 05:02:54 PM PDT 24
Finished Aug 07 05:02:55 PM PDT 24
Peak memory 201060 kb
Host smart-ece4dff1-b0c8-4574-b4a8-1ce103c25e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090714545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clk
mgr_alert_test.1090714545
Directory /workspace/21.clkmgr_alert_test/latest

Test location /workspace/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.821018348
Short name T106
Test name
Test status
Simulation time 38661573 ps
CPU time 0.93 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:02:52 PM PDT 24
Peak memory 201128 kb
Host smart-873f963e-5fee-4b8b-b269-5d8cf58748b8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821018348 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_clk_handshake_intersig_mubi.821018348
Directory /workspace/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_clk_status.18067119
Short name T320
Test name
Test status
Simulation time 69377345 ps
CPU time 0.86 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 200292 kb
Host smart-27728bf2-5942-40ae-9114-e6f03ae10f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067119 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.18067119
Directory /workspace/21.clkmgr_clk_status/latest

Test location /workspace/coverage/default/21.clkmgr_div_intersig_mubi.347799291
Short name T411
Test name
Test status
Simulation time 17682591 ps
CPU time 0.82 seconds
Started Aug 07 05:02:54 PM PDT 24
Finished Aug 07 05:02:55 PM PDT 24
Peak memory 201056 kb
Host smart-40f18d36-eda7-47a6-ada9-c6027559cf6f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347799291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.clkmgr_div_intersig_mubi.347799291
Directory /workspace/21.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_extclk.53316027
Short name T803
Test name
Test status
Simulation time 28625876 ps
CPU time 0.97 seconds
Started Aug 07 05:02:57 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201056 kb
Host smart-e29159ed-c5f3-466b-bf56-b473391ecc1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53316027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.53316027
Directory /workspace/21.clkmgr_extclk/latest

Test location /workspace/coverage/default/21.clkmgr_frequency.305218905
Short name T722
Test name
Test status
Simulation time 1407182953 ps
CPU time 6.56 seconds
Started Aug 07 05:03:03 PM PDT 24
Finished Aug 07 05:03:09 PM PDT 24
Peak memory 201200 kb
Host smart-6a98dadd-e2ab-4823-b62b-febe929f6438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305218905 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.305218905
Directory /workspace/21.clkmgr_frequency/latest

Test location /workspace/coverage/default/21.clkmgr_frequency_timeout.3099032526
Short name T418
Test name
Test status
Simulation time 1102897734 ps
CPU time 6.62 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201232 kb
Host smart-ea0dacf6-8370-446f-ac8f-41269d6b09f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099032526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_t
imeout.3099032526
Directory /workspace/21.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/21.clkmgr_idle_intersig_mubi.1551709687
Short name T713
Test name
Test status
Simulation time 27431642 ps
CPU time 0.76 seconds
Started Aug 07 05:02:49 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 200988 kb
Host smart-0b67304a-18a8-4101-987c-a37807e461b9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551709687 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_idle_intersig_mubi.1551709687
Directory /workspace/21.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.3122679439
Short name T578
Test name
Test status
Simulation time 33657631 ps
CPU time 0.83 seconds
Started Aug 07 05:02:48 PM PDT 24
Finished Aug 07 05:02:49 PM PDT 24
Peak memory 201072 kb
Host smart-bdf17fab-42bf-4cd8-bf2c-12ff26c6adfc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122679439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_clk_byp_req_intersig_mubi.3122679439
Directory /workspace/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.3271970301
Short name T752
Test name
Test status
Simulation time 20146663 ps
CPU time 0.83 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:02:52 PM PDT 24
Peak memory 201088 kb
Host smart-b4c46607-3d95-4a97-9f83-05a938dc5af5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271970301 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 21.clkmgr_lc_ctrl_intersig_mubi.3271970301
Directory /workspace/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/21.clkmgr_peri.3242743628
Short name T278
Test name
Test status
Simulation time 27844176 ps
CPU time 0.78 seconds
Started Aug 07 05:02:52 PM PDT 24
Finished Aug 07 05:02:53 PM PDT 24
Peak memory 201072 kb
Host smart-37c2c00f-7dba-4cbe-989b-d395d14643b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242743628 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3242743628
Directory /workspace/21.clkmgr_peri/latest

Test location /workspace/coverage/default/21.clkmgr_regwen.98843566
Short name T738
Test name
Test status
Simulation time 1427648786 ps
CPU time 6.26 seconds
Started Aug 07 05:02:52 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201264 kb
Host smart-84064831-7e6d-478b-8e2a-f585eb0bcd37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98843566 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.98843566
Directory /workspace/21.clkmgr_regwen/latest

Test location /workspace/coverage/default/21.clkmgr_smoke.2335125432
Short name T448
Test name
Test status
Simulation time 21445356 ps
CPU time 0.89 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:02:52 PM PDT 24
Peak memory 200984 kb
Host smart-9f1d7f24-0ce9-4290-a7d6-fad3fef5ad1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335125432 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.2335125432
Directory /workspace/21.clkmgr_smoke/latest

Test location /workspace/coverage/default/21.clkmgr_stress_all.1040093864
Short name T641
Test name
Test status
Simulation time 7325571062 ps
CPU time 37.04 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:04:41 PM PDT 24
Peak memory 201344 kb
Host smart-06d560c8-2dc3-4164-adc6-a5882dd87715
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040093864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.clkmgr_stress_all.1040093864
Directory /workspace/21.clkmgr_stress_all/latest

Test location /workspace/coverage/default/21.clkmgr_trans.2990572489
Short name T171
Test name
Test status
Simulation time 117739128 ps
CPU time 1.36 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:01 PM PDT 24
Peak memory 201076 kb
Host smart-2d64f490-2753-4994-befb-fbca3128ffa6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990572489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.2990572489
Directory /workspace/21.clkmgr_trans/latest

Test location /workspace/coverage/default/22.clkmgr_alert_test.1844707338
Short name T816
Test name
Test status
Simulation time 61846366 ps
CPU time 0.94 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201088 kb
Host smart-14330934-8dde-4031-adb2-8f3338fa2a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844707338 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clk
mgr_alert_test.1844707338
Directory /workspace/22.clkmgr_alert_test/latest

Test location /workspace/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.1294619985
Short name T717
Test name
Test status
Simulation time 54552118 ps
CPU time 1 seconds
Started Aug 07 05:02:59 PM PDT 24
Finished Aug 07 05:03:01 PM PDT 24
Peak memory 201088 kb
Host smart-3a38cfe6-3bf8-492f-89b9-d0e7c9b5add1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294619985 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_clk_handshake_intersig_mubi.1294619985
Directory /workspace/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_clk_status.309780600
Short name T34
Test name
Test status
Simulation time 21387432 ps
CPU time 0.72 seconds
Started Aug 07 05:02:52 PM PDT 24
Finished Aug 07 05:02:53 PM PDT 24
Peak memory 200308 kb
Host smart-a31bab5e-0586-4cff-babe-5c0ed80a2343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309780600 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.309780600
Directory /workspace/22.clkmgr_clk_status/latest

Test location /workspace/coverage/default/22.clkmgr_div_intersig_mubi.456773219
Short name T350
Test name
Test status
Simulation time 17238458 ps
CPU time 0.79 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201092 kb
Host smart-66c37247-beb5-460b-84aa-a453a10b05cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456773219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_div_intersig_mubi.456773219
Directory /workspace/22.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_extclk.4118396538
Short name T790
Test name
Test status
Simulation time 29677802 ps
CPU time 0.87 seconds
Started Aug 07 05:02:52 PM PDT 24
Finished Aug 07 05:02:53 PM PDT 24
Peak memory 201016 kb
Host smart-1104e2fd-136f-4fee-913b-7745288fa617
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118396538 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.4118396538
Directory /workspace/22.clkmgr_extclk/latest

Test location /workspace/coverage/default/22.clkmgr_frequency.3350441387
Short name T491
Test name
Test status
Simulation time 2817520091 ps
CPU time 10.57 seconds
Started Aug 07 05:02:57 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 201464 kb
Host smart-9e7725a9-2ccd-4388-af14-32fad504d104
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350441387 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3350441387
Directory /workspace/22.clkmgr_frequency/latest

Test location /workspace/coverage/default/22.clkmgr_frequency_timeout.894513371
Short name T332
Test name
Test status
Simulation time 1699996677 ps
CPU time 11.39 seconds
Started Aug 07 05:02:51 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201224 kb
Host smart-7240f2e2-7f10-474f-b8c5-1c8231c6b15e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894513371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_ti
meout.894513371
Directory /workspace/22.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/22.clkmgr_idle_intersig_mubi.264271596
Short name T809
Test name
Test status
Simulation time 52976267 ps
CPU time 1.1 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201040 kb
Host smart-eedd5908-d324-44fa-852d-aba9aef63376
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264271596 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
2.clkmgr_idle_intersig_mubi.264271596
Directory /workspace/22.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.3747585604
Short name T128
Test name
Test status
Simulation time 26856827 ps
CPU time 0.86 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 200952 kb
Host smart-9a56c2cc-fe8a-41e6-ae7e-b954476ecec0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747585604 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_clk_byp_req_intersig_mubi.3747585604
Directory /workspace/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1093432595
Short name T823
Test name
Test status
Simulation time 14880943 ps
CPU time 0.76 seconds
Started Aug 07 05:02:58 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201060 kb
Host smart-9f8300fe-ae33-4c9d-93ee-2e8776e13e25
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093432595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 22.clkmgr_lc_ctrl_intersig_mubi.1093432595
Directory /workspace/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/22.clkmgr_peri.970703386
Short name T670
Test name
Test status
Simulation time 15214717 ps
CPU time 0.71 seconds
Started Aug 07 05:02:47 PM PDT 24
Finished Aug 07 05:02:47 PM PDT 24
Peak memory 201068 kb
Host smart-a62cad2f-3970-4a4b-bce0-434a30419b39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970703386 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.970703386
Directory /workspace/22.clkmgr_peri/latest

Test location /workspace/coverage/default/22.clkmgr_regwen.2974313128
Short name T486
Test name
Test status
Simulation time 570827167 ps
CPU time 2.4 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201064 kb
Host smart-89d1918f-4206-4a5f-a756-163e91320bcb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974313128 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.2974313128
Directory /workspace/22.clkmgr_regwen/latest

Test location /workspace/coverage/default/22.clkmgr_smoke.1648650641
Short name T659
Test name
Test status
Simulation time 51760073 ps
CPU time 0.9 seconds
Started Aug 07 05:02:50 PM PDT 24
Finished Aug 07 05:02:51 PM PDT 24
Peak memory 201052 kb
Host smart-c3573a4e-176d-4484-926d-10d40ec2fdfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648650641 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1648650641
Directory /workspace/22.clkmgr_smoke/latest

Test location /workspace/coverage/default/22.clkmgr_stress_all.2384321850
Short name T191
Test name
Test status
Simulation time 46103580 ps
CPU time 1.11 seconds
Started Aug 07 05:02:58 PM PDT 24
Finished Aug 07 05:03:00 PM PDT 24
Peak memory 201096 kb
Host smart-81ad3cf7-65d2-44bd-8582-d94778f7ddaf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384321850 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.clkmgr_stress_all.2384321850
Directory /workspace/22.clkmgr_stress_all/latest

Test location /workspace/coverage/default/22.clkmgr_trans.3571339276
Short name T710
Test name
Test status
Simulation time 44696972 ps
CPU time 0.95 seconds
Started Aug 07 05:02:50 PM PDT 24
Finished Aug 07 05:02:51 PM PDT 24
Peak memory 201080 kb
Host smart-334495a1-4fd4-411d-b95a-d6096a045523
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571339276 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3571339276
Directory /workspace/22.clkmgr_trans/latest

Test location /workspace/coverage/default/23.clkmgr_alert_test.1563484822
Short name T476
Test name
Test status
Simulation time 15788248 ps
CPU time 0.76 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201144 kb
Host smart-b5a862cf-b907-49c4-9fb3-a1be12473af0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563484822 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clk
mgr_alert_test.1563484822
Directory /workspace/23.clkmgr_alert_test/latest

Test location /workspace/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.3227666823
Short name T400
Test name
Test status
Simulation time 56800859 ps
CPU time 1.02 seconds
Started Aug 07 05:02:59 PM PDT 24
Finished Aug 07 05:03:00 PM PDT 24
Peak memory 200928 kb
Host smart-d9dffe13-3202-4b37-a21f-38f47bace7fd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227666823 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_clk_handshake_intersig_mubi.3227666823
Directory /workspace/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_clk_status.126814851
Short name T512
Test name
Test status
Simulation time 16206219 ps
CPU time 0.78 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 200284 kb
Host smart-ac311e4c-ecea-4738-a43a-873212848b46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126814851 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.126814851
Directory /workspace/23.clkmgr_clk_status/latest

Test location /workspace/coverage/default/23.clkmgr_div_intersig_mubi.3583549893
Short name T723
Test name
Test status
Simulation time 19892653 ps
CPU time 0.88 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201108 kb
Host smart-9cd842f9-0f54-4406-b6b9-60ea4397df01
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583549893 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_div_intersig_mubi.3583549893
Directory /workspace/23.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_extclk.4152527998
Short name T129
Test name
Test status
Simulation time 100015692 ps
CPU time 1.17 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201000 kb
Host smart-ceff6d17-dce0-4784-8614-e480b22765be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152527998 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.4152527998
Directory /workspace/23.clkmgr_extclk/latest

Test location /workspace/coverage/default/23.clkmgr_frequency.2202614054
Short name T379
Test name
Test status
Simulation time 2121441448 ps
CPU time 16.26 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:04:06 PM PDT 24
Peak memory 201352 kb
Host smart-52b5d50c-55d3-4d8c-a609-be5c39ecf8fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202614054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.2202614054
Directory /workspace/23.clkmgr_frequency/latest

Test location /workspace/coverage/default/23.clkmgr_frequency_timeout.376437707
Short name T780
Test name
Test status
Simulation time 974592002 ps
CPU time 7.57 seconds
Started Aug 07 05:02:54 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201208 kb
Host smart-2fbf943b-6c3d-4955-a7c3-8f8c2c35d7fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376437707 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_ti
meout.376437707
Directory /workspace/23.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/23.clkmgr_idle_intersig_mubi.2154570254
Short name T666
Test name
Test status
Simulation time 43295622 ps
CPU time 0.87 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201024 kb
Host smart-cf72960c-f7a9-4e46-96c3-2bab45fe5e16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154570254 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.clkmgr_idle_intersig_mubi.2154570254
Directory /workspace/23.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.1300567849
Short name T224
Test name
Test status
Simulation time 192798647 ps
CPU time 1.28 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201052 kb
Host smart-eaf507db-9cb4-4113-8667-d7ebfba5e836
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300567849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_clk_byp_req_intersig_mubi.1300567849
Directory /workspace/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.4277041774
Short name T603
Test name
Test status
Simulation time 97087296 ps
CPU time 0.97 seconds
Started Aug 07 05:03:00 PM PDT 24
Finished Aug 07 05:03:01 PM PDT 24
Peak memory 201108 kb
Host smart-7d29c607-56e1-4c80-8492-592241cf7a37
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277041774 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 23.clkmgr_lc_ctrl_intersig_mubi.4277041774
Directory /workspace/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/23.clkmgr_peri.3022958946
Short name T781
Test name
Test status
Simulation time 135289151 ps
CPU time 1.07 seconds
Started Aug 07 05:02:54 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 201104 kb
Host smart-09cc2dac-caf5-44bc-9860-2e114f8aa3b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022958946 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3022958946
Directory /workspace/23.clkmgr_peri/latest

Test location /workspace/coverage/default/23.clkmgr_regwen.82764375
Short name T346
Test name
Test status
Simulation time 625839032 ps
CPU time 2.67 seconds
Started Aug 07 05:02:58 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201244 kb
Host smart-08821a25-7ef0-4734-ade8-a2c5beff6678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82764375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.82764375
Directory /workspace/23.clkmgr_regwen/latest

Test location /workspace/coverage/default/23.clkmgr_smoke.2599536949
Short name T44
Test name
Test status
Simulation time 290696818 ps
CPU time 1.7 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201068 kb
Host smart-76b8cc87-d260-48a4-8d07-90d7a07b428c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599536949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.2599536949
Directory /workspace/23.clkmgr_smoke/latest

Test location /workspace/coverage/default/23.clkmgr_trans.1020240997
Short name T721
Test name
Test status
Simulation time 20002395 ps
CPU time 0.89 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201000 kb
Host smart-b4a250b1-6635-4b66-8c31-3ed09fe0cb72
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020240997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.1020240997
Directory /workspace/23.clkmgr_trans/latest

Test location /workspace/coverage/default/24.clkmgr_alert_test.169298866
Short name T559
Test name
Test status
Simulation time 22215061 ps
CPU time 0.8 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 200964 kb
Host smart-0b53d952-060a-4053-bd7e-219aab1744c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169298866 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkm
gr_alert_test.169298866
Directory /workspace/24.clkmgr_alert_test/latest

Test location /workspace/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.3114764537
Short name T108
Test name
Test status
Simulation time 110044544 ps
CPU time 1.14 seconds
Started Aug 07 05:02:57 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201080 kb
Host smart-49f42cc0-0bc3-45be-add9-31e065195df3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114764537 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_clk_handshake_intersig_mubi.3114764537
Directory /workspace/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_clk_status.2264618669
Short name T658
Test name
Test status
Simulation time 15177260 ps
CPU time 0.73 seconds
Started Aug 07 05:02:58 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 200328 kb
Host smart-a71d2e68-1c4c-4f51-a878-289696d0223a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264618669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.2264618669
Directory /workspace/24.clkmgr_clk_status/latest

Test location /workspace/coverage/default/24.clkmgr_div_intersig_mubi.65665029
Short name T318
Test name
Test status
Simulation time 27786050 ps
CPU time 0.93 seconds
Started Aug 07 05:02:58 PM PDT 24
Finished Aug 07 05:02:59 PM PDT 24
Peak memory 201048 kb
Host smart-b1933a25-6665-4761-81c6-4882720fc372
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65665029 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.clkmgr_div_intersig_mubi.65665029
Directory /workspace/24.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_extclk.339171477
Short name T508
Test name
Test status
Simulation time 157611739 ps
CPU time 1.27 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:56 PM PDT 24
Peak memory 200988 kb
Host smart-fe109aad-d841-4ee1-9980-b40195d9085a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339171477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.339171477
Directory /workspace/24.clkmgr_extclk/latest

Test location /workspace/coverage/default/24.clkmgr_frequency.2080971465
Short name T715
Test name
Test status
Simulation time 1605845045 ps
CPU time 7.68 seconds
Started Aug 07 05:02:57 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201080 kb
Host smart-88d289a5-d3ab-4bf7-9c47-6947fa1b6ab2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080971465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.2080971465
Directory /workspace/24.clkmgr_frequency/latest

Test location /workspace/coverage/default/24.clkmgr_frequency_timeout.3987871176
Short name T17
Test name
Test status
Simulation time 500802006 ps
CPU time 3.22 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:59 PM PDT 24
Peak memory 201216 kb
Host smart-32983b23-4c3b-43a4-9246-58fbf6c61220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987871176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_t
imeout.3987871176
Directory /workspace/24.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/24.clkmgr_idle_intersig_mubi.3623847504
Short name T539
Test name
Test status
Simulation time 78164988 ps
CPU time 1.05 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201028 kb
Host smart-fa1872cc-f8c7-465c-b73f-8ac6ad3caae5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623847504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_idle_intersig_mubi.3623847504
Directory /workspace/24.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.2812665011
Short name T596
Test name
Test status
Simulation time 20328622 ps
CPU time 0.84 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201084 kb
Host smart-6fd3648e-58df-484e-80a6-3c970948e786
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812665011 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_clk_byp_req_intersig_mubi.2812665011
Directory /workspace/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.2604157574
Short name T188
Test name
Test status
Simulation time 23633772 ps
CPU time 0.9 seconds
Started Aug 07 05:02:59 PM PDT 24
Finished Aug 07 05:03:00 PM PDT 24
Peak memory 201116 kb
Host smart-db70e2fe-6510-4aef-802e-481edb9db11d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604157574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 24.clkmgr_lc_ctrl_intersig_mubi.2604157574
Directory /workspace/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/24.clkmgr_peri.921759478
Short name T521
Test name
Test status
Simulation time 16763482 ps
CPU time 0.75 seconds
Started Aug 07 05:02:55 PM PDT 24
Finished Aug 07 05:02:55 PM PDT 24
Peak memory 201056 kb
Host smart-f0d22ea3-1118-489c-98de-4139d345ba41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921759478 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.921759478
Directory /workspace/24.clkmgr_peri/latest

Test location /workspace/coverage/default/24.clkmgr_smoke.2882417340
Short name T792
Test name
Test status
Simulation time 122229714 ps
CPU time 1.16 seconds
Started Aug 07 05:02:57 PM PDT 24
Finished Aug 07 05:02:58 PM PDT 24
Peak memory 201016 kb
Host smart-c136f18c-3e96-426a-aabe-b8d4a9cecdc8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882417340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.2882417340
Directory /workspace/24.clkmgr_smoke/latest

Test location /workspace/coverage/default/24.clkmgr_stress_all.3927446380
Short name T480
Test name
Test status
Simulation time 8365297242 ps
CPU time 33.48 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:04:20 PM PDT 24
Peak memory 201464 kb
Host smart-d0ba7a30-66c3-4528-9609-399ff3dae39c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927446380 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.clkmgr_stress_all.3927446380
Directory /workspace/24.clkmgr_stress_all/latest

Test location /workspace/coverage/default/24.clkmgr_trans.2345253123
Short name T59
Test name
Test status
Simulation time 90516243 ps
CPU time 1.23 seconds
Started Aug 07 05:02:56 PM PDT 24
Finished Aug 07 05:02:57 PM PDT 24
Peak memory 201012 kb
Host smart-ab24a16d-a882-4da5-bea3-554dd35d344b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345253123 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2345253123
Directory /workspace/24.clkmgr_trans/latest

Test location /workspace/coverage/default/25.clkmgr_alert_test.3608902267
Short name T511
Test name
Test status
Simulation time 38422667 ps
CPU time 0.84 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 200956 kb
Host smart-24c89ee1-a88c-4b8a-ab7b-c59f289b1ded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608902267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clk
mgr_alert_test.3608902267
Directory /workspace/25.clkmgr_alert_test/latest

Test location /workspace/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1338308400
Short name T85
Test name
Test status
Simulation time 17260710 ps
CPU time 0.8 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201088 kb
Host smart-d277f1cd-f707-4f36-8522-18a6cfe1e203
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338308400 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_clk_handshake_intersig_mubi.1338308400
Directory /workspace/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_clk_status.3499838017
Short name T772
Test name
Test status
Simulation time 12626162 ps
CPU time 0.72 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 200184 kb
Host smart-c0725600-b659-4696-9cf5-38c28b0b57ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499838017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.3499838017
Directory /workspace/25.clkmgr_clk_status/latest

Test location /workspace/coverage/default/25.clkmgr_div_intersig_mubi.1793353091
Short name T694
Test name
Test status
Simulation time 32648943 ps
CPU time 0.88 seconds
Started Aug 07 05:03:07 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 201084 kb
Host smart-f662b0a4-07da-4913-9135-83ce37d2c45d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793353091 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_div_intersig_mubi.1793353091
Directory /workspace/25.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_extclk.4211494354
Short name T657
Test name
Test status
Simulation time 80167669 ps
CPU time 1.1 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201040 kb
Host smart-ab9cc24f-b064-4e72-8dc2-9f8a8e49b16d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211494354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.4211494354
Directory /workspace/25.clkmgr_extclk/latest

Test location /workspace/coverage/default/25.clkmgr_frequency.3591056434
Short name T12
Test name
Test status
Simulation time 338109226 ps
CPU time 2.14 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201160 kb
Host smart-05fb9bd2-857c-4fc3-9e6c-f88ba929fdbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591056434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3591056434
Directory /workspace/25.clkmgr_frequency/latest

Test location /workspace/coverage/default/25.clkmgr_frequency_timeout.1343067333
Short name T631
Test name
Test status
Simulation time 1988093312 ps
CPU time 8.57 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:11 PM PDT 24
Peak memory 201180 kb
Host smart-cd6d7d56-dc21-45fc-9a42-a25132eda552
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343067333 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_t
imeout.1343067333
Directory /workspace/25.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/25.clkmgr_idle_intersig_mubi.1857461111
Short name T308
Test name
Test status
Simulation time 50301062 ps
CPU time 0.85 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 200984 kb
Host smart-9625eab6-a0f5-43ed-93e9-2a69b2101d66
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857461111 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_idle_intersig_mubi.1857461111
Directory /workspace/25.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.1619388485
Short name T212
Test name
Test status
Simulation time 19997792 ps
CPU time 0.81 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 200928 kb
Host smart-64d4a27c-a497-4bb2-80e7-1398198839b3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619388485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_clk_byp_req_intersig_mubi.1619388485
Directory /workspace/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.3929882667
Short name T437
Test name
Test status
Simulation time 49930692 ps
CPU time 0.94 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201148 kb
Host smart-1b020d8e-177c-4a21-a0ee-c690cd894512
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929882667 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 25.clkmgr_lc_ctrl_intersig_mubi.3929882667
Directory /workspace/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/25.clkmgr_peri.930029343
Short name T237
Test name
Test status
Simulation time 13770677 ps
CPU time 0.73 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201024 kb
Host smart-12723197-d639-4a13-bfe0-9b2d3c1ec949
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930029343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.930029343
Directory /workspace/25.clkmgr_peri/latest

Test location /workspace/coverage/default/25.clkmgr_regwen.3523811755
Short name T324
Test name
Test status
Simulation time 765505001 ps
CPU time 4.54 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 201320 kb
Host smart-ecb21959-275b-4938-826e-9c64ad0d99b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523811755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.3523811755
Directory /workspace/25.clkmgr_regwen/latest

Test location /workspace/coverage/default/25.clkmgr_smoke.3919523258
Short name T156
Test name
Test status
Simulation time 25635916 ps
CPU time 0.97 seconds
Started Aug 07 05:03:03 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201116 kb
Host smart-92d272db-51ef-475d-ab8e-9c1b36455c7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919523258 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.3919523258
Directory /workspace/25.clkmgr_smoke/latest

Test location /workspace/coverage/default/25.clkmgr_stress_all.2867554141
Short name T568
Test name
Test status
Simulation time 2519416007 ps
CPU time 9.23 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:23 PM PDT 24
Peak memory 201380 kb
Host smart-2abac6b9-8cb7-40e2-a584-3f489ba2bfe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867554141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.clkmgr_stress_all.2867554141
Directory /workspace/25.clkmgr_stress_all/latest

Test location /workspace/coverage/default/25.clkmgr_trans.520812763
Short name T132
Test name
Test status
Simulation time 57123125 ps
CPU time 0.93 seconds
Started Aug 07 05:03:06 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 200992 kb
Host smart-a399848f-4414-456d-aed2-f8135599cdeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520812763 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.520812763
Directory /workspace/25.clkmgr_trans/latest

Test location /workspace/coverage/default/26.clkmgr_alert_test.3297511122
Short name T45
Test name
Test status
Simulation time 40013913 ps
CPU time 0.86 seconds
Started Aug 07 05:03:06 PM PDT 24
Finished Aug 07 05:03:07 PM PDT 24
Peak memory 201032 kb
Host smart-f42c9b8f-463d-4272-a55a-498ea42fd663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297511122 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clk
mgr_alert_test.3297511122
Directory /workspace/26.clkmgr_alert_test/latest

Test location /workspace/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.728713328
Short name T592
Test name
Test status
Simulation time 73442032 ps
CPU time 1.1 seconds
Started Aug 07 05:03:03 PM PDT 24
Finished Aug 07 05:03:04 PM PDT 24
Peak memory 201084 kb
Host smart-1bd40856-5215-4c25-9633-26408e21790d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728713328 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_clk_handshake_intersig_mubi.728713328
Directory /workspace/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_clk_status.2517373285
Short name T207
Test name
Test status
Simulation time 32611276 ps
CPU time 0.77 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201004 kb
Host smart-4707d0f3-7268-49c5-bbbd-c961c14b094f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517373285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.2517373285
Directory /workspace/26.clkmgr_clk_status/latest

Test location /workspace/coverage/default/26.clkmgr_div_intersig_mubi.1539833037
Short name T391
Test name
Test status
Simulation time 32944228 ps
CPU time 0.92 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201128 kb
Host smart-e3b2ea31-12bf-44da-b5fe-6fd9ede89866
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539833037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_div_intersig_mubi.1539833037
Directory /workspace/26.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_extclk.746291081
Short name T265
Test name
Test status
Simulation time 35240214 ps
CPU time 0.78 seconds
Started Aug 07 05:03:07 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 201068 kb
Host smart-218b8374-abcc-4306-a9a7-0083e4cb8e7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746291081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.746291081
Directory /workspace/26.clkmgr_extclk/latest

Test location /workspace/coverage/default/26.clkmgr_frequency.896743306
Short name T135
Test name
Test status
Simulation time 1515901843 ps
CPU time 11.75 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:13 PM PDT 24
Peak memory 201052 kb
Host smart-6fd29312-827a-469d-a7c7-4597d6ce93f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896743306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.896743306
Directory /workspace/26.clkmgr_frequency/latest

Test location /workspace/coverage/default/26.clkmgr_frequency_timeout.1052142064
Short name T409
Test name
Test status
Simulation time 974650618 ps
CPU time 7.38 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:09 PM PDT 24
Peak memory 201200 kb
Host smart-7bbe6053-42f5-4a41-bdc4-edb61b019ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052142064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_t
imeout.1052142064
Directory /workspace/26.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/26.clkmgr_idle_intersig_mubi.2216450549
Short name T349
Test name
Test status
Simulation time 21700037 ps
CPU time 0.74 seconds
Started Aug 07 05:05:22 PM PDT 24
Finished Aug 07 05:05:23 PM PDT 24
Peak memory 200988 kb
Host smart-047a92bc-f7e2-456a-a56d-039654aa150f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216450549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_idle_intersig_mubi.2216450549
Directory /workspace/26.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.89232912
Short name T711
Test name
Test status
Simulation time 29744852 ps
CPU time 0.79 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201040 kb
Host smart-8c6c1784-ee5c-4de3-a633-d750c9f436f6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89232912 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_lc_clk_byp_req_intersig_mubi.89232912
Directory /workspace/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.3038078984
Short name T174
Test name
Test status
Simulation time 23347476 ps
CPU time 0.89 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201088 kb
Host smart-bf232806-93b9-454b-9f35-75c74a5ea602
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038078984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 26.clkmgr_lc_ctrl_intersig_mubi.3038078984
Directory /workspace/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/26.clkmgr_peri.3910651503
Short name T193
Test name
Test status
Simulation time 40161033 ps
CPU time 0.84 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201044 kb
Host smart-6d9cc1f4-4c49-41eb-bdcb-9edea9ac30ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910651503 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3910651503
Directory /workspace/26.clkmgr_peri/latest

Test location /workspace/coverage/default/26.clkmgr_regwen.1308625798
Short name T382
Test name
Test status
Simulation time 192854377 ps
CPU time 1.47 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201052 kb
Host smart-7a4b7e88-5631-451c-999d-636c89e390ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308625798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1308625798
Directory /workspace/26.clkmgr_regwen/latest

Test location /workspace/coverage/default/26.clkmgr_smoke.3663843847
Short name T821
Test name
Test status
Simulation time 46666828 ps
CPU time 0.9 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201048 kb
Host smart-a77b9455-5c77-4ffd-bffe-349cc476d3e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663843847 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.3663843847
Directory /workspace/26.clkmgr_smoke/latest

Test location /workspace/coverage/default/26.clkmgr_stress_all.3221681670
Short name T671
Test name
Test status
Simulation time 9133217948 ps
CPU time 36.02 seconds
Started Aug 07 05:03:06 PM PDT 24
Finished Aug 07 05:03:42 PM PDT 24
Peak memory 201332 kb
Host smart-2c9e2ea7-bc34-46b5-bc9d-fb59c4beff3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221681670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.clkmgr_stress_all.3221681670
Directory /workspace/26.clkmgr_stress_all/latest

Test location /workspace/coverage/default/26.clkmgr_trans.3521338402
Short name T371
Test name
Test status
Simulation time 39828577 ps
CPU time 0.92 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:02 PM PDT 24
Peak memory 201040 kb
Host smart-5f6699ff-9935-4b0a-9443-ebcc21da934a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521338402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.3521338402
Directory /workspace/26.clkmgr_trans/latest

Test location /workspace/coverage/default/27.clkmgr_alert_test.1920794330
Short name T340
Test name
Test status
Simulation time 15977336 ps
CPU time 0.8 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201108 kb
Host smart-140ac8dc-9281-416c-a23b-38adb0de67d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920794330 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clk
mgr_alert_test.1920794330
Directory /workspace/27.clkmgr_alert_test/latest

Test location /workspace/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.4077248081
Short name T461
Test name
Test status
Simulation time 44325246 ps
CPU time 0.94 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201052 kb
Host smart-173dc33a-f7f9-4d37-9b86-f9261ee9cd84
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077248081 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_clk_handshake_intersig_mubi.4077248081
Directory /workspace/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_clk_status.2075744265
Short name T825
Test name
Test status
Simulation time 13001715 ps
CPU time 0.7 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 200236 kb
Host smart-4401a488-1c04-4ab7-ae9e-04962cf6a15e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075744265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.2075744265
Directory /workspace/27.clkmgr_clk_status/latest

Test location /workspace/coverage/default/27.clkmgr_div_intersig_mubi.3553440645
Short name T321
Test name
Test status
Simulation time 47458211 ps
CPU time 0.87 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 201068 kb
Host smart-bf1e60c2-f1ff-465f-80dc-bbe11d1e6b40
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553440645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_div_intersig_mubi.3553440645
Directory /workspace/27.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_extclk.1425803066
Short name T490
Test name
Test status
Simulation time 56528989 ps
CPU time 0.95 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:03:05 PM PDT 24
Peak memory 200968 kb
Host smart-2b26cf59-3595-497d-a54b-1fae52d26a3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425803066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.1425803066
Directory /workspace/27.clkmgr_extclk/latest

Test location /workspace/coverage/default/27.clkmgr_frequency.1837990858
Short name T13
Test name
Test status
Simulation time 1762434422 ps
CPU time 10.15 seconds
Started Aug 07 05:03:01 PM PDT 24
Finished Aug 07 05:03:11 PM PDT 24
Peak memory 201368 kb
Host smart-93dc88a0-1d98-4051-b092-62de7f79ec15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837990858 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.1837990858
Directory /workspace/27.clkmgr_frequency/latest

Test location /workspace/coverage/default/27.clkmgr_frequency_timeout.3172656684
Short name T701
Test name
Test status
Simulation time 902797637 ps
CPU time 4.42 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201168 kb
Host smart-4b816872-76b5-46e7-8c4c-faaead2ab292
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172656684 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_t
imeout.3172656684
Directory /workspace/27.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/27.clkmgr_idle_intersig_mubi.550910852
Short name T610
Test name
Test status
Simulation time 128370141 ps
CPU time 1.33 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201032 kb
Host smart-053eea4b-c94f-40cf-bd46-556ba972928e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550910852 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
7.clkmgr_idle_intersig_mubi.550910852
Directory /workspace/27.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.1768518817
Short name T18
Test name
Test status
Simulation time 61804513 ps
CPU time 0.95 seconds
Started Aug 07 05:03:07 PM PDT 24
Finished Aug 07 05:03:08 PM PDT 24
Peak memory 201076 kb
Host smart-fd12db0f-6ca0-4791-85f6-05dc42a3d1e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768518817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 27.clkmgr_lc_clk_byp_req_intersig_mubi.1768518817
Directory /workspace/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.552043266
Short name T317
Test name
Test status
Simulation time 21699720 ps
CPU time 0.84 seconds
Started Aug 07 05:03:06 PM PDT 24
Finished Aug 07 05:03:07 PM PDT 24
Peak memory 201092 kb
Host smart-c4ddb48c-5edd-4a12-b813-c974a025687e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552043266 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 27.clkmgr_lc_ctrl_intersig_mubi.552043266
Directory /workspace/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/27.clkmgr_peri.1385921737
Short name T766
Test name
Test status
Simulation time 31319422 ps
CPU time 0.75 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:03 PM PDT 24
Peak memory 201056 kb
Host smart-020456bd-4af4-46ce-99b0-d5bfabbbca37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385921737 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.1385921737
Directory /workspace/27.clkmgr_peri/latest

Test location /workspace/coverage/default/27.clkmgr_regwen.1383019300
Short name T553
Test name
Test status
Simulation time 523570600 ps
CPU time 2.41 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:04 PM PDT 24
Peak memory 201032 kb
Host smart-008797e6-a59e-4a6d-adb1-da0bd518905f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383019300 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.1383019300
Directory /workspace/27.clkmgr_regwen/latest

Test location /workspace/coverage/default/27.clkmgr_smoke.1088893758
Short name T399
Test name
Test status
Simulation time 18792528 ps
CPU time 0.81 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 200996 kb
Host smart-70721aec-6c4d-4a25-8507-cde63d3df978
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088893758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.1088893758
Directory /workspace/27.clkmgr_smoke/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all.578889454
Short name T407
Test name
Test status
Simulation time 7322634597 ps
CPU time 32.32 seconds
Started Aug 07 05:03:02 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 201400 kb
Host smart-fbe1b0b0-d069-4e28-8ab1-1fb968423adc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578889454 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.clkmgr_stress_all.578889454
Directory /workspace/27.clkmgr_stress_all/latest

Test location /workspace/coverage/default/27.clkmgr_stress_all_with_rand_reset.4043967793
Short name T25
Test name
Test status
Simulation time 132158433420 ps
CPU time 802.17 seconds
Started Aug 07 05:03:04 PM PDT 24
Finished Aug 07 05:16:26 PM PDT 24
Peak memory 217952 kb
Host smart-4a3a721a-054e-4c30-ae13-6e96d29e9ce3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4043967793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.4043967793
Directory /workspace/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.clkmgr_trans.2133154395
Short name T566
Test name
Test status
Simulation time 13932874 ps
CPU time 0.81 seconds
Started Aug 07 05:03:06 PM PDT 24
Finished Aug 07 05:03:07 PM PDT 24
Peak memory 201092 kb
Host smart-773eab75-9c9e-4079-8993-631d5169f064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133154395 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.2133154395
Directory /workspace/27.clkmgr_trans/latest

Test location /workspace/coverage/default/28.clkmgr_alert_test.1687783800
Short name T32
Test name
Test status
Simulation time 35065932 ps
CPU time 0.85 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201036 kb
Host smart-a0eef686-59a7-444c-b9d4-fd7b5f90a50b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687783800 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clk
mgr_alert_test.1687783800
Directory /workspace/28.clkmgr_alert_test/latest

Test location /workspace/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.66935836
Short name T354
Test name
Test status
Simulation time 53464829 ps
CPU time 0.92 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 200360 kb
Host smart-7d160047-2051-4c74-9e70-e35c671ec947
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66935836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_clk_handshake_intersig_mubi.66935836
Directory /workspace/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_clk_status.2206998775
Short name T35
Test name
Test status
Simulation time 36575073 ps
CPU time 0.75 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 200288 kb
Host smart-fac7884c-ca3f-44b2-a4c8-703e667843f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206998775 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.2206998775
Directory /workspace/28.clkmgr_clk_status/latest

Test location /workspace/coverage/default/28.clkmgr_div_intersig_mubi.685113169
Short name T256
Test name
Test status
Simulation time 14886208 ps
CPU time 0.76 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201100 kb
Host smart-7c9a587b-f2ed-4484-8438-04a10eb5c6f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685113169 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
8.clkmgr_div_intersig_mubi.685113169
Directory /workspace/28.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_extclk.456363512
Short name T813
Test name
Test status
Simulation time 55284613 ps
CPU time 0.94 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 200984 kb
Host smart-ffa1012a-617e-48fc-87a1-8d23ae188e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456363512 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.456363512
Directory /workspace/28.clkmgr_extclk/latest

Test location /workspace/coverage/default/28.clkmgr_frequency.3751337078
Short name T471
Test name
Test status
Simulation time 823073803 ps
CPU time 4.23 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:18 PM PDT 24
Peak memory 201128 kb
Host smart-b09bfb55-9ebb-44e2-8e34-e09ba066c2fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751337078 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.3751337078
Directory /workspace/28.clkmgr_frequency/latest

Test location /workspace/coverage/default/28.clkmgr_frequency_timeout.652726981
Short name T745
Test name
Test status
Simulation time 1469459728 ps
CPU time 7.72 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:23 PM PDT 24
Peak memory 201144 kb
Host smart-08d65416-bbc9-4212-ba11-8946c87c0b6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652726981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_ti
meout.652726981
Directory /workspace/28.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/28.clkmgr_idle_intersig_mubi.2022587440
Short name T270
Test name
Test status
Simulation time 57832581 ps
CPU time 1.05 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 200980 kb
Host smart-024ca900-f874-4c16-b708-efa787282b59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022587440 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_idle_intersig_mubi.2022587440
Directory /workspace/28.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.2021816708
Short name T383
Test name
Test status
Simulation time 48075488 ps
CPU time 0.92 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201048 kb
Host smart-12e6428f-572e-40e4-b21b-a4f34a6d82eb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021816708 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_clk_byp_req_intersig_mubi.2021816708
Directory /workspace/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.1727807569
Short name T799
Test name
Test status
Simulation time 29834785 ps
CPU time 0.8 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201096 kb
Host smart-8cb7a3c4-2ef7-4210-ae37-f3335bf73c09
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727807569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 28.clkmgr_lc_ctrl_intersig_mubi.1727807569
Directory /workspace/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/28.clkmgr_peri.2021575639
Short name T169
Test name
Test status
Simulation time 129607849 ps
CPU time 1.06 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201016 kb
Host smart-b50e4972-8389-49f8-bd21-d514d98d89d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021575639 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.2021575639
Directory /workspace/28.clkmgr_peri/latest

Test location /workspace/coverage/default/28.clkmgr_regwen.2654549281
Short name T276
Test name
Test status
Simulation time 1175984421 ps
CPU time 6.53 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201264 kb
Host smart-ec8eee15-2bea-4ed6-a83e-4ca507037e91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654549281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2654549281
Directory /workspace/28.clkmgr_regwen/latest

Test location /workspace/coverage/default/28.clkmgr_smoke.4053253793
Short name T404
Test name
Test status
Simulation time 22803957 ps
CPU time 0.86 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201036 kb
Host smart-8b5edffc-75d2-4dbd-860a-54713ea1afb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053253793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.4053253793
Directory /workspace/28.clkmgr_smoke/latest

Test location /workspace/coverage/default/28.clkmgr_stress_all.2839111967
Short name T700
Test name
Test status
Simulation time 2964487519 ps
CPU time 16.16 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201432 kb
Host smart-190dab74-a26f-48db-994f-c73025483fc9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839111967 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.clkmgr_stress_all.2839111967
Directory /workspace/28.clkmgr_stress_all/latest

Test location /workspace/coverage/default/28.clkmgr_trans.3737713981
Short name T333
Test name
Test status
Simulation time 34481932 ps
CPU time 1 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201076 kb
Host smart-d03434a5-c48b-4dc7-b2de-8753cffef4c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737713981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.3737713981
Directory /workspace/28.clkmgr_trans/latest

Test location /workspace/coverage/default/29.clkmgr_alert_test.3584019140
Short name T250
Test name
Test status
Simulation time 16936589 ps
CPU time 0.72 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201076 kb
Host smart-64ec4830-7165-4428-8faa-96b823f57a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584019140 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clk
mgr_alert_test.3584019140
Directory /workspace/29.clkmgr_alert_test/latest

Test location /workspace/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.2704921184
Short name T109
Test name
Test status
Simulation time 33338578 ps
CPU time 0.87 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201108 kb
Host smart-6cfc74b3-400a-4c57-b06d-2fc1af370ca5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704921184 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_clk_handshake_intersig_mubi.2704921184
Directory /workspace/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_clk_status.577909126
Short name T756
Test name
Test status
Simulation time 27736900 ps
CPU time 0.74 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 200272 kb
Host smart-94ee2292-bc80-4f01-8bf0-2df9b5f8125d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577909126 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.577909126
Directory /workspace/29.clkmgr_clk_status/latest

Test location /workspace/coverage/default/29.clkmgr_div_intersig_mubi.1035432210
Short name T454
Test name
Test status
Simulation time 15379188 ps
CPU time 0.8 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201132 kb
Host smart-3b43ac03-761c-4779-9dd7-fdef9fdf3a52
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035432210 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_div_intersig_mubi.1035432210
Directory /workspace/29.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_extclk.3782519497
Short name T222
Test name
Test status
Simulation time 14169556 ps
CPU time 0.73 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201012 kb
Host smart-da192645-2c5d-4d5c-adde-3be22366720c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782519497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.3782519497
Directory /workspace/29.clkmgr_extclk/latest

Test location /workspace/coverage/default/29.clkmgr_frequency.2989831507
Short name T251
Test name
Test status
Simulation time 2357120905 ps
CPU time 17.56 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201360 kb
Host smart-a32d7a75-4d7b-4c6d-914f-432a127cbece
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989831507 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.2989831507
Directory /workspace/29.clkmgr_frequency/latest

Test location /workspace/coverage/default/29.clkmgr_frequency_timeout.1482509613
Short name T231
Test name
Test status
Simulation time 738335460 ps
CPU time 5.89 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201184 kb
Host smart-1c7f7ff7-35b1-4103-a5c6-e0322c6370c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482509613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_t
imeout.1482509613
Directory /workspace/29.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/29.clkmgr_idle_intersig_mubi.3559606334
Short name T403
Test name
Test status
Simulation time 15972375 ps
CPU time 0.71 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201100 kb
Host smart-2af6ad1c-f301-4e32-91bf-569700fff80a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559606334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_idle_intersig_mubi.3559606334
Directory /workspace/29.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.2024021489
Short name T705
Test name
Test status
Simulation time 252972001 ps
CPU time 1.5 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201076 kb
Host smart-74baaa02-ef49-4a33-b0fe-3f233a28b0a8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024021489 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 29.clkmgr_lc_clk_byp_req_intersig_mubi.2024021489
Directory /workspace/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.844215080
Short name T54
Test name
Test status
Simulation time 59125175 ps
CPU time 1.01 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201092 kb
Host smart-60870d3a-661a-4fa8-ab58-830ffa5e4742
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844215080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 29.clkmgr_lc_ctrl_intersig_mubi.844215080
Directory /workspace/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/29.clkmgr_peri.1407451692
Short name T359
Test name
Test status
Simulation time 16693206 ps
CPU time 0.79 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:13 PM PDT 24
Peak memory 200988 kb
Host smart-51739d9e-7c4a-43ac-8dc3-23710323d926
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407451692 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.1407451692
Directory /workspace/29.clkmgr_peri/latest

Test location /workspace/coverage/default/29.clkmgr_regwen.2810821913
Short name T126
Test name
Test status
Simulation time 142238853 ps
CPU time 1.57 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201068 kb
Host smart-9757a79a-81ba-4ddf-9eaa-25f72dc2fa33
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810821913 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.2810821913
Directory /workspace/29.clkmgr_regwen/latest

Test location /workspace/coverage/default/29.clkmgr_smoke.1759706392
Short name T561
Test name
Test status
Simulation time 68214737 ps
CPU time 0.94 seconds
Started Aug 07 05:05:51 PM PDT 24
Finished Aug 07 05:05:52 PM PDT 24
Peak memory 200972 kb
Host smart-f9eeae8e-b6a3-4801-9b27-85954278cc92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759706392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.1759706392
Directory /workspace/29.clkmgr_smoke/latest

Test location /workspace/coverage/default/29.clkmgr_stress_all.4176249020
Short name T154
Test name
Test status
Simulation time 5750999650 ps
CPU time 20.48 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 201440 kb
Host smart-fa08b49f-720a-4769-a0e4-3cbf7653db57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176249020 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.clkmgr_stress_all.4176249020
Directory /workspace/29.clkmgr_stress_all/latest

Test location /workspace/coverage/default/29.clkmgr_trans.2168792365
Short name T232
Test name
Test status
Simulation time 71585051 ps
CPU time 1 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201132 kb
Host smart-eb0a4f2f-4961-45d4-851f-22e20dc98fe5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168792365 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.2168792365
Directory /workspace/29.clkmgr_trans/latest

Test location /workspace/coverage/default/3.clkmgr_alert_test.2776785490
Short name T329
Test name
Test status
Simulation time 35813154 ps
CPU time 0.84 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 201104 kb
Host smart-6d747445-3a3f-4c6f-a2e6-a8e141a81342
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776785490 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkm
gr_alert_test.2776785490
Directory /workspace/3.clkmgr_alert_test/latest

Test location /workspace/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.3667832996
Short name T520
Test name
Test status
Simulation time 22914233 ps
CPU time 0.86 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201056 kb
Host smart-fa86bd92-9833-44c2-b51e-a56e72d15837
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667832996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_clk_handshake_intersig_mubi.3667832996
Directory /workspace/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_clk_status.1983401113
Short name T389
Test name
Test status
Simulation time 48552555 ps
CPU time 0.81 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 201024 kb
Host smart-311b110b-af34-44a0-82c1-1377ba9a45b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983401113 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1983401113
Directory /workspace/3.clkmgr_clk_status/latest

Test location /workspace/coverage/default/3.clkmgr_div_intersig_mubi.2170217500
Short name T664
Test name
Test status
Simulation time 46712548 ps
CPU time 0.85 seconds
Started Aug 07 05:02:11 PM PDT 24
Finished Aug 07 05:02:12 PM PDT 24
Peak memory 200976 kb
Host smart-888eb7d7-c413-4534-9f0b-590e958c4708
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170217500 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_div_intersig_mubi.2170217500
Directory /workspace/3.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_extclk.4284002450
Short name T493
Test name
Test status
Simulation time 14374309 ps
CPU time 0.79 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 200980 kb
Host smart-735a536b-d044-4d78-a0d1-6f429afd9344
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284002450 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.4284002450
Directory /workspace/3.clkmgr_extclk/latest

Test location /workspace/coverage/default/3.clkmgr_frequency.1293636807
Short name T11
Test name
Test status
Simulation time 1039442413 ps
CPU time 6.62 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201060 kb
Host smart-1010990b-bb90-47b3-a174-70b0ab48cfbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293636807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.1293636807
Directory /workspace/3.clkmgr_frequency/latest

Test location /workspace/coverage/default/3.clkmgr_frequency_timeout.3365701281
Short name T198
Test name
Test status
Simulation time 674431972 ps
CPU time 2.91 seconds
Started Aug 07 05:02:05 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 201228 kb
Host smart-ac64618c-fbe0-4d27-b563-a5e283f59198
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365701281 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_ti
meout.3365701281
Directory /workspace/3.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/3.clkmgr_idle_intersig_mubi.3712798006
Short name T348
Test name
Test status
Simulation time 30533193 ps
CPU time 1 seconds
Started Aug 07 05:02:09 PM PDT 24
Finished Aug 07 05:02:10 PM PDT 24
Peak memory 201092 kb
Host smart-61ae9e30-c0d4-40b0-a2e0-594535db3552
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712798006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_idle_intersig_mubi.3712798006
Directory /workspace/3.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1485415013
Short name T505
Test name
Test status
Simulation time 59951593 ps
CPU time 0.97 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201100 kb
Host smart-15b3354e-15a0-4b36-90b5-4cff5d1deb42
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485415013 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_clk_byp_req_intersig_mubi.1485415013
Directory /workspace/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3984447676
Short name T791
Test name
Test status
Simulation time 36065669 ps
CPU time 0.85 seconds
Started Aug 07 05:02:06 PM PDT 24
Finished Aug 07 05:02:07 PM PDT 24
Peak memory 201060 kb
Host smart-3dd6d718-6d43-4cce-8fd4-f3227bb3bf7d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984447676 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 3.clkmgr_lc_ctrl_intersig_mubi.3984447676
Directory /workspace/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/3.clkmgr_peri.948418240
Short name T432
Test name
Test status
Simulation time 17643039 ps
CPU time 0.77 seconds
Started Aug 07 05:02:08 PM PDT 24
Finished Aug 07 05:02:09 PM PDT 24
Peak memory 201072 kb
Host smart-25e8976e-9f0d-4975-aeeb-e7faa7f270ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948418240 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.948418240
Directory /workspace/3.clkmgr_peri/latest

Test location /workspace/coverage/default/3.clkmgr_regwen.1226286211
Short name T277
Test name
Test status
Simulation time 687052312 ps
CPU time 2.59 seconds
Started Aug 07 05:02:10 PM PDT 24
Finished Aug 07 05:02:13 PM PDT 24
Peak memory 201280 kb
Host smart-e530ab34-ea15-4e41-a305-a9c4dd129124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226286211 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.1226286211
Directory /workspace/3.clkmgr_regwen/latest

Test location /workspace/coverage/default/3.clkmgr_smoke.2535716283
Short name T525
Test name
Test status
Simulation time 18645429 ps
CPU time 0.85 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201060 kb
Host smart-88a315bb-4fa8-4ddd-9faa-124602bcfcdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535716283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.2535716283
Directory /workspace/3.clkmgr_smoke/latest

Test location /workspace/coverage/default/3.clkmgr_stress_all.1874748760
Short name T369
Test name
Test status
Simulation time 330097022 ps
CPU time 2.52 seconds
Started Aug 07 05:02:06 PM PDT 24
Finished Aug 07 05:02:09 PM PDT 24
Peak memory 201264 kb
Host smart-30d69280-64a8-4b31-a061-d391d95b1a6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874748760 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.clkmgr_stress_all.1874748760
Directory /workspace/3.clkmgr_stress_all/latest

Test location /workspace/coverage/default/3.clkmgr_trans.4073317103
Short name T134
Test name
Test status
Simulation time 78923255 ps
CPU time 1.05 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 201036 kb
Host smart-dd6a15a0-7bc4-40e3-97a0-24b377152633
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073317103 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.4073317103
Directory /workspace/3.clkmgr_trans/latest

Test location /workspace/coverage/default/30.clkmgr_alert_test.1125587845
Short name T206
Test name
Test status
Simulation time 43644973 ps
CPU time 0.89 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201080 kb
Host smart-b0dd57eb-24a1-48cc-a4c1-5c334a83d6be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125587845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clk
mgr_alert_test.1125587845
Directory /workspace/30.clkmgr_alert_test/latest

Test location /workspace/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1975976777
Short name T43
Test name
Test status
Simulation time 17905519 ps
CPU time 0.83 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201088 kb
Host smart-7e1028d8-0499-4db6-9161-328c7b206e57
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975976777 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_clk_handshake_intersig_mubi.1975976777
Directory /workspace/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_clk_status.1590214475
Short name T211
Test name
Test status
Simulation time 15304803 ps
CPU time 0.71 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 200220 kb
Host smart-9e901346-eae6-47f8-b798-0b2191c8e7f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590214475 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1590214475
Directory /workspace/30.clkmgr_clk_status/latest

Test location /workspace/coverage/default/30.clkmgr_div_intersig_mubi.1176458502
Short name T361
Test name
Test status
Simulation time 91472317 ps
CPU time 1.03 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201088 kb
Host smart-c0b92c62-4443-40d2-ba8a-99d010d511d3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176458502 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_div_intersig_mubi.1176458502
Directory /workspace/30.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_extclk.709288265
Short name T526
Test name
Test status
Simulation time 37615476 ps
CPU time 0.88 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201116 kb
Host smart-e65a072a-e9da-4fba-8ef7-51af859d14ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709288265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.709288265
Directory /workspace/30.clkmgr_extclk/latest

Test location /workspace/coverage/default/30.clkmgr_frequency.2783538017
Short name T619
Test name
Test status
Simulation time 2397668787 ps
CPU time 11.01 seconds
Started Aug 07 05:03:55 PM PDT 24
Finished Aug 07 05:04:06 PM PDT 24
Peak memory 201396 kb
Host smart-f52e7def-99c6-4d9b-9181-155425ce38a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783538017 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.2783538017
Directory /workspace/30.clkmgr_frequency/latest

Test location /workspace/coverage/default/30.clkmgr_frequency_timeout.2259150802
Short name T286
Test name
Test status
Simulation time 2056923296 ps
CPU time 14.72 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201336 kb
Host smart-11a7e496-f7cd-42aa-80bb-d7fce0f55751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259150802 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_t
imeout.2259150802
Directory /workspace/30.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/30.clkmgr_idle_intersig_mubi.3327297403
Short name T202
Test name
Test status
Simulation time 71557381 ps
CPU time 0.95 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201100 kb
Host smart-8083b0eb-e4df-48ee-b35f-8aca7d9e012e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327297403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_idle_intersig_mubi.3327297403
Directory /workspace/30.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.358001225
Short name T40
Test name
Test status
Simulation time 89309787 ps
CPU time 1.03 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201004 kb
Host smart-794dc387-63de-4388-ab13-cd87e4261a76
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358001225 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 30.clkmgr_lc_clk_byp_req_intersig_mubi.358001225
Directory /workspace/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.1755280025
Short name T238
Test name
Test status
Simulation time 23427365 ps
CPU time 0.88 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201084 kb
Host smart-1b592b6d-9e9d-4e64-86b6-44379a69ff18
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755280025 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 30.clkmgr_lc_ctrl_intersig_mubi.1755280025
Directory /workspace/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/30.clkmgr_peri.397166780
Short name T798
Test name
Test status
Simulation time 34535781 ps
CPU time 0.78 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201024 kb
Host smart-af416a55-c52b-47d9-b3f6-178679b37c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397166780 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.397166780
Directory /workspace/30.clkmgr_peri/latest

Test location /workspace/coverage/default/30.clkmgr_regwen.3881549419
Short name T180
Test name
Test status
Simulation time 873322640 ps
CPU time 5.44 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201304 kb
Host smart-4b61bdec-2fe4-4e2d-8659-04da90c4e323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881549419 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3881549419
Directory /workspace/30.clkmgr_regwen/latest

Test location /workspace/coverage/default/30.clkmgr_smoke.886950904
Short name T228
Test name
Test status
Simulation time 63206855 ps
CPU time 0.99 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201092 kb
Host smart-6301937c-86bb-4eef-94a3-f59f9ade6138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886950904 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.886950904
Directory /workspace/30.clkmgr_smoke/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all.2764286354
Short name T380
Test name
Test status
Simulation time 2726506259 ps
CPU time 21.03 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:35 PM PDT 24
Peak memory 201416 kb
Host smart-ccad99da-9fd4-4b2f-a378-ecb2648e95c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764286354 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.clkmgr_stress_all.2764286354
Directory /workspace/30.clkmgr_stress_all/latest

Test location /workspace/coverage/default/30.clkmgr_stress_all_with_rand_reset.2952095105
Short name T3
Test name
Test status
Simulation time 60473315646 ps
CPU time 575.17 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:12:51 PM PDT 24
Peak memory 209804 kb
Host smart-ab966523-cf64-400b-968f-2da61893ba6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2952095105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2952095105
Directory /workspace/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.clkmgr_trans.2908215799
Short name T586
Test name
Test status
Simulation time 19505336 ps
CPU time 0.83 seconds
Started Aug 07 05:03:12 PM PDT 24
Finished Aug 07 05:03:13 PM PDT 24
Peak memory 201008 kb
Host smart-1e5593fd-9db8-48c6-9193-c928659c4e53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908215799 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.2908215799
Directory /workspace/30.clkmgr_trans/latest

Test location /workspace/coverage/default/31.clkmgr_alert_test.1086177546
Short name T741
Test name
Test status
Simulation time 92242692 ps
CPU time 1.09 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201100 kb
Host smart-df5ff0b0-8d42-4930-978b-6cb5a1b05dff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086177546 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clk
mgr_alert_test.1086177546
Directory /workspace/31.clkmgr_alert_test/latest

Test location /workspace/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.11942574
Short name T489
Test name
Test status
Simulation time 16521830 ps
CPU time 0.74 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201100 kb
Host smart-ef8d0aef-8b3f-41ee-a361-cdf92fe012f4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11942574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
1.clkmgr_clk_handshake_intersig_mubi.11942574
Directory /workspace/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_clk_status.3801754994
Short name T579
Test name
Test status
Simulation time 92783614 ps
CPU time 0.95 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 200220 kb
Host smart-56bf4f60-8dd7-4983-b7ed-8bfbf9cc490d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801754994 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.3801754994
Directory /workspace/31.clkmgr_clk_status/latest

Test location /workspace/coverage/default/31.clkmgr_div_intersig_mubi.4144095212
Short name T786
Test name
Test status
Simulation time 16465984 ps
CPU time 0.79 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201056 kb
Host smart-72dbdadb-4bf1-4e4a-9797-788d993530a7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144095212 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_div_intersig_mubi.4144095212
Directory /workspace/31.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_extclk.3161710114
Short name T762
Test name
Test status
Simulation time 40907866 ps
CPU time 0.89 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201032 kb
Host smart-cb6dafc2-6455-44c0-81be-3ac3ef695c1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161710114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3161710114
Directory /workspace/31.clkmgr_extclk/latest

Test location /workspace/coverage/default/31.clkmgr_frequency.2007340837
Short name T706
Test name
Test status
Simulation time 323566879 ps
CPU time 3.08 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201068 kb
Host smart-c7951127-ed45-41b3-b291-842560be74ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007340837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.2007340837
Directory /workspace/31.clkmgr_frequency/latest

Test location /workspace/coverage/default/31.clkmgr_frequency_timeout.2928770629
Short name T27
Test name
Test status
Simulation time 1819377505 ps
CPU time 14.29 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 200508 kb
Host smart-273f9ae0-3370-427b-872a-c8d0991dcdcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928770629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_t
imeout.2928770629
Directory /workspace/31.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/31.clkmgr_idle_intersig_mubi.1690302767
Short name T384
Test name
Test status
Simulation time 15036307 ps
CPU time 0.77 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201068 kb
Host smart-99139072-1abb-4431-be07-12adcc44b43d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690302767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_idle_intersig_mubi.1690302767
Directory /workspace/31.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2513015420
Short name T48
Test name
Test status
Simulation time 22379114 ps
CPU time 0.87 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201060 kb
Host smart-42d1c9a8-00d8-4fdb-b24a-84168957dbfa
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513015420 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_clk_byp_req_intersig_mubi.2513015420
Directory /workspace/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.1030200916
Short name T593
Test name
Test status
Simulation time 65021774 ps
CPU time 0.94 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201040 kb
Host smart-4a7c76eb-d2c1-484b-86cb-4d8ff44a6a43
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030200916 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 31.clkmgr_lc_ctrl_intersig_mubi.1030200916
Directory /workspace/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/31.clkmgr_peri.1362346824
Short name T616
Test name
Test status
Simulation time 29180187 ps
CPU time 0.76 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201040 kb
Host smart-759dfef0-f899-42d1-8e0a-c6e47431dac9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362346824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.1362346824
Directory /workspace/31.clkmgr_peri/latest

Test location /workspace/coverage/default/31.clkmgr_regwen.28712935
Short name T292
Test name
Test status
Simulation time 633222442 ps
CPU time 3.86 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 201300 kb
Host smart-d5863467-3d3e-4a9f-ae3e-9f8bee21a98b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28712935 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.28712935
Directory /workspace/31.clkmgr_regwen/latest

Test location /workspace/coverage/default/31.clkmgr_smoke.3143662416
Short name T709
Test name
Test status
Simulation time 53970629 ps
CPU time 0.95 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201056 kb
Host smart-5db10ceb-ee2e-400c-af75-b7855a87b941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143662416 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3143662416
Directory /workspace/31.clkmgr_smoke/latest

Test location /workspace/coverage/default/31.clkmgr_stress_all.1217899601
Short name T656
Test name
Test status
Simulation time 8150036247 ps
CPU time 54.73 seconds
Started Aug 07 05:03:15 PM PDT 24
Finished Aug 07 05:04:10 PM PDT 24
Peak memory 201416 kb
Host smart-5aa5d0a3-42d2-4b27-b88e-cf43d49471b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217899601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.clkmgr_stress_all.1217899601
Directory /workspace/31.clkmgr_stress_all/latest

Test location /workspace/coverage/default/31.clkmgr_trans.182588465
Short name T565
Test name
Test status
Simulation time 77078615 ps
CPU time 1.02 seconds
Started Aug 07 05:03:50 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 201060 kb
Host smart-bae1357c-7f08-4f4b-bca3-5249a19bdec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182588465 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.182588465
Directory /workspace/31.clkmgr_trans/latest

Test location /workspace/coverage/default/32.clkmgr_alert_test.4262701080
Short name T769
Test name
Test status
Simulation time 42269089 ps
CPU time 0.87 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201060 kb
Host smart-f6dc4c46-708a-4821-a7d5-48bf8eec48a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262701080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clk
mgr_alert_test.4262701080
Directory /workspace/32.clkmgr_alert_test/latest

Test location /workspace/coverage/default/32.clkmgr_clk_status.1194130445
Short name T590
Test name
Test status
Simulation time 147731253 ps
CPU time 1.07 seconds
Started Aug 07 05:03:17 PM PDT 24
Finished Aug 07 05:03:18 PM PDT 24
Peak memory 200876 kb
Host smart-25c137b0-5183-411f-8ce2-51c62bd9a79f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194130445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.1194130445
Directory /workspace/32.clkmgr_clk_status/latest

Test location /workspace/coverage/default/32.clkmgr_div_intersig_mubi.3971849520
Short name T287
Test name
Test status
Simulation time 45677745 ps
CPU time 1.02 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 201064 kb
Host smart-e7b51d8b-007e-49e4-84c0-bcf18647b6c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971849520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_div_intersig_mubi.3971849520
Directory /workspace/32.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_extclk.3905423430
Short name T239
Test name
Test status
Simulation time 125566166 ps
CPU time 1.14 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201104 kb
Host smart-0228d282-c7bf-46d7-bbce-437015ea4e99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905423430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.3905423430
Directory /workspace/32.clkmgr_extclk/latest

Test location /workspace/coverage/default/32.clkmgr_frequency.421534575
Short name T385
Test name
Test status
Simulation time 2238943887 ps
CPU time 17.26 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201380 kb
Host smart-a47702f2-3fd2-4c33-81bf-f717806188fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421534575 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.421534575
Directory /workspace/32.clkmgr_frequency/latest

Test location /workspace/coverage/default/32.clkmgr_frequency_timeout.1715926316
Short name T470
Test name
Test status
Simulation time 2376870279 ps
CPU time 10.33 seconds
Started Aug 07 05:03:17 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201308 kb
Host smart-db4cca06-5f2b-43e3-9313-aa13a02aa79b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715926316 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_t
imeout.1715926316
Directory /workspace/32.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/32.clkmgr_idle_intersig_mubi.1790211976
Short name T567
Test name
Test status
Simulation time 36993067 ps
CPU time 0.83 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201048 kb
Host smart-32bcef98-c1ad-4db1-9d9b-87a210ef333a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790211976 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_idle_intersig_mubi.1790211976
Directory /workspace/32.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.892865719
Short name T175
Test name
Test status
Simulation time 88323232 ps
CPU time 1.04 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201052 kb
Host smart-f73d60e3-1714-4e5d-b730-15dbfbffa58c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892865719 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 32.clkmgr_lc_clk_byp_req_intersig_mubi.892865719
Directory /workspace/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.1468747840
Short name T581
Test name
Test status
Simulation time 27080224 ps
CPU time 0.85 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 201080 kb
Host smart-5146a27f-245b-4662-9360-4a7333b249ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468747840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 32.clkmgr_lc_ctrl_intersig_mubi.1468747840
Directory /workspace/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/32.clkmgr_peri.1981355331
Short name T215
Test name
Test status
Simulation time 44408217 ps
CPU time 0.87 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:14 PM PDT 24
Peak memory 200968 kb
Host smart-89222782-3223-408a-a686-194c4dfffdb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981355331 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.1981355331
Directory /workspace/32.clkmgr_peri/latest

Test location /workspace/coverage/default/32.clkmgr_regwen.4241859574
Short name T442
Test name
Test status
Simulation time 1039025441 ps
CPU time 5.91 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201228 kb
Host smart-f6a415a3-5a33-40fb-aa38-a62e7a058dcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241859574 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.4241859574
Directory /workspace/32.clkmgr_regwen/latest

Test location /workspace/coverage/default/32.clkmgr_smoke.655432457
Short name T153
Test name
Test status
Simulation time 25664850 ps
CPU time 0.91 seconds
Started Aug 07 05:03:14 PM PDT 24
Finished Aug 07 05:03:16 PM PDT 24
Peak memory 201000 kb
Host smart-7a06889f-1c8d-4093-9daf-72a022e315d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655432457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.655432457
Directory /workspace/32.clkmgr_smoke/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all.1494542027
Short name T501
Test name
Test status
Simulation time 4686665349 ps
CPU time 33.58 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:54 PM PDT 24
Peak memory 201388 kb
Host smart-928f703c-8721-47ac-9756-698af5e47cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494542027 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.clkmgr_stress_all.1494542027
Directory /workspace/32.clkmgr_stress_all/latest

Test location /workspace/coverage/default/32.clkmgr_stress_all_with_rand_reset.437237730
Short name T56
Test name
Test status
Simulation time 151082366146 ps
CPU time 1228.21 seconds
Started Aug 07 05:03:22 PM PDT 24
Finished Aug 07 05:23:50 PM PDT 24
Peak memory 217916 kb
Host smart-c2ed0e62-10fe-419d-ab07-e4453e9aad30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=437237730 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.437237730
Directory /workspace/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.clkmgr_trans.3241117340
Short name T283
Test name
Test status
Simulation time 42286351 ps
CPU time 0.81 seconds
Started Aug 07 05:03:13 PM PDT 24
Finished Aug 07 05:03:15 PM PDT 24
Peak memory 201088 kb
Host smart-498dc383-f241-44d8-90c5-baaf1adf1edf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241117340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.3241117340
Directory /workspace/32.clkmgr_trans/latest

Test location /workspace/coverage/default/33.clkmgr_alert_test.2600079789
Short name T307
Test name
Test status
Simulation time 109766339 ps
CPU time 1.05 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201056 kb
Host smart-0c63013e-9471-4ea0-b5c8-b59de897a7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600079789 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clk
mgr_alert_test.2600079789
Directory /workspace/33.clkmgr_alert_test/latest

Test location /workspace/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.2071950268
Short name T365
Test name
Test status
Simulation time 16897748 ps
CPU time 0.74 seconds
Started Aug 07 05:04:01 PM PDT 24
Finished Aug 07 05:04:02 PM PDT 24
Peak memory 201100 kb
Host smart-7ec13cf0-1f11-410d-85f9-96df04194629
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071950268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_clk_handshake_intersig_mubi.2071950268
Directory /workspace/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_clk_status.2709775722
Short name T393
Test name
Test status
Simulation time 15260352 ps
CPU time 0.75 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 200332 kb
Host smart-9381d9b3-9cd3-469a-9839-6468e802a96b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709775722 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.2709775722
Directory /workspace/33.clkmgr_clk_status/latest

Test location /workspace/coverage/default/33.clkmgr_div_intersig_mubi.4110190438
Short name T336
Test name
Test status
Simulation time 48895704 ps
CPU time 0.92 seconds
Started Aug 07 05:03:16 PM PDT 24
Finished Aug 07 05:03:17 PM PDT 24
Peak memory 201108 kb
Host smart-d3fda400-0cf9-44ed-8865-4faa7a607173
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110190438 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_div_intersig_mubi.4110190438
Directory /workspace/33.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_extclk.71405498
Short name T503
Test name
Test status
Simulation time 15307780 ps
CPU time 0.8 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201088 kb
Host smart-a15e1bac-7ce4-437f-8341-fea8db5aacdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71405498 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.71405498
Directory /workspace/33.clkmgr_extclk/latest

Test location /workspace/coverage/default/33.clkmgr_frequency.208600606
Short name T392
Test name
Test status
Simulation time 319641529 ps
CPU time 3.01 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 201204 kb
Host smart-a2ffdca1-ee36-4c3a-982b-dc82ff8ea28d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208600606 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.208600606
Directory /workspace/33.clkmgr_frequency/latest

Test location /workspace/coverage/default/33.clkmgr_frequency_timeout.3525008455
Short name T532
Test name
Test status
Simulation time 2313993121 ps
CPU time 9.9 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201364 kb
Host smart-9b208b94-8b46-4729-889c-c0478e78e8c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525008455 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_t
imeout.3525008455
Directory /workspace/33.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/33.clkmgr_idle_intersig_mubi.246239468
Short name T494
Test name
Test status
Simulation time 59980105 ps
CPU time 0.91 seconds
Started Aug 07 05:03:17 PM PDT 24
Finished Aug 07 05:03:18 PM PDT 24
Peak memory 201076 kb
Host smart-c4c8ef6f-25e8-417f-8b01-babf4b4231f5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246239468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
3.clkmgr_idle_intersig_mubi.246239468
Directory /workspace/33.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.2023984545
Short name T802
Test name
Test status
Simulation time 23994883 ps
CPU time 0.87 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201072 kb
Host smart-cb4790fd-9958-458a-97fe-5e53f794233f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023984545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_clk_byp_req_intersig_mubi.2023984545
Directory /workspace/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.1677188224
Short name T305
Test name
Test status
Simulation time 51039572 ps
CPU time 0.85 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201132 kb
Host smart-6901cb23-096a-4ef1-a0ff-69ff4da8b8c2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677188224 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 33.clkmgr_lc_ctrl_intersig_mubi.1677188224
Directory /workspace/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/33.clkmgr_peri.545588940
Short name T79
Test name
Test status
Simulation time 49109893 ps
CPU time 0.89 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 201072 kb
Host smart-811b2260-d1a7-4a06-93f3-96f9fcd573e6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545588940 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.545588940
Directory /workspace/33.clkmgr_peri/latest

Test location /workspace/coverage/default/33.clkmgr_regwen.788290636
Short name T574
Test name
Test status
Simulation time 182596188 ps
CPU time 1.3 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 201008 kb
Host smart-ffbca4b6-2dd1-46bc-8a81-4a56f962a683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788290636 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.788290636
Directory /workspace/33.clkmgr_regwen/latest

Test location /workspace/coverage/default/33.clkmgr_smoke.4099774042
Short name T19
Test name
Test status
Simulation time 42065141 ps
CPU time 0.96 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 200932 kb
Host smart-0be16ea4-ad2d-4ca9-b067-b3c48143da35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099774042 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.4099774042
Directory /workspace/33.clkmgr_smoke/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all.2554497629
Short name T794
Test name
Test status
Simulation time 10028083216 ps
CPU time 34.99 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:55 PM PDT 24
Peak memory 201516 kb
Host smart-20f96df7-ff53-40f4-981d-d1b376746ae8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554497629 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.clkmgr_stress_all.2554497629
Directory /workspace/33.clkmgr_stress_all/latest

Test location /workspace/coverage/default/33.clkmgr_stress_all_with_rand_reset.229625265
Short name T73
Test name
Test status
Simulation time 41533057724 ps
CPU time 309.27 seconds
Started Aug 07 05:04:02 PM PDT 24
Finished Aug 07 05:09:12 PM PDT 24
Peak memory 217604 kb
Host smart-e8f7ce5d-c1b9-467d-93d5-2a3611dc6123
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=229625265 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.229625265
Directory /workspace/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.clkmgr_trans.3169055004
Short name T445
Test name
Test status
Simulation time 186774812 ps
CPU time 1.24 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201072 kb
Host smart-e3831a1e-9ad1-4b15-a8cd-587fd9d28395
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169055004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.3169055004
Directory /workspace/33.clkmgr_trans/latest

Test location /workspace/coverage/default/34.clkmgr_alert_test.1387995412
Short name T478
Test name
Test status
Simulation time 57368406 ps
CPU time 0.88 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201144 kb
Host smart-ba90fb32-8b25-43e3-899b-f5bae5458fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387995412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clk
mgr_alert_test.1387995412
Directory /workspace/34.clkmgr_alert_test/latest

Test location /workspace/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3714060622
Short name T748
Test name
Test status
Simulation time 53758807 ps
CPU time 0.88 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 200964 kb
Host smart-8b76fedf-c96b-4bd5-b0be-038b75c4c15a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714060622 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_clk_handshake_intersig_mubi.3714060622
Directory /workspace/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_clk_status.4189927598
Short name T291
Test name
Test status
Simulation time 17187783 ps
CPU time 0.75 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 200332 kb
Host smart-08680954-af20-400c-a178-f8858f316c4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189927598 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.4189927598
Directory /workspace/34.clkmgr_clk_status/latest

Test location /workspace/coverage/default/34.clkmgr_div_intersig_mubi.2776479528
Short name T352
Test name
Test status
Simulation time 102132499 ps
CPU time 1.06 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201100 kb
Host smart-7afdace1-192f-40e8-b634-37e1e331ce49
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776479528 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_div_intersig_mubi.2776479528
Directory /workspace/34.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_extclk.3921023706
Short name T300
Test name
Test status
Simulation time 20819751 ps
CPU time 0.79 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201084 kb
Host smart-cb7242b6-f4d7-44a5-a3e8-2907fda063c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921023706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.3921023706
Directory /workspace/34.clkmgr_extclk/latest

Test location /workspace/coverage/default/34.clkmgr_frequency.437857378
Short name T648
Test name
Test status
Simulation time 1674710848 ps
CPU time 6.94 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201112 kb
Host smart-f5a6abc2-0d99-4d3d-966b-50c5ea0ce170
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437857378 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.437857378
Directory /workspace/34.clkmgr_frequency/latest

Test location /workspace/coverage/default/34.clkmgr_frequency_timeout.1801189083
Short name T413
Test name
Test status
Simulation time 852660344 ps
CPU time 3.37 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:23 PM PDT 24
Peak memory 201196 kb
Host smart-6dc6572f-5aef-4b0d-902e-d13288eec738
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801189083 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_t
imeout.1801189083
Directory /workspace/34.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/34.clkmgr_idle_intersig_mubi.492326853
Short name T473
Test name
Test status
Simulation time 36426474 ps
CPU time 1.02 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201060 kb
Host smart-fdfab8ed-eadc-4c24-b4ad-03e8d30d8455
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492326853 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
4.clkmgr_idle_intersig_mubi.492326853
Directory /workspace/34.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.976712040
Short name T431
Test name
Test status
Simulation time 62658351 ps
CPU time 0.93 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201100 kb
Host smart-9bf0334a-b64e-474b-b0bf-ebe712b8aa24
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976712040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 34.clkmgr_lc_clk_byp_req_intersig_mubi.976712040
Directory /workspace/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.4096783646
Short name T637
Test name
Test status
Simulation time 35381828 ps
CPU time 0.79 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201116 kb
Host smart-00b16941-75da-4753-a580-eb77a4898199
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096783646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 34.clkmgr_lc_ctrl_intersig_mubi.4096783646
Directory /workspace/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/34.clkmgr_peri.1049394768
Short name T390
Test name
Test status
Simulation time 19436674 ps
CPU time 0.78 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 201068 kb
Host smart-7ddeb3c7-92a9-45ba-8e58-bb6cc25a72a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049394768 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.1049394768
Directory /workspace/34.clkmgr_peri/latest

Test location /workspace/coverage/default/34.clkmgr_regwen.373897848
Short name T176
Test name
Test status
Simulation time 1848721649 ps
CPU time 6.22 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 201280 kb
Host smart-a8ce65ad-9fb7-4945-9a2c-6cc80bf9091e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373897848 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.373897848
Directory /workspace/34.clkmgr_regwen/latest

Test location /workspace/coverage/default/34.clkmgr_smoke.4079523313
Short name T697
Test name
Test status
Simulation time 68269649 ps
CPU time 1.02 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201096 kb
Host smart-c037ff71-fa2f-462f-a78a-89433f92e201
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079523313 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.4079523313
Directory /workspace/34.clkmgr_smoke/latest

Test location /workspace/coverage/default/34.clkmgr_stress_all.907364180
Short name T731
Test name
Test status
Simulation time 15099648458 ps
CPU time 55.45 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:04:16 PM PDT 24
Peak memory 201516 kb
Host smart-c34da8de-3596-4044-b9c3-580826fd2ac7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907364180 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.clkmgr_stress_all.907364180
Directory /workspace/34.clkmgr_stress_all/latest

Test location /workspace/coverage/default/34.clkmgr_trans.639756018
Short name T487
Test name
Test status
Simulation time 56228435 ps
CPU time 1.03 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201060 kb
Host smart-8f44a39d-fb6e-4f64-90b0-45eebded3077
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639756018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.639756018
Directory /workspace/34.clkmgr_trans/latest

Test location /workspace/coverage/default/35.clkmgr_alert_test.1034875950
Short name T778
Test name
Test status
Simulation time 28056270 ps
CPU time 0.81 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 200964 kb
Host smart-dd8fb8c8-bba1-4dcf-801a-415c8c102656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034875950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clk
mgr_alert_test.1034875950
Directory /workspace/35.clkmgr_alert_test/latest

Test location /workspace/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.1260910543
Short name T103
Test name
Test status
Simulation time 101173467 ps
CPU time 1.14 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201024 kb
Host smart-fcae1798-ce09-404a-bc92-b9f3843aee7b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260910543 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_clk_handshake_intersig_mubi.1260910543
Directory /workspace/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_clk_status.646889671
Short name T364
Test name
Test status
Simulation time 27205445 ps
CPU time 0.73 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 200972 kb
Host smart-cf7bae75-6ada-4cf7-8502-c60a2be5007c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646889671 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.646889671
Directory /workspace/35.clkmgr_clk_status/latest

Test location /workspace/coverage/default/35.clkmgr_div_intersig_mubi.2752886662
Short name T301
Test name
Test status
Simulation time 66689640 ps
CPU time 1 seconds
Started Aug 07 05:03:22 PM PDT 24
Finished Aug 07 05:03:23 PM PDT 24
Peak memory 201112 kb
Host smart-b02d150b-9762-4489-bccb-4506dd5aedc6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752886662 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_div_intersig_mubi.2752886662
Directory /workspace/35.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_extclk.1507700724
Short name T189
Test name
Test status
Simulation time 33415227 ps
CPU time 0.88 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 201116 kb
Host smart-d25258ff-ac36-4cb0-9e4a-1189528b4c22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507700724 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.1507700724
Directory /workspace/35.clkmgr_extclk/latest

Test location /workspace/coverage/default/35.clkmgr_frequency.2474316064
Short name T257
Test name
Test status
Simulation time 1042925193 ps
CPU time 8.85 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:04:07 PM PDT 24
Peak memory 201228 kb
Host smart-793e873f-a711-4774-a57b-b4e9af6cb0ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474316064 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.2474316064
Directory /workspace/35.clkmgr_frequency/latest

Test location /workspace/coverage/default/35.clkmgr_frequency_timeout.2667541040
Short name T316
Test name
Test status
Simulation time 1588863165 ps
CPU time 8.7 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201208 kb
Host smart-da4b9e96-b2f2-4b46-9f83-5a31844dadb5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667541040 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_t
imeout.2667541040
Directory /workspace/35.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/35.clkmgr_idle_intersig_mubi.1447619402
Short name T22
Test name
Test status
Simulation time 32842220 ps
CPU time 1.04 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201040 kb
Host smart-13afaf22-bf23-4904-a3f6-e3b1f6ceb88f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447619402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_idle_intersig_mubi.1447619402
Directory /workspace/35.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3348946769
Short name T661
Test name
Test status
Simulation time 30980756 ps
CPU time 0.81 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201008 kb
Host smart-c6352805-d7e4-4a75-8e18-ce517acfc261
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348946769 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_clk_byp_req_intersig_mubi.3348946769
Directory /workspace/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1611131516
Short name T439
Test name
Test status
Simulation time 41962947 ps
CPU time 0.8 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201056 kb
Host smart-8a75f103-6f8e-4bd9-9133-a9e65daea14e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611131516 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 35.clkmgr_lc_ctrl_intersig_mubi.1611131516
Directory /workspace/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/35.clkmgr_peri.2456362939
Short name T654
Test name
Test status
Simulation time 92359700 ps
CPU time 0.91 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 201084 kb
Host smart-d55b1e4f-9d70-4467-9921-699f28a5a431
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456362939 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.2456362939
Directory /workspace/35.clkmgr_peri/latest

Test location /workspace/coverage/default/35.clkmgr_regwen.2012452923
Short name T678
Test name
Test status
Simulation time 228705318 ps
CPU time 1.24 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:21 PM PDT 24
Peak memory 201068 kb
Host smart-c002a34e-d8bf-4ee9-8d2e-c8edf59508b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012452923 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2012452923
Directory /workspace/35.clkmgr_regwen/latest

Test location /workspace/coverage/default/35.clkmgr_smoke.2540559619
Short name T167
Test name
Test status
Simulation time 16473578 ps
CPU time 0.83 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 200936 kb
Host smart-ce3d4772-9034-4183-8691-7e441a0e6d6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540559619 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2540559619
Directory /workspace/35.clkmgr_smoke/latest

Test location /workspace/coverage/default/35.clkmgr_stress_all.2069249145
Short name T158
Test name
Test status
Simulation time 1096044399 ps
CPU time 4.82 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 201084 kb
Host smart-97e3b16c-3d7c-4bca-bc92-2993b1c9106c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069249145 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.clkmgr_stress_all.2069249145
Directory /workspace/35.clkmgr_stress_all/latest

Test location /workspace/coverage/default/35.clkmgr_trans.1971432340
Short name T699
Test name
Test status
Simulation time 33240798 ps
CPU time 0.82 seconds
Started Aug 07 05:03:19 PM PDT 24
Finished Aug 07 05:03:20 PM PDT 24
Peak memory 201008 kb
Host smart-0fcdf155-d8a8-4c57-b409-2d6745785724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971432340 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.1971432340
Directory /workspace/35.clkmgr_trans/latest

Test location /workspace/coverage/default/36.clkmgr_alert_test.2109566932
Short name T381
Test name
Test status
Simulation time 16405102 ps
CPU time 0.77 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 200964 kb
Host smart-a9ca29e6-c976-4f4b-8205-c0f726264c47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109566932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clk
mgr_alert_test.2109566932
Directory /workspace/36.clkmgr_alert_test/latest

Test location /workspace/coverage/default/36.clkmgr_clk_handshake_intersig_mubi.3668373990
Short name T704
Test name
Test status
Simulation time 142677764 ps
CPU time 1.13 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 201068 kb
Host smart-32d076cc-59ba-4570-ae58-9fc19fbef0f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668373990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_clk_handshake_intersig_mubi.3668373990
Directory /workspace/36.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_clk_status.646001094
Short name T499
Test name
Test status
Simulation time 15068124 ps
CPU time 0.72 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 200260 kb
Host smart-505f22f5-b634-43f4-9582-915112e5dd71
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646001094 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_clk_status.646001094
Directory /workspace/36.clkmgr_clk_status/latest

Test location /workspace/coverage/default/36.clkmgr_div_intersig_mubi.2089441346
Short name T424
Test name
Test status
Simulation time 52694247 ps
CPU time 0.99 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201080 kb
Host smart-ae92c908-c769-474e-818b-86cfe6617fab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089441346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_div_intersig_mubi.2089441346
Directory /workspace/36.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_extclk.2672077417
Short name T685
Test name
Test status
Simulation time 25035071 ps
CPU time 0.78 seconds
Started Aug 07 05:03:24 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 201088 kb
Host smart-ba621f2f-03e9-42fe-ab92-3a684fe44d4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672077417 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.2672077417
Directory /workspace/36.clkmgr_extclk/latest

Test location /workspace/coverage/default/36.clkmgr_frequency.693850326
Short name T727
Test name
Test status
Simulation time 555481340 ps
CPU time 2.57 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:24 PM PDT 24
Peak memory 201124 kb
Host smart-054c39c7-242a-4a68-96e4-a5d5c9dd7d93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693850326 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.693850326
Directory /workspace/36.clkmgr_frequency/latest

Test location /workspace/coverage/default/36.clkmgr_frequency_timeout.1345934650
Short name T736
Test name
Test status
Simulation time 1718195781 ps
CPU time 7.12 seconds
Started Aug 07 05:03:20 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201268 kb
Host smart-b5c88e31-6a1c-49e4-8f29-e6add98219bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345934650 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_t
imeout.1345934650
Directory /workspace/36.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/36.clkmgr_idle_intersig_mubi.3277454793
Short name T331
Test name
Test status
Simulation time 209297074 ps
CPU time 1.48 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 201060 kb
Host smart-2337b08e-362b-4e9a-8fc7-c42621fead14
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277454793 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_idle_intersig_mubi.3277454793
Directory /workspace/36.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.4275784932
Short name T588
Test name
Test status
Simulation time 20446874 ps
CPU time 0.81 seconds
Started Aug 07 05:03:24 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 201028 kb
Host smart-d6e84984-86d4-4e7b-b8f9-d94677e8695b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275784932 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_clk_byp_req_intersig_mubi.4275784932
Directory /workspace/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_lc_ctrl_intersig_mubi.3132743412
Short name T680
Test name
Test status
Simulation time 35521742 ps
CPU time 0.87 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:28 PM PDT 24
Peak memory 201100 kb
Host smart-8fd2721f-2a9e-4ee0-a6d5-f088460cc394
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132743412 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 36.clkmgr_lc_ctrl_intersig_mubi.3132743412
Directory /workspace/36.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/36.clkmgr_peri.557945464
Short name T510
Test name
Test status
Simulation time 16411638 ps
CPU time 0.77 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201068 kb
Host smart-a498b03c-0585-4e3a-b289-e93bdd33ee79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557945464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.557945464
Directory /workspace/36.clkmgr_peri/latest

Test location /workspace/coverage/default/36.clkmgr_regwen.3844583405
Short name T812
Test name
Test status
Simulation time 676677327 ps
CPU time 4.13 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201252 kb
Host smart-f59a5e64-ddc1-4e3e-a77c-040e4cdc5aa1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844583405 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_regwen.3844583405
Directory /workspace/36.clkmgr_regwen/latest

Test location /workspace/coverage/default/36.clkmgr_smoke.3264406981
Short name T691
Test name
Test status
Simulation time 17425763 ps
CPU time 0.8 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 200996 kb
Host smart-879eb5fc-4311-4872-a394-2251f565f2f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264406981 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.3264406981
Directory /workspace/36.clkmgr_smoke/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all.2360136545
Short name T569
Test name
Test status
Simulation time 5060533964 ps
CPU time 30.73 seconds
Started Aug 07 05:03:23 PM PDT 24
Finished Aug 07 05:03:54 PM PDT 24
Peak memory 201384 kb
Host smart-91589544-f38e-4e64-904a-b008a188940f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360136545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.clkmgr_stress_all.2360136545
Directory /workspace/36.clkmgr_stress_all/latest

Test location /workspace/coverage/default/36.clkmgr_stress_all_with_rand_reset.2364002366
Short name T77
Test name
Test status
Simulation time 32606962871 ps
CPU time 311.36 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:08:33 PM PDT 24
Peak memory 217624 kb
Host smart-18de355d-8b1a-4e17-a3a3-84de67e0de72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2364002366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_stress_all_with_rand_reset.2364002366
Directory /workspace/36.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.clkmgr_trans.2059572530
Short name T712
Test name
Test status
Simulation time 31047041 ps
CPU time 0.96 seconds
Started Aug 07 05:03:18 PM PDT 24
Finished Aug 07 05:03:19 PM PDT 24
Peak memory 201052 kb
Host smart-e3f5bf58-94bc-4764-99dd-48cf9a53b997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059572530 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.2059572530
Directory /workspace/36.clkmgr_trans/latest

Test location /workspace/coverage/default/37.clkmgr_alert_test.1560410751
Short name T679
Test name
Test status
Simulation time 38854658 ps
CPU time 0.81 seconds
Started Aug 07 05:03:28 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201052 kb
Host smart-935ca675-f649-4b78-a870-74e081bd9453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560410751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clk
mgr_alert_test.1560410751
Directory /workspace/37.clkmgr_alert_test/latest

Test location /workspace/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1166217493
Short name T104
Test name
Test status
Simulation time 19314931 ps
CPU time 0.89 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201080 kb
Host smart-5a6b9f5a-9eee-463a-bf52-e720a20e139b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166217493 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_clk_handshake_intersig_mubi.1166217493
Directory /workspace/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_clk_status.1268772379
Short name T294
Test name
Test status
Simulation time 14402778 ps
CPU time 0.72 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201044 kb
Host smart-bce04c28-63e8-41ca-adde-a2ecd14e5daa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268772379 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1268772379
Directory /workspace/37.clkmgr_clk_status/latest

Test location /workspace/coverage/default/37.clkmgr_div_intersig_mubi.4076329077
Short name T558
Test name
Test status
Simulation time 128205885 ps
CPU time 1.15 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201084 kb
Host smart-5b369465-9f54-4ad8-911a-1bb956d0ff07
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076329077 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_div_intersig_mubi.4076329077
Directory /workspace/37.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_extclk.1725796107
Short name T272
Test name
Test status
Simulation time 27389850 ps
CPU time 0.76 seconds
Started Aug 07 05:03:21 PM PDT 24
Finished Aug 07 05:03:22 PM PDT 24
Peak memory 201052 kb
Host smart-0d7c5c05-5cfa-4873-98fd-8838aa27c59c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725796107 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1725796107
Directory /workspace/37.clkmgr_extclk/latest

Test location /workspace/coverage/default/37.clkmgr_frequency.1567065729
Short name T398
Test name
Test status
Simulation time 1999742317 ps
CPU time 15.39 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:41 PM PDT 24
Peak memory 201312 kb
Host smart-72379fad-303a-411f-8b78-09c4210929d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567065729 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.1567065729
Directory /workspace/37.clkmgr_frequency/latest

Test location /workspace/coverage/default/37.clkmgr_frequency_timeout.1088848468
Short name T271
Test name
Test status
Simulation time 2295055827 ps
CPU time 15.95 seconds
Started Aug 07 05:03:22 PM PDT 24
Finished Aug 07 05:03:39 PM PDT 24
Peak memory 201396 kb
Host smart-e3b6863e-7c94-4d53-a89f-e53895d233fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088848468 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_t
imeout.1088848468
Directory /workspace/37.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/37.clkmgr_idle_intersig_mubi.3773039869
Short name T575
Test name
Test status
Simulation time 145710545 ps
CPU time 1.36 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201028 kb
Host smart-a2885d48-9d8b-41b2-8a38-2e26b514a5b4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773039869 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.clkmgr_idle_intersig_mubi.3773039869
Directory /workspace/37.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.3276196285
Short name T643
Test name
Test status
Simulation time 23982470 ps
CPU time 0.89 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 201092 kb
Host smart-03cf9898-5005-4160-b57f-3d171c3fa233
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276196285 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_clk_byp_req_intersig_mubi.3276196285
Directory /workspace/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2842006228
Short name T675
Test name
Test status
Simulation time 57342254 ps
CPU time 0.92 seconds
Started Aug 07 05:03:37 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201096 kb
Host smart-ca428267-9481-435f-bc41-528dad9b3bd0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842006228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 37.clkmgr_lc_ctrl_intersig_mubi.2842006228
Directory /workspace/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/37.clkmgr_peri.4246634402
Short name T199
Test name
Test status
Simulation time 19580658 ps
CPU time 0.75 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:28 PM PDT 24
Peak memory 201056 kb
Host smart-c98a2a8b-d8ce-443f-87e7-721c322c561b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246634402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.4246634402
Directory /workspace/37.clkmgr_peri/latest

Test location /workspace/coverage/default/37.clkmgr_regwen.1776750558
Short name T601
Test name
Test status
Simulation time 1004267411 ps
CPU time 4.56 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201232 kb
Host smart-99b880cc-0035-4934-925f-fbeec14b20e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776750558 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.1776750558
Directory /workspace/37.clkmgr_regwen/latest

Test location /workspace/coverage/default/37.clkmgr_smoke.184037837
Short name T475
Test name
Test status
Simulation time 24101949 ps
CPU time 0.8 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 200976 kb
Host smart-6c6f88b0-2380-479e-ab98-476659f2425b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184037837 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.184037837
Directory /workspace/37.clkmgr_smoke/latest

Test location /workspace/coverage/default/37.clkmgr_trans.903664721
Short name T625
Test name
Test status
Simulation time 40448168 ps
CPU time 0.95 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 200984 kb
Host smart-b9b483c9-6b6e-4abb-8c69-6fda14deec4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903664721 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.903664721
Directory /workspace/37.clkmgr_trans/latest

Test location /workspace/coverage/default/38.clkmgr_alert_test.4105136334
Short name T597
Test name
Test status
Simulation time 40116093 ps
CPU time 0.88 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:28 PM PDT 24
Peak memory 201016 kb
Host smart-c3a4ae9e-fef4-4dea-a085-fec540969c78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105136334 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clk
mgr_alert_test.4105136334
Directory /workspace/38.clkmgr_alert_test/latest

Test location /workspace/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.2719580406
Short name T351
Test name
Test status
Simulation time 56371551 ps
CPU time 0.89 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 200988 kb
Host smart-978fc2b6-a671-4b00-99ed-40da10bc0ba2
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719580406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_clk_handshake_intersig_mubi.2719580406
Directory /workspace/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_clk_status.633777908
Short name T632
Test name
Test status
Simulation time 28700635 ps
CPU time 0.79 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 200188 kb
Host smart-f41b102a-5a0a-48ed-b0ce-67f769e5f07e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633777908 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.633777908
Directory /workspace/38.clkmgr_clk_status/latest

Test location /workspace/coverage/default/38.clkmgr_div_intersig_mubi.393325804
Short name T459
Test name
Test status
Simulation time 56800751 ps
CPU time 0.83 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:28 PM PDT 24
Peak memory 201096 kb
Host smart-f4b2294f-293a-419f-a311-96abe079adad
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393325804 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.clkmgr_div_intersig_mubi.393325804
Directory /workspace/38.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_extclk.2242426618
Short name T372
Test name
Test status
Simulation time 45097515 ps
CPU time 0.94 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201076 kb
Host smart-5e096c78-76c6-4dc7-a9eb-b6c2d080293a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242426618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2242426618
Directory /workspace/38.clkmgr_extclk/latest

Test location /workspace/coverage/default/38.clkmgr_frequency.1762482384
Short name T427
Test name
Test status
Simulation time 1296936786 ps
CPU time 6.1 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:37 PM PDT 24
Peak memory 201124 kb
Host smart-ebaecfc6-1e12-42bf-8d5e-21e9508902db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762482384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.1762482384
Directory /workspace/38.clkmgr_frequency/latest

Test location /workspace/coverage/default/38.clkmgr_frequency_timeout.1060090888
Short name T801
Test name
Test status
Simulation time 2295660035 ps
CPU time 14.71 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:44 PM PDT 24
Peak memory 201464 kb
Host smart-9699867c-a3c3-42bd-a9e7-508fd3e057ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060090888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_t
imeout.1060090888
Directory /workspace/38.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/38.clkmgr_idle_intersig_mubi.2048199190
Short name T720
Test name
Test status
Simulation time 16605084 ps
CPU time 0.75 seconds
Started Aug 07 05:03:24 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 201096 kb
Host smart-3eb89ad6-4e50-4d4f-b4b2-085f5f8c1b2a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048199190 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_idle_intersig_mubi.2048199190
Directory /workspace/38.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_clk_byp_req_intersig_mubi.212398544
Short name T573
Test name
Test status
Simulation time 85093277 ps
CPU time 1.02 seconds
Started Aug 07 05:03:37 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201056 kb
Host smart-b62b63f5-00bd-4969-a8ea-ebf8899e6591
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212398544 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_clk_byp_req_intersig_mubi.212398544
Directory /workspace/38.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.725399407
Short name T474
Test name
Test status
Simulation time 83696984 ps
CPU time 0.95 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201052 kb
Host smart-e0e1e194-7288-4c58-9ab9-929f3d9f5e3e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725399407 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 38.clkmgr_lc_ctrl_intersig_mubi.725399407
Directory /workspace/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/38.clkmgr_peri.2602629625
Short name T776
Test name
Test status
Simulation time 33445253 ps
CPU time 0.77 seconds
Started Aug 07 05:03:36 PM PDT 24
Finished Aug 07 05:03:37 PM PDT 24
Peak memory 200968 kb
Host smart-cdc13e60-d9ab-410a-9fbd-b098736aaf79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602629625 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.2602629625
Directory /workspace/38.clkmgr_peri/latest

Test location /workspace/coverage/default/38.clkmgr_regwen.1039057031
Short name T422
Test name
Test status
Simulation time 847117914 ps
CPU time 3.33 seconds
Started Aug 07 05:03:36 PM PDT 24
Finished Aug 07 05:03:40 PM PDT 24
Peak memory 201264 kb
Host smart-e8129a6e-5bb6-42fc-a5a5-9f9de8c34332
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039057031 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1039057031
Directory /workspace/38.clkmgr_regwen/latest

Test location /workspace/coverage/default/38.clkmgr_smoke.3729774630
Short name T303
Test name
Test status
Simulation time 42251192 ps
CPU time 0.86 seconds
Started Aug 07 05:03:28 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201056 kb
Host smart-a474440c-47f6-4acc-91fa-9806ecae4681
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729774630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3729774630
Directory /workspace/38.clkmgr_smoke/latest

Test location /workspace/coverage/default/38.clkmgr_stress_all.753711659
Short name T783
Test name
Test status
Simulation time 8295744582 ps
CPU time 44.18 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:04:16 PM PDT 24
Peak memory 201416 kb
Host smart-57f81c32-8e29-4289-9177-9a0f0e07e743
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753711659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.clkmgr_stress_all.753711659
Directory /workspace/38.clkmgr_stress_all/latest

Test location /workspace/coverage/default/38.clkmgr_trans.3910999569
Short name T326
Test name
Test status
Simulation time 25028311 ps
CPU time 0.86 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 201064 kb
Host smart-d12dcab9-0e2e-460a-81bf-06f0d44f0969
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910999569 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.3910999569
Directory /workspace/38.clkmgr_trans/latest

Test location /workspace/coverage/default/39.clkmgr_alert_test.215482335
Short name T551
Test name
Test status
Simulation time 16072639 ps
CPU time 0.77 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 201048 kb
Host smart-831a8b9b-bdfd-4598-ab38-f511feeed183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215482335 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkm
gr_alert_test.215482335
Directory /workspace/39.clkmgr_alert_test/latest

Test location /workspace/coverage/default/39.clkmgr_clk_handshake_intersig_mubi.337345504
Short name T515
Test name
Test status
Simulation time 73153486 ps
CPU time 0.99 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201080 kb
Host smart-5551836a-55cb-40ad-847a-30ee49d82555
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337345504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_clk_handshake_intersig_mubi.337345504
Directory /workspace/39.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_clk_status.854414149
Short name T644
Test name
Test status
Simulation time 57425996 ps
CPU time 0.78 seconds
Started Aug 07 05:03:24 PM PDT 24
Finished Aug 07 05:03:25 PM PDT 24
Peak memory 200188 kb
Host smart-c17758cf-cbd2-45e7-95ef-71c6f6cf6c41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854414149 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.854414149
Directory /workspace/39.clkmgr_clk_status/latest

Test location /workspace/coverage/default/39.clkmgr_div_intersig_mubi.2142456950
Short name T466
Test name
Test status
Simulation time 32723886 ps
CPU time 0.86 seconds
Started Aug 07 05:03:36 PM PDT 24
Finished Aug 07 05:03:42 PM PDT 24
Peak memory 201076 kb
Host smart-534529ff-5c1d-48c9-8911-367ac7e3ade0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142456950 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_div_intersig_mubi.2142456950
Directory /workspace/39.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_extclk.2431486898
Short name T173
Test name
Test status
Simulation time 32585520 ps
CPU time 1.01 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:35 PM PDT 24
Peak memory 201044 kb
Host smart-d1c57c8a-b927-4796-a981-27e1762741ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431486898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.2431486898
Directory /workspace/39.clkmgr_extclk/latest

Test location /workspace/coverage/default/39.clkmgr_frequency.2622585997
Short name T497
Test name
Test status
Simulation time 2362721406 ps
CPU time 10.38 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:42 PM PDT 24
Peak memory 201384 kb
Host smart-a17c2e39-26a6-4621-acd8-4b54725fbc16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622585997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.2622585997
Directory /workspace/39.clkmgr_frequency/latest

Test location /workspace/coverage/default/39.clkmgr_frequency_timeout.3662141872
Short name T605
Test name
Test status
Simulation time 866741283 ps
CPU time 4.81 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 201224 kb
Host smart-702013aa-85f0-4541-ae33-f2423e09f7a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662141872 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_t
imeout.3662141872
Directory /workspace/39.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/39.clkmgr_idle_intersig_mubi.1266225341
Short name T269
Test name
Test status
Simulation time 109689090 ps
CPU time 1.17 seconds
Started Aug 07 05:03:27 PM PDT 24
Finished Aug 07 05:03:28 PM PDT 24
Peak memory 201088 kb
Host smart-2116604e-16de-4299-a781-0c58861de2d5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266225341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_idle_intersig_mubi.1266225341
Directory /workspace/39.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_clk_byp_req_intersig_mubi.707475580
Short name T506
Test name
Test status
Simulation time 39363200 ps
CPU time 0.8 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201068 kb
Host smart-fbdd638b-d920-450a-a80d-a744d30ccc80
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707475580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 39.clkmgr_lc_clk_byp_req_intersig_mubi.707475580
Directory /workspace/39.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_lc_ctrl_intersig_mubi.1955949864
Short name T101
Test name
Test status
Simulation time 67557232 ps
CPU time 0.95 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201100 kb
Host smart-2deefd9f-5f4b-4d97-a1f8-5f4b6811d3d1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955949864 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 39.clkmgr_lc_ctrl_intersig_mubi.1955949864
Directory /workspace/39.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/39.clkmgr_peri.847782816
Short name T55
Test name
Test status
Simulation time 27907923 ps
CPU time 0.78 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201092 kb
Host smart-406334ea-ab96-4e43-84f4-2d0701817909
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847782816 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.847782816
Directory /workspace/39.clkmgr_peri/latest

Test location /workspace/coverage/default/39.clkmgr_smoke.2360201168
Short name T543
Test name
Test status
Simulation time 25633018 ps
CPU time 0.87 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:27 PM PDT 24
Peak memory 201052 kb
Host smart-10b3e0fe-e510-4e81-98a7-7242e12c1df5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360201168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.2360201168
Directory /workspace/39.clkmgr_smoke/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all.1852890819
Short name T24
Test name
Test status
Simulation time 9396827307 ps
CPU time 38.89 seconds
Started Aug 07 05:03:35 PM PDT 24
Finished Aug 07 05:04:14 PM PDT 24
Peak memory 201400 kb
Host smart-d746df9f-fa59-4551-b97e-2f6e643d17f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852890819 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.clkmgr_stress_all.1852890819
Directory /workspace/39.clkmgr_stress_all/latest

Test location /workspace/coverage/default/39.clkmgr_stress_all_with_rand_reset.447349928
Short name T194
Test name
Test status
Simulation time 49494725135 ps
CPU time 311.75 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:08:37 PM PDT 24
Peak memory 209776 kb
Host smart-5f992c2f-6f58-4ed8-a9ce-a80684167102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=447349928 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_stress_all_with_rand_reset.447349928
Directory /workspace/39.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.clkmgr_trans.1185479607
Short name T226
Test name
Test status
Simulation time 128429778 ps
CPU time 1.21 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201012 kb
Host smart-9d5c9530-7848-4ca8-93e6-a928d2abc536
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185479607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_trans.1185479607
Directory /workspace/39.clkmgr_trans/latest

Test location /workspace/coverage/default/4.clkmgr_alert_test.4173111861
Short name T789
Test name
Test status
Simulation time 37459800 ps
CPU time 0.81 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201060 kb
Host smart-e942097f-ee71-45d3-b696-11f47c0382b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173111861 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkm
gr_alert_test.4173111861
Directory /workspace/4.clkmgr_alert_test/latest

Test location /workspace/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.1642668302
Short name T456
Test name
Test status
Simulation time 40981004 ps
CPU time 0.84 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 200700 kb
Host smart-cab08142-59b9-43a7-a66d-1f794d4ab85c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642668302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_clk_handshake_intersig_mubi.1642668302
Directory /workspace/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_clk_status.4220135580
Short name T210
Test name
Test status
Simulation time 23929180 ps
CPU time 0.76 seconds
Started Aug 07 05:02:14 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 200248 kb
Host smart-99cb87aa-7570-41b0-b30e-7f08d26ebed1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220135580 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.4220135580
Directory /workspace/4.clkmgr_clk_status/latest

Test location /workspace/coverage/default/4.clkmgr_div_intersig_mubi.3470019647
Short name T500
Test name
Test status
Simulation time 35462279 ps
CPU time 0.83 seconds
Started Aug 07 05:02:14 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 201036 kb
Host smart-bd38955e-dcca-482b-bc8f-004475b99466
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470019647 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_div_intersig_mubi.3470019647
Directory /workspace/4.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_extclk.1407951366
Short name T522
Test name
Test status
Simulation time 17759833 ps
CPU time 0.78 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201012 kb
Host smart-18104ccb-ec7a-4dcf-bacd-68630ababf47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407951366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.1407951366
Directory /workspace/4.clkmgr_extclk/latest

Test location /workspace/coverage/default/4.clkmgr_frequency.2178570154
Short name T527
Test name
Test status
Simulation time 2357690499 ps
CPU time 17.92 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:25 PM PDT 24
Peak memory 201348 kb
Host smart-a5796297-2063-436a-9149-0743d569636f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178570154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.2178570154
Directory /workspace/4.clkmgr_frequency/latest

Test location /workspace/coverage/default/4.clkmgr_frequency_timeout.1137319018
Short name T460
Test name
Test status
Simulation time 1583363359 ps
CPU time 7.86 seconds
Started Aug 07 05:02:06 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201168 kb
Host smart-361600d7-d384-4f1c-b068-f2d22d19de28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137319018 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_ti
meout.1137319018
Directory /workspace/4.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/4.clkmgr_idle_intersig_mubi.2348891836
Short name T290
Test name
Test status
Simulation time 41043054 ps
CPU time 1.02 seconds
Started Aug 07 05:02:06 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 201016 kb
Host smart-f2076c65-531e-4375-aa34-5072968e6b32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348891836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_idle_intersig_mubi.2348891836
Directory /workspace/4.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.2871944022
Short name T547
Test name
Test status
Simulation time 20625828 ps
CPU time 0.86 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201064 kb
Host smart-dff3998f-d5c7-43c2-b44e-12448e620269
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871944022 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_clk_byp_req_intersig_mubi.2871944022
Directory /workspace/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.2603869824
Short name T267
Test name
Test status
Simulation time 79952426 ps
CPU time 1.04 seconds
Started Aug 07 05:02:15 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201080 kb
Host smart-dc36b4f7-13d9-48d1-a2a7-ab039590dd98
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603869824 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 4.clkmgr_lc_ctrl_intersig_mubi.2603869824
Directory /workspace/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/4.clkmgr_peri.3610809439
Short name T613
Test name
Test status
Simulation time 30550152 ps
CPU time 0.83 seconds
Started Aug 07 05:02:05 PM PDT 24
Finished Aug 07 05:02:06 PM PDT 24
Peak memory 201068 kb
Host smart-1b13749c-17d3-4534-b7ce-3a51e89ecb6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610809439 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3610809439
Directory /workspace/4.clkmgr_peri/latest

Test location /workspace/coverage/default/4.clkmgr_regwen.150046514
Short name T782
Test name
Test status
Simulation time 210920374 ps
CPU time 1.72 seconds
Started Aug 07 05:02:11 PM PDT 24
Finished Aug 07 05:02:13 PM PDT 24
Peak memory 201068 kb
Host smart-0f0afb4d-812b-412f-a77d-2525af533ced
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150046514 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.150046514
Directory /workspace/4.clkmgr_regwen/latest

Test location /workspace/coverage/default/4.clkmgr_sec_cm.911599147
Short name T39
Test name
Test status
Simulation time 204653796 ps
CPU time 2 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 220512 kb
Host smart-33001307-1ab5-4182-8075-f9950221bedb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911599147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TES
T_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr
_sec_cm.911599147
Directory /workspace/4.clkmgr_sec_cm/latest

Test location /workspace/coverage/default/4.clkmgr_smoke.2118204540
Short name T345
Test name
Test status
Simulation time 51898022 ps
CPU time 0.91 seconds
Started Aug 07 05:02:24 PM PDT 24
Finished Aug 07 05:02:25 PM PDT 24
Peak memory 201012 kb
Host smart-bd7f3be7-04da-44c4-8dd0-a658375d77ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118204540 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2118204540
Directory /workspace/4.clkmgr_smoke/latest

Test location /workspace/coverage/default/4.clkmgr_stress_all.2857031179
Short name T23
Test name
Test status
Simulation time 17712403817 ps
CPU time 70.09 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201052 kb
Host smart-7ade823e-88d1-49eb-8ded-b0970e2fd8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857031179 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.clkmgr_stress_all.2857031179
Directory /workspace/4.clkmgr_stress_all/latest

Test location /workspace/coverage/default/4.clkmgr_trans.1120345479
Short name T639
Test name
Test status
Simulation time 92205764 ps
CPU time 1.16 seconds
Started Aug 07 05:02:07 PM PDT 24
Finished Aug 07 05:02:08 PM PDT 24
Peak memory 201072 kb
Host smart-05b50978-f7d7-415d-938c-24e2284fc0dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120345479 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1120345479
Directory /workspace/4.clkmgr_trans/latest

Test location /workspace/coverage/default/40.clkmgr_alert_test.1756356219
Short name T242
Test name
Test status
Simulation time 34132254 ps
CPU time 0.8 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:46 PM PDT 24
Peak memory 201096 kb
Host smart-011a3447-3f56-4fc9-aa69-bbd57597eddb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756356219 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clk
mgr_alert_test.1756356219
Directory /workspace/40.clkmgr_alert_test/latest

Test location /workspace/coverage/default/40.clkmgr_clk_handshake_intersig_mubi.4210481934
Short name T538
Test name
Test status
Simulation time 22606595 ps
CPU time 0.78 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201044 kb
Host smart-f9210745-acc0-4f17-91f4-a19bcfb9f60c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210481934 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_clk_handshake_intersig_mubi.4210481934
Directory /workspace/40.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_clk_status.1989021428
Short name T622
Test name
Test status
Simulation time 26924480 ps
CPU time 0.69 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 200956 kb
Host smart-28e53d14-435e-4388-804b-704ce034d185
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989021428 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_clk_status.1989021428
Directory /workspace/40.clkmgr_clk_status/latest

Test location /workspace/coverage/default/40.clkmgr_div_intersig_mubi.284953410
Short name T796
Test name
Test status
Simulation time 88961931 ps
CPU time 1.07 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 201000 kb
Host smart-6fdae131-d0ac-42ee-b801-0546de4294cb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284953410 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
0.clkmgr_div_intersig_mubi.284953410
Directory /workspace/40.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_extclk.1152401366
Short name T41
Test name
Test status
Simulation time 60528083 ps
CPU time 0.95 seconds
Started Aug 07 05:03:25 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 201080 kb
Host smart-2db63ed6-d7b5-494b-b9a0-fd66073e2c69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152401366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_extclk.1152401366
Directory /workspace/40.clkmgr_extclk/latest

Test location /workspace/coverage/default/40.clkmgr_frequency.1896521910
Short name T524
Test name
Test status
Simulation time 1754808570 ps
CPU time 13.38 seconds
Started Aug 07 05:03:37 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201312 kb
Host smart-99db36c7-bc24-4ce0-9504-35d2ba6e5f45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896521910 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency.1896521910
Directory /workspace/40.clkmgr_frequency/latest

Test location /workspace/coverage/default/40.clkmgr_frequency_timeout.809856938
Short name T441
Test name
Test status
Simulation time 1459603961 ps
CPU time 10.51 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:41 PM PDT 24
Peak memory 201184 kb
Host smart-262b07c1-dc78-4734-8eff-01d217fa82c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809856938 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_frequency_ti
meout.809856938
Directory /workspace/40.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/40.clkmgr_idle_intersig_mubi.1940121279
Short name T205
Test name
Test status
Simulation time 65286687 ps
CPU time 0.98 seconds
Started Aug 07 05:03:36 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201004 kb
Host smart-2fb312de-e5a7-4dfe-8c61-a34eaaaddd59
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940121279 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_idle_intersig_mubi.1940121279
Directory /workspace/40.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_clk_byp_req_intersig_mubi.1469146406
Short name T82
Test name
Test status
Simulation time 19505834 ps
CPU time 0.78 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 200996 kb
Host smart-d63f92e2-9d54-4d3c-a30b-e6f8d7e16c10
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469146406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_clk_byp_req_intersig_mubi.1469146406
Directory /workspace/40.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_lc_ctrl_intersig_mubi.2468755002
Short name T464
Test name
Test status
Simulation time 46727435 ps
CPU time 0.82 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 201056 kb
Host smart-83c3a8ba-681a-47c2-816e-fafc7fdd2c06
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468755002 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 40.clkmgr_lc_ctrl_intersig_mubi.2468755002
Directory /workspace/40.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/40.clkmgr_peri.3243332423
Short name T788
Test name
Test status
Simulation time 21637542 ps
CPU time 0.74 seconds
Started Aug 07 05:03:53 PM PDT 24
Finished Aug 07 05:03:54 PM PDT 24
Peak memory 200988 kb
Host smart-c988fe33-5206-4820-ac3d-23d177aa4023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243332423 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_peri.3243332423
Directory /workspace/40.clkmgr_peri/latest

Test location /workspace/coverage/default/40.clkmgr_regwen.3386250984
Short name T580
Test name
Test status
Simulation time 816507315 ps
CPU time 3.22 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201280 kb
Host smart-f19c460b-6261-4f03-869f-68ba8159e754
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386250984 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.3386250984
Directory /workspace/40.clkmgr_regwen/latest

Test location /workspace/coverage/default/40.clkmgr_smoke.2803422525
Short name T755
Test name
Test status
Simulation time 17078083 ps
CPU time 0.8 seconds
Started Aug 07 05:03:26 PM PDT 24
Finished Aug 07 05:03:26 PM PDT 24
Peak memory 201068 kb
Host smart-bde3891f-fcdb-4fdf-bcd3-89a04d8a5d4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803422525 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_smoke.2803422525
Directory /workspace/40.clkmgr_smoke/latest

Test location /workspace/coverage/default/40.clkmgr_stress_all.1609721291
Short name T594
Test name
Test status
Simulation time 9607970342 ps
CPU time 49.55 seconds
Started Aug 07 05:03:24 PM PDT 24
Finished Aug 07 05:04:13 PM PDT 24
Peak memory 201396 kb
Host smart-ec4c7057-15b8-41a3-bb5b-40fe4343ebd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609721291 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.clkmgr_stress_all.1609721291
Directory /workspace/40.clkmgr_stress_all/latest

Test location /workspace/coverage/default/40.clkmgr_trans.2183610100
Short name T248
Test name
Test status
Simulation time 82692315 ps
CPU time 1.06 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201060 kb
Host smart-9861d02c-dc81-4ede-8196-c2c0ba898b09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183610100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_trans.2183610100
Directory /workspace/40.clkmgr_trans/latest

Test location /workspace/coverage/default/41.clkmgr_alert_test.1560309992
Short name T253
Test name
Test status
Simulation time 20612972 ps
CPU time 0.8 seconds
Started Aug 07 05:03:28 PM PDT 24
Finished Aug 07 05:03:29 PM PDT 24
Peak memory 201056 kb
Host smart-15ec5a46-9a39-4c0d-8f75-88c599c0d560
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560309992 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clk
mgr_alert_test.1560309992
Directory /workspace/41.clkmgr_alert_test/latest

Test location /workspace/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.4058335942
Short name T734
Test name
Test status
Simulation time 39760264 ps
CPU time 0.94 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 201076 kb
Host smart-aaa262e3-ce0d-4049-a575-72f16a8a87d4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058335942 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_clk_handshake_intersig_mubi.4058335942
Directory /workspace/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_clk_status.4014227134
Short name T502
Test name
Test status
Simulation time 20878132 ps
CPU time 0.68 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 200264 kb
Host smart-2dd6e17c-5617-4ac1-bc07-511229632054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014227134 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.4014227134
Directory /workspace/41.clkmgr_clk_status/latest

Test location /workspace/coverage/default/41.clkmgr_div_intersig_mubi.799949399
Short name T296
Test name
Test status
Simulation time 69356856 ps
CPU time 1.05 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201112 kb
Host smart-3ea4585a-e3f9-44b4-858c-9401764c8457
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799949399 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.clkmgr_div_intersig_mubi.799949399
Directory /workspace/41.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_extclk.679669001
Short name T6
Test name
Test status
Simulation time 111093262 ps
CPU time 1.2 seconds
Started Aug 07 05:03:46 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201092 kb
Host smart-d283d7cd-f72a-431a-a378-7a4966efabd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679669001 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.679669001
Directory /workspace/41.clkmgr_extclk/latest

Test location /workspace/coverage/default/41.clkmgr_frequency.1534761743
Short name T696
Test name
Test status
Simulation time 1526656063 ps
CPU time 8.64 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:41 PM PDT 24
Peak memory 201100 kb
Host smart-a24dc30a-3499-4f53-bcc4-4421b2544050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534761743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency.1534761743
Directory /workspace/41.clkmgr_frequency/latest

Test location /workspace/coverage/default/41.clkmgr_frequency_timeout.364853427
Short name T289
Test name
Test status
Simulation time 2300841144 ps
CPU time 16.46 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:04:04 PM PDT 24
Peak memory 201460 kb
Host smart-34cb2df4-c843-45b3-af22-0cb75985c659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364853427 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_frequency_ti
meout.364853427
Directory /workspace/41.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/41.clkmgr_idle_intersig_mubi.2763016584
Short name T299
Test name
Test status
Simulation time 29032787 ps
CPU time 0.75 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:46 PM PDT 24
Peak memory 201076 kb
Host smart-756a5e5d-887d-4429-a3c0-fabf06bdc9c5
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763016584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.clkmgr_idle_intersig_mubi.2763016584
Directory /workspace/41.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.4114087513
Short name T347
Test name
Test status
Simulation time 13888831 ps
CPU time 0.72 seconds
Started Aug 07 05:04:02 PM PDT 24
Finished Aug 07 05:04:03 PM PDT 24
Peak memory 201012 kb
Host smart-4893275c-dcea-4939-8d53-bf6134a82267
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114087513 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_clk_byp_req_intersig_mubi.4114087513
Directory /workspace/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.1760138426
Short name T519
Test name
Test status
Simulation time 67466065 ps
CPU time 1 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 201116 kb
Host smart-3b383e14-fd09-4ca6-bf5f-23e7b6a95acc
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760138426 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 41.clkmgr_lc_ctrl_intersig_mubi.1760138426
Directory /workspace/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/41.clkmgr_peri.3443988630
Short name T362
Test name
Test status
Simulation time 21110679 ps
CPU time 0.72 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 200984 kb
Host smart-ca5660e2-19a2-4f05-9254-7aa29ceccdbc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443988630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.3443988630
Directory /workspace/41.clkmgr_peri/latest

Test location /workspace/coverage/default/41.clkmgr_regwen.2673635873
Short name T375
Test name
Test status
Simulation time 1218046233 ps
CPU time 4.2 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 201292 kb
Host smart-f751cca4-bfec-45e4-9084-537b017d648a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673635873 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.2673635873
Directory /workspace/41.clkmgr_regwen/latest

Test location /workspace/coverage/default/41.clkmgr_smoke.393557747
Short name T650
Test name
Test status
Simulation time 32035393 ps
CPU time 0.94 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201048 kb
Host smart-b7278055-d90c-4206-b093-6f385f2b1b04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393557747 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.393557747
Directory /workspace/41.clkmgr_smoke/latest

Test location /workspace/coverage/default/41.clkmgr_trans.1210911250
Short name T642
Test name
Test status
Simulation time 119795157 ps
CPU time 1.22 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201072 kb
Host smart-4bd344de-5555-4f31-b1c8-adfe08b38a5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210911250 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1210911250
Directory /workspace/41.clkmgr_trans/latest

Test location /workspace/coverage/default/42.clkmgr_alert_test.2670161562
Short name T636
Test name
Test status
Simulation time 54014662 ps
CPU time 0.86 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:46 PM PDT 24
Peak memory 201068 kb
Host smart-a9a6c15f-9a8d-4ef1-ba30-d64493cf7e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670161562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clk
mgr_alert_test.2670161562
Directory /workspace/42.clkmgr_alert_test/latest

Test location /workspace/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.2109554447
Short name T541
Test name
Test status
Simulation time 15054219 ps
CPU time 0.77 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 200928 kb
Host smart-b8f7470d-cad3-431a-9cde-c11f1d3656f7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109554447 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_clk_handshake_intersig_mubi.2109554447
Directory /workspace/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_clk_status.1168456357
Short name T36
Test name
Test status
Simulation time 40994856 ps
CPU time 0.74 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:45 PM PDT 24
Peak memory 200988 kb
Host smart-5a1eea07-2658-4a76-8d19-ae867257d35e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168456357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.1168456357
Directory /workspace/42.clkmgr_clk_status/latest

Test location /workspace/coverage/default/42.clkmgr_div_intersig_mubi.2065380646
Short name T281
Test name
Test status
Simulation time 38096073 ps
CPU time 0.85 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:30 PM PDT 24
Peak memory 201116 kb
Host smart-29b817de-c3c2-4c54-a0c6-3e15264a8fd1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065380646 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_div_intersig_mubi.2065380646
Directory /workspace/42.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_extclk.2665370051
Short name T130
Test name
Test status
Simulation time 36838425 ps
CPU time 0.85 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 200876 kb
Host smart-925fe835-3dd9-4400-800c-72a0c1bfc587
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665370051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.2665370051
Directory /workspace/42.clkmgr_extclk/latest

Test location /workspace/coverage/default/42.clkmgr_frequency.1647376638
Short name T495
Test name
Test status
Simulation time 2170574141 ps
CPU time 8.44 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:40 PM PDT 24
Peak memory 201400 kb
Host smart-eede44e7-f959-4989-8396-75709618ae95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647376638 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.1647376638
Directory /workspace/42.clkmgr_frequency/latest

Test location /workspace/coverage/default/42.clkmgr_frequency_timeout.906770414
Short name T819
Test name
Test status
Simulation time 2075211842 ps
CPU time 7.89 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:55 PM PDT 24
Peak memory 201384 kb
Host smart-b74f0235-8c97-4ccd-b72a-5b00a277fbf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906770414 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_ti
meout.906770414
Directory /workspace/42.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/42.clkmgr_idle_intersig_mubi.480072253
Short name T241
Test name
Test status
Simulation time 156964821 ps
CPU time 1.33 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201052 kb
Host smart-b1adcc6e-3068-4e7a-8401-06d1add3752c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480072253 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
2.clkmgr_idle_intersig_mubi.480072253
Directory /workspace/42.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.3047128815
Short name T638
Test name
Test status
Simulation time 36400655 ps
CPU time 0.88 seconds
Started Aug 07 05:03:42 PM PDT 24
Finished Aug 07 05:03:43 PM PDT 24
Peak memory 201072 kb
Host smart-a5040667-53ab-4e8b-90de-ef6c84637a5e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047128815 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 42.clkmgr_lc_clk_byp_req_intersig_mubi.3047128815
Directory /workspace/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.499374740
Short name T779
Test name
Test status
Simulation time 85163364 ps
CPU time 1.08 seconds
Started Aug 07 05:03:30 PM PDT 24
Finished Aug 07 05:03:31 PM PDT 24
Peak memory 201104 kb
Host smart-efbd6a67-a48e-408a-987d-8e6ec31c5c0b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499374740 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 42.clkmgr_lc_ctrl_intersig_mubi.499374740
Directory /workspace/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/42.clkmgr_peri.1439338157
Short name T78
Test name
Test status
Simulation time 36782273 ps
CPU time 0.81 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201052 kb
Host smart-32ed09df-f4ee-46f1-aeaf-a21dba94a3f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439338157 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.1439338157
Directory /workspace/42.clkmgr_peri/latest

Test location /workspace/coverage/default/42.clkmgr_regwen.812218618
Short name T550
Test name
Test status
Simulation time 599007406 ps
CPU time 3 seconds
Started Aug 07 05:03:34 PM PDT 24
Finished Aug 07 05:03:37 PM PDT 24
Peak memory 201248 kb
Host smart-d535d0fc-5b21-4312-9319-5f30d7d3b78c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812218618 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.812218618
Directory /workspace/42.clkmgr_regwen/latest

Test location /workspace/coverage/default/42.clkmgr_smoke.581903888
Short name T488
Test name
Test status
Simulation time 67695565 ps
CPU time 1 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:34 PM PDT 24
Peak memory 201084 kb
Host smart-f47d01cb-4256-482a-8e0f-25e6095fae59
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581903888 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.581903888
Directory /workspace/42.clkmgr_smoke/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all.3632239209
Short name T533
Test name
Test status
Simulation time 5885999672 ps
CPU time 21.76 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:03:55 PM PDT 24
Peak memory 201472 kb
Host smart-1fce9f8d-cea2-4fef-84f5-d0997e43977e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632239209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.clkmgr_stress_all.3632239209
Directory /workspace/42.clkmgr_stress_all/latest

Test location /workspace/coverage/default/42.clkmgr_stress_all_with_rand_reset.7032287
Short name T195
Test name
Test status
Simulation time 16670823259 ps
CPU time 224.03 seconds
Started Aug 07 05:03:33 PM PDT 24
Finished Aug 07 05:07:17 PM PDT 24
Peak memory 217908 kb
Host smart-f2e39e94-d2cd-41a4-912c-e08cbe397beb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=7032287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.7032287
Directory /workspace/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.clkmgr_trans.2162212613
Short name T428
Test name
Test status
Simulation time 90905354 ps
CPU time 1.03 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201068 kb
Host smart-36609007-4f8c-4ecf-a38e-c9c19e7b79b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162212613 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.2162212613
Directory /workspace/42.clkmgr_trans/latest

Test location /workspace/coverage/default/43.clkmgr_alert_test.2171315805
Short name T417
Test name
Test status
Simulation time 18822842 ps
CPU time 0.8 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 200992 kb
Host smart-2e4e071b-b5e4-4b28-bcd6-45ae6b016e4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171315805 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clk
mgr_alert_test.2171315805
Directory /workspace/43.clkmgr_alert_test/latest

Test location /workspace/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.4243889098
Short name T564
Test name
Test status
Simulation time 34106264 ps
CPU time 0.94 seconds
Started Aug 07 05:03:40 PM PDT 24
Finished Aug 07 05:03:41 PM PDT 24
Peak memory 200996 kb
Host smart-988a9ae6-2d15-43d7-86ed-9b2e4a3b6abd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243889098 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_clk_handshake_intersig_mubi.4243889098
Directory /workspace/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_clk_status.2717178118
Short name T535
Test name
Test status
Simulation time 95246167 ps
CPU time 0.93 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 200324 kb
Host smart-db007896-6740-405d-81b4-6bce7edff088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717178118 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.2717178118
Directory /workspace/43.clkmgr_clk_status/latest

Test location /workspace/coverage/default/43.clkmgr_div_intersig_mubi.1244357223
Short name T342
Test name
Test status
Simulation time 42127589 ps
CPU time 0.98 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201072 kb
Host smart-51bd7841-a539-4efb-bd09-a3ac7c4a6b35
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244357223 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_div_intersig_mubi.1244357223
Directory /workspace/43.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_extclk.1418765105
Short name T293
Test name
Test status
Simulation time 94092921 ps
CPU time 1.03 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201056 kb
Host smart-40afb5c8-f68b-4f16-995d-4c8bed39ff9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418765105 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.1418765105
Directory /workspace/43.clkmgr_extclk/latest

Test location /workspace/coverage/default/43.clkmgr_frequency.635145006
Short name T14
Test name
Test status
Simulation time 2235369570 ps
CPU time 10.11 seconds
Started Aug 07 05:04:06 PM PDT 24
Finished Aug 07 05:04:17 PM PDT 24
Peak memory 201344 kb
Host smart-f10e3d61-7d1b-445e-84d9-2d83bc1e36eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635145006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.635145006
Directory /workspace/43.clkmgr_frequency/latest

Test location /workspace/coverage/default/43.clkmgr_frequency_timeout.2607185607
Short name T450
Test name
Test status
Simulation time 1459273300 ps
CPU time 10.04 seconds
Started Aug 07 05:03:29 PM PDT 24
Finished Aug 07 05:03:39 PM PDT 24
Peak memory 201224 kb
Host smart-a4f130aa-3135-40d6-9559-89596c6a461d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607185607 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_t
imeout.2607185607
Directory /workspace/43.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/43.clkmgr_idle_intersig_mubi.1317468826
Short name T728
Test name
Test status
Simulation time 23053555 ps
CPU time 0.92 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201132 kb
Host smart-ebd9dda7-7176-4b6a-b2c3-da37687307bb
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317468826 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_idle_intersig_mubi.1317468826
Directory /workspace/43.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2398639411
Short name T481
Test name
Test status
Simulation time 24304293 ps
CPU time 0.87 seconds
Started Aug 07 05:03:46 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201080 kb
Host smart-9691dfff-04cd-46c5-8577-4b5858c14c50
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398639411 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 43.clkmgr_lc_clk_byp_req_intersig_mubi.2398639411
Directory /workspace/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.527572821
Short name T355
Test name
Test status
Simulation time 24328831 ps
CPU time 0.9 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 200992 kb
Host smart-235da179-9a1a-4fbe-97ed-8169e0b79cdf
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527572821 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 43.clkmgr_lc_ctrl_intersig_mubi.527572821
Directory /workspace/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/43.clkmgr_peri.3565225770
Short name T754
Test name
Test status
Simulation time 16244570 ps
CPU time 0.72 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:33 PM PDT 24
Peak memory 201100 kb
Host smart-b5f085f1-9e68-4e9e-99d4-58d1525dd41e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565225770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3565225770
Directory /workspace/43.clkmgr_peri/latest

Test location /workspace/coverage/default/43.clkmgr_regwen.290158066
Short name T436
Test name
Test status
Simulation time 1068326027 ps
CPU time 3.85 seconds
Started Aug 07 05:03:36 PM PDT 24
Finished Aug 07 05:03:40 PM PDT 24
Peak memory 201248 kb
Host smart-dbd1dfd1-7518-4be8-966b-2b2b57d8a09c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290158066 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.290158066
Directory /workspace/43.clkmgr_regwen/latest

Test location /workspace/coverage/default/43.clkmgr_smoke.76539193
Short name T531
Test name
Test status
Simulation time 13673854 ps
CPU time 0.8 seconds
Started Aug 07 05:03:32 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201016 kb
Host smart-a6e0a71c-8ade-4603-83bb-3db99b4a7769
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76539193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.76539193
Directory /workspace/43.clkmgr_smoke/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all.1749296602
Short name T310
Test name
Test status
Simulation time 1111166183 ps
CPU time 6.14 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:05 PM PDT 24
Peak memory 201256 kb
Host smart-fc083c55-1818-475a-b26e-e51dc494b1ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749296602 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.clkmgr_stress_all.1749296602
Directory /workspace/43.clkmgr_stress_all/latest

Test location /workspace/coverage/default/43.clkmgr_stress_all_with_rand_reset.4176924778
Short name T743
Test name
Test status
Simulation time 92614597227 ps
CPU time 644.53 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:14:34 PM PDT 24
Peak memory 209740 kb
Host smart-3840d693-59b1-4bac-b868-8db16a2e8856
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4176924778 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.4176924778
Directory /workspace/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.clkmgr_trans.3363498581
Short name T225
Test name
Test status
Simulation time 101631286 ps
CPU time 1.14 seconds
Started Aug 07 05:03:31 PM PDT 24
Finished Aug 07 05:03:32 PM PDT 24
Peak memory 201024 kb
Host smart-5bf35190-5fc7-467a-8eaf-94c08c5951ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363498581 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.3363498581
Directory /workspace/43.clkmgr_trans/latest

Test location /workspace/coverage/default/44.clkmgr_alert_test.1495830299
Short name T739
Test name
Test status
Simulation time 44476064 ps
CPU time 0.83 seconds
Started Aug 07 05:03:37 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201064 kb
Host smart-0cfc64d2-f542-4648-918b-04bbefc94a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495830299 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clk
mgr_alert_test.1495830299
Directory /workspace/44.clkmgr_alert_test/latest

Test location /workspace/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.17752881
Short name T20
Test name
Test status
Simulation time 19917819 ps
CPU time 0.82 seconds
Started Aug 07 05:03:34 PM PDT 24
Finished Aug 07 05:03:35 PM PDT 24
Peak memory 201120 kb
Host smart-af58e4d2-d563-4390-a052-7a1fb86c8bf6
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17752881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_clk_handshake_intersig_mubi.17752881
Directory /workspace/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_clk_status.907449944
Short name T484
Test name
Test status
Simulation time 37141500 ps
CPU time 0.74 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 200256 kb
Host smart-73994999-4f20-42f3-b913-af85ce4f9200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907449944 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.907449944
Directory /workspace/44.clkmgr_clk_status/latest

Test location /workspace/coverage/default/44.clkmgr_div_intersig_mubi.1507770142
Short name T757
Test name
Test status
Simulation time 47831485 ps
CPU time 0.89 seconds
Started Aug 07 05:04:37 PM PDT 24
Finished Aug 07 05:04:38 PM PDT 24
Peak memory 201056 kb
Host smart-8e44b25f-d471-4b97-bcbe-d7310563b7cd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507770142 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_div_intersig_mubi.1507770142
Directory /workspace/44.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_extclk.3468025376
Short name T585
Test name
Test status
Simulation time 22887689 ps
CPU time 0.84 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201052 kb
Host smart-1a893e7e-c335-4acf-9d57-4db72e5dc571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468025376 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.3468025376
Directory /workspace/44.clkmgr_extclk/latest

Test location /workspace/coverage/default/44.clkmgr_frequency.1476928350
Short name T203
Test name
Test status
Simulation time 1997739209 ps
CPU time 16.42 seconds
Started Aug 07 05:03:35 PM PDT 24
Finished Aug 07 05:03:52 PM PDT 24
Peak memory 201256 kb
Host smart-543af7b9-b50a-4272-9f8e-47b8b722c564
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476928350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.1476928350
Directory /workspace/44.clkmgr_frequency/latest

Test location /workspace/coverage/default/44.clkmgr_frequency_timeout.1580590176
Short name T452
Test name
Test status
Simulation time 1221069661 ps
CPU time 9.05 seconds
Started Aug 07 05:03:44 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 201240 kb
Host smart-cc53f079-9127-499b-90ef-fd5e3e2c786c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580590176 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_t
imeout.1580590176
Directory /workspace/44.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/44.clkmgr_idle_intersig_mubi.815087948
Short name T576
Test name
Test status
Simulation time 33080563 ps
CPU time 0.96 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:04:05 PM PDT 24
Peak memory 201032 kb
Host smart-be1332b2-fe89-40fc-a286-ff97f8da4cd0
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815087948 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
4.clkmgr_idle_intersig_mubi.815087948
Directory /workspace/44.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1438509941
Short name T485
Test name
Test status
Simulation time 22732255 ps
CPU time 0.77 seconds
Started Aug 07 05:03:35 PM PDT 24
Finished Aug 07 05:03:36 PM PDT 24
Peak memory 201096 kb
Host smart-01d23aaa-eecb-437c-9e72-06456fb433f8
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438509941 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_clk_byp_req_intersig_mubi.1438509941
Directory /workspace/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.1287436980
Short name T313
Test name
Test status
Simulation time 28716359 ps
CPU time 0.87 seconds
Started Aug 07 05:03:56 PM PDT 24
Finished Aug 07 05:03:57 PM PDT 24
Peak memory 201020 kb
Host smart-ac4466da-e196-473b-8fc1-0bdbc7491104
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287436980 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 44.clkmgr_lc_ctrl_intersig_mubi.1287436980
Directory /workspace/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/44.clkmgr_peri.3912969287
Short name T513
Test name
Test status
Simulation time 15171109 ps
CPU time 0.72 seconds
Started Aug 07 05:03:45 PM PDT 24
Finished Aug 07 05:03:46 PM PDT 24
Peak memory 201080 kb
Host smart-38f7d830-8406-4f22-aa1b-ec42f8869011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912969287 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.3912969287
Directory /workspace/44.clkmgr_peri/latest

Test location /workspace/coverage/default/44.clkmgr_regwen.3614136898
Short name T507
Test name
Test status
Simulation time 75026513 ps
CPU time 1.05 seconds
Started Aug 07 05:03:54 PM PDT 24
Finished Aug 07 05:03:56 PM PDT 24
Peak memory 200960 kb
Host smart-526526c7-84d8-451e-a3e0-f6567a2cb229
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614136898 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.3614136898
Directory /workspace/44.clkmgr_regwen/latest

Test location /workspace/coverage/default/44.clkmgr_smoke.3898241392
Short name T330
Test name
Test status
Simulation time 18145894 ps
CPU time 0.84 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 200944 kb
Host smart-1e995675-4e79-4787-a92f-922dabe08abf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898241392 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3898241392
Directory /workspace/44.clkmgr_smoke/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all.780212949
Short name T414
Test name
Test status
Simulation time 14126685356 ps
CPU time 56.64 seconds
Started Aug 07 05:04:01 PM PDT 24
Finished Aug 07 05:04:58 PM PDT 24
Peak memory 201376 kb
Host smart-0bd7f252-57f2-41ca-a217-93e5ae1d7e0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780212949 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.clkmgr_stress_all.780212949
Directory /workspace/44.clkmgr_stress_all/latest

Test location /workspace/coverage/default/44.clkmgr_stress_all_with_rand_reset.881348699
Short name T218
Test name
Test status
Simulation time 84528852991 ps
CPU time 569.36 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:13:33 PM PDT 24
Peak memory 212760 kb
Host smart-53d1c9fc-56ad-4355-bea3-01cf9542936b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=881348699 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.881348699
Directory /workspace/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.clkmgr_trans.1832288895
Short name T315
Test name
Test status
Simulation time 102564246 ps
CPU time 1.18 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 200992 kb
Host smart-52dc644d-9cb1-415e-8ed7-0833aef28b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832288895 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.1832288895
Directory /workspace/44.clkmgr_trans/latest

Test location /workspace/coverage/default/45.clkmgr_alert_test.1522433173
Short name T674
Test name
Test status
Simulation time 42698872 ps
CPU time 0.84 seconds
Started Aug 07 05:03:56 PM PDT 24
Finished Aug 07 05:03:57 PM PDT 24
Peak memory 200944 kb
Host smart-b87d9521-46c6-4acd-928c-7ad6636ef2fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522433173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clk
mgr_alert_test.1522433173
Directory /workspace/45.clkmgr_alert_test/latest

Test location /workspace/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.2207294797
Short name T279
Test name
Test status
Simulation time 22354285 ps
CPU time 0.86 seconds
Started Aug 07 05:03:44 PM PDT 24
Finished Aug 07 05:03:45 PM PDT 24
Peak memory 201088 kb
Host smart-2784a822-90cf-4d93-8893-415b375b0e85
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207294797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_clk_handshake_intersig_mubi.2207294797
Directory /workspace/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_clk_status.3231030332
Short name T797
Test name
Test status
Simulation time 50538580 ps
CPU time 0.8 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 200188 kb
Host smart-b4b49c2a-a207-4456-9253-3741440b142f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231030332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.3231030332
Directory /workspace/45.clkmgr_clk_status/latest

Test location /workspace/coverage/default/45.clkmgr_div_intersig_mubi.2321905481
Short name T100
Test name
Test status
Simulation time 29031347 ps
CPU time 0.82 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 201144 kb
Host smart-7523fe14-5dcb-4f45-b692-1d70fb4aa3a4
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321905481 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.clkmgr_div_intersig_mubi.2321905481
Directory /workspace/45.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_extclk.3834143429
Short name T698
Test name
Test status
Simulation time 188814702 ps
CPU time 1.36 seconds
Started Aug 07 05:03:55 PM PDT 24
Finished Aug 07 05:03:57 PM PDT 24
Peak memory 201072 kb
Host smart-d80ef34f-25d6-459c-a2c5-927ae0dcebb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834143429 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.3834143429
Directory /workspace/45.clkmgr_extclk/latest

Test location /workspace/coverage/default/45.clkmgr_frequency.54508422
Short name T764
Test name
Test status
Simulation time 2252820358 ps
CPU time 12.98 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:04:01 PM PDT 24
Peak memory 201280 kb
Host smart-6162d613-bc5b-43e9-8b93-8d3628f6d380
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54508422 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.54508422
Directory /workspace/45.clkmgr_frequency/latest

Test location /workspace/coverage/default/45.clkmgr_frequency_timeout.864677907
Short name T517
Test name
Test status
Simulation time 920021311 ps
CPU time 4.12 seconds
Started Aug 07 05:03:46 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201188 kb
Host smart-fe0960b7-4ea1-4ed6-a771-a1897e0bf787
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864677907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_ti
meout.864677907
Directory /workspace/45.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/45.clkmgr_idle_intersig_mubi.77192614
Short name T408
Test name
Test status
Simulation time 25216300 ps
CPU time 0.82 seconds
Started Aug 07 05:04:01 PM PDT 24
Finished Aug 07 05:04:02 PM PDT 24
Peak memory 201008 kb
Host smart-cd5b54f4-82e1-4d8a-b2e4-7be9da222f3a
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77192614 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.clkmgr_idle_intersig_mubi.77192614
Directory /workspace/45.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1896432217
Short name T733
Test name
Test status
Simulation time 129909834 ps
CPU time 1.09 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201064 kb
Host smart-6444e081-e391-4ed5-8b06-c5f808882e6d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896432217 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_clk_byp_req_intersig_mubi.1896432217
Directory /workspace/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3323327393
Short name T367
Test name
Test status
Simulation time 55735328 ps
CPU time 0.89 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201052 kb
Host smart-f1875cac-645d-4842-a65b-92e8eb266776
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323327393 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 45.clkmgr_lc_ctrl_intersig_mubi.3323327393
Directory /workspace/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/45.clkmgr_peri.2938340808
Short name T548
Test name
Test status
Simulation time 14792256 ps
CPU time 0.74 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201032 kb
Host smart-5b908999-397a-418b-a64d-fb4f92200de5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938340808 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.2938340808
Directory /workspace/45.clkmgr_peri/latest

Test location /workspace/coverage/default/45.clkmgr_regwen.2285076485
Short name T751
Test name
Test status
Simulation time 194301512 ps
CPU time 1.72 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 200996 kb
Host smart-437d84b8-3dba-4bc7-acde-e6b69747785a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285076485 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.2285076485
Directory /workspace/45.clkmgr_regwen/latest

Test location /workspace/coverage/default/45.clkmgr_smoke.2536759160
Short name T155
Test name
Test status
Simulation time 24084555 ps
CPU time 0.89 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201096 kb
Host smart-c0690ee1-1344-4483-82b2-67bb18afb4e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536759160 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.2536759160
Directory /workspace/45.clkmgr_smoke/latest

Test location /workspace/coverage/default/45.clkmgr_stress_all.19055189
Short name T607
Test name
Test status
Simulation time 5683127998 ps
CPU time 41.85 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:04:31 PM PDT 24
Peak memory 201356 kb
Host smart-20173e26-61b5-4e74-bf9c-005181831b14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19055189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_
TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
5.clkmgr_stress_all.19055189
Directory /workspace/45.clkmgr_stress_all/latest

Test location /workspace/coverage/default/45.clkmgr_trans.3422574878
Short name T98
Test name
Test status
Simulation time 56487290 ps
CPU time 1.04 seconds
Started Aug 07 05:03:37 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201072 kb
Host smart-ba92146d-0619-436f-9ac4-216fdd5f49c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422574878 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.3422574878
Directory /workspace/45.clkmgr_trans/latest

Test location /workspace/coverage/default/46.clkmgr_alert_test.805751561
Short name T53
Test name
Test status
Simulation time 30070466 ps
CPU time 0.77 seconds
Started Aug 07 05:03:52 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 200996 kb
Host smart-8f079bb4-6bde-4980-80c0-992069307759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805751561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TE
ST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkm
gr_alert_test.805751561
Directory /workspace/46.clkmgr_alert_test/latest

Test location /workspace/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.3924705834
Short name T344
Test name
Test status
Simulation time 17980140 ps
CPU time 0.81 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201088 kb
Host smart-1e614b85-a13a-4c24-8004-6491ee6b215b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924705834 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_clk_handshake_intersig_mubi.3924705834
Directory /workspace/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_clk_status.1731490401
Short name T208
Test name
Test status
Simulation time 14487101 ps
CPU time 0.77 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:04:05 PM PDT 24
Peak memory 200324 kb
Host smart-1029a205-c65e-4727-84ff-91a8cbd450d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731490401 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.1731490401
Directory /workspace/46.clkmgr_clk_status/latest

Test location /workspace/coverage/default/46.clkmgr_div_intersig_mubi.41708965
Short name T614
Test name
Test status
Simulation time 67310267 ps
CPU time 1 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 200928 kb
Host smart-fb03ddb4-b860-4c6a-a5c1-7b43be2da02c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41708965 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +U
VM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.clkmgr_div_intersig_mubi.41708965
Directory /workspace/46.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_extclk.216023472
Short name T482
Test name
Test status
Simulation time 62606085 ps
CPU time 0.94 seconds
Started Aug 07 05:04:06 PM PDT 24
Finished Aug 07 05:04:07 PM PDT 24
Peak memory 201140 kb
Host smart-fe878f05-00aa-464f-bed2-c181f1420182
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216023472 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.216023472
Directory /workspace/46.clkmgr_extclk/latest

Test location /workspace/coverage/default/46.clkmgr_frequency.729319560
Short name T263
Test name
Test status
Simulation time 319475950 ps
CPU time 3.05 seconds
Started Aug 07 05:03:43 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201176 kb
Host smart-a3a11f8b-fd9b-44ef-845c-c7483da68973
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729319560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.729319560
Directory /workspace/46.clkmgr_frequency/latest

Test location /workspace/coverage/default/46.clkmgr_frequency_timeout.2769724874
Short name T714
Test name
Test status
Simulation time 981839051 ps
CPU time 5.41 seconds
Started Aug 07 05:03:51 PM PDT 24
Finished Aug 07 05:03:56 PM PDT 24
Peak memory 201200 kb
Host smart-95c65004-bb56-4012-9bc3-e24dd7c94f8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769724874 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_t
imeout.2769724874
Directory /workspace/46.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/46.clkmgr_idle_intersig_mubi.122458239
Short name T335
Test name
Test status
Simulation time 16140579 ps
CPU time 0.78 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:58 PM PDT 24
Peak memory 201140 kb
Host smart-27a08e9e-65f6-4084-af9c-971b87e95166
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122458239 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.clkmgr_idle_intersig_mubi.122458239
Directory /workspace/46.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.894735088
Short name T765
Test name
Test status
Simulation time 39355777 ps
CPU time 0.81 seconds
Started Aug 07 05:04:02 PM PDT 24
Finished Aug 07 05:04:03 PM PDT 24
Peak memory 201136 kb
Host smart-5171e6b8-aa21-4833-b51c-f836b2446033
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894735088 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 46.clkmgr_lc_clk_byp_req_intersig_mubi.894735088
Directory /workspace/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.21662693
Short name T516
Test name
Test status
Simulation time 20781954 ps
CPU time 0.73 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201056 kb
Host smart-385d1b5c-4bf9-48ff-bc49-cafb6a7130f9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21662693 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_lc_ctrl_intersig_mubi.21662693
Directory /workspace/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/46.clkmgr_peri.7821586
Short name T653
Test name
Test status
Simulation time 43565286 ps
CPU time 0.8 seconds
Started Aug 07 05:03:46 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201028 kb
Host smart-21462b7d-4544-4f99-86a0-a087b48c8550
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7821586 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.7821586
Directory /workspace/46.clkmgr_peri/latest

Test location /workspace/coverage/default/46.clkmgr_regwen.1173923458
Short name T363
Test name
Test status
Simulation time 1080456402 ps
CPU time 6.08 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:55 PM PDT 24
Peak memory 201196 kb
Host smart-214e35d8-62ef-4a2f-a524-39abcde1f9b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173923458 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.1173923458
Directory /workspace/46.clkmgr_regwen/latest

Test location /workspace/coverage/default/46.clkmgr_smoke.3892591982
Short name T425
Test name
Test status
Simulation time 22029588 ps
CPU time 0.88 seconds
Started Aug 07 05:03:52 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 200948 kb
Host smart-bd9ffa34-ead1-49f6-8e21-ed160d0c55d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892591982 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.3892591982
Directory /workspace/46.clkmgr_smoke/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all.862726783
Short name T405
Test name
Test status
Simulation time 2721799729 ps
CPU time 15.11 seconds
Started Aug 07 05:03:38 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 201424 kb
Host smart-9ff12c0b-5349-4806-b4ba-4d90668f79bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862726783 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM
_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.clkmgr_stress_all.862726783
Directory /workspace/46.clkmgr_stress_all/latest

Test location /workspace/coverage/default/46.clkmgr_stress_all_with_rand_reset.178610469
Short name T184
Test name
Test status
Simulation time 22783675618 ps
CPU time 321.8 seconds
Started Aug 07 05:03:49 PM PDT 24
Finished Aug 07 05:09:11 PM PDT 24
Peak memory 217864 kb
Host smart-97f6802c-5bfe-4517-8321-9144885b3552
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=178610469 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.178610469
Directory /workspace/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.clkmgr_trans.2505288019
Short name T319
Test name
Test status
Simulation time 23193739 ps
CPU time 0.76 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201056 kb
Host smart-34727db9-3062-47a5-bb1e-910a1c3e17e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505288019 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.2505288019
Directory /workspace/46.clkmgr_trans/latest

Test location /workspace/coverage/default/47.clkmgr_alert_test.2458318209
Short name T200
Test name
Test status
Simulation time 16785310 ps
CPU time 0.81 seconds
Started Aug 07 05:03:53 PM PDT 24
Finished Aug 07 05:03:54 PM PDT 24
Peak memory 201032 kb
Host smart-55af24f9-c7f9-4eeb-8f04-af160f1d6cec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458318209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clk
mgr_alert_test.2458318209
Directory /workspace/47.clkmgr_alert_test/latest

Test location /workspace/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.2059389915
Short name T552
Test name
Test status
Simulation time 13683329 ps
CPU time 0.73 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201084 kb
Host smart-783adb67-0a79-46c5-9269-322b1b8a060d
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059389915 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_clk_handshake_intersig_mubi.2059389915
Directory /workspace/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_clk_status.2569321881
Short name T453
Test name
Test status
Simulation time 38279948 ps
CPU time 0.76 seconds
Started Aug 07 05:03:57 PM PDT 24
Finished Aug 07 05:03:58 PM PDT 24
Peak memory 200996 kb
Host smart-7770181b-bcdb-4ca1-a515-712030f70219
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569321881 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.2569321881
Directory /workspace/47.clkmgr_clk_status/latest

Test location /workspace/coverage/default/47.clkmgr_div_intersig_mubi.1838506262
Short name T744
Test name
Test status
Simulation time 85871800 ps
CPU time 1.01 seconds
Started Aug 07 05:03:57 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 201148 kb
Host smart-55ec042b-92a2-49e6-9db6-e1552abd7519
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838506262 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_div_intersig_mubi.1838506262
Directory /workspace/47.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_extclk.4239408884
Short name T612
Test name
Test status
Simulation time 67299685 ps
CPU time 1.03 seconds
Started Aug 07 05:03:50 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 201060 kb
Host smart-d225e6aa-3271-41b7-8a73-80d847209064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239408884 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.4239408884
Directory /workspace/47.clkmgr_extclk/latest

Test location /workspace/coverage/default/47.clkmgr_frequency.4171890173
Short name T760
Test name
Test status
Simulation time 440624941 ps
CPU time 3.96 seconds
Started Aug 07 05:03:53 PM PDT 24
Finished Aug 07 05:03:57 PM PDT 24
Peak memory 201124 kb
Host smart-1ff4f5af-9724-4fbc-a707-8dc47a51a7b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171890173 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.4171890173
Directory /workspace/47.clkmgr_frequency/latest

Test location /workspace/coverage/default/47.clkmgr_frequency_timeout.2395325901
Short name T577
Test name
Test status
Simulation time 274104154 ps
CPU time 1.71 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201244 kb
Host smart-f9a32c60-d736-48e7-ad2b-61bd76307c36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395325901 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_t
imeout.2395325901
Directory /workspace/47.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/47.clkmgr_idle_intersig_mubi.2383094238
Short name T689
Test name
Test status
Simulation time 63477847 ps
CPU time 1.03 seconds
Started Aug 07 05:04:00 PM PDT 24
Finished Aug 07 05:04:01 PM PDT 24
Peak memory 201084 kb
Host smart-362184d8-be16-4554-924b-843b26d3d529
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383094238 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_idle_intersig_mubi.2383094238
Directory /workspace/47.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.2830048051
Short name T164
Test name
Test status
Simulation time 30779821 ps
CPU time 0.83 seconds
Started Aug 07 05:04:02 PM PDT 24
Finished Aug 07 05:04:03 PM PDT 24
Peak memory 201136 kb
Host smart-660d5b1f-d461-47b1-8872-14876f67bbef
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830048051 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 47.clkmgr_lc_clk_byp_req_intersig_mubi.2830048051
Directory /workspace/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.783563744
Short name T430
Test name
Test status
Simulation time 18191760 ps
CPU time 0.76 seconds
Started Aug 07 05:03:55 PM PDT 24
Finished Aug 07 05:03:56 PM PDT 24
Peak memory 200992 kb
Host smart-c9f31102-a918-4b29-bb0e-670a2a24a908
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783563744 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 47.clkmgr_lc_ctrl_intersig_mubi.783563744
Directory /workspace/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/47.clkmgr_peri.2265126922
Short name T805
Test name
Test status
Simulation time 15195674 ps
CPU time 0.74 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 201072 kb
Host smart-9c4a49cb-5a8f-451b-94fa-323d995115c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265126922 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.2265126922
Directory /workspace/47.clkmgr_peri/latest

Test location /workspace/coverage/default/47.clkmgr_regwen.1384451100
Short name T673
Test name
Test status
Simulation time 482465951 ps
CPU time 2.97 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:50 PM PDT 24
Peak memory 201280 kb
Host smart-f36d6e29-02ee-422f-acdb-741114f7d4f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384451100 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.1384451100
Directory /workspace/47.clkmgr_regwen/latest

Test location /workspace/coverage/default/47.clkmgr_smoke.1418990797
Short name T686
Test name
Test status
Simulation time 29764682 ps
CPU time 0.87 seconds
Started Aug 07 05:04:06 PM PDT 24
Finished Aug 07 05:04:07 PM PDT 24
Peak memory 201140 kb
Host smart-7a47bc99-0994-448d-a466-6ef2144b8cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418990797 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1418990797
Directory /workspace/47.clkmgr_smoke/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all.1559852936
Short name T584
Test name
Test status
Simulation time 1933313022 ps
CPU time 8.74 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:57 PM PDT 24
Peak memory 201372 kb
Host smart-3ca7a31f-80e9-4d14-b38a-ccf92bda3d3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559852936 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.clkmgr_stress_all.1559852936
Directory /workspace/47.clkmgr_stress_all/latest

Test location /workspace/coverage/default/47.clkmgr_stress_all_with_rand_reset.3022329584
Short name T807
Test name
Test status
Simulation time 26925804589 ps
CPU time 498.42 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:12:07 PM PDT 24
Peak memory 217928 kb
Host smart-9923b518-70bd-4a02-8d5b-e3a595e99ad4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3022329584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.3022329584
Directory /workspace/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.clkmgr_trans.245958807
Short name T306
Test name
Test status
Simulation time 312820987 ps
CPU time 1.82 seconds
Started Aug 07 05:03:50 PM PDT 24
Finished Aug 07 05:03:52 PM PDT 24
Peak memory 201076 kb
Host smart-15573421-2148-462f-82c1-0d7cc06da747
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245958807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.245958807
Directory /workspace/47.clkmgr_trans/latest

Test location /workspace/coverage/default/48.clkmgr_alert_test.2128548080
Short name T702
Test name
Test status
Simulation time 41056468 ps
CPU time 0.79 seconds
Started Aug 07 05:04:06 PM PDT 24
Finished Aug 07 05:04:07 PM PDT 24
Peak memory 201144 kb
Host smart-70bb536e-da6e-4532-9a40-107f3ede06c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128548080 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clk
mgr_alert_test.2128548080
Directory /workspace/48.clkmgr_alert_test/latest

Test location /workspace/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.1392453732
Short name T740
Test name
Test status
Simulation time 64144076 ps
CPU time 1.04 seconds
Started Aug 07 05:04:09 PM PDT 24
Finished Aug 07 05:04:10 PM PDT 24
Peak memory 201320 kb
Host smart-beb66d92-7d97-4efc-9d2e-bae14ec785f1
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392453732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_clk_handshake_intersig_mubi.1392453732
Directory /workspace/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_clk_status.2432006491
Short name T209
Test name
Test status
Simulation time 46887579 ps
CPU time 0.8 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 200280 kb
Host smart-d6275586-b216-448d-a151-dcabaaa9fbeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432006491 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.2432006491
Directory /workspace/48.clkmgr_clk_status/latest

Test location /workspace/coverage/default/48.clkmgr_div_intersig_mubi.4111789645
Short name T822
Test name
Test status
Simulation time 15365132 ps
CPU time 0.78 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201072 kb
Host smart-35d035e2-37f4-4e9e-b50b-a4066a40bd2c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111789645 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_div_intersig_mubi.4111789645
Directory /workspace/48.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_extclk.4280609039
Short name T732
Test name
Test status
Simulation time 120166456 ps
CPU time 1.06 seconds
Started Aug 07 05:03:52 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 200984 kb
Host smart-7cc85475-1428-4bda-ad33-aa75b8b5b775
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280609039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.4280609039
Directory /workspace/48.clkmgr_extclk/latest

Test location /workspace/coverage/default/48.clkmgr_frequency.3692523903
Short name T21
Test name
Test status
Simulation time 214224772 ps
CPU time 1.55 seconds
Started Aug 07 05:04:02 PM PDT 24
Finished Aug 07 05:04:04 PM PDT 24
Peak memory 201180 kb
Host smart-3d0e6439-e171-4f09-9674-094c12cf740f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692523903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.3692523903
Directory /workspace/48.clkmgr_frequency/latest

Test location /workspace/coverage/default/48.clkmgr_idle_intersig_mubi.1042967732
Short name T562
Test name
Test status
Simulation time 25302818 ps
CPU time 0.82 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201076 kb
Host smart-675087b7-9936-4bcc-80b2-fa4ebe27d2e3
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042967732 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_idle_intersig_mubi.1042967732
Directory /workspace/48.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.586251526
Short name T323
Test name
Test status
Simulation time 73463618 ps
CPU time 1 seconds
Started Aug 07 05:03:54 PM PDT 24
Finished Aug 07 05:03:55 PM PDT 24
Peak memory 201056 kb
Host smart-778c7092-ca8f-4e4e-82be-b557bb230a04
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586251526 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 48.clkmgr_lc_clk_byp_req_intersig_mubi.586251526
Directory /workspace/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1509370464
Short name T784
Test name
Test status
Simulation time 24864754 ps
CPU time 0.89 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201124 kb
Host smart-e3b8f42e-aeb0-4463-842d-d932d8ca28ab
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509370464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 48.clkmgr_lc_ctrl_intersig_mubi.1509370464
Directory /workspace/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/48.clkmgr_peri.1275820969
Short name T814
Test name
Test status
Simulation time 23039120 ps
CPU time 0.81 seconds
Started Aug 07 05:03:46 PM PDT 24
Finished Aug 07 05:03:47 PM PDT 24
Peak memory 201084 kb
Host smart-9759b09d-69c5-40fd-9979-711cb38778f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275820969 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1275820969
Directory /workspace/48.clkmgr_peri/latest

Test location /workspace/coverage/default/48.clkmgr_regwen.3714368841
Short name T127
Test name
Test status
Simulation time 479491138 ps
CPU time 2.18 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 201076 kb
Host smart-f42ed90f-4b4f-46a1-94cf-bb3855da241d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714368841 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.3714368841
Directory /workspace/48.clkmgr_regwen/latest

Test location /workspace/coverage/default/48.clkmgr_smoke.1622494343
Short name T161
Test name
Test status
Simulation time 43861763 ps
CPU time 0.98 seconds
Started Aug 07 05:03:50 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 201044 kb
Host smart-9f515234-f4a8-491b-800e-495b6d9c5ce5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622494343 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.1622494343
Directory /workspace/48.clkmgr_smoke/latest

Test location /workspace/coverage/default/48.clkmgr_stress_all.4142983906
Short name T549
Test name
Test status
Simulation time 654043070 ps
CPU time 4.72 seconds
Started Aug 07 05:04:07 PM PDT 24
Finished Aug 07 05:04:12 PM PDT 24
Peak memory 201612 kb
Host smart-0bfd3873-0d65-4f3f-9020-9138538d6d48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142983906 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.clkmgr_stress_all.4142983906
Directory /workspace/48.clkmgr_stress_all/latest

Test location /workspace/coverage/default/48.clkmgr_trans.2181674341
Short name T435
Test name
Test status
Simulation time 113435685 ps
CPU time 1.27 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 201116 kb
Host smart-01cf37a1-93cc-4fd2-893c-ecff5a0db3cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181674341 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.2181674341
Directory /workspace/48.clkmgr_trans/latest

Test location /workspace/coverage/default/49.clkmgr_alert_test.1302026705
Short name T284
Test name
Test status
Simulation time 22555695 ps
CPU time 0.77 seconds
Started Aug 07 05:04:15 PM PDT 24
Finished Aug 07 05:04:16 PM PDT 24
Peak memory 201076 kb
Host smart-44e095f9-0410-419f-8582-f28e0da40e71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302026705 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clk
mgr_alert_test.1302026705
Directory /workspace/49.clkmgr_alert_test/latest

Test location /workspace/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.475277016
Short name T105
Test name
Test status
Simulation time 81371004 ps
CPU time 1.05 seconds
Started Aug 07 05:03:58 PM PDT 24
Finished Aug 07 05:03:59 PM PDT 24
Peak memory 201320 kb
Host smart-7450f736-0ffd-461b-9e3f-0708bfc48208
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475277016 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_clk_handshake_intersig_mubi.475277016
Directory /workspace/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_clk_status.1609991520
Short name T504
Test name
Test status
Simulation time 53746994 ps
CPU time 0.81 seconds
Started Aug 07 05:03:50 PM PDT 24
Finished Aug 07 05:03:51 PM PDT 24
Peak memory 200252 kb
Host smart-c85f47c7-ace0-4f5e-9867-3e89235783fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609991520 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.1609991520
Directory /workspace/49.clkmgr_clk_status/latest

Test location /workspace/coverage/default/49.clkmgr_div_intersig_mubi.2929812406
Short name T492
Test name
Test status
Simulation time 25750366 ps
CPU time 0.92 seconds
Started Aug 07 05:03:51 PM PDT 24
Finished Aug 07 05:03:52 PM PDT 24
Peak memory 201044 kb
Host smart-4a7525ba-096c-41d0-829b-0a078aacaf16
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929812406 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_div_intersig_mubi.2929812406
Directory /workspace/49.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_extclk.3096287375
Short name T747
Test name
Test status
Simulation time 78317576 ps
CPU time 1.1 seconds
Started Aug 07 05:04:09 PM PDT 24
Finished Aug 07 05:04:10 PM PDT 24
Peak memory 201316 kb
Host smart-9c6b3a94-ce35-4c7e-a61a-1de854e95961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096287375 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.3096287375
Directory /workspace/49.clkmgr_extclk/latest

Test location /workspace/coverage/default/49.clkmgr_frequency.4134399840
Short name T787
Test name
Test status
Simulation time 562273908 ps
CPU time 4.9 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:53 PM PDT 24
Peak memory 201140 kb
Host smart-bb59f30a-4b18-4ea0-898d-670173393871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134399840 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.4134399840
Directory /workspace/49.clkmgr_frequency/latest

Test location /workspace/coverage/default/49.clkmgr_frequency_timeout.2261880497
Short name T264
Test name
Test status
Simulation time 1215491068 ps
CPU time 9.07 seconds
Started Aug 07 05:04:12 PM PDT 24
Finished Aug 07 05:04:22 PM PDT 24
Peak memory 201168 kb
Host smart-097f83af-5f9e-4263-a6fe-6a8084ef013c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261880497 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_t
imeout.2261880497
Directory /workspace/49.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/49.clkmgr_idle_intersig_mubi.3363323616
Short name T282
Test name
Test status
Simulation time 67237415 ps
CPU time 1.13 seconds
Started Aug 07 05:03:48 PM PDT 24
Finished Aug 07 05:03:49 PM PDT 24
Peak memory 201000 kb
Host smart-035f8d9d-6f6c-45ad-b128-4ad0be8e9d2f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363323616 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_idle_intersig_mubi.3363323616
Directory /workspace/49.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.1062027488
Short name T617
Test name
Test status
Simulation time 19212022 ps
CPU time 0.77 seconds
Started Aug 07 05:04:13 PM PDT 24
Finished Aug 07 05:04:14 PM PDT 24
Peak memory 201132 kb
Host smart-c6098aa2-fc14-4162-89bc-472ad7812729
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062027488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_clk_byp_req_intersig_mubi.1062027488
Directory /workspace/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.4258469048
Short name T542
Test name
Test status
Simulation time 38091158 ps
CPU time 0.83 seconds
Started Aug 07 05:03:47 PM PDT 24
Finished Aug 07 05:03:48 PM PDT 24
Peak memory 201048 kb
Host smart-5be22c4e-0633-429a-8b60-73cbdc7bfaec
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258469048 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 49.clkmgr_lc_ctrl_intersig_mubi.4258469048
Directory /workspace/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/49.clkmgr_peri.1688509188
Short name T337
Test name
Test status
Simulation time 32405028 ps
CPU time 0.79 seconds
Started Aug 07 05:03:59 PM PDT 24
Finished Aug 07 05:04:00 PM PDT 24
Peak memory 201128 kb
Host smart-85a13313-d6b5-4931-a703-9cbb8fb7c653
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688509188 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.1688509188
Directory /workspace/49.clkmgr_peri/latest

Test location /workspace/coverage/default/49.clkmgr_regwen.3763236283
Short name T177
Test name
Test status
Simulation time 695126388 ps
CPU time 3.5 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:04:08 PM PDT 24
Peak memory 201304 kb
Host smart-1ac2dcf5-3584-4509-96b7-edf3402fb09d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763236283 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.3763236283
Directory /workspace/49.clkmgr_regwen/latest

Test location /workspace/coverage/default/49.clkmgr_smoke.2514299288
Short name T683
Test name
Test status
Simulation time 36953920 ps
CPU time 0.92 seconds
Started Aug 07 05:03:53 PM PDT 24
Finished Aug 07 05:03:54 PM PDT 24
Peak memory 201040 kb
Host smart-dbd385fd-f33f-4823-87c6-05a20b379a42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514299288 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.2514299288
Directory /workspace/49.clkmgr_smoke/latest

Test location /workspace/coverage/default/49.clkmgr_stress_all.2700008377
Short name T446
Test name
Test status
Simulation time 5158848149 ps
CPU time 27.8 seconds
Started Aug 07 05:04:09 PM PDT 24
Finished Aug 07 05:04:37 PM PDT 24
Peak memory 201704 kb
Host smart-a2238351-c0e8-4bb9-bbf9-5c1c7d7f58ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700008377 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.clkmgr_stress_all.2700008377
Directory /workspace/49.clkmgr_stress_all/latest

Test location /workspace/coverage/default/49.clkmgr_trans.3574875307
Short name T204
Test name
Test status
Simulation time 34444910 ps
CPU time 1 seconds
Started Aug 07 05:04:04 PM PDT 24
Finished Aug 07 05:04:06 PM PDT 24
Peak memory 201316 kb
Host smart-787ffe8d-a1ae-4c21-bebc-d281a4950897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574875307 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.3574875307
Directory /workspace/49.clkmgr_trans/latest

Test location /workspace/coverage/default/5.clkmgr_alert_test.1503633264
Short name T247
Test name
Test status
Simulation time 21254180 ps
CPU time 0.84 seconds
Started Aug 07 05:02:15 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201072 kb
Host smart-5d12e88b-dd26-4401-817e-cb30110e5df2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503633264 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkm
gr_alert_test.1503633264
Directory /workspace/5.clkmgr_alert_test/latest

Test location /workspace/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.1810141241
Short name T628
Test name
Test status
Simulation time 32453369 ps
CPU time 0.84 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201040 kb
Host smart-676d3397-3b65-4cb1-bbc5-9382c821a3ea
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810141241 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_clk_handshake_intersig_mubi.1810141241
Directory /workspace/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_clk_status.3892206366
Short name T434
Test name
Test status
Simulation time 15731795 ps
CPU time 0.77 seconds
Started Aug 07 05:02:14 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 200304 kb
Host smart-f2e09665-1de2-4e8e-98e6-cc9bc87e424a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892206366 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.3892206366
Directory /workspace/5.clkmgr_clk_status/latest

Test location /workspace/coverage/default/5.clkmgr_div_intersig_mubi.1864897973
Short name T416
Test name
Test status
Simulation time 49050638 ps
CPU time 0.98 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201104 kb
Host smart-0da7d407-8e39-40a9-ad34-8908c397e835
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864897973 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_div_intersig_mubi.1864897973
Directory /workspace/5.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_extclk.666401363
Short name T288
Test name
Test status
Simulation time 169199814 ps
CPU time 1.31 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 200992 kb
Host smart-083a0493-f2c1-46a3-aa72-f4836b37a93b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666401363 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.666401363
Directory /workspace/5.clkmgr_extclk/latest

Test location /workspace/coverage/default/5.clkmgr_frequency.2331398753
Short name T10
Test name
Test status
Simulation time 1754243379 ps
CPU time 13.44 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201284 kb
Host smart-201a79d0-d647-415e-a285-83b5d1074f3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331398753 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.2331398753
Directory /workspace/5.clkmgr_frequency/latest

Test location /workspace/coverage/default/5.clkmgr_frequency_timeout.1228028562
Short name T690
Test name
Test status
Simulation time 1937480486 ps
CPU time 13.79 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201208 kb
Host smart-c4cf3771-3ea3-4698-aa74-c64b2d7d3a39
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228028562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_ti
meout.1228028562
Directory /workspace/5.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/5.clkmgr_idle_intersig_mubi.670096894
Short name T630
Test name
Test status
Simulation time 16555212 ps
CPU time 0.78 seconds
Started Aug 07 05:02:15 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201008 kb
Host smart-fcbde2de-02da-4a99-bf17-2bb7f5532a28
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670096894 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5
.clkmgr_idle_intersig_mubi.670096894
Directory /workspace/5.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.1207532755
Short name T260
Test name
Test status
Simulation time 23245887 ps
CPU time 0.87 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201048 kb
Host smart-29eb8359-8302-4ae7-9dfe-f17118cbd2fe
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207532755 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 5.clkmgr_lc_clk_byp_req_intersig_mubi.1207532755
Directory /workspace/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.797268723
Short name T168
Test name
Test status
Simulation time 55412070 ps
CPU time 1.03 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 200972 kb
Host smart-ff7dbf06-54d3-4d87-927b-acc976ae0d86
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797268723 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.clkmgr_lc_ctrl_intersig_mubi.797268723
Directory /workspace/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/5.clkmgr_peri.652004917
Short name T214
Test name
Test status
Simulation time 23134418 ps
CPU time 0.8 seconds
Started Aug 07 05:02:14 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 201000 kb
Host smart-1a1a1141-0fb2-4cdc-bffb-510b2989aed2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652004917 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.652004917
Directory /workspace/5.clkmgr_peri/latest

Test location /workspace/coverage/default/5.clkmgr_regwen.111660593
Short name T645
Test name
Test status
Simulation time 215904501 ps
CPU time 1.92 seconds
Started Aug 07 05:02:14 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201112 kb
Host smart-ef38b5a4-f34a-40b1-b1ac-cb251dbe70e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111660593 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.111660593
Directory /workspace/5.clkmgr_regwen/latest

Test location /workspace/coverage/default/5.clkmgr_smoke.2970576835
Short name T750
Test name
Test status
Simulation time 53364431 ps
CPU time 0.91 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201056 kb
Host smart-f399497f-8886-4506-80ae-da1b2589b742
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970576835 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2970576835
Directory /workspace/5.clkmgr_smoke/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all.1835231228
Short name T767
Test name
Test status
Simulation time 11157153218 ps
CPU time 46.72 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:03:13 PM PDT 24
Peak memory 201412 kb
Host smart-04ad64cf-67af-48df-9a90-d2e38699e0a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835231228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.clkmgr_stress_all.1835231228
Directory /workspace/5.clkmgr_stress_all/latest

Test location /workspace/coverage/default/5.clkmgr_stress_all_with_rand_reset.1118911560
Short name T181
Test name
Test status
Simulation time 167209956622 ps
CPU time 600.79 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:12:14 PM PDT 24
Peak memory 209748 kb
Host smart-2389c0b2-ef8e-401e-aafd-f9efcd27c9c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1118911560 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1118911560
Directory /workspace/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.clkmgr_trans.35232274
Short name T280
Test name
Test status
Simulation time 37610130 ps
CPU time 1.08 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 201020 kb
Host smart-ab0d01bd-be40-4d7b-9434-3e3ffab8b907
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35232274 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.35232274
Directory /workspace/5.clkmgr_trans/latest

Test location /workspace/coverage/default/6.clkmgr_alert_test.4051523672
Short name T368
Test name
Test status
Simulation time 26282228 ps
CPU time 0.78 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201016 kb
Host smart-e572bc9a-675f-4082-9e55-86282849f989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051523672 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkm
gr_alert_test.4051523672
Directory /workspace/6.clkmgr_alert_test/latest

Test location /workspace/coverage/default/6.clkmgr_clk_handshake_intersig_mubi.3319975562
Short name T692
Test name
Test status
Simulation time 25557967 ps
CPU time 0.93 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201056 kb
Host smart-5a2da867-cb87-4ff5-8080-64169519f41b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319975562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_clk_handshake_intersig_mubi.3319975562
Directory /workspace/6.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_clk_status.2648033054
Short name T498
Test name
Test status
Simulation time 16460226 ps
CPU time 0.77 seconds
Started Aug 07 05:02:15 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 200260 kb
Host smart-76d5e710-33c9-436c-a742-b0639ce23e4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648033054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2648033054
Directory /workspace/6.clkmgr_clk_status/latest

Test location /workspace/coverage/default/6.clkmgr_div_intersig_mubi.389659746
Short name T311
Test name
Test status
Simulation time 38263003 ps
CPU time 0.87 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201108 kb
Host smart-f2f4eb94-8042-4182-8dd1-a6b2ec26636b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389659746 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +
UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6
.clkmgr_div_intersig_mubi.389659746
Directory /workspace/6.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_extclk.1932657464
Short name T536
Test name
Test status
Simulation time 119648576 ps
CPU time 1.03 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:15 PM PDT 24
Peak memory 201052 kb
Host smart-7eb8bdef-d7ba-48ea-882e-17d8505bde5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932657464 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1932657464
Directory /workspace/6.clkmgr_extclk/latest

Test location /workspace/coverage/default/6.clkmgr_frequency.2688873037
Short name T719
Test name
Test status
Simulation time 460810194 ps
CPU time 2.54 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201024 kb
Host smart-8cf62bfe-9530-4bf7-b715-e997f0c53cdb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688873037 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2688873037
Directory /workspace/6.clkmgr_frequency/latest

Test location /workspace/coverage/default/6.clkmgr_frequency_timeout.3282608457
Short name T262
Test name
Test status
Simulation time 1700486847 ps
CPU time 11.9 seconds
Started Aug 07 05:02:11 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201256 kb
Host smart-6b9d068e-5184-4894-9d42-a311e727984b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282608457 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_ti
meout.3282608457
Directory /workspace/6.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/6.clkmgr_idle_intersig_mubi.3727185668
Short name T339
Test name
Test status
Simulation time 30350860 ps
CPU time 0.88 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201104 kb
Host smart-f865557c-584b-4c5f-b5f8-438298b3e9da
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727185668 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_idle_intersig_mubi.3727185668
Directory /workspace/6.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_clk_byp_req_intersig_mubi.2553997228
Short name T606
Test name
Test status
Simulation time 172555297 ps
CPU time 1.3 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201100 kb
Host smart-5827c7e8-b01e-4b16-95a5-bfc576becbd7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553997228 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_clk_byp_req_intersig_mubi.2553997228
Directory /workspace/6.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_lc_ctrl_intersig_mubi.3663609008
Short name T529
Test name
Test status
Simulation time 25386648 ps
CPU time 0.96 seconds
Started Aug 07 05:02:15 PM PDT 24
Finished Aug 07 05:02:16 PM PDT 24
Peak memory 201072 kb
Host smart-eab61428-f36e-4c22-b844-8ae93800c708
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3663609008 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 6.clkmgr_lc_ctrl_intersig_mubi.3663609008
Directory /workspace/6.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/6.clkmgr_peri.3804917170
Short name T598
Test name
Test status
Simulation time 41895913 ps
CPU time 0.81 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201072 kb
Host smart-355614bc-5591-4eda-a16b-f72749df9bb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804917170 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3804917170
Directory /workspace/6.clkmgr_peri/latest

Test location /workspace/coverage/default/6.clkmgr_regwen.3805339706
Short name T737
Test name
Test status
Simulation time 739201575 ps
CPU time 4.28 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201264 kb
Host smart-3d1e61a2-1860-4f62-a34b-858ba4c96bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805339706 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.3805339706
Directory /workspace/6.clkmgr_regwen/latest

Test location /workspace/coverage/default/6.clkmgr_smoke.543077812
Short name T151
Test name
Test status
Simulation time 41774781 ps
CPU time 0.98 seconds
Started Aug 07 05:02:13 PM PDT 24
Finished Aug 07 05:02:14 PM PDT 24
Peak memory 201020 kb
Host smart-c47b8ca6-2b9c-4439-b3b6-1e647462cf55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543077812 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.543077812
Directory /workspace/6.clkmgr_smoke/latest

Test location /workspace/coverage/default/6.clkmgr_stress_all.2090096006
Short name T162
Test name
Test status
Simulation time 10163984240 ps
CPU time 76.02 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201464 kb
Host smart-82f2abb5-b8ae-4530-acf0-1225c89ede38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090096006 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.clkmgr_stress_all.2090096006
Directory /workspace/6.clkmgr_stress_all/latest

Test location /workspace/coverage/default/6.clkmgr_trans.1950512996
Short name T718
Test name
Test status
Simulation time 95930471 ps
CPU time 1.17 seconds
Started Aug 07 05:02:26 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201056 kb
Host smart-adf39a3a-f170-4f53-a879-663764ab5ef8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950512996 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.1950512996
Directory /workspace/6.clkmgr_trans/latest

Test location /workspace/coverage/default/7.clkmgr_alert_test.3456252284
Short name T729
Test name
Test status
Simulation time 13431197 ps
CPU time 0.71 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:26 PM PDT 24
Peak memory 201096 kb
Host smart-e5161bc3-8c45-4d49-8584-aaa1b16000f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456252284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkm
gr_alert_test.3456252284
Directory /workspace/7.clkmgr_alert_test/latest

Test location /workspace/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1242777567
Short name T804
Test name
Test status
Simulation time 39154516 ps
CPU time 0.78 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201072 kb
Host smart-3e4895bf-01a2-46a7-be3d-1f77612af6de
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242777567 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_clk_handshake_intersig_mubi.1242777567
Directory /workspace/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_clk_status.2354150846
Short name T298
Test name
Test status
Simulation time 86778815 ps
CPU time 0.86 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 200188 kb
Host smart-29bf3db7-442d-48b2-8624-f80e3d3b86d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354150846 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.2354150846
Directory /workspace/7.clkmgr_clk_status/latest

Test location /workspace/coverage/default/7.clkmgr_div_intersig_mubi.1102166459
Short name T254
Test name
Test status
Simulation time 21668408 ps
CPU time 0.84 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201056 kb
Host smart-a8d743f7-a967-48e4-b0b6-b7b43059c56e
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102166459 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_div_intersig_mubi.1102166459
Directory /workspace/7.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_extclk.3364654970
Short name T397
Test name
Test status
Simulation time 34445733 ps
CPU time 0.87 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201072 kb
Host smart-cd91b75e-cf85-4621-83ef-c5a517c090a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364654970 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.3364654970
Directory /workspace/7.clkmgr_extclk/latest

Test location /workspace/coverage/default/7.clkmgr_frequency.1883996630
Short name T724
Test name
Test status
Simulation time 1760018040 ps
CPU time 14.01 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:35 PM PDT 24
Peak memory 201396 kb
Host smart-b028f65b-d176-42b4-b48f-4b6d46960f6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883996630 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.1883996630
Directory /workspace/7.clkmgr_frequency/latest

Test location /workspace/coverage/default/7.clkmgr_frequency_timeout.1978564907
Short name T230
Test name
Test status
Simulation time 2070246835 ps
CPU time 10.86 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:34 PM PDT 24
Peak memory 201416 kb
Host smart-fd92dbf0-83d6-473a-938e-a849e42d2e78
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978564907 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_ti
meout.1978564907
Directory /workspace/7.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/7.clkmgr_idle_intersig_mubi.3504683403
Short name T582
Test name
Test status
Simulation time 53181124 ps
CPU time 1.01 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201024 kb
Host smart-d74331a4-ead1-47a6-ad36-d0602046dfe9
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504683403 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_idle_intersig_mubi.3504683403
Directory /workspace/7.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.4114136364
Short name T377
Test name
Test status
Simulation time 50383854 ps
CPU time 0.87 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201072 kb
Host smart-a8eb63a5-0f32-4ce3-bdab-03461ba52bde
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114136364 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 7.clkmgr_lc_clk_byp_req_intersig_mubi.4114136364
Directory /workspace/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.996048332
Short name T620
Test name
Test status
Simulation time 12915929 ps
CPU time 0.73 seconds
Started Aug 07 05:02:19 PM PDT 24
Finished Aug 07 05:02:20 PM PDT 24
Peak memory 201116 kb
Host smart-977287da-11b4-4df1-af65-201ea7191652
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996048332 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 7.clkmgr_lc_ctrl_intersig_mubi.996048332
Directory /workspace/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/7.clkmgr_peri.3649048162
Short name T669
Test name
Test status
Simulation time 30409736 ps
CPU time 0.84 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201072 kb
Host smart-c00543d6-7b72-40dd-8418-4d93ef3651a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649048162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.3649048162
Directory /workspace/7.clkmgr_peri/latest

Test location /workspace/coverage/default/7.clkmgr_regwen.2662306269
Short name T178
Test name
Test status
Simulation time 602148921 ps
CPU time 3.75 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201280 kb
Host smart-2d02d86b-f889-47a9-a31d-9f6582399cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662306269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.2662306269
Directory /workspace/7.clkmgr_regwen/latest

Test location /workspace/coverage/default/7.clkmgr_smoke.481127154
Short name T660
Test name
Test status
Simulation time 73263980 ps
CPU time 0.98 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:26 PM PDT 24
Peak memory 201028 kb
Host smart-cd276c90-9d7f-4c59-a803-c2ce23772bdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481127154 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.481127154
Directory /workspace/7.clkmgr_smoke/latest

Test location /workspace/coverage/default/7.clkmgr_stress_all.1083437350
Short name T514
Test name
Test status
Simulation time 10143055673 ps
CPU time 76.45 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:03:38 PM PDT 24
Peak memory 201456 kb
Host smart-86191959-a4d3-46a8-bf2a-5cedc758c301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083437350 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.clkmgr_stress_all.1083437350
Directory /workspace/7.clkmgr_stress_all/latest

Test location /workspace/coverage/default/7.clkmgr_trans.478579298
Short name T16
Test name
Test status
Simulation time 221375462 ps
CPU time 1.43 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201092 kb
Host smart-3f961ecb-db92-4719-8797-727e90c0aae6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478579298 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.478579298
Directory /workspace/7.clkmgr_trans/latest

Test location /workspace/coverage/default/8.clkmgr_alert_test.3611810595
Short name T800
Test name
Test status
Simulation time 16254729 ps
CPU time 0.77 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 200928 kb
Host smart-cd3e935f-e070-4676-967f-508e386a047b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611810595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkm
gr_alert_test.3611810595
Directory /workspace/8.clkmgr_alert_test/latest

Test location /workspace/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.971575388
Short name T95
Test name
Test status
Simulation time 16421021 ps
CPU time 0.78 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201040 kb
Host smart-b3a840cf-b3f0-420b-af72-57abd7eeca32
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971575388 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_clk_handshake_intersig_mubi.971575388
Directory /workspace/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_clk_status.1085907202
Short name T604
Test name
Test status
Simulation time 18798585 ps
CPU time 0.74 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 200976 kb
Host smart-cb09bb34-c644-46fc-a705-ebb0464644ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085907202 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1085907202
Directory /workspace/8.clkmgr_clk_status/latest

Test location /workspace/coverage/default/8.clkmgr_div_intersig_mubi.2760991284
Short name T771
Test name
Test status
Simulation time 70545771 ps
CPU time 1.05 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201116 kb
Host smart-7ef7375d-c5e3-436e-9fbd-551474bba111
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760991284 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_div_intersig_mubi.2760991284
Directory /workspace/8.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_extclk.3503182843
Short name T618
Test name
Test status
Simulation time 33383816 ps
CPU time 0.8 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:26 PM PDT 24
Peak memory 201012 kb
Host smart-a8eb7f9a-e30a-46ba-83a4-36e2a30287a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503182843 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_extclk.3503182843
Directory /workspace/8.clkmgr_extclk/latest

Test location /workspace/coverage/default/8.clkmgr_frequency.4056604059
Short name T386
Test name
Test status
Simulation time 573836402 ps
CPU time 3.45 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:31 PM PDT 24
Peak memory 201112 kb
Host smart-f82a513b-43aa-420a-935d-084582f33ba3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056604059 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.4056604059
Directory /workspace/8.clkmgr_frequency/latest

Test location /workspace/coverage/default/8.clkmgr_frequency_timeout.1922722663
Short name T360
Test name
Test status
Simulation time 2424339876 ps
CPU time 15.12 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:36 PM PDT 24
Peak memory 201460 kb
Host smart-3ff8203c-ee10-40eb-96ca-5ad48121567b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922722663 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_t
imeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_ti
meout.1922722663
Directory /workspace/8.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/8.clkmgr_idle_intersig_mubi.1545483451
Short name T240
Test name
Test status
Simulation time 81222177 ps
CPU time 1.1 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 201072 kb
Host smart-31e399cc-2d59-49c3-b439-e6a9c560a7bd
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545483451 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_idle_intersig_mubi.1545483451
Directory /workspace/8.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.3764133193
Short name T523
Test name
Test status
Simulation time 21376398 ps
CPU time 0.91 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201136 kb
Host smart-35b02f27-0a03-4324-97e6-045313085a8b
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764133193 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_clk_byp_req_intersig_mubi.3764133193
Directory /workspace/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1617204004
Short name T646
Test name
Test status
Simulation time 59656218 ps
CPU time 0.96 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201056 kb
Host smart-9fefd0f2-efd8-409a-afec-42e0908e501f
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617204004 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 8.clkmgr_lc_ctrl_intersig_mubi.1617204004
Directory /workspace/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/8.clkmgr_peri.3492594003
Short name T621
Test name
Test status
Simulation time 19536455 ps
CPU time 0.73 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:22 PM PDT 24
Peak memory 201056 kb
Host smart-f1d8a8e3-de4b-4dd3-a451-0d9f33883ea9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492594003 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.3492594003
Directory /workspace/8.clkmgr_peri/latest

Test location /workspace/coverage/default/8.clkmgr_regwen.1587686039
Short name T192
Test name
Test status
Simulation time 1072791603 ps
CPU time 4.15 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:27 PM PDT 24
Peak memory 201220 kb
Host smart-6b99c252-8163-4ee9-8e0f-67c8fe22df0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587686039 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.1587686039
Directory /workspace/8.clkmgr_regwen/latest

Test location /workspace/coverage/default/8.clkmgr_smoke.3608211595
Short name T157
Test name
Test status
Simulation time 21966880 ps
CPU time 0.86 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201024 kb
Host smart-aa05636f-42f5-4102-ab0d-e92996b0a9af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608211595 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3608211595
Directory /workspace/8.clkmgr_smoke/latest

Test location /workspace/coverage/default/8.clkmgr_stress_all.3874623044
Short name T15
Test name
Test status
Simulation time 8137368339 ps
CPU time 30.01 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:50 PM PDT 24
Peak memory 201496 kb
Host smart-23e1b5b3-b542-4b81-982f-b78de86f7538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874623044 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.clkmgr_stress_all.3874623044
Directory /workspace/8.clkmgr_stress_all/latest

Test location /workspace/coverage/default/8.clkmgr_trans.1789837268
Short name T655
Test name
Test status
Simulation time 26235585 ps
CPU time 0.83 seconds
Started Aug 07 05:02:24 PM PDT 24
Finished Aug 07 05:02:25 PM PDT 24
Peak memory 200980 kb
Host smart-3bf0bf40-c0ab-450a-8d44-87342972ab46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789837268 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.1789837268
Directory /workspace/8.clkmgr_trans/latest

Test location /workspace/coverage/default/9.clkmgr_alert_test.4063578357
Short name T275
Test name
Test status
Simulation time 15391749 ps
CPU time 0.82 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 200996 kb
Host smart-59f4a07d-4948-442d-a7ea-958d856f34cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l
icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063578357 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_T
EST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkm
gr_alert_test.4063578357
Directory /workspace/9.clkmgr_alert_test/latest

Test location /workspace/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.1462975117
Short name T457
Test name
Test status
Simulation time 21900980 ps
CPU time 0.9 seconds
Started Aug 07 05:02:19 PM PDT 24
Finished Aug 07 05:02:20 PM PDT 24
Peak memory 201064 kb
Host smart-034a0bd5-e3fb-4da3-8122-e4a0322811b7
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462975117 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_clk_handshake_intersig_mubi.1462975117
Directory /workspace/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_clk_status.4070547561
Short name T419
Test name
Test status
Simulation time 45927313 ps
CPU time 0.81 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 200296 kb
Host smart-8cb09b21-a1c4-4c30-97e3-ea93e4bc31eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070547561 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4070547561
Directory /workspace/9.clkmgr_clk_status/latest

Test location /workspace/coverage/default/9.clkmgr_div_intersig_mubi.3931878990
Short name T394
Test name
Test status
Simulation time 22427997 ps
CPU time 0.73 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201036 kb
Host smart-8f0fd19f-ed01-4f04-bfa6-98e86a66470c
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931878990 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_div_intersig_mubi.3931878990
Directory /workspace/9.clkmgr_div_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_extclk.1093545195
Short name T726
Test name
Test status
Simulation time 72978194 ps
CPU time 0.99 seconds
Started Aug 07 05:02:24 PM PDT 24
Finished Aug 07 05:02:25 PM PDT 24
Peak memory 200920 kb
Host smart-5d644883-3720-4072-b21b-66340ac9c960
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093545195 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_extclk.1093545195
Directory /workspace/9.clkmgr_extclk/latest

Test location /workspace/coverage/default/9.clkmgr_frequency.2940293430
Short name T433
Test name
Test status
Simulation time 1740779481 ps
CPU time 7.86 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:28 PM PDT 24
Peak memory 201156 kb
Host smart-24790bb2-2efd-4b45-a6da-242af0ca54be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940293430 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2940293430
Directory /workspace/9.clkmgr_frequency/latest

Test location /workspace/coverage/default/9.clkmgr_frequency_timeout.821028704
Short name T815
Test name
Test status
Simulation time 1035853843 ps
CPU time 4.75 seconds
Started Aug 07 05:02:19 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201200 kb
Host smart-263fa5cf-8371-412d-9f58-af1ddb26fd40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821028704 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_ti
meout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_tim
eout.821028704
Directory /workspace/9.clkmgr_frequency_timeout/latest

Test location /workspace/coverage/default/9.clkmgr_idle_intersig_mubi.1096206213
Short name T477
Test name
Test status
Simulation time 21238620 ps
CPU time 0.83 seconds
Started Aug 07 05:02:22 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201076 kb
Host smart-96ef4647-08d7-4a5b-9ded-d6abba33e320
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096206213 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test
+UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_idle_intersig_mubi.1096206213
Directory /workspace/9.clkmgr_idle_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.470751683
Short name T563
Test name
Test status
Simulation time 22321949 ps
CPU time 0.85 seconds
Started Aug 07 05:02:21 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201108 kb
Host smart-56a2b7ae-00f6-4339-a07f-f643ea2bca13
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470751683 -assert nopostproc +UVM_TESTNAME=clkmgr_base_tes
t +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.clkmgr_lc_clk_byp_req_intersig_mubi.470751683
Directory /workspace/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.3807394236
Short name T599
Test name
Test status
Simulation time 22011657 ps
CPU time 0.87 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201092 kb
Host smart-3a0c82c0-ea14-4805-b7e5-3c9bf7f13c79
User root
Command /workspace/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=U
VM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807394236 -assert nopostproc +UVM_TESTNAME=clkmgr_base_te
st +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na
me 9.clkmgr_lc_ctrl_intersig_mubi.3807394236
Directory /workspace/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspace/coverage/default/9.clkmgr_peri.693663751
Short name T388
Test name
Test status
Simulation time 16022763 ps
CPU time 0.75 seconds
Started Aug 07 05:02:25 PM PDT 24
Finished Aug 07 05:02:26 PM PDT 24
Peak memory 201096 kb
Host smart-b8040b07-b22b-4208-a1db-76aa2dfd7874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693663751 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.693663751
Directory /workspace/9.clkmgr_peri/latest

Test location /workspace/coverage/default/9.clkmgr_regwen.2521461845
Short name T86
Test name
Test status
Simulation time 784292245 ps
CPU time 2.9 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:23 PM PDT 24
Peak memory 201252 kb
Host smart-c38ed707-fe98-4743-88d5-26bbf795f490
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521461845 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.2521461845
Directory /workspace/9.clkmgr_regwen/latest

Test location /workspace/coverage/default/9.clkmgr_smoke.1626952233
Short name T735
Test name
Test status
Simulation time 51195054 ps
CPU time 0.92 seconds
Started Aug 07 05:02:23 PM PDT 24
Finished Aug 07 05:02:24 PM PDT 24
Peak memory 201036 kb
Host smart-59d5905a-78cc-48fb-89d2-607f6125d782
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626952233 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1626952233
Directory /workspace/9.clkmgr_smoke/latest

Test location /workspace/coverage/default/9.clkmgr_stress_all.3690162620
Short name T746
Test name
Test status
Simulation time 3484697355 ps
CPU time 15.82 seconds
Started Aug 07 05:02:27 PM PDT 24
Finished Aug 07 05:02:43 PM PDT 24
Peak memory 201364 kb
Host smart-a6901c71-2ec7-4c47-b80f-a7a92aa00763
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690162620 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UV
M_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.clkmgr_stress_all.3690162620
Directory /workspace/9.clkmgr_stress_all/latest

Test location /workspace/coverage/default/9.clkmgr_trans.1052508887
Short name T46
Test name
Test status
Simulation time 61469874 ps
CPU time 0.9 seconds
Started Aug 07 05:02:20 PM PDT 24
Finished Aug 07 05:02:21 PM PDT 24
Peak memory 201048 kb
Host smart-13049e0e-6127-46d0-9c9c-044f08b55eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052508887 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.1052508887
Directory /workspace/9.clkmgr_trans/latest
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