Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324333106

1

T4

2804

T5

1418

T6

2804

auto[1]

401612

1

T4

818

T5

82

T6

736

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324321828

1

T4

3010

T5

1488

T6

3020

auto[1]

412890

1

T4

612

T5

12

T6

520

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

324239748

1

T4

2812

T5

1460

T6

3028

auto[1]

494970

1

T4

810

T5

40

T6

512

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

301333294

1

T4

542

T5

60

T6

3540

auto[1]

23401424

1

T4

3080

T5

1440

T2

1720

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

209165168

1

T4

3450

T5

1334

T6

1712

auto[1]

115569550

1

T4

172

T5

166

T6

1828

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

187605568

1

T4

300

T5

34

T6

920

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

113379860

1

T5

26

T6

1704

T2

116126

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

30770

1

T4

52

T6

234

T2

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7286

1

T3

18

T21

6

T23

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

20976438

1

T4

2102

T5

1260

T2

1384

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

2079432

1

T4

80

T5

58

T3

138

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

48656

1

T4

70

T2

78

T3

30

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

11712

1

T4

30

T5

82

T3

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48354

1

T6

22

T27

6

T107

50

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1246

1

T3

2

T21

12

T10

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

11356

1

T6

148

T27

56

T11

116

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2742

1

T3

52

T21

72

T10

64

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10278

1

T4

104

T2

26

T3

32

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2474

1

T3

2

T10

2

T77

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

18640

1

T4

74

T2

64

T3

60

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4936

1

T3

58

T10

64

T77

82

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

35842

1

T4

16

T6

8

T3

56

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3910

1

T6

26

T21

34

T107

36

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33748

1

T4

74

T6

78

T3

294

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6958

1

T6

50

T21

64

T107

90

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27450

1

T4

100

T5

28

T3

20

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7774

1

T4

6

T3

20

T19

26

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

52602

1

T4

124

T3

62

T19

252

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

13822

1

T4

56

T20

46

T10

98

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

97946

1

T4

34

T6

76

T2

26

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5624

1

T6

48

T3

2

T23

62

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

50636

1

T4

66

T6

226

T2

48

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

11448

1

T3

52

T23

70

T107

70

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40058

1

T4

62

T5

12

T2

6

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10852

1

T19

4

T20

16

T107

20

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

76826

1

T4

272

T2

162

T3

228

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

19474

1

T19

50

T107

156

T10

106