Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322555386

1

T4

2296

T5

2104

T6

3304

auto[1]

427626

1

T6

730

T1

762

T15

208

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322554316

1

T4

2296

T5

2104

T6

3474

auto[1]

428696

1

T6

560

T1

632

T15

154

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

322465858

1

T4

2296

T5

2104

T6

3332

auto[1]

517154

1

T6

702

T1

596

T15

214

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

303169734

1

T4

2296

T5

2104

T6

2696

auto[1]

19813278

1

T6

1338

T1

4876

T15

138

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181474592

1

T4

2110

T5

2104

T6

4034

auto[1]

141508420

1

T4

186

T1

22862

T15

164

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

166676796

1

T4

2110

T5

2104

T6

2390

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

136128292

1

T4

186

T1

19278

T15

104

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

32352

1

T6

36

T1

44

T15

32

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7868

1

T2

22

T3

92

T72

58

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

14170554

1

T6

666

T1

666

T15

58

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5264020

1

T1

3560

T2

124

T3

162

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

55090

1

T6

108

T1

150

T2

172

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

12738

1

T2

12

T3

96

T8

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

60620

1

T6

4

T1

20

T2

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1582

1

T8

32

T119

4

T12

16

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

13232

1

T6

82

T1

68

T2

56

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2674

1

T119

92

T12

72

T24

88

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10862

1

T6

46

T1

62

T2

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3374

1

T3

8

T8

42

T9

94

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

20472

1

T1

154

T2

36

T8

68

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5332

1

T3

64

T9

138

T14

92

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

50908

1

T6

12

T1

48

T2

32

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3594

1

T15

6

T9

86

T119

14

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

35906

1

T6

80

T1

54

T2

142

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8160

1

T15

54

T9

162

T119

60

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32570

1

T6

16

T1

62

T2

48

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

7946

1

T1

24

T2

8

T8

24

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

54728

1

T6

166

T1

80

T2

262

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12794

1

T8

98

T9

142

T164

84

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

76370

1

T6

92

T1

56

T15

10

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

6590

1

T2

14

T119

32

T143

22

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52028

1

T1

154

T15

64

T2

174

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

12762

1

T2

148

T119

42

T143

148

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

49568

1

T6

78

T1

60

T15

22

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

11740

1

T2

2

T8

74

T72

30

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

82536

1

T6

258

T1

58

T15

58

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18954

1

T2

62

T8

172

T72

50