Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333650602 1 T7 3852 T8 1736 T6 25148
auto[1] 442890 1 T8 382 T26 186 T28 88


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333672810 1 T7 3852 T8 1960 T6 25148
auto[1] 420682 1 T8 158 T26 152 T29 264


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 333572540 1 T7 3852 T8 1672 T6 25148
auto[1] 520952 1 T8 446 T26 130 T28 84


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 304130906 1 T7 3852 T8 1544 T6 25148
auto[1] 29962586 1 T8 574 T26 490 T29 2194


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 194266864 1 T7 674 T8 1916 T6 25148
auto[1] 139826628 1 T7 3178 T8 202 T26 18


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 169048730 1 T7 674 T8 1228 T6 25148
auto[0] auto[0] auto[0] auto[0] auto[1] 134729308 1 T7 3178 T8 88 T26 18
auto[0] auto[0] auto[0] auto[1] auto[0] 32164 1 T28 24 T32 6 T34 6
auto[0] auto[0] auto[0] auto[1] auto[1] 8494 1 T8 34 T29 4 T32 26
auto[0] auto[0] auto[1] auto[0] auto[0] 24604788 1 T8 288 T26 256 T29 1548
auto[0] auto[0] auto[1] auto[0] auto[1] 4971430 1 T29 92 T32 1886 T34 218
auto[0] auto[0] auto[1] auto[1] auto[0] 54388 1 T8 34 T26 124 T29 82
auto[0] auto[0] auto[1] auto[1] auto[1] 12936 1 T29 4 T34 24 T77 28
auto[0] auto[1] auto[0] auto[0] auto[0] 52258 1 T26 42 T34 12 T85 8
auto[0] auto[1] auto[0] auto[0] auto[1] 1838 1 T77 24 T2 32 T13 10
auto[0] auto[1] auto[0] auto[1] auto[0] 13654 1 T34 40 T21 62 T2 516
auto[0] auto[1] auto[0] auto[1] auto[1] 3102 1 T77 72 T2 60 T13 42
auto[0] auto[1] auto[1] auto[0] auto[0] 11002 1 T26 38 T29 12 T34 8
auto[0] auto[1] auto[1] auto[0] auto[1] 2310 1 T34 10 T85 8 T2 80
auto[0] auto[1] auto[1] auto[1] auto[0] 20172 1 T29 56 T2 514 T100 74
auto[0] auto[1] auto[1] auto[1] auto[1] 5966 1 T34 48 T2 52 T25 64
auto[1] auto[0] auto[0] auto[0] auto[0] 48768 1 T8 48 T26 58 T28 20
auto[1] auto[0] auto[0] auto[0] auto[1] 5202 1 T8 10 T29 6 T32 24
auto[1] auto[0] auto[0] auto[1] auto[0] 34152 1 T8 66 T28 64 T77 142
auto[1] auto[0] auto[0] auto[1] auto[1] 9624 1 T8 70 T29 58 T32 122
auto[1] auto[0] auto[1] auto[0] auto[0] 32088 1 T8 18 T29 24 T32 78
auto[1] auto[0] auto[1] auto[0] auto[1] 7514 1 T29 6 T77 28 T85 8
auto[1] auto[0] auto[1] auto[1] auto[0] 58586 1 T8 76 T29 106 T32 120
auto[1] auto[0] auto[1] auto[1] auto[1] 14638 1 T29 68 T77 174 T2 842
auto[1] auto[1] auto[0] auto[0] auto[0] 71244 1 T32 62 T34 10 T77 152
auto[1] auto[1] auto[0] auto[0] auto[1] 6688 1 T34 22 T2 184 T83 38
auto[1] auto[1] auto[0] auto[1] auto[0] 52226 1 T32 100 T34 44 T77 76
auto[1] auto[1] auto[0] auto[1] auto[1] 13454 1 T34 60 T2 276 T83 112
auto[1] auto[1] auto[1] auto[0] auto[0] 45292 1 T8 56 T26 10 T29 32
auto[1] auto[1] auto[1] auto[0] auto[1] 12142 1 T32 62 T34 6 T77 56
auto[1] auto[1] auto[1] auto[1] auto[0] 87352 1 T8 102 T26 62 T29 164
auto[1] auto[1] auto[1] auto[1] auto[1] 21982 1 T34 36 T2 766 T23 44

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