Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319813366 1 T1 61582 T2 64004 T4 3318
auto[1] 406284 1 T12 226 T15 610 T16 150


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319814338 1 T1 61582 T2 64004 T4 3318
auto[1] 405312 1 T12 102 T15 464 T16 64


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 319739278 1 T1 61582 T2 64004 T4 3318
auto[1] 480372 1 T12 234 T15 430 T16 102


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 301755488 1 T1 61582 T2 64004 T4 3318
auto[1] 18464162 1 T12 2224 T15 2974 T23 1470


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 181857994 1 T1 61582 T2 63976 T4 310
auto[1] 138361656 1 T2 28 T4 3008 T12 224


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 166245774 1 T1 61582 T2 63976 T4 310
auto[0] auto[0] auto[0] auto[0] auto[1] 135163792 1 T2 28 T4 3008 T12 106
auto[0] auto[0] auto[0] auto[1] auto[0] 28928 1 T15 24 T16 52 T23 42
auto[0] auto[0] auto[0] auto[1] auto[1] 7754 1 T12 24 T23 18 T125 62
auto[0] auto[0] auto[1] auto[0] auto[0] 15022664 1 T12 2058 T15 2470 T23 814
auto[0] auto[0] auto[1] auto[0] auto[1] 3084770 1 T23 68 T84 2064 T35 176
auto[0] auto[0] auto[1] auto[1] auto[0] 50092 1 T12 26 T15 164 T23 44
auto[0] auto[0] auto[1] auto[1] auto[1] 12966 1 T96 6 T7 232 T81 2
auto[0] auto[1] auto[0] auto[0] auto[0] 65362 1 T15 70 T16 8 T125 16
auto[0] auto[1] auto[0] auto[0] auto[1] 1712 1 T125 4 T118 14 T7 26
auto[0] auto[1] auto[0] auto[1] auto[0] 12720 1 T15 74 T125 38 T6 44
auto[0] auto[1] auto[0] auto[1] auto[1] 3550 1 T125 40 T118 78 T7 96
auto[0] auto[1] auto[1] auto[0] auto[0] 10398 1 T15 40 T23 10 T6 12
auto[0] auto[1] auto[1] auto[0] auto[1] 3496 1 T35 16 T7 192 T11 152
auto[0] auto[1] auto[1] auto[1] auto[0] 20406 1 T23 44 T6 86 T7 406
auto[0] auto[1] auto[1] auto[1] auto[1] 4894 1 T11 170 T25 210 T70 42
auto[1] auto[0] auto[0] auto[0] auto[0] 53038 1 T15 22 T16 2 T23 22
auto[1] auto[0] auto[0] auto[0] auto[1] 4608 1 T12 6 T35 42 T125 16
auto[1] auto[0] auto[0] auto[1] auto[0] 31168 1 T16 44 T23 122 T125 198
auto[1] auto[0] auto[0] auto[1] auto[1] 8186 1 T12 88 T125 56 T6 40
auto[1] auto[0] auto[1] auto[0] auto[0] 28860 1 T12 38 T15 22 T23 24
auto[1] auto[0] auto[1] auto[0] auto[1] 6662 1 T84 2 T35 42 T96 22
auto[1] auto[0] auto[1] auto[1] auto[0] 52688 1 T15 106 T23 58 T6 250
auto[1] auto[0] auto[1] auto[1] auto[1] 12388 1 T84 62 T96 106 T7 302
auto[1] auto[1] auto[0] auto[0] auto[0] 62930 1 T15 10 T16 2 T23 30
auto[1] auto[1] auto[0] auto[0] auto[1] 5446 1 T23 2 T35 38 T125 26
auto[1] auto[1] auto[0] auto[1] auto[0] 48898 1 T15 98 T16 54 T23 96
auto[1] auto[1] auto[0] auto[1] auto[1] 11622 1 T23 64 T125 112 T6 52
auto[1] auto[1] auto[1] auto[0] auto[0] 43698 1 T12 14 T15 28 T23 66
auto[1] auto[1] auto[1] auto[0] auto[1] 10156 1 T23 14 T6 18 T96 24
auto[1] auto[1] auto[1] auto[1] auto[0] 80370 1 T12 88 T15 144 T23 288
auto[1] auto[1] auto[1] auto[1] auto[1] 19654 1 T23 40 T6 64 T124 44

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