Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

67014600

1

T5

2904

T6

1882

T7

2340

auto[1]

274834

1

T5

954

T6

90

T25

1300

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66993704

1

T5

3182

T6

1798

T7

2340

auto[1]

295730

1

T5

676

T6

174

T25

636

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66944364

1

T5

3048

T6

1788

T7

2340

auto[1]

345070

1

T5

810

T6

184

T25

1306

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

66103444

1

T5

2336

T6

1446

T7

2340

auto[1]

1185990

1

T5

1522

T6

526

T26

4366

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48729998

1

T5

3152

T6

442

T7

2340

auto[1]

18559436

1

T5

706

T6

1530

T24

2926

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

47508734

1

T5

1864

T6

34

T7

2340

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18332336

1

T5

132

T6

1376

T24

2926

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20900

1

T5

82

T25

330

T26

38

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5540

1

T5

10

T25

32

T1

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

797356

1

T5

458

T6

222

T26

3072

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

150194

1

T5

240

T6

92

T26

184

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

33302

1

T5

82

T6

38

T26

206

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8450

1

T5

48

T26

14

T28

24

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

52920

1

T39

76

T1

38

T17

34

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1142

1

T25

2

T39

32

T17

24

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7078

1

T39

142

T17

122

T147

96

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2004

1

T25

72

T17

50

T18

68

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8004

1

T5

6

T26

70

T1

54

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1748

1

T5

38

T6

26

T21

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

11702

1

T5

88

T26

86

T1

360

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2954

1

T21

62

T3

66

T12

280

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37254

1

T5

66

T25

180

T26

44

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2902

1

T6

36

T25

32

T39

50

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

20938

1

T5

130

T25

354

T26

78

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5934

1

T25

178

T39

78

T1

78

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20508

1

T26

28

T28

38

T39

12

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4706

1

T5

4

T26

14

T39

18

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36106

1

T26

202

T39

112

T1

350

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8544

1

T5

66

T26

88

T39

46

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

59216

1

T25

166

T26

96

T28

26

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3936

1

T5

10

T25

62

T27

16

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

33768

1

T25

334

T26

46

T28

158

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8842

1

T5

42

T27

74

T19

158

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27206

1

T5

68

T6

96

T26

116

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6438

1

T5

18

T26

34

T28

16

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

55006

1

T5

308

T6

52

T26

252

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13766

1

T5

98

T28

98

T1

142