Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 60702850 1 T10 2708 T11 2812 T12 2024
auto[1] 254352 1 T10 348 T7 1636 T32 366


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 60685414 1 T10 2802 T11 2812 T12 2024
auto[1] 271788 1 T10 254 T7 924 T32 268


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 60623936 1 T10 2724 T11 2812 T12 2024
auto[1] 333266 1 T10 332 T7 1126 T32 338


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 59477832 1 T10 680 T11 2812 T12 2024
auto[1] 1479370 1 T10 2376 T7 6740 T32 1914


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 43250994 1 T10 2982 T11 2792 T12 2024
auto[1] 17706208 1 T10 74 T11 20 T7 50772


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 42011038 1 T10 386 T11 2792 T12 2024
auto[0] auto[0] auto[0] auto[0] auto[1] 17224156 1 T11 20 T7 50298 T32 200
auto[0] auto[0] auto[0] auto[1] auto[0] 18878 1 T10 74 T7 114 T32 74
auto[0] auto[0] auto[0] auto[1] auto[1] 5372 1 T7 12 T34 4 T49 10
auto[0] auto[0] auto[1] auto[0] auto[0] 856872 1 T10 2186 T7 5154 T32 1556
auto[0] auto[0] auto[1] auto[0] auto[1] 407836 1 T10 66 T7 198 T32 154
auto[0] auto[0] auto[1] auto[1] auto[0] 30620 1 T10 12 T7 448 T32 16
auto[0] auto[0] auto[1] auto[1] auto[1] 8230 1 T7 28 T34 4 T39 20
auto[0] auto[1] auto[0] auto[0] auto[0] 29850 1 T7 14 T49 28 T39 2
auto[0] auto[1] auto[0] auto[0] auto[1] 884 1 T158 16 T161 8 T66 40
auto[0] auto[1] auto[0] auto[1] auto[0] 7580 1 T7 86 T49 54 T39 38
auto[0] auto[1] auto[0] auto[1] auto[1] 1980 1 T158 44 T66 120 T154 58
auto[0] auto[1] auto[1] auto[0] auto[0] 5970 1 T7 20 T32 36 T34 20
auto[0] auto[1] auto[1] auto[0] auto[1] 1360 1 T32 12 T115 18 T188 42
auto[0] auto[1] auto[1] auto[1] auto[0] 10446 1 T7 62 T34 66 T84 70
auto[0] auto[1] auto[1] auto[1] auto[1] 2864 1 T32 56 T115 56 T3 154
auto[1] auto[0] auto[0] auto[0] auto[0] 29326 1 T10 2 T7 50 T32 16
auto[1] auto[0] auto[0] auto[0] auto[1] 2876 1 T7 8 T32 60 T84 20
auto[1] auto[0] auto[0] auto[1] auto[0] 20476 1 T10 44 T32 50 T40 70
auto[1] auto[0] auto[0] auto[1] auto[1] 6606 1 T7 56 T32 48 T84 60
auto[1] auto[0] auto[1] auto[0] auto[0] 16330 1 T10 32 T7 56 T40 62
auto[1] auto[0] auto[1] auto[0] auto[1] 4788 1 T7 30 T39 2 T40 10
auto[1] auto[0] auto[1] auto[1] auto[0] 33244 1 T7 116 T40 134 T84 182
auto[1] auto[0] auto[1] auto[1] auto[1] 8766 1 T7 68 T39 60 T40 82
auto[1] auto[1] auto[0] auto[0] auto[0] 76296 1 T10 18 T7 20 T32 8
auto[1] auto[1] auto[0] auto[0] auto[1] 3588 1 T7 2 T34 16 T49 2
auto[1] auto[1] auto[0] auto[1] auto[0] 30328 1 T10 156 T7 104 T32 72
auto[1] auto[1] auto[0] auto[1] auto[1] 8598 1 T7 56 T34 66 T49 52
auto[1] auto[1] auto[1] auto[0] auto[0] 25074 1 T10 10 T7 58 T32 10
auto[1] auto[1] auto[1] auto[0] auto[1] 6606 1 T10 8 T7 16 T32 24
auto[1] auto[1] auto[1] auto[1] auto[0] 48666 1 T10 62 T7 486 T32 50
auto[1] auto[1] auto[1] auto[1] auto[1] 11698 1 T34 82 T40 50 T37 44

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