Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 68228124 1 T7 3164 T8 14126 T9 1268
auto[1] 260260 1 T9 48 T29 118 T21 680


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 68219208 1 T7 3164 T8 14126 T9 1274
auto[1] 269176 1 T9 42 T29 94 T19 56


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 68178908 1 T7 3164 T8 14126 T9 1316
auto[1] 309476 1 T29 98 T19 110 T21 698


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 66939770 1 T7 3164 T8 14126 T9 34
auto[1] 1548614 1 T9 1282 T29 542 T19 356


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 48992050 1 T7 2146 T8 14126 T9 1316
auto[1] 19496334 1 T7 1018 T26 4158 T27 1376


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 47465396 1 T7 2146 T8 14126 T9 34
auto[0] auto[0] auto[0] auto[0] auto[1] 19243560 1 T7 1018 T26 4158 T27 1376
auto[0] auto[0] auto[0] auto[1] auto[0] 21390 1 T21 46 T41 50 T79 38
auto[0] auto[0] auto[0] auto[1] auto[1] 4948 1 T21 12 T41 12 T124 14
auto[0] auto[0] auto[1] auto[0] auto[0] 1142038 1 T9 1232 T29 374 T19 204
auto[0] auto[0] auto[1] auto[0] auto[1] 178514 1 T19 70 T41 94 T79 2290
auto[0] auto[0] auto[1] auto[1] auto[0] 32460 1 T9 8 T29 56 T21 82
auto[0] auto[0] auto[1] auto[1] auto[1] 8110 1 T79 20 T114 30 T123 4
auto[0] auto[1] auto[0] auto[0] auto[0] 45146 1 T126 16 T13 108 T15 164
auto[0] auto[1] auto[0] auto[0] auto[1] 592 1 T41 22 T126 20 T173 8
auto[0] auto[1] auto[0] auto[1] auto[0] 8482 1 T126 76 T13 354 T15 136
auto[0] auto[1] auto[0] auto[1] auto[1] 1928 1 T126 62 T174 58 T175 48
auto[0] auto[1] auto[1] auto[0] auto[0] 7718 1 T9 2 T29 22 T79 6
auto[0] auto[1] auto[1] auto[0] auto[1] 2136 1 T114 74 T13 22 T15 118
auto[0] auto[1] auto[1] auto[1] auto[0] 12914 1 T9 40 T79 44 T73 42
auto[0] auto[1] auto[1] auto[1] auto[1] 3576 1 T13 106 T15 70 T16 318
auto[1] auto[0] auto[0] auto[0] auto[0] 26200 1 T19 28 T41 4 T80 18
auto[1] auto[0] auto[0] auto[0] auto[1] 3306 1 T29 8 T114 92 T124 10
auto[1] auto[0] auto[0] auto[1] auto[0] 21504 1 T41 52 T80 112 T114 152
auto[1] auto[0] auto[0] auto[1] auto[1] 5850 1 T114 78 T124 86 T15 92
auto[1] auto[0] auto[1] auto[0] auto[0] 20778 1 T29 18 T19 26 T21 38
auto[1] auto[0] auto[1] auto[0] auto[1] 5082 1 T123 2 T125 22 T176 68
auto[1] auto[0] auto[1] auto[1] auto[0] 31766 1 T21 124 T79 48 T80 58
auto[1] auto[0] auto[1] auto[1] auto[1] 8306 1 T123 56 T13 80 T15 152
auto[1] auto[1] auto[0] auto[0] auto[0] 47742 1 T21 42 T41 30 T79 4
auto[1] auto[1] auto[0] auto[0] auto[1] 3922 1 T21 16 T41 2 T126 62
auto[1] auto[1] auto[0] auto[1] auto[0] 31910 1 T21 170 T41 126 T79 38
auto[1] auto[1] auto[0] auto[1] auto[1] 7894 1 T21 42 T41 66 T126 150
auto[1] auto[1] auto[1] auto[0] auto[0] 28438 1 T29 10 T19 16 T21 62
auto[1] auto[1] auto[1] auto[0] auto[1] 7556 1 T19 40 T41 46 T79 2
auto[1] auto[1] auto[1] auto[1] auto[0] 48168 1 T29 62 T21 204 T41 70
auto[1] auto[1] auto[1] auto[1] auto[1] 11054 1 T79 56 T80 48 T114 58

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