Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75358012

1

T5

11926

T8

3798

T9

3242

auto[1]

283170

1

T5

392

T8

50

T9

824

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75312832

1

T5

12042

T8

3500

T9

3698

auto[1]

328350

1

T5

276

T8

348

T9

368

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75290020

1

T5

11852

T8

3348

T9

3454

auto[1]

351162

1

T5

466

T8

500

T9

612

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74348760

1

T5

11460

T8

2226

T9

800

auto[1]

1292422

1

T5

858

T8

1622

T9

3266

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54955192

1

T5

5768

T8

3336

T9

3472

auto[1]

20685990

1

T5

6550

T8

512

T9

594

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53617548

1

T5

5178

T8

1772

T9

282

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

20451748

1

T5

6084

T8

278

T9

198

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

22120

1

T5

20

T9

120

T29

82

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5810

1

T9

10

T6

62

T77

24

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

892406

1

T5

266

T8

1112

T9

2526

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

151830

1

T5

244

T8

106

T9

184

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

36090

1

T5

4

T9

62

T26

32

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8732

1

T5

56

T9

26

T26

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

67412

1

T9

2

T29

34

T6

50

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1012

1

T6

18

T35

44

T185

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

7572

1

T9

44

T29

118

T6

50

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2172

1

T6

62

T35

120

T185

40

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

6654

1

T8

30

T26

2

T29

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2244

1

T29

2

T46

26

T13

18

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12730

1

T8

50

T26

58

T29

50

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3940

1

T29

70

T46

38

T13

120

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

25562

1

T8

32

T9

16

T26

22

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3038

1

T8

40

T6

70

T83

8

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23122

1

T9

62

T29

58

T6

66

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5526

1

T6

106

T32

68

T186

38

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

19990

1

T5

52

T8

120

T9

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5490

1

T5

14

T8

40

T9

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

34982

1

T5

70

T9

98

T29

56

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8838

1

T5

54

T9

106

T26

58

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

66826

1

T5

50

T8

56

T29

52

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

5306

1

T8

48

T9

2

T6

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34454

1

T5

128

T29

114

T6

650

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9532

1

T9

64

T6

244

T77

54

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

33396

1

T8

164

T9

24

T26

4

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7550

1

T5

38

T26

10

T6

38

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

54328

1

T9

232

T26

106

T29

70

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13222

1

T5

60

T26

38

T6

216