Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75859242

1

T5

2770

T6

4104

T7

2936

auto[1]

283276

1

T6

1262

T23

1174

T24

122

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75823252

1

T5

2770

T6

4610

T7

2936

auto[1]

319266

1

T6

756

T23

436

T24

246

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75807282

1

T5

2770

T6

4372

T7

2936

auto[1]

335236

1

T6

994

T23

1122

T24

344

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

74772056

1

T5

2770

T6

1038

T7

2936

auto[1]

1370462

1

T6

4328

T23

4250

T24

2026

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54837874

1

T5

2770

T6

5072

T7

2902

auto[1]

21304644

1

T6

294

T7

34

T23

3100

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53439406

1

T5

2770

T6

546

T7

2902

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21038718

1

T7

34

T23

106

T24

224

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

22410

1

T6

158

T23

102

T2

136

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5712

1

T23

12

T24

22

T2

64

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

951330

1

T6

3166

T23

702

T24

1906

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

178780

1

T6

156

T23

2734

T2

428

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

32434

1

T6

122

T23

164

T2

266

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10284

1

T23

16

T2

44

T20

52

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

88534

1

T6

6

T23

10

T2

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1342

1

T10

18

T106

2

T55

24

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8542

1

T6

78

T23

68

T2

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3010

1

T106

62

T166

72

T36

58

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7408

1

T6

32

T20

18

T93

26

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1598

1

T2

56

T104

8

T10

60

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

14114

1

T6

108

T20

74

T103

92

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3660

1

T10

62

T167

80

T36

62

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

42642

1

T6

2

T23

52

T24

52

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3850

1

T23

8

T2

78

T20

22

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

23814

1

T6

74

T23

284

T105

118

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6536

1

T23

74

T2

148

T20

80

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

19542

1

T6

32

T23

76

T24

46

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5008

1

T6

62

T23

4

T2

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33230

1

T6

216

T23

184

T2

124

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9556

1

T6

76

T23

82

T2

58

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39882

1

T6

44

T23

16

T24

32

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4654

1

T24

40

T2

32

T93

42

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

33748

1

T6

130

T23

54

T2

322

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9256

1

T24

100

T2

112

T10

64

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

28660

1

T6

58

T23

90

T24

74

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7888

1

T23

64

T2

82

T20

74

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52178

1

T6

300

T23

134

T2

532

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14792

1

T2

224

T20

128

T103

78