Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64230942

1

T5

5164

T6

4700

T7

2594

auto[1]

271690

1

T26

78

T1

616

T19

820

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64212322

1

T5

5164

T6

4700

T7

2594

auto[1]

290310

1

T26

60

T27

98

T1

574

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

64133850

1

T5

5164

T6

4700

T7

2594

auto[1]

368782

1

T26

68

T27

144

T1

502

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

63069310

1

T5

5164

T6

4700

T7

2594

auto[1]

1433322

1

T26

1662

T27

380

T1

2788

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45742512

1

T5

4828

T6

1512

T7

2566

auto[1]

18760120

1

T5

336

T6

3188

T7

28

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

44365714

1

T5

4828

T6

1512

T7

2566

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18424226

1

T5

336

T6

3188

T7

28

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

20124

1

T1

22

T19

104

T33

48

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5116

1

T26

20

T33

20

T11

138

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

938040

1

T26

1654

T27

184

T1

2138

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

258596

1

T27

118

T19

1802

T32

260

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

32644

1

T1

176

T19

132

T32

26

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7462

1

T19

26

T32

8

T11

130

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46348

1

T27

22

T1

6

T33

48

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

864

1

T33

2

T103

14

T193

64

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8214

1

T1

56

T33

158

T103

58

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3016

1

T33

62

T103

98

T31

44

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

6520

1

T1

98

T19

40

T32

22

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1568

1

T19

18

T105

8

T194

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12358

1

T19

150

T32

50

T33

188

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3040

1

T19

72

T105

60

T194

56

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

58354

1

T1

12

T19

20

T32

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3644

1

T27

12

T33

42

T11

52

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22722

1

T1

76

T19

74

T33

40

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5384

1

T11

84

T101

54

T103

108

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20664

1

T26

8

T27

22

T19

10

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5076

1

T27

34

T33

24

T11

20

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35948

1

T19

52

T32

194

T33

180

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8608

1

T33

54

T11

42

T101

120

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57960

1

T27

54

T1

38

T19

14

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4270

1

T26

2

T33

34

T11

80

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

35068

1

T19

68

T33

338

T11

110

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

8286

1

T26

58

T33

64

T11

124

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

31486

1

T27

22

T1

90

T19

32

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7612

1

T32

22

T33

2

T11

150

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

50348

1

T1

286

T19

142

T32

90

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13352

1

T32

52

T33

46

T11

312