Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76458540 1 T4 1608 T5 3334 T6 1106
auto[1] 299496 1 T6 66 T21 420 T1 4492


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76411070 1 T4 1608 T5 3334 T6 1172
auto[1] 346966 1 T21 478 T1 2806 T16 458


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76384308 1 T4 1608 T5 3334 T6 1092
auto[1] 373728 1 T6 80 T21 706 T1 4586


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 75281486 1 T4 1608 T5 3334 T6 54
auto[1] 1476550 1 T6 1118 T21 814 T1 13550


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55039754 1 T4 70 T5 410 T6 1172
auto[1] 21718282 1 T4 1538 T5 2924 T21 2076


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 53538410 1 T4 70 T5 410 T6 54
auto[0] auto[0] auto[0] auto[0] auto[1] 21455290 1 T4 1538 T5 2924 T21 1806
auto[0] auto[0] auto[0] auto[1] auto[0] 22424 1 T21 28 T1 448 T16 108
auto[0] auto[0] auto[0] auto[1] auto[1] 5686 1 T1 24 T11 160 T107 58
auto[0] auto[0] auto[1] auto[0] auto[0] 1028334 1 T6 1038 T21 316 T1 7716
auto[0] auto[0] auto[1] auto[0] auto[1] 185272 1 T21 124 T1 986 T3 2908
auto[0] auto[0] auto[1] auto[1] auto[0] 39830 1 T21 48 T1 658 T16 112
auto[0] auto[0] auto[1] auto[1] auto[1] 8928 1 T1 404 T3 140 T10 12
auto[0] auto[1] auto[0] auto[0] auto[0] 59044 1 T21 34 T1 112 T11 274
auto[0] auto[1] auto[0] auto[0] auto[1] 970 1 T1 64 T106 10 T107 16
auto[0] auto[1] auto[0] auto[1] auto[0] 9480 1 T11 164 T106 62 T14 182
auto[0] auto[1] auto[0] auto[1] auto[1] 1692 1 T106 90 T107 74 T158 50
auto[0] auto[1] auto[1] auto[0] auto[0] 8866 1 T1 76 T16 58 T3 32
auto[0] auto[1] auto[1] auto[0] auto[1] 1694 1 T1 26 T3 48 T11 44
auto[0] auto[1] auto[1] auto[1] auto[0] 15802 1 T1 124 T16 66 T3 178
auto[0] auto[1] auto[1] auto[1] auto[1] 2586 1 T1 72 T14 86 T159 48
auto[1] auto[0] auto[0] auto[0] auto[0] 21580 1 T21 82 T1 134 T3 48
auto[1] auto[0] auto[0] auto[0] auto[1] 3298 1 T21 108 T11 38 T107 22
auto[1] auto[0] auto[0] auto[1] auto[0] 25380 1 T21 72 T1 192 T3 180
auto[1] auto[0] auto[0] auto[1] auto[1] 5280 1 T11 130 T107 154 T15 50
auto[1] auto[0] auto[1] auto[0] auto[0] 20714 1 T6 14 T1 582 T16 38
auto[1] auto[0] auto[1] auto[0] auto[1] 4946 1 T1 268 T3 92 T10 38
auto[1] auto[0] auto[1] auto[1] auto[0] 37644 1 T6 66 T1 704 T16 66
auto[1] auto[0] auto[1] auto[1] auto[1] 8054 1 T1 374 T3 68 T11 282
auto[1] auto[1] auto[0] auto[0] auto[0] 83026 1 T21 54 T1 226 T16 26
auto[1] auto[1] auto[0] auto[0] auto[1] 4234 1 T1 48 T16 24 T11 54
auto[1] auto[1] auto[0] auto[1] auto[0] 37130 1 T21 64 T1 434 T16 152
auto[1] auto[1] auto[0] auto[1] auto[1] 8562 1 T1 64 T11 74 T107 84
auto[1] auto[1] auto[1] auto[0] auto[0] 34450 1 T21 80 T1 484 T16 10
auto[1] auto[1] auto[1] auto[0] auto[1] 8412 1 T21 38 T1 82 T3 2
auto[1] auto[1] auto[1] auto[1] auto[0] 57640 1 T21 208 T1 810 T16 122
auto[1] auto[1] auto[1] auto[1] auto[1] 13378 1 T1 184 T3 66 T10 62

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