Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74140818 1 T4 2552 T5 2000 T6 2944
auto[1] 248926 1 T4 244 T34 576 T35 466


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74137368 1 T4 2674 T5 2000 T6 2944
auto[1] 252376 1 T4 122 T34 288 T35 394


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74061568 1 T4 2524 T5 2000 T6 2944
auto[1] 328176 1 T4 272 T34 564 T35 454


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72501138 1 T4 1952 T5 2000 T6 2944
auto[1] 1888606 1 T4 844 T35 2944 T36 2014


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 52423540 1 T4 2796 T5 2000 T6 464
auto[1] 21966204 1 T6 2480 T32 2546 T34 368


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 50940308 1 T4 1940 T5 2000 T6 464
auto[0] auto[0] auto[0] auto[0] auto[1] 21319624 1 T6 2480 T32 2546 T34 202
auto[0] auto[0] auto[0] auto[1] auto[0] 16678 1 T34 164 T36 16 T22 114
auto[0] auto[0] auto[0] auto[1] auto[1] 5524 1 T34 78 T103 56 T130 36
auto[0] auto[0] auto[1] auto[0] auto[0] 1098186 1 T4 550 T35 1952 T36 230
auto[0] auto[0] auto[1] auto[0] auto[1] 572660 1 T35 298 T36 1422 T37 1800
auto[0] auto[0] auto[1] auto[1] auto[0] 30962 1 T4 34 T35 64 T36 50
auto[0] auto[0] auto[1] auto[1] auto[1] 8370 1 T35 28 T36 70 T37 16
auto[0] auto[1] auto[0] auto[0] auto[0] 34856 1 T36 8 T37 42 T12 2468
auto[0] auto[1] auto[0] auto[0] auto[1] 1104 1 T104 4 T204 12 T175 6
auto[0] auto[1] auto[0] auto[1] auto[0] 7940 1 T205 74 T178 266 T206 74
auto[0] auto[1] auto[0] auto[1] auto[1] 2592 1 T104 116 T204 54 T175 46
auto[0] auto[1] auto[1] auto[0] auto[0] 6408 1 T35 26 T37 102 T22 26
auto[0] auto[1] auto[1] auto[0] auto[1] 1578 1 T35 30 T37 44 T130 16
auto[0] auto[1] auto[1] auto[1] auto[0] 11900 1 T22 126 T27 48 T182 52
auto[0] auto[1] auto[1] auto[1] auto[1] 2878 1 T35 116 T130 100 T46 50
auto[1] auto[0] auto[0] auto[0] auto[0] 58930 1 T4 12 T34 138 T36 16
auto[1] auto[0] auto[0] auto[0] auto[1] 1990 1 T36 18 T37 44 T177 24
auto[1] auto[0] auto[0] auto[1] auto[0] 19222 1 T34 138 T36 156 T22 54
auto[1] auto[0] auto[0] auto[1] auto[1] 3666 1 T177 82 T183 62 T46 46
auto[1] auto[0] auto[1] auto[0] auto[0] 16850 1 T4 30 T35 60 T37 192
auto[1] auto[0] auto[1] auto[0] auto[1] 4498 1 T36 4 T37 108 T22 12
auto[1] auto[0] auto[1] auto[1] auto[0] 30876 1 T4 108 T35 172 T22 52
auto[1] auto[0] auto[1] auto[1] auto[1] 9024 1 T36 114 T37 84 T22 60
auto[1] auto[1] auto[0] auto[0] auto[0] 45484 1 T34 70 T35 24 T36 20
auto[1] auto[1] auto[0] auto[0] auto[1] 4462 1 T34 22 T22 32 T130 22
auto[1] auto[1] auto[0] auto[1] auto[0] 29598 1 T34 130 T36 92 T22 48
auto[1] auto[1] auto[0] auto[1] auto[1] 9160 1 T34 66 T130 166 T204 64
auto[1] auto[1] auto[1] auto[0] auto[0] 27002 1 T4 20 T35 80 T36 10
auto[1] auto[1] auto[1] auto[0] auto[1] 6878 1 T35 32 T36 8 T37 44
auto[1] auto[1] auto[1] auto[1] auto[0] 48340 1 T4 102 T35 86 T36 106
auto[1] auto[1] auto[1] auto[1] auto[1] 12196 1 T22 72 T103 54 T130 80

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