Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

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Summary for Group clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
idle_cnt_cp	2	0	2	100.00	100	1	1	2
reg_integ_cp	2	0	2	100.00	100	1	1	2
shadow_storage_cp	2	0	2	100.00	100	1	1	2

Summary for Variable idle_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for idle_cnt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2726

1

T4

1

T5

1

T6

1

auto[1]

240

1

T53

40

T60

40

T61

40

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Summary for Variable reg_integ_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for reg_integ_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2606

1

T4

1

T5

1

T6

1

auto[1]

360

1

T53

10

T60

10

T61

10

---

Summary for Variable shadow_storage_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for shadow_storage_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2588

1

T4

1

T5

1

T6

1

auto[1]

378

1

T71

16

T72

9

T73

15