|  |  |  |  |  |  |  |     
    
| u_alert_test_fatal_fault | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_alert_test_recov_fault | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_chk | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
100.00 | 
    
    
| u_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_tlul_data_integ_dec | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_data_chk | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_clk_enables_clk_io_div2_peri_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_enables_clk_io_div4_peri_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_enables_clk_io_peri_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_enables_clk_usb_peri_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_hints_clk_main_aes_hint | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_hints_clk_main_hmac_hint | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_hints_clk_main_kmac_hint | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_clk_hints_clk_main_otbn_hint | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
u_clk_hints_status_clk_main_aes_val  | 
 92.59 | 
 77.78 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
u_clk_hints_status_clk_main_hmac_val  | 
 92.59 | 
 77.78 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
u_clk_hints_status_clk_main_kmac_val  | 
 92.59 | 
 77.78 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
u_clk_hints_status_clk_main_otbn_val  | 
 92.59 | 
 77.78 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_extclk_ctrl_hi_speed_sel | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_extclk_ctrl_regwen | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_extclk_ctrl_sel | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_extclk_status | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_fatal_err_code_idle_cnt | 
 96.30 | 
 88.89 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_fatal_err_code_reg_intg | 
 96.30 | 
 88.89 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_fatal_err_code_shadow_storage_err | 
 96.30 | 
 88.89 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 50.00 | 
 50.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_io_div2_meas_ctrl_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_en_cdc | 
 89.66 | 
 96.24 | 
 80.88 | 
 | 
 | 
 91.53 | 
 90.00 | 
    
    
u_arb  | 
 83.59 | 
 94.90 | 
 76.09 | 
 | 
 | 
 88.37 | 
 75.00 | 
    
    
gen_wr_req.u_dst_update_sync  | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_cdc | 
 98.39 | 
100.00 | 
 93.55 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_arb | 
 97.73 | 
100.00 | 
 90.91 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_passthru.u_dst_to_src_ack | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_hi | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_hi_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_lo | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div2_meas_ctrl_shadowed_lo_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_en_cdc | 
 92.36 | 
 97.74 | 
 86.76 | 
 | 
 | 
 94.92 | 
 90.00 | 
    
    
u_arb  | 
 87.44 | 
 96.94 | 
 84.78 | 
 | 
 | 
 93.02 | 
 75.00 | 
    
    
gen_wr_req.u_dst_update_sync  | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_cdc | 
 98.39 | 
100.00 | 
 93.55 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_arb | 
 97.73 | 
100.00 | 
 90.91 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_passthru.u_dst_to_src_ack | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_hi | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_hi_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_lo | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_div4_meas_ctrl_shadowed_lo_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_en_cdc | 
 89.66 | 
 96.24 | 
 80.88 | 
 | 
 | 
 91.53 | 
 90.00 | 
    
    
u_arb  | 
 83.59 | 
 94.90 | 
 76.09 | 
 | 
 | 
 88.37 | 
 75.00 | 
    
    
gen_wr_req.u_dst_update_sync  | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_cdc | 
 98.39 | 
100.00 | 
 93.55 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_arb | 
 97.73 | 
100.00 | 
 90.91 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_passthru.u_dst_to_src_ack | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_hi | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_hi_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_hi_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_lo | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_lo_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_io_meas_ctrl_shadowed_lo_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_jitter_enable | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_jitter_regwen | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_main_meas_ctrl_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_en_cdc | 
 89.66 | 
 96.24 | 
 80.88 | 
 | 
 | 
 91.53 | 
 90.00 | 
    
    
u_arb  | 
 83.59 | 
 94.90 | 
 76.09 | 
 | 
 | 
 88.37 | 
 75.00 | 
    
    
gen_wr_req.u_dst_update_sync  | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_cdc | 
 98.39 | 
100.00 | 
 93.55 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_arb | 
 97.73 | 
100.00 | 
 90.91 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_passthru.u_dst_to_src_ack | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_hi | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_hi_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_hi_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_lo | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_lo_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_main_meas_ctrl_shadowed_lo_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_measure_ctrl_regwen | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_reg_we_check | 
100.00 | 
100.00 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_prim_buf | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_prim_onehot_check | 
100.00 | 
 | 
 | 
100.00 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_div2_measure_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_div2_timeout_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_div4_measure_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_div4_timeout_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_measure_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_io_timeout_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_main_measure_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_main_timeout_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_shadow_update_err | 
 97.22 | 
100.00 | 
 91.67 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
 95.00 | 
100.00 | 
 90.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_usb_measure_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
| u_recov_err_code_usb_timeout_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
    
    
u_reg_if  | 
 98.98 | 
 97.14 | 
 98.80 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_err | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_rsp_intg_gen | 
 83.33 | 
 66.67 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| u_rsp_intg_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
100.00 | 
    
    
| gen_data_intg.u_tlul_data_integ_enc | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_data_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| gen_rsp_intg.u_rsp_gen | 
100.00 | 
100.00 | 
 | 
 | 
 | 
 | 
 | 
    
    
| u_usb_meas_ctrl_en | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_en_cdc | 
 89.66 | 
 96.24 | 
 80.88 | 
 | 
 | 
 91.53 | 
 90.00 | 
    
    
u_arb  | 
 83.59 | 
 94.90 | 
 76.09 | 
 | 
 | 
 88.37 | 
 75.00 | 
    
    
gen_wr_req.u_dst_update_sync  | 
 93.75 | 
100.00 | 
 75.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_nrz_hs_protocol.ack_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_nrz_hs_protocol.req_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_cdc | 
 98.39 | 
100.00 | 
 93.55 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| u_arb | 
 97.73 | 
100.00 | 
 90.91 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| gen_passthru.u_dst_to_src_ack | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_src_to_dst_req | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_hi | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_hi_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_hi_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_lo | 
 99.55 | 
100.00 | 
 98.21 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| committed_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| shadow_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| staged_reg | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| wr_en_data_arb | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_lo_err_storage_sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_usb_meas_ctrl_shadowed_lo_err_update_sync | 
100.00 | 
100.00 | 
100.00 | 
 | 
 | 
100.00 | 
100.00 | 
    
    
| prim_flop_2sync | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_1 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| u_sync_2 | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 | 
    
    
| gen_generic.u_impl_generic | 
100.00 | 
100.00 | 
 | 
 | 
 | 
100.00 | 
 |