Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73037890 1 T4 4548 T5 3650 T6 1660
auto[1] 264828 1 T5 1160 T30 666 T31 216


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73013556 1 T4 4548 T5 3762 T6 1660
auto[1] 289162 1 T5 1048 T30 400 T31 368


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72969366 1 T4 4548 T5 3462 T6 1660
auto[1] 333352 1 T5 1348 T30 586 T31 510


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 71785576 1 T4 4548 T5 3002 T6 1660
auto[1] 1517142 1 T5 1808 T30 142 T31 1326


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 54678086 1 T4 4520 T5 2566 T6 80
auto[1] 18624632 1 T4 28 T5 2244 T6 1580


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 53112860 1 T4 4520 T5 834 T6 80
auto[0] auto[0] auto[0] auto[0] auto[1] 18406856 1 T4 28 T5 1394 T6 1580
auto[0] auto[0] auto[0] auto[1] auto[0] 19916 1 T5 42 T30 72 T31 12
auto[0] auto[0] auto[0] auto[1] auto[1] 4326 1 T30 70 T51 34 T69 20
auto[0] auto[0] auto[1] auto[0] auto[0] 1140406 1 T5 554 T30 88 T31 738
auto[0] auto[0] auto[1] auto[0] auto[1] 143444 1 T5 362 T31 206 T51 1226
auto[0] auto[0] auto[1] auto[1] auto[0] 32208 1 T5 58 T31 32 T33 86
auto[0] auto[0] auto[1] auto[1] auto[1] 8576 1 T5 20 T51 8 T52 4
auto[0] auto[1] auto[0] auto[0] auto[0] 67850 1 T31 58 T2 4224 T73 8
auto[0] auto[1] auto[0] auto[0] auto[1] 1204 1 T5 104 T30 34 T95 8
auto[0] auto[1] auto[0] auto[1] auto[0] 7818 1 T27 68 T196 50 T95 114
auto[0] auto[1] auto[0] auto[1] auto[1] 1624 1 T30 118 T95 60 T197 90
auto[0] auto[1] auto[1] auto[0] auto[0] 6480 1 T5 18 T31 30 T51 8
auto[0] auto[1] auto[1] auto[0] auto[1] 1582 1 T44 2 T172 28 T106 14
auto[0] auto[1] auto[1] auto[1] auto[0] 11296 1 T5 76 T51 54 T70 62
auto[0] auto[1] auto[1] auto[1] auto[1] 2920 1 T44 62 T106 44 T108 42
auto[1] auto[0] auto[0] auto[0] auto[0] 47900 1 T5 62 T30 34 T31 86
auto[1] auto[0] auto[0] auto[0] auto[1] 2940 1 T30 78 T51 32 T69 18
auto[1] auto[0] auto[0] auto[1] auto[0] 21672 1 T5 214 T30 120 T51 60
auto[1] auto[0] auto[0] auto[1] auto[1] 5754 1 T30 106 T51 172 T69 66
auto[1] auto[0] auto[1] auto[0] auto[0] 18336 1 T5 50 T31 70 T51 238
auto[1] auto[0] auto[1] auto[0] auto[1] 5328 1 T5 18 T23 56 T43 30
auto[1] auto[0] auto[1] auto[1] auto[0] 34678 1 T31 74 T51 272 T70 150
auto[1] auto[0] auto[1] auto[1] auto[1] 8356 1 T5 154 T23 58 T49 64
auto[1] auto[1] auto[0] auto[0] auto[0] 41892 1 T5 126 T30 64 T31 40
auto[1] auto[1] auto[0] auto[0] auto[1] 3582 1 T31 12 T51 22 T69 28
auto[1] auto[1] auto[0] auto[1] auto[0] 32316 1 T5 226 T30 130 T31 52
auto[1] auto[1] auto[0] auto[1] auto[1] 7066 1 T51 66 T69 82 T73 60
auto[1] auto[1] auto[1] auto[0] auto[0] 29988 1 T5 112 T30 4 T31 82
auto[1] auto[1] auto[1] auto[0] auto[1] 7242 1 T5 16 T31 48 T51 10
auto[1] auto[1] auto[1] auto[1] auto[0] 52470 1 T5 194 T30 50 T33 62
auto[1] auto[1] auto[1] auto[1] auto[1] 13832 1 T5 176 T31 46 T51 90

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