Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 71345468 1 T4 2028 T5 3302 T6 2044
auto[1] 255456 1 T4 516 T31 974 T32 252


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 71282918 1 T4 2312 T5 3302 T6 2044
auto[1] 318006 1 T4 232 T28 20 T31 840


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 71227110 1 T4 2066 T5 3302 T6 2044
auto[1] 373814 1 T4 478 T28 20 T31 972


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 70070070 1 T4 1490 T5 3302 T6 2044
auto[1] 1530854 1 T4 1054 T31 330 T32 2652


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 50953578 1 T4 2118 T5 3280 T6 1644
auto[1] 20647346 1 T4 426 T5 22 T6 400


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 49326538 1 T4 1348 T5 3280 T6 1644
auto[0] auto[0] auto[0] auto[0] auto[1] 20443596 1 T5 22 T6 400 T28 92
auto[0] auto[0] auto[0] auto[1] auto[0] 20842 1 T4 18 T31 156 T34 108
auto[0] auto[0] auto[0] auto[1] auto[1] 5374 1 T31 112 T134 32 T155 14
auto[0] auto[0] auto[1] auto[0] auto[0] 1179438 1 T4 398 T31 82 T32 2356
auto[0] auto[0] auto[1] auto[0] auto[1] 132320 1 T4 216 T31 104 T134 102
auto[0] auto[0] auto[1] auto[1] auto[0] 29644 1 T4 40 T31 12 T32 24
auto[0] auto[0] auto[1] auto[1] auto[1] 7770 1 T4 46 T153 6 T97 8
auto[0] auto[1] auto[0] auto[0] auto[0] 49314 1 T154 12 T155 22 T156 10
auto[0] auto[1] auto[0] auto[0] auto[1] 752 1 T31 36 T93 2 T20 38
auto[0] auto[1] auto[0] auto[1] auto[0] 5968 1 T154 46 T156 60 T179 92
auto[0] auto[1] auto[0] auto[1] auto[1] 2374 1 T93 38 T203 56 T204 40
auto[0] auto[1] auto[1] auto[0] auto[0] 6730 1 T34 10 T153 36 T154 2
auto[0] auto[1] auto[1] auto[0] auto[1] 1678 1 T153 10 T180 4 T181 20
auto[0] auto[1] auto[1] auto[1] auto[0] 11458 1 T34 44 T153 76 T154 60
auto[0] auto[1] auto[1] auto[1] auto[1] 3314 1 T153 42 T180 96 T181 76
auto[1] auto[0] auto[0] auto[0] auto[0] 43668 1 T4 24 T31 64 T34 6
auto[1] auto[0] auto[0] auto[0] auto[1] 2334 1 T31 24 T32 36 T134 20
auto[1] auto[0] auto[0] auto[1] auto[0] 21652 1 T4 100 T31 80 T34 36
auto[1] auto[0] auto[0] auto[1] auto[1] 4440 1 T134 64 T20 70 T182 84
auto[1] auto[0] auto[1] auto[0] auto[0] 19392 1 T4 4 T32 42 T34 30
auto[1] auto[0] auto[1] auto[0] auto[1] 4496 1 T4 2 T154 24 T155 8
auto[1] auto[0] auto[1] auto[1] auto[0] 34004 1 T4 50 T32 42 T34 268
auto[1] auto[0] auto[1] auto[1] auto[1] 7410 1 T4 66 T20 66 T70 48
auto[1] auto[1] auto[0] auto[0] auto[0] 97106 1 T28 20 T31 74 T32 14
auto[1] auto[1] auto[0] auto[0] auto[1] 4220 1 T31 76 T134 26 T154 34
auto[1] auto[1] auto[0] auto[1] auto[0] 33788 1 T31 328 T32 66 T34 44
auto[1] auto[1] auto[0] auto[1] auto[1] 8104 1 T31 194 T134 168 T155 66
auto[1] auto[1] auto[1] auto[0] auto[0] 26898 1 T4 32 T31 10 T32 68
auto[1] auto[1] auto[1] auto[0] auto[1] 6988 1 T4 4 T31 30 T134 26
auto[1] auto[1] auto[1] auto[1] auto[0] 47138 1 T4 104 T31 92 T32 120
auto[1] auto[1] auto[1] auto[1] auto[1] 12176 1 T4 92 T20 76 T97 80

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