Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69501022

1

T4

2794

T5

4586

T6

2790

auto[1]

235094

1

T4

286

T6

452

T26

284

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69430138

1

T4

2966

T5

4586

T6

3044

auto[1]

305978

1

T4

114

T6

198

T24

54

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69395780

1

T4

2780

T5

4586

T6

2780

auto[1]

340336

1

T4

300

T6

462

T24

82

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68681284

1

T4

208

T5

4586

T6

2554

auto[1]

1054832

1

T4

2872

T6

688

T24

222

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47832498

1

T4

3060

T5

4586

T6

2880

auto[1]

21903618

1

T4

20

T6

362

T24

18

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

46715028

1

T4

100

T5

4586

T6

2224

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

21677302

1

T4

20

T6

82

T24

18

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

19348

1

T4

26

T6

30

T101

94

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3948

1

T6

14

T101

32

T172

34

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

690302

1

T4

2626

T6

282

T24

182

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

163558

1

T6

104

T26

84

T101

476

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

28972

1

T4

8

T6

28

T26

10

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6668

1

T6

16

T101

20

T102

62

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

62568

1

T26

14

T126

84

T61

16

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

642

1

T172

8

T173

20

T174

20

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

6578

1

T26

56

T126

46

T172

80

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1430

1

T172

64

T173

66

T174

70

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5840

1

T26

4

T101

50

T114

36

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1566

1

T101

16

T102

2

T114

14

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9510

1

T26

64

T114

98

T172

48

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2520

1

T101

96

T102

52

T114

44

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

39532

1

T24

10

T26

20

T55

30

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

3476

1

T6

20

T101

10

T129

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

21262

1

T55

122

T101

78

T102

44

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4390

1

T6

56

T101

80

T175

36

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

15582

1

T4

30

T6

52

T24

18

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4282

1

T101

62

T114

2

T58

36

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

28416

1

T4

156

T6

136

T59

64

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8072

1

T101

66

T114

62

T32

154

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

84876

1

T4

2

T6

12

T24

32

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3486

1

T101

6

T129

28

T172

10

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

31534

1

T4

60

T6

116

T55

54

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5884

1

T101

76

T172

84

T85

70

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

27138

1

T4

16

T24

22

T26

20

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5844

1

T6

14

T26

26

T101

36

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

46012

1

T4

36

T26

110

T101

68

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

10550

1

T6

56

T26

44

T101

82