Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67749102 1 T4 2502 T5 3088 T6 1192
auto[1] 277064 1 T5 766 T34 90 T37 402


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67746078 1 T4 2502 T5 3434 T6 1192
auto[1] 280088 1 T5 420 T32 14 T34 40


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67661242 1 T4 2502 T5 3184 T6 1192
auto[1] 364924 1 T5 670 T33 8 T34 174


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 66340462 1 T4 2502 T5 546 T6 1192
auto[1] 1685704 1 T5 3308 T33 1742 T34 162


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 49259200 1 T4 2386 T5 3832 T6 1192
auto[1] 18766966 1 T4 116 T5 22 T29 1886


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 48014152 1 T4 2386 T5 244 T6 1192
auto[0] auto[0] auto[0] auto[0] auto[1] 18063392 1 T4 116 T5 22 T29 1886
auto[0] auto[0] auto[0] auto[1] auto[0] 20382 1 T5 54 T34 12 T37 8
auto[0] auto[0] auto[0] auto[1] auto[1] 4748 1 T63 34 T26 22 T95 4
auto[0] auto[0] auto[1] auto[0] auto[0] 817728 1 T5 2594 T33 1734 T34 126
auto[0] auto[0] auto[1] auto[0] auto[1] 627368 1 T37 78 T43 182 T62 222
auto[0] auto[0] auto[1] auto[1] auto[0] 34122 1 T5 86 T37 14 T60 34
auto[0] auto[0] auto[1] auto[1] auto[1] 8956 1 T63 14 T94 38 T95 28
auto[0] auto[1] auto[0] auto[0] auto[0] 32386 1 T32 14 T62 38 T63 12
auto[0] auto[1] auto[0] auto[0] auto[1] 1306 1 T61 4 T28 28 T95 22
auto[0] auto[1] auto[0] auto[1] auto[0] 7950 1 T63 54 T94 56 T111 54
auto[0] auto[1] auto[0] auto[1] auto[1] 2332 1 T61 80 T95 46 T111 66
auto[0] auto[1] auto[1] auto[0] auto[0] 8282 1 T5 40 T37 28 T63 44
auto[0] auto[1] auto[1] auto[0] auto[1] 1408 1 T22 36 T150 14 T179 28
auto[0] auto[1] auto[1] auto[1] auto[0] 14410 1 T5 144 T37 112 T26 46
auto[0] auto[1] auto[1] auto[1] auto[1] 2320 1 T179 66 T15 64 T180 48
auto[1] auto[0] auto[0] auto[0] auto[0] 53566 1 T5 36 T34 20 T37 8
auto[1] auto[0] auto[0] auto[0] auto[1] 2330 1 T63 112 T26 10 T95 38
auto[1] auto[0] auto[0] auto[1] auto[0] 25410 1 T5 160 T34 78 T37 54
auto[1] auto[0] auto[0] auto[1] auto[1] 4694 1 T63 146 T26 72 T151 44
auto[1] auto[0] auto[1] auto[0] auto[0] 18486 1 T5 46 T33 8 T34 36
auto[1] auto[0] auto[1] auto[0] auto[1] 5070 1 T43 24 T27 8 T95 46
auto[1] auto[0] auto[1] auto[1] auto[0] 36920 1 T5 192 T60 56 T63 350
auto[1] auto[0] auto[1] auto[1] auto[1] 8754 1 T95 68 T181 86 T182 66
auto[1] auto[1] auto[0] auto[0] auto[0] 63204 1 T5 30 T34 40 T37 84
auto[1] auto[1] auto[0] auto[0] auto[1] 3722 1 T22 32 T94 30 T11 8
auto[1] auto[1] auto[0] auto[1] auto[0] 33132 1 T37 214 T43 66 T61 142
auto[1] auto[1] auto[0] auto[1] auto[1] 7756 1 T11 54 T151 164 T111 56
auto[1] auto[1] auto[1] auto[0] auto[0] 28274 1 T5 76 T37 22 T43 38
auto[1] auto[1] auto[1] auto[0] auto[1] 8428 1 T37 42 T43 12 T62 34
auto[1] auto[1] auto[1] auto[1] auto[0] 50796 1 T5 130 T63 222 T22 62
auto[1] auto[1] auto[1] auto[1] auto[1] 14382 1 T43 82 T63 150 T27 44

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