Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73106636 1 T4 1736 T5 1594 T6 3064
auto[1] 248656 1 T5 284 T33 1088 T34 490


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73063262 1 T4 1736 T5 1796 T6 3064
auto[1] 292030 1 T5 82 T32 8 T33 936


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73019766 1 T4 1736 T5 1604 T6 3064
auto[1] 335526 1 T5 274 T32 16 T33 1198


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72103168 1 T4 1736 T5 182 T6 3064
auto[1] 1252124 1 T5 1696 T32 1690 T33 178


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 52002176 1 T4 1720 T5 1686 T6 3064
auto[1] 21353116 1 T4 16 T5 192 T30 692


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 50834394 1 T4 1720 T5 170 T6 3064
auto[0] auto[0] auto[0] auto[0] auto[1] 21000862 1 T4 16 T30 692 T31 1008
auto[0] auto[0] auto[0] auto[1] auto[0] 19148 1 T33 164 T34 34 T57 18
auto[0] auto[0] auto[0] auto[1] auto[1] 4892 1 T33 80 T35 20 T63 20
auto[0] auto[0] auto[1] auto[0] auto[0] 751310 1 T5 1254 T32 1682 T33 76
auto[0] auto[0] auto[1] auto[0] auto[1] 282670 1 T5 94 T34 66 T83 150
auto[0] auto[0] auto[1] auto[1] auto[0] 33112 1 T5 46 T33 12 T34 26
auto[0] auto[0] auto[1] auto[1] auto[1] 6806 1 T5 20 T34 22 T64 2
auto[0] auto[1] auto[0] auto[0] auto[0] 51792 1 T33 112 T34 20 T58 70
auto[0] auto[1] auto[0] auto[0] auto[1] 1184 1 T203 36 T204 2 T12 4
auto[0] auto[1] auto[0] auto[1] auto[0] 8338 1 T34 64 T58 300 T63 48
auto[0] auto[1] auto[0] auto[1] auto[1] 2282 1 T204 40 T12 62 T205 122
auto[0] auto[1] auto[1] auto[0] auto[0] 6978 1 T5 20 T34 18 T83 8
auto[0] auto[1] auto[1] auto[0] auto[1] 1414 1 T206 24 T207 8 T74 48
auto[0] auto[1] auto[1] auto[1] auto[0] 11684 1 T34 66 T64 64 T74 60
auto[0] auto[1] auto[1] auto[1] auto[1] 2900 1 T206 52 T131 72 T208 100
auto[1] auto[0] auto[0] auto[0] auto[0] 39186 1 T33 62 T9 832 T58 86
auto[1] auto[0] auto[0] auto[0] auto[1] 2444 1 T33 38 T57 4 T65 26
auto[1] auto[0] auto[0] auto[1] auto[0] 19372 1 T33 184 T58 126 T62 50
auto[1] auto[0] auto[0] auto[1] auto[1] 5478 1 T57 36 T65 50 T122 136
auto[1] auto[0] auto[1] auto[0] auto[0] 19236 1 T5 16 T32 8 T33 10
auto[1] auto[0] auto[1] auto[0] auto[1] 5360 1 T5 18 T83 8 T62 54
auto[1] auto[0] auto[1] auto[1] auto[0] 31478 1 T5 118 T33 80 T57 84
auto[1] auto[0] auto[1] auto[1] auto[1] 7514 1 T5 60 T64 104 T203 52
auto[1] auto[1] auto[0] auto[0] auto[0] 71406 1 T5 12 T32 8 T33 228
auto[1] auto[1] auto[0] auto[0] auto[1] 4090 1 T33 28 T35 22 T58 36
auto[1] auto[1] auto[0] auto[1] auto[0] 31068 1 T33 354 T34 52 T57 74
auto[1] auto[1] auto[0] auto[1] auto[1] 7232 1 T33 214 T35 80 T63 46
auto[1] auto[1] auto[1] auto[0] auto[0] 26626 1 T5 10 T34 96 T35 22
auto[1] auto[1] auto[1] auto[0] auto[1] 7684 1 T34 20 T83 20 T65 22
auto[1] auto[1] auto[1] auto[1] auto[0] 47048 1 T5 40 T34 154 T35 88
auto[1] auto[1] auto[1] auto[1] auto[1] 10304 1 T34 72 T65 42 T12 116

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