Go
back
81 always_ff @(posedge clk_i or negedge rst_ni) begin
82 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
83 1/1 err_q <= '0;
Tests: T4 T5 T6
84 1/1 end else if (intg_err || reg_we_err) begin
Tests: T4 T5 T6
85 1/1 err_q <= 1'b1;
Tests: T69 T20 T71
86 end
MISSING_ELSE
87 end
88
89 // integrity error output is permanent and should be used for alert generation
90 // register errors are transactional
91 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T4 T5 T29
92
93 // outgoing integrity generation
94 tlul_pkg::tl_d2h_t tl_o_pre;
95 tlul_rsp_intg_gen #(
96 .EnableRspIntgGen(1),
97 .EnableDataIntgGen(1)
98 ) u_rsp_intg_gen (
99 .tl_i(tl_o_pre),
100 .tl_o(tl_o)
101 );
102
103 1/1 assign tl_reg_h2d = tl_i;
Tests: T4 T5 T6
104 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T4 T5 T29
105
106 tlul_adapter_reg #(
107 .RegAw(AW),
108 .RegDw(DW),
109 .EnableDataIntgGen(0)
110 ) u_reg_if (
111 .clk_i (clk_i),
112 .rst_ni (rst_ni),
113
114 .tl_i (tl_reg_h2d),
115 .tl_o (tl_reg_d2h),
116
117 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
118 .intg_error_o(),
119
120 .we_o (reg_we),
121 .re_o (reg_re),
122 .addr_o (reg_addr),
123 .wdata_o (reg_wdata),
124 .be_o (reg_be),
125 .busy_i (reg_busy),
126 .rdata_i (reg_rdata),
127 .error_i (reg_error)
128 );
129
130 // cdc oversampling signals
131
132 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T4 T5 T29
133 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T4 T29 T30
134
135 // Define SW related signals
136 // Format: <reg>_<field>_{wd|we|qs}
137 // or <reg>_{wd|we|qs} if field == 1 or 0
138 logic alert_test_we;
139 logic alert_test_recov_fault_wd;
140 logic alert_test_fatal_fault_wd;
141 logic extclk_ctrl_regwen_we;
142 logic extclk_ctrl_regwen_qs;
143 logic extclk_ctrl_regwen_wd;
144 logic extclk_ctrl_we;
145 logic [3:0] extclk_ctrl_sel_qs;
146 logic [3:0] extclk_ctrl_sel_wd;
147 logic [3:0] extclk_ctrl_hi_speed_sel_qs;
148 logic [3:0] extclk_ctrl_hi_speed_sel_wd;
149 logic extclk_status_re;
150 logic [3:0] extclk_status_qs;
151 logic jitter_regwen_we;
152 logic jitter_regwen_qs;
153 logic jitter_regwen_wd;
154 logic jitter_enable_we;
155 logic [3:0] jitter_enable_qs;
156 logic [3:0] jitter_enable_wd;
157 logic clk_enables_we;
158 logic clk_enables_clk_io_div4_peri_en_qs;
159 logic clk_enables_clk_io_div4_peri_en_wd;
160 logic clk_enables_clk_io_div2_peri_en_qs;
161 logic clk_enables_clk_io_div2_peri_en_wd;
162 logic clk_enables_clk_io_peri_en_qs;
163 logic clk_enables_clk_io_peri_en_wd;
164 logic clk_enables_clk_usb_peri_en_qs;
165 logic clk_enables_clk_usb_peri_en_wd;
166 logic clk_hints_we;
167 logic clk_hints_clk_main_aes_hint_qs;
168 logic clk_hints_clk_main_aes_hint_wd;
169 logic clk_hints_clk_main_hmac_hint_qs;
170 logic clk_hints_clk_main_hmac_hint_wd;
171 logic clk_hints_clk_main_kmac_hint_qs;
172 logic clk_hints_clk_main_kmac_hint_wd;
173 logic clk_hints_clk_main_otbn_hint_qs;
174 logic clk_hints_clk_main_otbn_hint_wd;
175 logic clk_hints_status_clk_main_aes_val_qs;
176 logic clk_hints_status_clk_main_hmac_val_qs;
177 logic clk_hints_status_clk_main_kmac_val_qs;
178 logic clk_hints_status_clk_main_otbn_val_qs;
179 logic measure_ctrl_regwen_we;
180 logic measure_ctrl_regwen_qs;
181 logic measure_ctrl_regwen_wd;
182 logic io_meas_ctrl_en_we;
183 logic [3:0] io_meas_ctrl_en_qs;
184 logic io_meas_ctrl_en_busy;
185 logic io_meas_ctrl_shadowed_re;
186 logic io_meas_ctrl_shadowed_we;
187 logic [19:0] io_meas_ctrl_shadowed_qs;
188 logic io_meas_ctrl_shadowed_busy;
189 logic io_meas_ctrl_shadowed_hi_storage_err;
190 logic io_meas_ctrl_shadowed_hi_update_err;
191 logic io_meas_ctrl_shadowed_lo_storage_err;
192 logic io_meas_ctrl_shadowed_lo_update_err;
193 logic io_div2_meas_ctrl_en_we;
194 logic [3:0] io_div2_meas_ctrl_en_qs;
195 logic io_div2_meas_ctrl_en_busy;
196 logic io_div2_meas_ctrl_shadowed_re;
197 logic io_div2_meas_ctrl_shadowed_we;
198 logic [17:0] io_div2_meas_ctrl_shadowed_qs;
199 logic io_div2_meas_ctrl_shadowed_busy;
200 logic io_div2_meas_ctrl_shadowed_hi_storage_err;
201 logic io_div2_meas_ctrl_shadowed_hi_update_err;
202 logic io_div2_meas_ctrl_shadowed_lo_storage_err;
203 logic io_div2_meas_ctrl_shadowed_lo_update_err;
204 logic io_div4_meas_ctrl_en_we;
205 logic [3:0] io_div4_meas_ctrl_en_qs;
206 logic io_div4_meas_ctrl_en_busy;
207 logic io_div4_meas_ctrl_shadowed_re;
208 logic io_div4_meas_ctrl_shadowed_we;
209 logic [15:0] io_div4_meas_ctrl_shadowed_qs;
210 logic io_div4_meas_ctrl_shadowed_busy;
211 logic io_div4_meas_ctrl_shadowed_hi_storage_err;
212 logic io_div4_meas_ctrl_shadowed_hi_update_err;
213 logic io_div4_meas_ctrl_shadowed_lo_storage_err;
214 logic io_div4_meas_ctrl_shadowed_lo_update_err;
215 logic main_meas_ctrl_en_we;
216 logic [3:0] main_meas_ctrl_en_qs;
217 logic main_meas_ctrl_en_busy;
218 logic main_meas_ctrl_shadowed_re;
219 logic main_meas_ctrl_shadowed_we;
220 logic [19:0] main_meas_ctrl_shadowed_qs;
221 logic main_meas_ctrl_shadowed_busy;
222 logic main_meas_ctrl_shadowed_hi_storage_err;
223 logic main_meas_ctrl_shadowed_hi_update_err;
224 logic main_meas_ctrl_shadowed_lo_storage_err;
225 logic main_meas_ctrl_shadowed_lo_update_err;
226 logic usb_meas_ctrl_en_we;
227 logic [3:0] usb_meas_ctrl_en_qs;
228 logic usb_meas_ctrl_en_busy;
229 logic usb_meas_ctrl_shadowed_re;
230 logic usb_meas_ctrl_shadowed_we;
231 logic [17:0] usb_meas_ctrl_shadowed_qs;
232 logic usb_meas_ctrl_shadowed_busy;
233 logic usb_meas_ctrl_shadowed_hi_storage_err;
234 logic usb_meas_ctrl_shadowed_hi_update_err;
235 logic usb_meas_ctrl_shadowed_lo_storage_err;
236 logic usb_meas_ctrl_shadowed_lo_update_err;
237 logic recov_err_code_we;
238 logic recov_err_code_shadow_update_err_qs;
239 logic recov_err_code_shadow_update_err_wd;
240 logic recov_err_code_io_measure_err_qs;
241 logic recov_err_code_io_measure_err_wd;
242 logic recov_err_code_io_div2_measure_err_qs;
243 logic recov_err_code_io_div2_measure_err_wd;
244 logic recov_err_code_io_div4_measure_err_qs;
245 logic recov_err_code_io_div4_measure_err_wd;
246 logic recov_err_code_main_measure_err_qs;
247 logic recov_err_code_main_measure_err_wd;
248 logic recov_err_code_usb_measure_err_qs;
249 logic recov_err_code_usb_measure_err_wd;
250 logic recov_err_code_io_timeout_err_qs;
251 logic recov_err_code_io_timeout_err_wd;
252 logic recov_err_code_io_div2_timeout_err_qs;
253 logic recov_err_code_io_div2_timeout_err_wd;
254 logic recov_err_code_io_div4_timeout_err_qs;
255 logic recov_err_code_io_div4_timeout_err_wd;
256 logic recov_err_code_main_timeout_err_qs;
257 logic recov_err_code_main_timeout_err_wd;
258 logic recov_err_code_usb_timeout_err_qs;
259 logic recov_err_code_usb_timeout_err_wd;
260 logic fatal_err_code_reg_intg_qs;
261 logic fatal_err_code_idle_cnt_qs;
262 logic fatal_err_code_shadow_storage_err_qs;
263 // Define register CDC handling.
264 // CDC handling is done on a per-reg instead of per-field boundary.
265
266 logic [3:0] io_io_meas_ctrl_en_ds_int;
267 logic [3:0] io_io_meas_ctrl_en_qs_int;
268 logic [3:0] io_io_meas_ctrl_en_ds;
269 logic io_io_meas_ctrl_en_qe;
270 logic [3:0] io_io_meas_ctrl_en_qs;
271 logic [3:0] io_io_meas_ctrl_en_wdata;
272 logic io_io_meas_ctrl_en_we;
273 logic unused_io_io_meas_ctrl_en_wdata;
274 logic io_io_meas_ctrl_en_regwen;
275
276 always_comb begin
277 1/1 io_io_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
278 1/1 io_io_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
279 1/1 io_io_meas_ctrl_en_ds = io_io_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
280 1/1 io_io_meas_ctrl_en_qs = io_io_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
281 end
282
283 prim_reg_cdc #(
284 .DataWidth(4),
285 .ResetVal(4'h9),
286 .BitMask(4'hf),
287 .DstWrReq(1)
288 ) u_io_meas_ctrl_en_cdc (
289 .clk_src_i (clk_i),
290 .rst_src_ni (rst_ni),
291 .clk_dst_i (clk_io_i),
292 .rst_dst_ni (rst_io_ni),
293 .src_regwen_i (measure_ctrl_regwen_qs),
294 .src_we_i (io_meas_ctrl_en_we),
295 .src_re_i ('0),
296 .src_wd_i (reg_wdata[3:0]),
297 .src_busy_o (io_meas_ctrl_en_busy),
298 .src_qs_o (io_meas_ctrl_en_qs), // for software read back
299 .dst_update_i (io_io_meas_ctrl_en_qe),
300 .dst_ds_i (io_io_meas_ctrl_en_ds),
301 .dst_qs_i (io_io_meas_ctrl_en_qs),
302 .dst_we_o (io_io_meas_ctrl_en_we),
303 .dst_re_o (),
304 .dst_regwen_o (io_io_meas_ctrl_en_regwen),
305 .dst_wd_o (io_io_meas_ctrl_en_wdata)
306 );
307 1/1 assign unused_io_io_meas_ctrl_en_wdata =
Tests: T1 T10 T2
308 ^io_io_meas_ctrl_en_wdata;
309
310 logic [9:0] io_io_meas_ctrl_shadowed_hi_qs_int;
311 logic [9:0] io_io_meas_ctrl_shadowed_lo_qs_int;
312 logic [19:0] io_io_meas_ctrl_shadowed_qs;
313 logic [19:0] io_io_meas_ctrl_shadowed_wdata;
314 logic io_io_meas_ctrl_shadowed_we;
315 logic unused_io_io_meas_ctrl_shadowed_wdata;
316 logic io_io_meas_ctrl_shadowed_re;
317 logic io_io_meas_ctrl_shadowed_regwen;
318
319 always_comb begin
320 1/1 io_io_meas_ctrl_shadowed_qs = 20'h759ea;
Tests: T1 T2 T3
321 1/1 io_io_meas_ctrl_shadowed_qs[9:0] = io_io_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
322 1/1 io_io_meas_ctrl_shadowed_qs[19:10] = io_io_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
323 end
324
325 prim_reg_cdc #(
326 .DataWidth(20),
327 .ResetVal(20'h759ea),
328 .BitMask(20'hfffff),
329 .DstWrReq(0)
330 ) u_io_meas_ctrl_shadowed_cdc (
331 .clk_src_i (clk_i),
332 .rst_src_ni (rst_ni),
333 .clk_dst_i (clk_io_i),
334 .rst_dst_ni (rst_io_ni),
335 .src_regwen_i (measure_ctrl_regwen_qs),
336 .src_we_i (io_meas_ctrl_shadowed_we),
337 .src_re_i (io_meas_ctrl_shadowed_re),
338 .src_wd_i (reg_wdata[19:0]),
339 .src_busy_o (io_meas_ctrl_shadowed_busy),
340 .src_qs_o (io_meas_ctrl_shadowed_qs), // for software read back
341 .dst_update_i ('0),
342 .dst_ds_i ('0),
343 .dst_qs_i (io_io_meas_ctrl_shadowed_qs),
344 .dst_we_o (io_io_meas_ctrl_shadowed_we),
345 .dst_re_o (io_io_meas_ctrl_shadowed_re),
346 .dst_regwen_o (io_io_meas_ctrl_shadowed_regwen),
347 .dst_wd_o (io_io_meas_ctrl_shadowed_wdata)
348 );
349 1/1 assign unused_io_io_meas_ctrl_shadowed_wdata =
Tests: T9 T1 T10
350 ^io_io_meas_ctrl_shadowed_wdata;
351
352 logic [3:0] io_div2_io_div2_meas_ctrl_en_ds_int;
353 logic [3:0] io_div2_io_div2_meas_ctrl_en_qs_int;
354 logic [3:0] io_div2_io_div2_meas_ctrl_en_ds;
355 logic io_div2_io_div2_meas_ctrl_en_qe;
356 logic [3:0] io_div2_io_div2_meas_ctrl_en_qs;
357 logic [3:0] io_div2_io_div2_meas_ctrl_en_wdata;
358 logic io_div2_io_div2_meas_ctrl_en_we;
359 logic unused_io_div2_io_div2_meas_ctrl_en_wdata;
360 logic io_div2_io_div2_meas_ctrl_en_regwen;
361
362 always_comb begin
363 1/1 io_div2_io_div2_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
364 1/1 io_div2_io_div2_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
365 1/1 io_div2_io_div2_meas_ctrl_en_ds = io_div2_io_div2_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
366 1/1 io_div2_io_div2_meas_ctrl_en_qs = io_div2_io_div2_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
367 end
368
369 prim_reg_cdc #(
370 .DataWidth(4),
371 .ResetVal(4'h9),
372 .BitMask(4'hf),
373 .DstWrReq(1)
374 ) u_io_div2_meas_ctrl_en_cdc (
375 .clk_src_i (clk_i),
376 .rst_src_ni (rst_ni),
377 .clk_dst_i (clk_io_div2_i),
378 .rst_dst_ni (rst_io_div2_ni),
379 .src_regwen_i (measure_ctrl_regwen_qs),
380 .src_we_i (io_div2_meas_ctrl_en_we),
381 .src_re_i ('0),
382 .src_wd_i (reg_wdata[3:0]),
383 .src_busy_o (io_div2_meas_ctrl_en_busy),
384 .src_qs_o (io_div2_meas_ctrl_en_qs), // for software read back
385 .dst_update_i (io_div2_io_div2_meas_ctrl_en_qe),
386 .dst_ds_i (io_div2_io_div2_meas_ctrl_en_ds),
387 .dst_qs_i (io_div2_io_div2_meas_ctrl_en_qs),
388 .dst_we_o (io_div2_io_div2_meas_ctrl_en_we),
389 .dst_re_o (),
390 .dst_regwen_o (io_div2_io_div2_meas_ctrl_en_regwen),
391 .dst_wd_o (io_div2_io_div2_meas_ctrl_en_wdata)
392 );
393 1/1 assign unused_io_div2_io_div2_meas_ctrl_en_wdata =
Tests: T9 T1 T10
394 ^io_div2_io_div2_meas_ctrl_en_wdata;
395
396 logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
397 logic [8:0] io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
398 logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_qs;
399 logic [17:0] io_div2_io_div2_meas_ctrl_shadowed_wdata;
400 logic io_div2_io_div2_meas_ctrl_shadowed_we;
401 logic unused_io_div2_io_div2_meas_ctrl_shadowed_wdata;
402 logic io_div2_io_div2_meas_ctrl_shadowed_re;
403 logic io_div2_io_div2_meas_ctrl_shadowed_regwen;
404
405 always_comb begin
406 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs = 18'h1ccfa;
Tests: T1 T2 T3
407 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs[8:0] = io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
408 1/1 io_div2_io_div2_meas_ctrl_shadowed_qs[17:9] = io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
409 end
410
411 prim_reg_cdc #(
412 .DataWidth(18),
413 .ResetVal(18'h1ccfa),
414 .BitMask(18'h3ffff),
415 .DstWrReq(0)
416 ) u_io_div2_meas_ctrl_shadowed_cdc (
417 .clk_src_i (clk_i),
418 .rst_src_ni (rst_ni),
419 .clk_dst_i (clk_io_div2_i),
420 .rst_dst_ni (rst_io_div2_ni),
421 .src_regwen_i (measure_ctrl_regwen_qs),
422 .src_we_i (io_div2_meas_ctrl_shadowed_we),
423 .src_re_i (io_div2_meas_ctrl_shadowed_re),
424 .src_wd_i (reg_wdata[17:0]),
425 .src_busy_o (io_div2_meas_ctrl_shadowed_busy),
426 .src_qs_o (io_div2_meas_ctrl_shadowed_qs), // for software read back
427 .dst_update_i ('0),
428 .dst_ds_i ('0),
429 .dst_qs_i (io_div2_io_div2_meas_ctrl_shadowed_qs),
430 .dst_we_o (io_div2_io_div2_meas_ctrl_shadowed_we),
431 .dst_re_o (io_div2_io_div2_meas_ctrl_shadowed_re),
432 .dst_regwen_o (io_div2_io_div2_meas_ctrl_shadowed_regwen),
433 .dst_wd_o (io_div2_io_div2_meas_ctrl_shadowed_wdata)
434 );
435 1/1 assign unused_io_div2_io_div2_meas_ctrl_shadowed_wdata =
Tests: T9 T1 T10
436 ^io_div2_io_div2_meas_ctrl_shadowed_wdata;
437
438 logic [3:0] io_div4_io_div4_meas_ctrl_en_ds_int;
439 logic [3:0] io_div4_io_div4_meas_ctrl_en_qs_int;
440 logic [3:0] io_div4_io_div4_meas_ctrl_en_ds;
441 logic io_div4_io_div4_meas_ctrl_en_qe;
442 logic [3:0] io_div4_io_div4_meas_ctrl_en_qs;
443 logic [3:0] io_div4_io_div4_meas_ctrl_en_wdata;
444 logic io_div4_io_div4_meas_ctrl_en_we;
445 logic unused_io_div4_io_div4_meas_ctrl_en_wdata;
446 logic io_div4_io_div4_meas_ctrl_en_regwen;
447
448 always_comb begin
449 1/1 io_div4_io_div4_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
450 1/1 io_div4_io_div4_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
451 1/1 io_div4_io_div4_meas_ctrl_en_ds = io_div4_io_div4_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
452 1/1 io_div4_io_div4_meas_ctrl_en_qs = io_div4_io_div4_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
453 end
454
455 prim_reg_cdc #(
456 .DataWidth(4),
457 .ResetVal(4'h9),
458 .BitMask(4'hf),
459 .DstWrReq(1)
460 ) u_io_div4_meas_ctrl_en_cdc (
461 .clk_src_i (clk_i),
462 .rst_src_ni (rst_ni),
463 .clk_dst_i (clk_io_div4_i),
464 .rst_dst_ni (rst_io_div4_ni),
465 .src_regwen_i (measure_ctrl_regwen_qs),
466 .src_we_i (io_div4_meas_ctrl_en_we),
467 .src_re_i ('0),
468 .src_wd_i (reg_wdata[3:0]),
469 .src_busy_o (io_div4_meas_ctrl_en_busy),
470 .src_qs_o (io_div4_meas_ctrl_en_qs), // for software read back
471 .dst_update_i (io_div4_io_div4_meas_ctrl_en_qe),
472 .dst_ds_i (io_div4_io_div4_meas_ctrl_en_ds),
473 .dst_qs_i (io_div4_io_div4_meas_ctrl_en_qs),
474 .dst_we_o (io_div4_io_div4_meas_ctrl_en_we),
475 .dst_re_o (),
476 .dst_regwen_o (io_div4_io_div4_meas_ctrl_en_regwen),
477 .dst_wd_o (io_div4_io_div4_meas_ctrl_en_wdata)
478 );
479 1/1 assign unused_io_div4_io_div4_meas_ctrl_en_wdata =
Tests: T1 T10 T2
480 ^io_div4_io_div4_meas_ctrl_en_wdata;
481
482 logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
483 logic [7:0] io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
484 logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_qs;
485 logic [15:0] io_div4_io_div4_meas_ctrl_shadowed_wdata;
486 logic io_div4_io_div4_meas_ctrl_shadowed_we;
487 logic unused_io_div4_io_div4_meas_ctrl_shadowed_wdata;
488 logic io_div4_io_div4_meas_ctrl_shadowed_re;
489 logic io_div4_io_div4_meas_ctrl_shadowed_regwen;
490
491 always_comb begin
492 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs = 16'h6e82;
Tests: T1 T2 T3
493 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs[7:0] = io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
494 1/1 io_div4_io_div4_meas_ctrl_shadowed_qs[15:8] = io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
495 end
496
497 prim_reg_cdc #(
498 .DataWidth(16),
499 .ResetVal(16'h6e82),
500 .BitMask(16'hffff),
501 .DstWrReq(0)
502 ) u_io_div4_meas_ctrl_shadowed_cdc (
503 .clk_src_i (clk_i),
504 .rst_src_ni (rst_ni),
505 .clk_dst_i (clk_io_div4_i),
506 .rst_dst_ni (rst_io_div4_ni),
507 .src_regwen_i (measure_ctrl_regwen_qs),
508 .src_we_i (io_div4_meas_ctrl_shadowed_we),
509 .src_re_i (io_div4_meas_ctrl_shadowed_re),
510 .src_wd_i (reg_wdata[15:0]),
511 .src_busy_o (io_div4_meas_ctrl_shadowed_busy),
512 .src_qs_o (io_div4_meas_ctrl_shadowed_qs), // for software read back
513 .dst_update_i ('0),
514 .dst_ds_i ('0),
515 .dst_qs_i (io_div4_io_div4_meas_ctrl_shadowed_qs),
516 .dst_we_o (io_div4_io_div4_meas_ctrl_shadowed_we),
517 .dst_re_o (io_div4_io_div4_meas_ctrl_shadowed_re),
518 .dst_regwen_o (io_div4_io_div4_meas_ctrl_shadowed_regwen),
519 .dst_wd_o (io_div4_io_div4_meas_ctrl_shadowed_wdata)
520 );
521 1/1 assign unused_io_div4_io_div4_meas_ctrl_shadowed_wdata =
Tests: T9 T1 T10
522 ^io_div4_io_div4_meas_ctrl_shadowed_wdata;
523
524 logic [3:0] main_main_meas_ctrl_en_ds_int;
525 logic [3:0] main_main_meas_ctrl_en_qs_int;
526 logic [3:0] main_main_meas_ctrl_en_ds;
527 logic main_main_meas_ctrl_en_qe;
528 logic [3:0] main_main_meas_ctrl_en_qs;
529 logic [3:0] main_main_meas_ctrl_en_wdata;
530 logic main_main_meas_ctrl_en_we;
531 logic unused_main_main_meas_ctrl_en_wdata;
532 logic main_main_meas_ctrl_en_regwen;
533
534 always_comb begin
535 1/1 main_main_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
536 1/1 main_main_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
537 1/1 main_main_meas_ctrl_en_ds = main_main_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
538 1/1 main_main_meas_ctrl_en_qs = main_main_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
539 end
540
541 prim_reg_cdc #(
542 .DataWidth(4),
543 .ResetVal(4'h9),
544 .BitMask(4'hf),
545 .DstWrReq(1)
546 ) u_main_meas_ctrl_en_cdc (
547 .clk_src_i (clk_i),
548 .rst_src_ni (rst_ni),
549 .clk_dst_i (clk_main_i),
550 .rst_dst_ni (rst_main_ni),
551 .src_regwen_i (measure_ctrl_regwen_qs),
552 .src_we_i (main_meas_ctrl_en_we),
553 .src_re_i ('0),
554 .src_wd_i (reg_wdata[3:0]),
555 .src_busy_o (main_meas_ctrl_en_busy),
556 .src_qs_o (main_meas_ctrl_en_qs), // for software read back
557 .dst_update_i (main_main_meas_ctrl_en_qe),
558 .dst_ds_i (main_main_meas_ctrl_en_ds),
559 .dst_qs_i (main_main_meas_ctrl_en_qs),
560 .dst_we_o (main_main_meas_ctrl_en_we),
561 .dst_re_o (),
562 .dst_regwen_o (main_main_meas_ctrl_en_regwen),
563 .dst_wd_o (main_main_meas_ctrl_en_wdata)
564 );
565 1/1 assign unused_main_main_meas_ctrl_en_wdata =
Tests: T9 T1 T10
566 ^main_main_meas_ctrl_en_wdata;
567
568 logic [9:0] main_main_meas_ctrl_shadowed_hi_qs_int;
569 logic [9:0] main_main_meas_ctrl_shadowed_lo_qs_int;
570 logic [19:0] main_main_meas_ctrl_shadowed_qs;
571 logic [19:0] main_main_meas_ctrl_shadowed_wdata;
572 logic main_main_meas_ctrl_shadowed_we;
573 logic unused_main_main_meas_ctrl_shadowed_wdata;
574 logic main_main_meas_ctrl_shadowed_re;
575 logic main_main_meas_ctrl_shadowed_regwen;
576
577 always_comb begin
578 1/1 main_main_meas_ctrl_shadowed_qs = 20'h7a9fe;
Tests: T1 T2 T3
579 1/1 main_main_meas_ctrl_shadowed_qs[9:0] = main_main_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
580 1/1 main_main_meas_ctrl_shadowed_qs[19:10] = main_main_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
581 end
582
583 prim_reg_cdc #(
584 .DataWidth(20),
585 .ResetVal(20'h7a9fe),
586 .BitMask(20'hfffff),
587 .DstWrReq(0)
588 ) u_main_meas_ctrl_shadowed_cdc (
589 .clk_src_i (clk_i),
590 .rst_src_ni (rst_ni),
591 .clk_dst_i (clk_main_i),
592 .rst_dst_ni (rst_main_ni),
593 .src_regwen_i (measure_ctrl_regwen_qs),
594 .src_we_i (main_meas_ctrl_shadowed_we),
595 .src_re_i (main_meas_ctrl_shadowed_re),
596 .src_wd_i (reg_wdata[19:0]),
597 .src_busy_o (main_meas_ctrl_shadowed_busy),
598 .src_qs_o (main_meas_ctrl_shadowed_qs), // for software read back
599 .dst_update_i ('0),
600 .dst_ds_i ('0),
601 .dst_qs_i (main_main_meas_ctrl_shadowed_qs),
602 .dst_we_o (main_main_meas_ctrl_shadowed_we),
603 .dst_re_o (main_main_meas_ctrl_shadowed_re),
604 .dst_regwen_o (main_main_meas_ctrl_shadowed_regwen),
605 .dst_wd_o (main_main_meas_ctrl_shadowed_wdata)
606 );
607 1/1 assign unused_main_main_meas_ctrl_shadowed_wdata =
Tests: T9 T1 T10
608 ^main_main_meas_ctrl_shadowed_wdata;
609
610 logic [3:0] usb_usb_meas_ctrl_en_ds_int;
611 logic [3:0] usb_usb_meas_ctrl_en_qs_int;
612 logic [3:0] usb_usb_meas_ctrl_en_ds;
613 logic usb_usb_meas_ctrl_en_qe;
614 logic [3:0] usb_usb_meas_ctrl_en_qs;
615 logic [3:0] usb_usb_meas_ctrl_en_wdata;
616 logic usb_usb_meas_ctrl_en_we;
617 logic unused_usb_usb_meas_ctrl_en_wdata;
618 logic usb_usb_meas_ctrl_en_regwen;
619
620 always_comb begin
621 1/1 usb_usb_meas_ctrl_en_qs = 4'h9;
Tests: T1 T2 T3
622 1/1 usb_usb_meas_ctrl_en_ds = 4'h9;
Tests: T1 T2 T3
623 1/1 usb_usb_meas_ctrl_en_ds = usb_usb_meas_ctrl_en_ds_int;
Tests: T1 T2 T3
624 1/1 usb_usb_meas_ctrl_en_qs = usb_usb_meas_ctrl_en_qs_int;
Tests: T1 T2 T3
625 end
626
627 prim_reg_cdc #(
628 .DataWidth(4),
629 .ResetVal(4'h9),
630 .BitMask(4'hf),
631 .DstWrReq(1)
632 ) u_usb_meas_ctrl_en_cdc (
633 .clk_src_i (clk_i),
634 .rst_src_ni (rst_ni),
635 .clk_dst_i (clk_usb_i),
636 .rst_dst_ni (rst_usb_ni),
637 .src_regwen_i (measure_ctrl_regwen_qs),
638 .src_we_i (usb_meas_ctrl_en_we),
639 .src_re_i ('0),
640 .src_wd_i (reg_wdata[3:0]),
641 .src_busy_o (usb_meas_ctrl_en_busy),
642 .src_qs_o (usb_meas_ctrl_en_qs), // for software read back
643 .dst_update_i (usb_usb_meas_ctrl_en_qe),
644 .dst_ds_i (usb_usb_meas_ctrl_en_ds),
645 .dst_qs_i (usb_usb_meas_ctrl_en_qs),
646 .dst_we_o (usb_usb_meas_ctrl_en_we),
647 .dst_re_o (),
648 .dst_regwen_o (usb_usb_meas_ctrl_en_regwen),
649 .dst_wd_o (usb_usb_meas_ctrl_en_wdata)
650 );
651 1/1 assign unused_usb_usb_meas_ctrl_en_wdata =
Tests: T9 T1 T10
652 ^usb_usb_meas_ctrl_en_wdata;
653
654 logic [8:0] usb_usb_meas_ctrl_shadowed_hi_qs_int;
655 logic [8:0] usb_usb_meas_ctrl_shadowed_lo_qs_int;
656 logic [17:0] usb_usb_meas_ctrl_shadowed_qs;
657 logic [17:0] usb_usb_meas_ctrl_shadowed_wdata;
658 logic usb_usb_meas_ctrl_shadowed_we;
659 logic unused_usb_usb_meas_ctrl_shadowed_wdata;
660 logic usb_usb_meas_ctrl_shadowed_re;
661 logic usb_usb_meas_ctrl_shadowed_regwen;
662
663 always_comb begin
664 1/1 usb_usb_meas_ctrl_shadowed_qs = 18'h1ccfa;
Tests: T1 T2 T3
665 1/1 usb_usb_meas_ctrl_shadowed_qs[8:0] = usb_usb_meas_ctrl_shadowed_hi_qs_int;
Tests: T1 T2 T3
666 1/1 usb_usb_meas_ctrl_shadowed_qs[17:9] = usb_usb_meas_ctrl_shadowed_lo_qs_int;
Tests: T1 T2 T3
667 end
668
669 prim_reg_cdc #(
670 .DataWidth(18),
671 .ResetVal(18'h1ccfa),
672 .BitMask(18'h3ffff),
673 .DstWrReq(0)
674 ) u_usb_meas_ctrl_shadowed_cdc (
675 .clk_src_i (clk_i),
676 .rst_src_ni (rst_ni),
677 .clk_dst_i (clk_usb_i),
678 .rst_dst_ni (rst_usb_ni),
679 .src_regwen_i (measure_ctrl_regwen_qs),
680 .src_we_i (usb_meas_ctrl_shadowed_we),
681 .src_re_i (usb_meas_ctrl_shadowed_re),
682 .src_wd_i (reg_wdata[17:0]),
683 .src_busy_o (usb_meas_ctrl_shadowed_busy),
684 .src_qs_o (usb_meas_ctrl_shadowed_qs), // for software read back
685 .dst_update_i ('0),
686 .dst_ds_i ('0),
687 .dst_qs_i (usb_usb_meas_ctrl_shadowed_qs),
688 .dst_we_o (usb_usb_meas_ctrl_shadowed_we),
689 .dst_re_o (usb_usb_meas_ctrl_shadowed_re),
690 .dst_regwen_o (usb_usb_meas_ctrl_shadowed_regwen),
691 .dst_wd_o (usb_usb_meas_ctrl_shadowed_wdata)
692 );
693 1/1 assign unused_usb_usb_meas_ctrl_shadowed_wdata =
Tests: T9 T1 T10
694 ^usb_usb_meas_ctrl_shadowed_wdata;
695
696 // Register instances
697 // R[alert_test]: V(True)
698 logic alert_test_qe;
699 logic [1:0] alert_test_flds_we;
700 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T59 T73 T23
701 // F[recov_fault]: 0:0
702 prim_subreg_ext #(
703 .DW (1)
704 ) u_alert_test_recov_fault (
705 .re (1'b0),
706 .we (alert_test_we),
707 .wd (alert_test_recov_fault_wd),
708 .d ('0),
709 .qre (),
710 .qe (alert_test_flds_we[0]),
711 .q (reg2hw.alert_test.recov_fault.q),
712 .ds (),
713 .qs ()
714 );
715 1/1 assign reg2hw.alert_test.recov_fault.qe = alert_test_qe;
Tests: T59 T73 T23
716
717 // F[fatal_fault]: 1:1
718 prim_subreg_ext #(
719 .DW (1)
720 ) u_alert_test_fatal_fault (
721 .re (1'b0),
722 .we (alert_test_we),
723 .wd (alert_test_fatal_fault_wd),
724 .d ('0),
725 .qre (),
726 .qe (alert_test_flds_we[1]),
727 .q (reg2hw.alert_test.fatal_fault.q),
728 .ds (),
729 .qs ()
730 );
731 1/1 assign reg2hw.alert_test.fatal_fault.qe = alert_test_qe;
Tests: T59 T73 T23
732
733
734 // R[extclk_ctrl_regwen]: V(False)
735 prim_subreg #(
736 .DW (1),
737 .SwAccess(prim_subreg_pkg::SwAccessW0C),
738 .RESVAL (1'h1),
739 .Mubi (1'b0)
740 ) u_extclk_ctrl_regwen (
741 .clk_i (clk_i),
742 .rst_ni (rst_ni),
743
744 // from register interface
745 .we (extclk_ctrl_regwen_we),
746 .wd (extclk_ctrl_regwen_wd),
747
748 // from internal hardware
749 .de (1'b0),
750 .d ('0),
751
752 // to internal hardware
753 .qe (),
754 .q (),
755 .ds (),
756
757 // to register interface (read)
758 .qs (extclk_ctrl_regwen_qs)
759 );
760
761
762 // R[extclk_ctrl]: V(False)
763 // Create REGWEN-gated WE signal
764 logic extclk_ctrl_gated_we;
765 1/1 assign extclk_ctrl_gated_we = extclk_ctrl_we & extclk_ctrl_regwen_qs;
Tests: T5 T32 T33
766 // F[sel]: 3:0
767 prim_subreg #(
768 .DW (4),
769 .SwAccess(prim_subreg_pkg::SwAccessRW),
770 .RESVAL (4'h9),
771 .Mubi (1'b1)
772 ) u_extclk_ctrl_sel (
773 .clk_i (clk_i),
774 .rst_ni (rst_ni),
775
776 // from register interface
777 .we (extclk_ctrl_gated_we),
778 .wd (extclk_ctrl_sel_wd),
779
780 // from internal hardware
781 .de (1'b0),
782 .d ('0),
783
784 // to internal hardware
785 .qe (),
786 .q (reg2hw.extclk_ctrl.sel.q),
787 .ds (),
788
789 // to register interface (read)
790 .qs (extclk_ctrl_sel_qs)
791 );
792
793 // F[hi_speed_sel]: 7:4
794 prim_subreg #(
795 .DW (4),
796 .SwAccess(prim_subreg_pkg::SwAccessRW),
797 .RESVAL (4'h9),
798 .Mubi (1'b1)
799 ) u_extclk_ctrl_hi_speed_sel (
800 .clk_i (clk_i),
801 .rst_ni (rst_ni),
802
803 // from register interface
804 .we (extclk_ctrl_gated_we),
805 .wd (extclk_ctrl_hi_speed_sel_wd),
806
807 // from internal hardware
808 .de (1'b0),
809 .d ('0),
810
811 // to internal hardware
812 .qe (),
813 .q (reg2hw.extclk_ctrl.hi_speed_sel.q),
814 .ds (),
815
816 // to register interface (read)
817 .qs (extclk_ctrl_hi_speed_sel_qs)
818 );
819
820
821 // R[extclk_status]: V(True)
822 prim_subreg_ext #(
823 .DW (4)
824 ) u_extclk_status (
825 .re (extclk_status_re),
826 .we (1'b0),
827 .wd ('0),
828 .d (hw2reg.extclk_status.d),
829 .qre (),
830 .qe (),
831 .q (),
832 .ds (),
833 .qs (extclk_status_qs)
834 );
835
836
837 // R[jitter_regwen]: V(False)
838 prim_subreg #(
839 .DW (1),
840 .SwAccess(prim_subreg_pkg::SwAccessW0C),
841 .RESVAL (1'h1),
842 .Mubi (1'b0)
843 ) u_jitter_regwen (
844 .clk_i (clk_i),
845 .rst_ni (rst_ni),
846
847 // from register interface
848 .we (jitter_regwen_we),
849 .wd (jitter_regwen_wd),
850
851 // from internal hardware
852 .de (1'b0),
853 .d ('0),
854
855 // to internal hardware
856 .qe (),
857 .q (),
858 .ds (),
859
860 // to register interface (read)
861 .qs (jitter_regwen_qs)
862 );
863
864
865 // R[jitter_enable]: V(False)
866 prim_subreg #(
867 .DW (4),
868 .SwAccess(prim_subreg_pkg::SwAccessRW),
869 .RESVAL (4'h9),
870 .Mubi (1'b1)
871 ) u_jitter_enable (
872 .clk_i (clk_i),
873 .rst_ni (rst_ni),
874
875 // from register interface
876 .we (jitter_enable_we),
877 .wd (jitter_enable_wd),
878
879 // from internal hardware
880 .de (1'b0),
881 .d ('0),
882
883 // to internal hardware
884 .qe (),
885 .q (reg2hw.jitter_enable.q),
886 .ds (),
887
888 // to register interface (read)
889 .qs (jitter_enable_qs)
890 );
891
892
893 // R[clk_enables]: V(False)
894 // F[clk_io_div4_peri_en]: 0:0
895 prim_subreg #(
896 .DW (1),
897 .SwAccess(prim_subreg_pkg::SwAccessRW),
898 .RESVAL (1'h1),
899 .Mubi (1'b0)
900 ) u_clk_enables_clk_io_div4_peri_en (
901 .clk_i (clk_i),
902 .rst_ni (rst_ni),
903
904 // from register interface
905 .we (clk_enables_we),
906 .wd (clk_enables_clk_io_div4_peri_en_wd),
907
908 // from internal hardware
909 .de (1'b0),
910 .d ('0),
911
912 // to internal hardware
913 .qe (),
914 .q (reg2hw.clk_enables.clk_io_div4_peri_en.q),
915 .ds (),
916
917 // to register interface (read)
918 .qs (clk_enables_clk_io_div4_peri_en_qs)
919 );
920
921 // F[clk_io_div2_peri_en]: 1:1
922 prim_subreg #(
923 .DW (1),
924 .SwAccess(prim_subreg_pkg::SwAccessRW),
925 .RESVAL (1'h1),
926 .Mubi (1'b0)
927 ) u_clk_enables_clk_io_div2_peri_en (
928 .clk_i (clk_i),
929 .rst_ni (rst_ni),
930
931 // from register interface
932 .we (clk_enables_we),
933 .wd (clk_enables_clk_io_div2_peri_en_wd),
934
935 // from internal hardware
936 .de (1'b0),
937 .d ('0),
938
939 // to internal hardware
940 .qe (),
941 .q (reg2hw.clk_enables.clk_io_div2_peri_en.q),
942 .ds (),
943
944 // to register interface (read)
945 .qs (clk_enables_clk_io_div2_peri_en_qs)
946 );
947
948 // F[clk_io_peri_en]: 2:2
949 prim_subreg #(
950 .DW (1),
951 .SwAccess(prim_subreg_pkg::SwAccessRW),
952 .RESVAL (1'h1),
953 .Mubi (1'b0)
954 ) u_clk_enables_clk_io_peri_en (
955 .clk_i (clk_i),
956 .rst_ni (rst_ni),
957
958 // from register interface
959 .we (clk_enables_we),
960 .wd (clk_enables_clk_io_peri_en_wd),
961
962 // from internal hardware
963 .de (1'b0),
964 .d ('0),
965
966 // to internal hardware
967 .qe (),
968 .q (reg2hw.clk_enables.clk_io_peri_en.q),
969 .ds (),
970
971 // to register interface (read)
972 .qs (clk_enables_clk_io_peri_en_qs)
973 );
974
975 // F[clk_usb_peri_en]: 3:3
976 prim_subreg #(
977 .DW (1),
978 .SwAccess(prim_subreg_pkg::SwAccessRW),
979 .RESVAL (1'h1),
980 .Mubi (1'b0)
981 ) u_clk_enables_clk_usb_peri_en (
982 .clk_i (clk_i),
983 .rst_ni (rst_ni),
984
985 // from register interface
986 .we (clk_enables_we),
987 .wd (clk_enables_clk_usb_peri_en_wd),
988
989 // from internal hardware
990 .de (1'b0),
991 .d ('0),
992
993 // to internal hardware
994 .qe (),
995 .q (reg2hw.clk_enables.clk_usb_peri_en.q),
996 .ds (),
997
998 // to register interface (read)
999 .qs (clk_enables_clk_usb_peri_en_qs)
1000 );
1001
1002
1003 // R[clk_hints]: V(False)
1004 // F[clk_main_aes_hint]: 0:0
1005 prim_subreg #(
1006 .DW (1),
1007 .SwAccess(prim_subreg_pkg::SwAccessRW),
1008 .RESVAL (1'h1),
1009 .Mubi (1'b0)
1010 ) u_clk_hints_clk_main_aes_hint (
1011 .clk_i (clk_i),
1012 .rst_ni (rst_ni),
1013
1014 // from register interface
1015 .we (clk_hints_we),
1016 .wd (clk_hints_clk_main_aes_hint_wd),
1017
1018 // from internal hardware
1019 .de (1'b0),
1020 .d ('0),
1021
1022 // to internal hardware
1023 .qe (),
1024 .q (reg2hw.clk_hints.clk_main_aes_hint.q),
1025 .ds (),
1026
1027 // to register interface (read)
1028 .qs (clk_hints_clk_main_aes_hint_qs)
1029 );
1030
1031 // F[clk_main_hmac_hint]: 1:1
1032 prim_subreg #(
1033 .DW (1),
1034 .SwAccess(prim_subreg_pkg::SwAccessRW),
1035 .RESVAL (1'h1),
1036 .Mubi (1'b0)
1037 ) u_clk_hints_clk_main_hmac_hint (
1038 .clk_i (clk_i),
1039 .rst_ni (rst_ni),
1040
1041 // from register interface
1042 .we (clk_hints_we),
1043 .wd (clk_hints_clk_main_hmac_hint_wd),
1044
1045 // from internal hardware
1046 .de (1'b0),
1047 .d ('0),
1048
1049 // to internal hardware
1050 .qe (),
1051 .q (reg2hw.clk_hints.clk_main_hmac_hint.q),
1052 .ds (),
1053
1054 // to register interface (read)
1055 .qs (clk_hints_clk_main_hmac_hint_qs)
1056 );
1057
1058 // F[clk_main_kmac_hint]: 2:2
1059 prim_subreg #(
1060 .DW (1),
1061 .SwAccess(prim_subreg_pkg::SwAccessRW),
1062 .RESVAL (1'h1),
1063 .Mubi (1'b0)
1064 ) u_clk_hints_clk_main_kmac_hint (
1065 .clk_i (clk_i),
1066 .rst_ni (rst_ni),
1067
1068 // from register interface
1069 .we (clk_hints_we),
1070 .wd (clk_hints_clk_main_kmac_hint_wd),
1071
1072 // from internal hardware
1073 .de (1'b0),
1074 .d ('0),
1075
1076 // to internal hardware
1077 .qe (),
1078 .q (reg2hw.clk_hints.clk_main_kmac_hint.q),
1079 .ds (),
1080
1081 // to register interface (read)
1082 .qs (clk_hints_clk_main_kmac_hint_qs)
1083 );
1084
1085 // F[clk_main_otbn_hint]: 3:3
1086 prim_subreg #(
1087 .DW (1),
1088 .SwAccess(prim_subreg_pkg::SwAccessRW),
1089 .RESVAL (1'h1),
1090 .Mubi (1'b0)
1091 ) u_clk_hints_clk_main_otbn_hint (
1092 .clk_i (clk_i),
1093 .rst_ni (rst_ni),
1094
1095 // from register interface
1096 .we (clk_hints_we),
1097 .wd (clk_hints_clk_main_otbn_hint_wd),
1098
1099 // from internal hardware
1100 .de (1'b0),
1101 .d ('0),
1102
1103 // to internal hardware
1104 .qe (),
1105 .q (reg2hw.clk_hints.clk_main_otbn_hint.q),
1106 .ds (),
1107
1108 // to register interface (read)
1109 .qs (clk_hints_clk_main_otbn_hint_qs)
1110 );
1111
1112
1113 // R[clk_hints_status]: V(False)
1114 // F[clk_main_aes_val]: 0:0
1115 prim_subreg #(
1116 .DW (1),
1117 .SwAccess(prim_subreg_pkg::SwAccessRO),
1118 .RESVAL (1'h1),
1119 .Mubi (1'b0)
1120 ) u_clk_hints_status_clk_main_aes_val (
1121 .clk_i (clk_i),
1122 .rst_ni (rst_ni),
1123
1124 // from register interface
1125 .we (1'b0),
1126 .wd ('0),
1127
1128 // from internal hardware
1129 .de (hw2reg.clk_hints_status.clk_main_aes_val.de),
1130 .d (hw2reg.clk_hints_status.clk_main_aes_val.d),
1131
1132 // to internal hardware
1133 .qe (),
1134 .q (),
1135 .ds (),
1136
1137 // to register interface (read)
1138 .qs (clk_hints_status_clk_main_aes_val_qs)
1139 );
1140
1141 // F[clk_main_hmac_val]: 1:1
1142 prim_subreg #(
1143 .DW (1),
1144 .SwAccess(prim_subreg_pkg::SwAccessRO),
1145 .RESVAL (1'h1),
1146 .Mubi (1'b0)
1147 ) u_clk_hints_status_clk_main_hmac_val (
1148 .clk_i (clk_i),
1149 .rst_ni (rst_ni),
1150
1151 // from register interface
1152 .we (1'b0),
1153 .wd ('0),
1154
1155 // from internal hardware
1156 .de (hw2reg.clk_hints_status.clk_main_hmac_val.de),
1157 .d (hw2reg.clk_hints_status.clk_main_hmac_val.d),
1158
1159 // to internal hardware
1160 .qe (),
1161 .q (),
1162 .ds (),
1163
1164 // to register interface (read)
1165 .qs (clk_hints_status_clk_main_hmac_val_qs)
1166 );
1167
1168 // F[clk_main_kmac_val]: 2:2
1169 prim_subreg #(
1170 .DW (1),
1171 .SwAccess(prim_subreg_pkg::SwAccessRO),
1172 .RESVAL (1'h1),
1173 .Mubi (1'b0)
1174 ) u_clk_hints_status_clk_main_kmac_val (
1175 .clk_i (clk_i),
1176 .rst_ni (rst_ni),
1177
1178 // from register interface
1179 .we (1'b0),
1180 .wd ('0),
1181
1182 // from internal hardware
1183 .de (hw2reg.clk_hints_status.clk_main_kmac_val.de),
1184 .d (hw2reg.clk_hints_status.clk_main_kmac_val.d),
1185
1186 // to internal hardware
1187 .qe (),
1188 .q (),
1189 .ds (),
1190
1191 // to register interface (read)
1192 .qs (clk_hints_status_clk_main_kmac_val_qs)
1193 );
1194
1195 // F[clk_main_otbn_val]: 3:3
1196 prim_subreg #(
1197 .DW (1),
1198 .SwAccess(prim_subreg_pkg::SwAccessRO),
1199 .RESVAL (1'h1),
1200 .Mubi (1'b0)
1201 ) u_clk_hints_status_clk_main_otbn_val (
1202 .clk_i (clk_i),
1203 .rst_ni (rst_ni),
1204
1205 // from register interface
1206 .we (1'b0),
1207 .wd ('0),
1208
1209 // from internal hardware
1210 .de (hw2reg.clk_hints_status.clk_main_otbn_val.de),
1211 .d (hw2reg.clk_hints_status.clk_main_otbn_val.d),
1212
1213 // to internal hardware
1214 .qe (),
1215 .q (),
1216 .ds (),
1217
1218 // to register interface (read)
1219 .qs (clk_hints_status_clk_main_otbn_val_qs)
1220 );
1221
1222
1223 // R[measure_ctrl_regwen]: V(False)
1224 prim_subreg #(
1225 .DW (1),
1226 .SwAccess(prim_subreg_pkg::SwAccessW0C),
1227 .RESVAL (1'h1),
1228 .Mubi (1'b0)
1229 ) u_measure_ctrl_regwen (
1230 .clk_i (clk_i),
1231 .rst_ni (rst_ni),
1232
1233 // from register interface
1234 .we (measure_ctrl_regwen_we),
1235 .wd (measure_ctrl_regwen_wd),
1236
1237 // from internal hardware
1238 .de (hw2reg.measure_ctrl_regwen.de),
1239 .d (hw2reg.measure_ctrl_regwen.d),
1240
1241 // to internal hardware
1242 .qe (),
1243 .q (reg2hw.measure_ctrl_regwen.q),
1244 .ds (),
1245
1246 // to register interface (read)
1247 .qs (measure_ctrl_regwen_qs)
1248 );
1249
1250
1251 // R[io_meas_ctrl_en]: V(False)
1252 logic [0:0] io_meas_ctrl_en_flds_we;
1253 1/1 assign io_io_meas_ctrl_en_qe = |io_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1254 // Create REGWEN-gated WE signal
1255 logic io_io_meas_ctrl_en_gated_we;
1256 1/1 assign io_io_meas_ctrl_en_gated_we = io_io_meas_ctrl_en_we & io_io_meas_ctrl_en_regwen;
Tests: T9 T1 T10
1257 prim_subreg #(
1258 .DW (4),
1259 .SwAccess(prim_subreg_pkg::SwAccessRW),
1260 .RESVAL (4'h9),
1261 .Mubi (1'b1)
1262 ) u_io_meas_ctrl_en (
1263 .clk_i (clk_io_i),
1264 .rst_ni (rst_io_ni),
1265
1266 // from register interface
1267 .we (io_io_meas_ctrl_en_gated_we),
1268 .wd (io_io_meas_ctrl_en_wdata[3:0]),
1269
1270 // from internal hardware
1271 .de (hw2reg.io_meas_ctrl_en.de),
1272 .d (hw2reg.io_meas_ctrl_en.d),
1273
1274 // to internal hardware
1275 .qe (io_meas_ctrl_en_flds_we[0]),
1276 .q (reg2hw.io_meas_ctrl_en.q),
1277 .ds (io_io_meas_ctrl_en_ds_int),
1278
1279 // to register interface (read)
1280 .qs (io_io_meas_ctrl_en_qs_int)
1281 );
1282
1283
1284 // R[io_meas_ctrl_shadowed]: V(False)
1285 // Create REGWEN-gated WE signal
1286 logic io_io_meas_ctrl_shadowed_gated_we;
1287 1/1 assign io_io_meas_ctrl_shadowed_gated_we =
Tests: T9 T1 T10
1288 io_io_meas_ctrl_shadowed_we & io_io_meas_ctrl_shadowed_regwen;
1289 // F[hi]: 9:0
1290 logic async_io_meas_ctrl_shadowed_hi_err_update;
1291 logic async_io_meas_ctrl_shadowed_hi_err_storage;
1292
1293 // storage error is persistent and can be sampled at any time
1294 prim_flop_2sync #(
1295 .Width(1),
1296 .ResetValue('0)
1297 ) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
1298 .clk_i,
1299 .rst_ni,
1300 .d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
1301 .q_o(io_meas_ctrl_shadowed_hi_storage_err)
1302 );
1303
1304 // update error is transient and must be immediately captured
1305 prim_pulse_sync u_io_meas_ctrl_shadowed_hi_err_update_sync (
1306 .clk_src_i(clk_io_i),
1307 .rst_src_ni(rst_io_ni),
1308 .src_pulse_i(async_io_meas_ctrl_shadowed_hi_err_update),
1309 .clk_dst_i(clk_i),
1310 .rst_dst_ni(rst_ni),
1311 .dst_pulse_o(io_meas_ctrl_shadowed_hi_update_err)
1312 );
1313 prim_subreg_shadow #(
1314 .DW (10),
1315 .SwAccess(prim_subreg_pkg::SwAccessRW),
1316 .RESVAL (10'h1ea),
1317 .Mubi (1'b0)
1318 ) u_io_meas_ctrl_shadowed_hi (
1319 .clk_i (clk_io_i),
1320 .rst_ni (rst_io_ni),
1321 .rst_shadowed_ni (rst_shadowed_ni),
1322
1323 // from register interface
1324 .re (io_io_meas_ctrl_shadowed_re),
1325 .we (io_io_meas_ctrl_shadowed_gated_we),
1326 .wd (io_io_meas_ctrl_shadowed_wdata[9:0]),
1327
1328 // from internal hardware
1329 .de (1'b0),
1330 .d ('0),
1331
1332 // to internal hardware
1333 .qe (),
1334 .q (reg2hw.io_meas_ctrl_shadowed.hi.q),
1335 .ds (),
1336
1337 // to register interface (read)
1338 .qs (io_io_meas_ctrl_shadowed_hi_qs_int),
1339
1340 // Shadow register phase. Relevant for hwext only.
1341 .phase (),
1342
1343 // Shadow register error conditions
1344 .err_update (async_io_meas_ctrl_shadowed_hi_err_update),
1345 .err_storage (async_io_meas_ctrl_shadowed_hi_err_storage)
1346 );
1347
1348 // F[lo]: 19:10
1349 logic async_io_meas_ctrl_shadowed_lo_err_update;
1350 logic async_io_meas_ctrl_shadowed_lo_err_storage;
1351
1352 // storage error is persistent and can be sampled at any time
1353 prim_flop_2sync #(
1354 .Width(1),
1355 .ResetValue('0)
1356 ) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
1357 .clk_i,
1358 .rst_ni,
1359 .d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
1360 .q_o(io_meas_ctrl_shadowed_lo_storage_err)
1361 );
1362
1363 // update error is transient and must be immediately captured
1364 prim_pulse_sync u_io_meas_ctrl_shadowed_lo_err_update_sync (
1365 .clk_src_i(clk_io_i),
1366 .rst_src_ni(rst_io_ni),
1367 .src_pulse_i(async_io_meas_ctrl_shadowed_lo_err_update),
1368 .clk_dst_i(clk_i),
1369 .rst_dst_ni(rst_ni),
1370 .dst_pulse_o(io_meas_ctrl_shadowed_lo_update_err)
1371 );
1372 prim_subreg_shadow #(
1373 .DW (10),
1374 .SwAccess(prim_subreg_pkg::SwAccessRW),
1375 .RESVAL (10'h1d6),
1376 .Mubi (1'b0)
1377 ) u_io_meas_ctrl_shadowed_lo (
1378 .clk_i (clk_io_i),
1379 .rst_ni (rst_io_ni),
1380 .rst_shadowed_ni (rst_shadowed_ni),
1381
1382 // from register interface
1383 .re (io_io_meas_ctrl_shadowed_re),
1384 .we (io_io_meas_ctrl_shadowed_gated_we),
1385 .wd (io_io_meas_ctrl_shadowed_wdata[19:10]),
1386
1387 // from internal hardware
1388 .de (1'b0),
1389 .d ('0),
1390
1391 // to internal hardware
1392 .qe (),
1393 .q (reg2hw.io_meas_ctrl_shadowed.lo.q),
1394 .ds (),
1395
1396 // to register interface (read)
1397 .qs (io_io_meas_ctrl_shadowed_lo_qs_int),
1398
1399 // Shadow register phase. Relevant for hwext only.
1400 .phase (),
1401
1402 // Shadow register error conditions
1403 .err_update (async_io_meas_ctrl_shadowed_lo_err_update),
1404 .err_storage (async_io_meas_ctrl_shadowed_lo_err_storage)
1405 );
1406
1407
1408 // R[io_div2_meas_ctrl_en]: V(False)
1409 logic [0:0] io_div2_meas_ctrl_en_flds_we;
1410 1/1 assign io_div2_io_div2_meas_ctrl_en_qe = |io_div2_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1411 // Create REGWEN-gated WE signal
1412 logic io_div2_io_div2_meas_ctrl_en_gated_we;
1413 1/1 assign io_div2_io_div2_meas_ctrl_en_gated_we =
Tests: T9 T1 T10
1414 io_div2_io_div2_meas_ctrl_en_we & io_div2_io_div2_meas_ctrl_en_regwen;
1415 prim_subreg #(
1416 .DW (4),
1417 .SwAccess(prim_subreg_pkg::SwAccessRW),
1418 .RESVAL (4'h9),
1419 .Mubi (1'b1)
1420 ) u_io_div2_meas_ctrl_en (
1421 .clk_i (clk_io_div2_i),
1422 .rst_ni (rst_io_div2_ni),
1423
1424 // from register interface
1425 .we (io_div2_io_div2_meas_ctrl_en_gated_we),
1426 .wd (io_div2_io_div2_meas_ctrl_en_wdata[3:0]),
1427
1428 // from internal hardware
1429 .de (hw2reg.io_div2_meas_ctrl_en.de),
1430 .d (hw2reg.io_div2_meas_ctrl_en.d),
1431
1432 // to internal hardware
1433 .qe (io_div2_meas_ctrl_en_flds_we[0]),
1434 .q (reg2hw.io_div2_meas_ctrl_en.q),
1435 .ds (io_div2_io_div2_meas_ctrl_en_ds_int),
1436
1437 // to register interface (read)
1438 .qs (io_div2_io_div2_meas_ctrl_en_qs_int)
1439 );
1440
1441
1442 // R[io_div2_meas_ctrl_shadowed]: V(False)
1443 // Create REGWEN-gated WE signal
1444 logic io_div2_io_div2_meas_ctrl_shadowed_gated_we;
1445 1/1 assign io_div2_io_div2_meas_ctrl_shadowed_gated_we =
Tests: T9 T1 T10
1446 io_div2_io_div2_meas_ctrl_shadowed_we & io_div2_io_div2_meas_ctrl_shadowed_regwen;
1447 // F[hi]: 8:0
1448 logic async_io_div2_meas_ctrl_shadowed_hi_err_update;
1449 logic async_io_div2_meas_ctrl_shadowed_hi_err_storage;
1450
1451 // storage error is persistent and can be sampled at any time
1452 prim_flop_2sync #(
1453 .Width(1),
1454 .ResetValue('0)
1455 ) u_io_div2_meas_ctrl_shadowed_hi_err_storage_sync (
1456 .clk_i,
1457 .rst_ni,
1458 .d_i(async_io_div2_meas_ctrl_shadowed_hi_err_storage),
1459 .q_o(io_div2_meas_ctrl_shadowed_hi_storage_err)
1460 );
1461
1462 // update error is transient and must be immediately captured
1463 prim_pulse_sync u_io_div2_meas_ctrl_shadowed_hi_err_update_sync (
1464 .clk_src_i(clk_io_div2_i),
1465 .rst_src_ni(rst_io_div2_ni),
1466 .src_pulse_i(async_io_div2_meas_ctrl_shadowed_hi_err_update),
1467 .clk_dst_i(clk_i),
1468 .rst_dst_ni(rst_ni),
1469 .dst_pulse_o(io_div2_meas_ctrl_shadowed_hi_update_err)
1470 );
1471 prim_subreg_shadow #(
1472 .DW (9),
1473 .SwAccess(prim_subreg_pkg::SwAccessRW),
1474 .RESVAL (9'hfa),
1475 .Mubi (1'b0)
1476 ) u_io_div2_meas_ctrl_shadowed_hi (
1477 .clk_i (clk_io_div2_i),
1478 .rst_ni (rst_io_div2_ni),
1479 .rst_shadowed_ni (rst_shadowed_ni),
1480
1481 // from register interface
1482 .re (io_div2_io_div2_meas_ctrl_shadowed_re),
1483 .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
1484 .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[8:0]),
1485
1486 // from internal hardware
1487 .de (1'b0),
1488 .d ('0),
1489
1490 // to internal hardware
1491 .qe (),
1492 .q (reg2hw.io_div2_meas_ctrl_shadowed.hi.q),
1493 .ds (),
1494
1495 // to register interface (read)
1496 .qs (io_div2_io_div2_meas_ctrl_shadowed_hi_qs_int),
1497
1498 // Shadow register phase. Relevant for hwext only.
1499 .phase (),
1500
1501 // Shadow register error conditions
1502 .err_update (async_io_div2_meas_ctrl_shadowed_hi_err_update),
1503 .err_storage (async_io_div2_meas_ctrl_shadowed_hi_err_storage)
1504 );
1505
1506 // F[lo]: 17:9
1507 logic async_io_div2_meas_ctrl_shadowed_lo_err_update;
1508 logic async_io_div2_meas_ctrl_shadowed_lo_err_storage;
1509
1510 // storage error is persistent and can be sampled at any time
1511 prim_flop_2sync #(
1512 .Width(1),
1513 .ResetValue('0)
1514 ) u_io_div2_meas_ctrl_shadowed_lo_err_storage_sync (
1515 .clk_i,
1516 .rst_ni,
1517 .d_i(async_io_div2_meas_ctrl_shadowed_lo_err_storage),
1518 .q_o(io_div2_meas_ctrl_shadowed_lo_storage_err)
1519 );
1520
1521 // update error is transient and must be immediately captured
1522 prim_pulse_sync u_io_div2_meas_ctrl_shadowed_lo_err_update_sync (
1523 .clk_src_i(clk_io_div2_i),
1524 .rst_src_ni(rst_io_div2_ni),
1525 .src_pulse_i(async_io_div2_meas_ctrl_shadowed_lo_err_update),
1526 .clk_dst_i(clk_i),
1527 .rst_dst_ni(rst_ni),
1528 .dst_pulse_o(io_div2_meas_ctrl_shadowed_lo_update_err)
1529 );
1530 prim_subreg_shadow #(
1531 .DW (9),
1532 .SwAccess(prim_subreg_pkg::SwAccessRW),
1533 .RESVAL (9'he6),
1534 .Mubi (1'b0)
1535 ) u_io_div2_meas_ctrl_shadowed_lo (
1536 .clk_i (clk_io_div2_i),
1537 .rst_ni (rst_io_div2_ni),
1538 .rst_shadowed_ni (rst_shadowed_ni),
1539
1540 // from register interface
1541 .re (io_div2_io_div2_meas_ctrl_shadowed_re),
1542 .we (io_div2_io_div2_meas_ctrl_shadowed_gated_we),
1543 .wd (io_div2_io_div2_meas_ctrl_shadowed_wdata[17:9]),
1544
1545 // from internal hardware
1546 .de (1'b0),
1547 .d ('0),
1548
1549 // to internal hardware
1550 .qe (),
1551 .q (reg2hw.io_div2_meas_ctrl_shadowed.lo.q),
1552 .ds (),
1553
1554 // to register interface (read)
1555 .qs (io_div2_io_div2_meas_ctrl_shadowed_lo_qs_int),
1556
1557 // Shadow register phase. Relevant for hwext only.
1558 .phase (),
1559
1560 // Shadow register error conditions
1561 .err_update (async_io_div2_meas_ctrl_shadowed_lo_err_update),
1562 .err_storage (async_io_div2_meas_ctrl_shadowed_lo_err_storage)
1563 );
1564
1565
1566 // R[io_div4_meas_ctrl_en]: V(False)
1567 logic [0:0] io_div4_meas_ctrl_en_flds_we;
1568 1/1 assign io_div4_io_div4_meas_ctrl_en_qe = |io_div4_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1569 // Create REGWEN-gated WE signal
1570 logic io_div4_io_div4_meas_ctrl_en_gated_we;
1571 1/1 assign io_div4_io_div4_meas_ctrl_en_gated_we =
Tests: T9 T1 T10
1572 io_div4_io_div4_meas_ctrl_en_we & io_div4_io_div4_meas_ctrl_en_regwen;
1573 prim_subreg #(
1574 .DW (4),
1575 .SwAccess(prim_subreg_pkg::SwAccessRW),
1576 .RESVAL (4'h9),
1577 .Mubi (1'b1)
1578 ) u_io_div4_meas_ctrl_en (
1579 .clk_i (clk_io_div4_i),
1580 .rst_ni (rst_io_div4_ni),
1581
1582 // from register interface
1583 .we (io_div4_io_div4_meas_ctrl_en_gated_we),
1584 .wd (io_div4_io_div4_meas_ctrl_en_wdata[3:0]),
1585
1586 // from internal hardware
1587 .de (hw2reg.io_div4_meas_ctrl_en.de),
1588 .d (hw2reg.io_div4_meas_ctrl_en.d),
1589
1590 // to internal hardware
1591 .qe (io_div4_meas_ctrl_en_flds_we[0]),
1592 .q (reg2hw.io_div4_meas_ctrl_en.q),
1593 .ds (io_div4_io_div4_meas_ctrl_en_ds_int),
1594
1595 // to register interface (read)
1596 .qs (io_div4_io_div4_meas_ctrl_en_qs_int)
1597 );
1598
1599
1600 // R[io_div4_meas_ctrl_shadowed]: V(False)
1601 // Create REGWEN-gated WE signal
1602 logic io_div4_io_div4_meas_ctrl_shadowed_gated_we;
1603 1/1 assign io_div4_io_div4_meas_ctrl_shadowed_gated_we =
Tests: T9 T1 T10
1604 io_div4_io_div4_meas_ctrl_shadowed_we & io_div4_io_div4_meas_ctrl_shadowed_regwen;
1605 // F[hi]: 7:0
1606 logic async_io_div4_meas_ctrl_shadowed_hi_err_update;
1607 logic async_io_div4_meas_ctrl_shadowed_hi_err_storage;
1608
1609 // storage error is persistent and can be sampled at any time
1610 prim_flop_2sync #(
1611 .Width(1),
1612 .ResetValue('0)
1613 ) u_io_div4_meas_ctrl_shadowed_hi_err_storage_sync (
1614 .clk_i,
1615 .rst_ni,
1616 .d_i(async_io_div4_meas_ctrl_shadowed_hi_err_storage),
1617 .q_o(io_div4_meas_ctrl_shadowed_hi_storage_err)
1618 );
1619
1620 // update error is transient and must be immediately captured
1621 prim_pulse_sync u_io_div4_meas_ctrl_shadowed_hi_err_update_sync (
1622 .clk_src_i(clk_io_div4_i),
1623 .rst_src_ni(rst_io_div4_ni),
1624 .src_pulse_i(async_io_div4_meas_ctrl_shadowed_hi_err_update),
1625 .clk_dst_i(clk_i),
1626 .rst_dst_ni(rst_ni),
1627 .dst_pulse_o(io_div4_meas_ctrl_shadowed_hi_update_err)
1628 );
1629 prim_subreg_shadow #(
1630 .DW (8),
1631 .SwAccess(prim_subreg_pkg::SwAccessRW),
1632 .RESVAL (8'h82),
1633 .Mubi (1'b0)
1634 ) u_io_div4_meas_ctrl_shadowed_hi (
1635 .clk_i (clk_io_div4_i),
1636 .rst_ni (rst_io_div4_ni),
1637 .rst_shadowed_ni (rst_shadowed_ni),
1638
1639 // from register interface
1640 .re (io_div4_io_div4_meas_ctrl_shadowed_re),
1641 .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
1642 .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[7:0]),
1643
1644 // from internal hardware
1645 .de (1'b0),
1646 .d ('0),
1647
1648 // to internal hardware
1649 .qe (),
1650 .q (reg2hw.io_div4_meas_ctrl_shadowed.hi.q),
1651 .ds (),
1652
1653 // to register interface (read)
1654 .qs (io_div4_io_div4_meas_ctrl_shadowed_hi_qs_int),
1655
1656 // Shadow register phase. Relevant for hwext only.
1657 .phase (),
1658
1659 // Shadow register error conditions
1660 .err_update (async_io_div4_meas_ctrl_shadowed_hi_err_update),
1661 .err_storage (async_io_div4_meas_ctrl_shadowed_hi_err_storage)
1662 );
1663
1664 // F[lo]: 15:8
1665 logic async_io_div4_meas_ctrl_shadowed_lo_err_update;
1666 logic async_io_div4_meas_ctrl_shadowed_lo_err_storage;
1667
1668 // storage error is persistent and can be sampled at any time
1669 prim_flop_2sync #(
1670 .Width(1),
1671 .ResetValue('0)
1672 ) u_io_div4_meas_ctrl_shadowed_lo_err_storage_sync (
1673 .clk_i,
1674 .rst_ni,
1675 .d_i(async_io_div4_meas_ctrl_shadowed_lo_err_storage),
1676 .q_o(io_div4_meas_ctrl_shadowed_lo_storage_err)
1677 );
1678
1679 // update error is transient and must be immediately captured
1680 prim_pulse_sync u_io_div4_meas_ctrl_shadowed_lo_err_update_sync (
1681 .clk_src_i(clk_io_div4_i),
1682 .rst_src_ni(rst_io_div4_ni),
1683 .src_pulse_i(async_io_div4_meas_ctrl_shadowed_lo_err_update),
1684 .clk_dst_i(clk_i),
1685 .rst_dst_ni(rst_ni),
1686 .dst_pulse_o(io_div4_meas_ctrl_shadowed_lo_update_err)
1687 );
1688 prim_subreg_shadow #(
1689 .DW (8),
1690 .SwAccess(prim_subreg_pkg::SwAccessRW),
1691 .RESVAL (8'h6e),
1692 .Mubi (1'b0)
1693 ) u_io_div4_meas_ctrl_shadowed_lo (
1694 .clk_i (clk_io_div4_i),
1695 .rst_ni (rst_io_div4_ni),
1696 .rst_shadowed_ni (rst_shadowed_ni),
1697
1698 // from register interface
1699 .re (io_div4_io_div4_meas_ctrl_shadowed_re),
1700 .we (io_div4_io_div4_meas_ctrl_shadowed_gated_we),
1701 .wd (io_div4_io_div4_meas_ctrl_shadowed_wdata[15:8]),
1702
1703 // from internal hardware
1704 .de (1'b0),
1705 .d ('0),
1706
1707 // to internal hardware
1708 .qe (),
1709 .q (reg2hw.io_div4_meas_ctrl_shadowed.lo.q),
1710 .ds (),
1711
1712 // to register interface (read)
1713 .qs (io_div4_io_div4_meas_ctrl_shadowed_lo_qs_int),
1714
1715 // Shadow register phase. Relevant for hwext only.
1716 .phase (),
1717
1718 // Shadow register error conditions
1719 .err_update (async_io_div4_meas_ctrl_shadowed_lo_err_update),
1720 .err_storage (async_io_div4_meas_ctrl_shadowed_lo_err_storage)
1721 );
1722
1723
1724 // R[main_meas_ctrl_en]: V(False)
1725 logic [0:0] main_meas_ctrl_en_flds_we;
1726 1/1 assign main_main_meas_ctrl_en_qe = |main_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1727 // Create REGWEN-gated WE signal
1728 logic main_main_meas_ctrl_en_gated_we;
1729 1/1 assign main_main_meas_ctrl_en_gated_we =
Tests: T9 T1 T10
1730 main_main_meas_ctrl_en_we & main_main_meas_ctrl_en_regwen;
1731 prim_subreg #(
1732 .DW (4),
1733 .SwAccess(prim_subreg_pkg::SwAccessRW),
1734 .RESVAL (4'h9),
1735 .Mubi (1'b1)
1736 ) u_main_meas_ctrl_en (
1737 .clk_i (clk_main_i),
1738 .rst_ni (rst_main_ni),
1739
1740 // from register interface
1741 .we (main_main_meas_ctrl_en_gated_we),
1742 .wd (main_main_meas_ctrl_en_wdata[3:0]),
1743
1744 // from internal hardware
1745 .de (hw2reg.main_meas_ctrl_en.de),
1746 .d (hw2reg.main_meas_ctrl_en.d),
1747
1748 // to internal hardware
1749 .qe (main_meas_ctrl_en_flds_we[0]),
1750 .q (reg2hw.main_meas_ctrl_en.q),
1751 .ds (main_main_meas_ctrl_en_ds_int),
1752
1753 // to register interface (read)
1754 .qs (main_main_meas_ctrl_en_qs_int)
1755 );
1756
1757
1758 // R[main_meas_ctrl_shadowed]: V(False)
1759 // Create REGWEN-gated WE signal
1760 logic main_main_meas_ctrl_shadowed_gated_we;
1761 1/1 assign main_main_meas_ctrl_shadowed_gated_we =
Tests: T9 T1 T10
1762 main_main_meas_ctrl_shadowed_we & main_main_meas_ctrl_shadowed_regwen;
1763 // F[hi]: 9:0
1764 logic async_main_meas_ctrl_shadowed_hi_err_update;
1765 logic async_main_meas_ctrl_shadowed_hi_err_storage;
1766
1767 // storage error is persistent and can be sampled at any time
1768 prim_flop_2sync #(
1769 .Width(1),
1770 .ResetValue('0)
1771 ) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
1772 .clk_i,
1773 .rst_ni,
1774 .d_i(async_main_meas_ctrl_shadowed_hi_err_storage),
1775 .q_o(main_meas_ctrl_shadowed_hi_storage_err)
1776 );
1777
1778 // update error is transient and must be immediately captured
1779 prim_pulse_sync u_main_meas_ctrl_shadowed_hi_err_update_sync (
1780 .clk_src_i(clk_main_i),
1781 .rst_src_ni(rst_main_ni),
1782 .src_pulse_i(async_main_meas_ctrl_shadowed_hi_err_update),
1783 .clk_dst_i(clk_i),
1784 .rst_dst_ni(rst_ni),
1785 .dst_pulse_o(main_meas_ctrl_shadowed_hi_update_err)
1786 );
1787 prim_subreg_shadow #(
1788 .DW (10),
1789 .SwAccess(prim_subreg_pkg::SwAccessRW),
1790 .RESVAL (10'h1fe),
1791 .Mubi (1'b0)
1792 ) u_main_meas_ctrl_shadowed_hi (
1793 .clk_i (clk_main_i),
1794 .rst_ni (rst_main_ni),
1795 .rst_shadowed_ni (rst_shadowed_ni),
1796
1797 // from register interface
1798 .re (main_main_meas_ctrl_shadowed_re),
1799 .we (main_main_meas_ctrl_shadowed_gated_we),
1800 .wd (main_main_meas_ctrl_shadowed_wdata[9:0]),
1801
1802 // from internal hardware
1803 .de (1'b0),
1804 .d ('0),
1805
1806 // to internal hardware
1807 .qe (),
1808 .q (reg2hw.main_meas_ctrl_shadowed.hi.q),
1809 .ds (),
1810
1811 // to register interface (read)
1812 .qs (main_main_meas_ctrl_shadowed_hi_qs_int),
1813
1814 // Shadow register phase. Relevant for hwext only.
1815 .phase (),
1816
1817 // Shadow register error conditions
1818 .err_update (async_main_meas_ctrl_shadowed_hi_err_update),
1819 .err_storage (async_main_meas_ctrl_shadowed_hi_err_storage)
1820 );
1821
1822 // F[lo]: 19:10
1823 logic async_main_meas_ctrl_shadowed_lo_err_update;
1824 logic async_main_meas_ctrl_shadowed_lo_err_storage;
1825
1826 // storage error is persistent and can be sampled at any time
1827 prim_flop_2sync #(
1828 .Width(1),
1829 .ResetValue('0)
1830 ) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
1831 .clk_i,
1832 .rst_ni,
1833 .d_i(async_main_meas_ctrl_shadowed_lo_err_storage),
1834 .q_o(main_meas_ctrl_shadowed_lo_storage_err)
1835 );
1836
1837 // update error is transient and must be immediately captured
1838 prim_pulse_sync u_main_meas_ctrl_shadowed_lo_err_update_sync (
1839 .clk_src_i(clk_main_i),
1840 .rst_src_ni(rst_main_ni),
1841 .src_pulse_i(async_main_meas_ctrl_shadowed_lo_err_update),
1842 .clk_dst_i(clk_i),
1843 .rst_dst_ni(rst_ni),
1844 .dst_pulse_o(main_meas_ctrl_shadowed_lo_update_err)
1845 );
1846 prim_subreg_shadow #(
1847 .DW (10),
1848 .SwAccess(prim_subreg_pkg::SwAccessRW),
1849 .RESVAL (10'h1ea),
1850 .Mubi (1'b0)
1851 ) u_main_meas_ctrl_shadowed_lo (
1852 .clk_i (clk_main_i),
1853 .rst_ni (rst_main_ni),
1854 .rst_shadowed_ni (rst_shadowed_ni),
1855
1856 // from register interface
1857 .re (main_main_meas_ctrl_shadowed_re),
1858 .we (main_main_meas_ctrl_shadowed_gated_we),
1859 .wd (main_main_meas_ctrl_shadowed_wdata[19:10]),
1860
1861 // from internal hardware
1862 .de (1'b0),
1863 .d ('0),
1864
1865 // to internal hardware
1866 .qe (),
1867 .q (reg2hw.main_meas_ctrl_shadowed.lo.q),
1868 .ds (),
1869
1870 // to register interface (read)
1871 .qs (main_main_meas_ctrl_shadowed_lo_qs_int),
1872
1873 // Shadow register phase. Relevant for hwext only.
1874 .phase (),
1875
1876 // Shadow register error conditions
1877 .err_update (async_main_meas_ctrl_shadowed_lo_err_update),
1878 .err_storage (async_main_meas_ctrl_shadowed_lo_err_storage)
1879 );
1880
1881
1882 // R[usb_meas_ctrl_en]: V(False)
1883 logic [0:0] usb_meas_ctrl_en_flds_we;
1884 1/1 assign usb_usb_meas_ctrl_en_qe = |usb_meas_ctrl_en_flds_we;
Tests: T1 T2 T3
1885 // Create REGWEN-gated WE signal
1886 logic usb_usb_meas_ctrl_en_gated_we;
1887 1/1 assign usb_usb_meas_ctrl_en_gated_we = usb_usb_meas_ctrl_en_we & usb_usb_meas_ctrl_en_regwen;
Tests: T9 T1 T10
1888 prim_subreg #(
1889 .DW (4),
1890 .SwAccess(prim_subreg_pkg::SwAccessRW),
1891 .RESVAL (4'h9),
1892 .Mubi (1'b1)
1893 ) u_usb_meas_ctrl_en (
1894 .clk_i (clk_usb_i),
1895 .rst_ni (rst_usb_ni),
1896
1897 // from register interface
1898 .we (usb_usb_meas_ctrl_en_gated_we),
1899 .wd (usb_usb_meas_ctrl_en_wdata[3:0]),
1900
1901 // from internal hardware
1902 .de (hw2reg.usb_meas_ctrl_en.de),
1903 .d (hw2reg.usb_meas_ctrl_en.d),
1904
1905 // to internal hardware
1906 .qe (usb_meas_ctrl_en_flds_we[0]),
1907 .q (reg2hw.usb_meas_ctrl_en.q),
1908 .ds (usb_usb_meas_ctrl_en_ds_int),
1909
1910 // to register interface (read)
1911 .qs (usb_usb_meas_ctrl_en_qs_int)
1912 );
1913
1914
1915 // R[usb_meas_ctrl_shadowed]: V(False)
1916 // Create REGWEN-gated WE signal
1917 logic usb_usb_meas_ctrl_shadowed_gated_we;
1918 1/1 assign usb_usb_meas_ctrl_shadowed_gated_we =
Tests: T9 T1 T10
1919 usb_usb_meas_ctrl_shadowed_we & usb_usb_meas_ctrl_shadowed_regwen;
1920 // F[hi]: 8:0
1921 logic async_usb_meas_ctrl_shadowed_hi_err_update;
1922 logic async_usb_meas_ctrl_shadowed_hi_err_storage;
1923
1924 // storage error is persistent and can be sampled at any time
1925 prim_flop_2sync #(
1926 .Width(1),
1927 .ResetValue('0)
1928 ) u_usb_meas_ctrl_shadowed_hi_err_storage_sync (
1929 .clk_i,
1930 .rst_ni,
1931 .d_i(async_usb_meas_ctrl_shadowed_hi_err_storage),
1932 .q_o(usb_meas_ctrl_shadowed_hi_storage_err)
1933 );
1934
1935 // update error is transient and must be immediately captured
1936 prim_pulse_sync u_usb_meas_ctrl_shadowed_hi_err_update_sync (
1937 .clk_src_i(clk_usb_i),
1938 .rst_src_ni(rst_usb_ni),
1939 .src_pulse_i(async_usb_meas_ctrl_shadowed_hi_err_update),
1940 .clk_dst_i(clk_i),
1941 .rst_dst_ni(rst_ni),
1942 .dst_pulse_o(usb_meas_ctrl_shadowed_hi_update_err)
1943 );
1944 prim_subreg_shadow #(
1945 .DW (9),
1946 .SwAccess(prim_subreg_pkg::SwAccessRW),
1947 .RESVAL (9'hfa),
1948 .Mubi (1'b0)
1949 ) u_usb_meas_ctrl_shadowed_hi (
1950 .clk_i (clk_usb_i),
1951 .rst_ni (rst_usb_ni),
1952 .rst_shadowed_ni (rst_shadowed_ni),
1953
1954 // from register interface
1955 .re (usb_usb_meas_ctrl_shadowed_re),
1956 .we (usb_usb_meas_ctrl_shadowed_gated_we),
1957 .wd (usb_usb_meas_ctrl_shadowed_wdata[8:0]),
1958
1959 // from internal hardware
1960 .de (1'b0),
1961 .d ('0),
1962
1963 // to internal hardware
1964 .qe (),
1965 .q (reg2hw.usb_meas_ctrl_shadowed.hi.q),
1966 .ds (),
1967
1968 // to register interface (read)
1969 .qs (usb_usb_meas_ctrl_shadowed_hi_qs_int),
1970
1971 // Shadow register phase. Relevant for hwext only.
1972 .phase (),
1973
1974 // Shadow register error conditions
1975 .err_update (async_usb_meas_ctrl_shadowed_hi_err_update),
1976 .err_storage (async_usb_meas_ctrl_shadowed_hi_err_storage)
1977 );
1978
1979 // F[lo]: 17:9
1980 logic async_usb_meas_ctrl_shadowed_lo_err_update;
1981 logic async_usb_meas_ctrl_shadowed_lo_err_storage;
1982
1983 // storage error is persistent and can be sampled at any time
1984 prim_flop_2sync #(
1985 .Width(1),
1986 .ResetValue('0)
1987 ) u_usb_meas_ctrl_shadowed_lo_err_storage_sync (
1988 .clk_i,
1989 .rst_ni,
1990 .d_i(async_usb_meas_ctrl_shadowed_lo_err_storage),
1991 .q_o(usb_meas_ctrl_shadowed_lo_storage_err)
1992 );
1993
1994 // update error is transient and must be immediately captured
1995 prim_pulse_sync u_usb_meas_ctrl_shadowed_lo_err_update_sync (
1996 .clk_src_i(clk_usb_i),
1997 .rst_src_ni(rst_usb_ni),
1998 .src_pulse_i(async_usb_meas_ctrl_shadowed_lo_err_update),
1999 .clk_dst_i(clk_i),
2000 .rst_dst_ni(rst_ni),
2001 .dst_pulse_o(usb_meas_ctrl_shadowed_lo_update_err)
2002 );
2003 prim_subreg_shadow #(
2004 .DW (9),
2005 .SwAccess(prim_subreg_pkg::SwAccessRW),
2006 .RESVAL (9'he6),
2007 .Mubi (1'b0)
2008 ) u_usb_meas_ctrl_shadowed_lo (
2009 .clk_i (clk_usb_i),
2010 .rst_ni (rst_usb_ni),
2011 .rst_shadowed_ni (rst_shadowed_ni),
2012
2013 // from register interface
2014 .re (usb_usb_meas_ctrl_shadowed_re),
2015 .we (usb_usb_meas_ctrl_shadowed_gated_we),
2016 .wd (usb_usb_meas_ctrl_shadowed_wdata[17:9]),
2017
2018 // from internal hardware
2019 .de (1'b0),
2020 .d ('0),
2021
2022 // to internal hardware
2023 .qe (),
2024 .q (reg2hw.usb_meas_ctrl_shadowed.lo.q),
2025 .ds (),
2026
2027 // to register interface (read)
2028 .qs (usb_usb_meas_ctrl_shadowed_lo_qs_int),
2029
2030 // Shadow register phase. Relevant for hwext only.
2031 .phase (),
2032
2033 // Shadow register error conditions
2034 .err_update (async_usb_meas_ctrl_shadowed_lo_err_update),
2035 .err_storage (async_usb_meas_ctrl_shadowed_lo_err_storage)
2036 );
2037
2038
2039 // R[recov_err_code]: V(False)
2040 // F[shadow_update_err]: 0:0
2041 prim_subreg #(
2042 .DW (1),
2043 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2044 .RESVAL (1'h0),
2045 .Mubi (1'b0)
2046 ) u_recov_err_code_shadow_update_err (
2047 .clk_i (clk_i),
2048 .rst_ni (rst_ni),
2049
2050 // from register interface
2051 .we (recov_err_code_we),
2052 .wd (recov_err_code_shadow_update_err_wd),
2053
2054 // from internal hardware
2055 .de (hw2reg.recov_err_code.shadow_update_err.de),
2056 .d (hw2reg.recov_err_code.shadow_update_err.d),
2057
2058 // to internal hardware
2059 .qe (),
2060 .q (),
2061 .ds (),
2062
2063 // to register interface (read)
2064 .qs (recov_err_code_shadow_update_err_qs)
2065 );
2066
2067 // F[io_measure_err]: 1:1
2068 prim_subreg #(
2069 .DW (1),
2070 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2071 .RESVAL (1'h0),
2072 .Mubi (1'b0)
2073 ) u_recov_err_code_io_measure_err (
2074 .clk_i (clk_i),
2075 .rst_ni (rst_ni),
2076
2077 // from register interface
2078 .we (recov_err_code_we),
2079 .wd (recov_err_code_io_measure_err_wd),
2080
2081 // from internal hardware
2082 .de (hw2reg.recov_err_code.io_measure_err.de),
2083 .d (hw2reg.recov_err_code.io_measure_err.d),
2084
2085 // to internal hardware
2086 .qe (),
2087 .q (),
2088 .ds (),
2089
2090 // to register interface (read)
2091 .qs (recov_err_code_io_measure_err_qs)
2092 );
2093
2094 // F[io_div2_measure_err]: 2:2
2095 prim_subreg #(
2096 .DW (1),
2097 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2098 .RESVAL (1'h0),
2099 .Mubi (1'b0)
2100 ) u_recov_err_code_io_div2_measure_err (
2101 .clk_i (clk_i),
2102 .rst_ni (rst_ni),
2103
2104 // from register interface
2105 .we (recov_err_code_we),
2106 .wd (recov_err_code_io_div2_measure_err_wd),
2107
2108 // from internal hardware
2109 .de (hw2reg.recov_err_code.io_div2_measure_err.de),
2110 .d (hw2reg.recov_err_code.io_div2_measure_err.d),
2111
2112 // to internal hardware
2113 .qe (),
2114 .q (),
2115 .ds (),
2116
2117 // to register interface (read)
2118 .qs (recov_err_code_io_div2_measure_err_qs)
2119 );
2120
2121 // F[io_div4_measure_err]: 3:3
2122 prim_subreg #(
2123 .DW (1),
2124 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2125 .RESVAL (1'h0),
2126 .Mubi (1'b0)
2127 ) u_recov_err_code_io_div4_measure_err (
2128 .clk_i (clk_i),
2129 .rst_ni (rst_ni),
2130
2131 // from register interface
2132 .we (recov_err_code_we),
2133 .wd (recov_err_code_io_div4_measure_err_wd),
2134
2135 // from internal hardware
2136 .de (hw2reg.recov_err_code.io_div4_measure_err.de),
2137 .d (hw2reg.recov_err_code.io_div4_measure_err.d),
2138
2139 // to internal hardware
2140 .qe (),
2141 .q (),
2142 .ds (),
2143
2144 // to register interface (read)
2145 .qs (recov_err_code_io_div4_measure_err_qs)
2146 );
2147
2148 // F[main_measure_err]: 4:4
2149 prim_subreg #(
2150 .DW (1),
2151 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2152 .RESVAL (1'h0),
2153 .Mubi (1'b0)
2154 ) u_recov_err_code_main_measure_err (
2155 .clk_i (clk_i),
2156 .rst_ni (rst_ni),
2157
2158 // from register interface
2159 .we (recov_err_code_we),
2160 .wd (recov_err_code_main_measure_err_wd),
2161
2162 // from internal hardware
2163 .de (hw2reg.recov_err_code.main_measure_err.de),
2164 .d (hw2reg.recov_err_code.main_measure_err.d),
2165
2166 // to internal hardware
2167 .qe (),
2168 .q (),
2169 .ds (),
2170
2171 // to register interface (read)
2172 .qs (recov_err_code_main_measure_err_qs)
2173 );
2174
2175 // F[usb_measure_err]: 5:5
2176 prim_subreg #(
2177 .DW (1),
2178 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2179 .RESVAL (1'h0),
2180 .Mubi (1'b0)
2181 ) u_recov_err_code_usb_measure_err (
2182 .clk_i (clk_i),
2183 .rst_ni (rst_ni),
2184
2185 // from register interface
2186 .we (recov_err_code_we),
2187 .wd (recov_err_code_usb_measure_err_wd),
2188
2189 // from internal hardware
2190 .de (hw2reg.recov_err_code.usb_measure_err.de),
2191 .d (hw2reg.recov_err_code.usb_measure_err.d),
2192
2193 // to internal hardware
2194 .qe (),
2195 .q (),
2196 .ds (),
2197
2198 // to register interface (read)
2199 .qs (recov_err_code_usb_measure_err_qs)
2200 );
2201
2202 // F[io_timeout_err]: 6:6
2203 prim_subreg #(
2204 .DW (1),
2205 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2206 .RESVAL (1'h0),
2207 .Mubi (1'b0)
2208 ) u_recov_err_code_io_timeout_err (
2209 .clk_i (clk_i),
2210 .rst_ni (rst_ni),
2211
2212 // from register interface
2213 .we (recov_err_code_we),
2214 .wd (recov_err_code_io_timeout_err_wd),
2215
2216 // from internal hardware
2217 .de (hw2reg.recov_err_code.io_timeout_err.de),
2218 .d (hw2reg.recov_err_code.io_timeout_err.d),
2219
2220 // to internal hardware
2221 .qe (),
2222 .q (),
2223 .ds (),
2224
2225 // to register interface (read)
2226 .qs (recov_err_code_io_timeout_err_qs)
2227 );
2228
2229 // F[io_div2_timeout_err]: 7:7
2230 prim_subreg #(
2231 .DW (1),
2232 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2233 .RESVAL (1'h0),
2234 .Mubi (1'b0)
2235 ) u_recov_err_code_io_div2_timeout_err (
2236 .clk_i (clk_i),
2237 .rst_ni (rst_ni),
2238
2239 // from register interface
2240 .we (recov_err_code_we),
2241 .wd (recov_err_code_io_div2_timeout_err_wd),
2242
2243 // from internal hardware
2244 .de (hw2reg.recov_err_code.io_div2_timeout_err.de),
2245 .d (hw2reg.recov_err_code.io_div2_timeout_err.d),
2246
2247 // to internal hardware
2248 .qe (),
2249 .q (),
2250 .ds (),
2251
2252 // to register interface (read)
2253 .qs (recov_err_code_io_div2_timeout_err_qs)
2254 );
2255
2256 // F[io_div4_timeout_err]: 8:8
2257 prim_subreg #(
2258 .DW (1),
2259 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2260 .RESVAL (1'h0),
2261 .Mubi (1'b0)
2262 ) u_recov_err_code_io_div4_timeout_err (
2263 .clk_i (clk_i),
2264 .rst_ni (rst_ni),
2265
2266 // from register interface
2267 .we (recov_err_code_we),
2268 .wd (recov_err_code_io_div4_timeout_err_wd),
2269
2270 // from internal hardware
2271 .de (hw2reg.recov_err_code.io_div4_timeout_err.de),
2272 .d (hw2reg.recov_err_code.io_div4_timeout_err.d),
2273
2274 // to internal hardware
2275 .qe (),
2276 .q (),
2277 .ds (),
2278
2279 // to register interface (read)
2280 .qs (recov_err_code_io_div4_timeout_err_qs)
2281 );
2282
2283 // F[main_timeout_err]: 9:9
2284 prim_subreg #(
2285 .DW (1),
2286 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2287 .RESVAL (1'h0),
2288 .Mubi (1'b0)
2289 ) u_recov_err_code_main_timeout_err (
2290 .clk_i (clk_i),
2291 .rst_ni (rst_ni),
2292
2293 // from register interface
2294 .we (recov_err_code_we),
2295 .wd (recov_err_code_main_timeout_err_wd),
2296
2297 // from internal hardware
2298 .de (hw2reg.recov_err_code.main_timeout_err.de),
2299 .d (hw2reg.recov_err_code.main_timeout_err.d),
2300
2301 // to internal hardware
2302 .qe (),
2303 .q (),
2304 .ds (),
2305
2306 // to register interface (read)
2307 .qs (recov_err_code_main_timeout_err_qs)
2308 );
2309
2310 // F[usb_timeout_err]: 10:10
2311 prim_subreg #(
2312 .DW (1),
2313 .SwAccess(prim_subreg_pkg::SwAccessW1C),
2314 .RESVAL (1'h0),
2315 .Mubi (1'b0)
2316 ) u_recov_err_code_usb_timeout_err (
2317 .clk_i (clk_i),
2318 .rst_ni (rst_ni),
2319
2320 // from register interface
2321 .we (recov_err_code_we),
2322 .wd (recov_err_code_usb_timeout_err_wd),
2323
2324 // from internal hardware
2325 .de (hw2reg.recov_err_code.usb_timeout_err.de),
2326 .d (hw2reg.recov_err_code.usb_timeout_err.d),
2327
2328 // to internal hardware
2329 .qe (),
2330 .q (),
2331 .ds (),
2332
2333 // to register interface (read)
2334 .qs (recov_err_code_usb_timeout_err_qs)
2335 );
2336
2337
2338 // R[fatal_err_code]: V(False)
2339 // F[reg_intg]: 0:0
2340 prim_subreg #(
2341 .DW (1),
2342 .SwAccess(prim_subreg_pkg::SwAccessRO),
2343 .RESVAL (1'h0),
2344 .Mubi (1'b0)
2345 ) u_fatal_err_code_reg_intg (
2346 .clk_i (clk_i),
2347 .rst_ni (rst_ni),
2348
2349 // from register interface
2350 .we (1'b0),
2351 .wd ('0),
2352
2353 // from internal hardware
2354 .de (hw2reg.fatal_err_code.reg_intg.de),
2355 .d (hw2reg.fatal_err_code.reg_intg.d),
2356
2357 // to internal hardware
2358 .qe (),
2359 .q (reg2hw.fatal_err_code.reg_intg.q),
2360 .ds (),
2361
2362 // to register interface (read)
2363 .qs (fatal_err_code_reg_intg_qs)
2364 );
2365
2366 // F[idle_cnt]: 1:1
2367 prim_subreg #(
2368 .DW (1),
2369 .SwAccess(prim_subreg_pkg::SwAccessRO),
2370 .RESVAL (1'h0),
2371 .Mubi (1'b0)
2372 ) u_fatal_err_code_idle_cnt (
2373 .clk_i (clk_i),
2374 .rst_ni (rst_ni),
2375
2376 // from register interface
2377 .we (1'b0),
2378 .wd ('0),
2379
2380 // from internal hardware
2381 .de (hw2reg.fatal_err_code.idle_cnt.de),
2382 .d (hw2reg.fatal_err_code.idle_cnt.d),
2383
2384 // to internal hardware
2385 .qe (),
2386 .q (reg2hw.fatal_err_code.idle_cnt.q),
2387 .ds (),
2388
2389 // to register interface (read)
2390 .qs (fatal_err_code_idle_cnt_qs)
2391 );
2392
2393 // F[shadow_storage_err]: 2:2
2394 prim_subreg #(
2395 .DW (1),
2396 .SwAccess(prim_subreg_pkg::SwAccessRO),
2397 .RESVAL (1'h0),
2398 .Mubi (1'b0)
2399 ) u_fatal_err_code_shadow_storage_err (
2400 .clk_i (clk_i),
2401 .rst_ni (rst_ni),
2402
2403 // from register interface
2404 .we (1'b0),
2405 .wd ('0),
2406
2407 // from internal hardware
2408 .de (hw2reg.fatal_err_code.shadow_storage_err.de),
2409 .d (hw2reg.fatal_err_code.shadow_storage_err.d),
2410
2411 // to internal hardware
2412 .qe (),
2413 .q (reg2hw.fatal_err_code.shadow_storage_err.q),
2414 .ds (),
2415
2416 // to register interface (read)
2417 .qs (fatal_err_code_shadow_storage_err_qs)
2418 );
2419
2420
2421
2422 logic [21:0] addr_hit;
2423 always_comb begin
2424 1/1 addr_hit = '0;
Tests: T4 T5 T29
2425 1/1 addr_hit[ 0] = (reg_addr == CLKMGR_ALERT_TEST_OFFSET);
Tests: T4 T5 T29
2426 1/1 addr_hit[ 1] = (reg_addr == CLKMGR_EXTCLK_CTRL_REGWEN_OFFSET);
Tests: T4 T5 T29
2427 1/1 addr_hit[ 2] = (reg_addr == CLKMGR_EXTCLK_CTRL_OFFSET);
Tests: T4 T5 T29
2428 1/1 addr_hit[ 3] = (reg_addr == CLKMGR_EXTCLK_STATUS_OFFSET);
Tests: T4 T5 T29
2429 1/1 addr_hit[ 4] = (reg_addr == CLKMGR_JITTER_REGWEN_OFFSET);
Tests: T4 T5 T29
2430 1/1 addr_hit[ 5] = (reg_addr == CLKMGR_JITTER_ENABLE_OFFSET);
Tests: T4 T5 T29
2431 1/1 addr_hit[ 6] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET);
Tests: T4 T5 T29
2432 1/1 addr_hit[ 7] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET);
Tests: T4 T5 T29
2433 1/1 addr_hit[ 8] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET);
Tests: T4 T5 T29
2434 1/1 addr_hit[ 9] = (reg_addr == CLKMGR_MEASURE_CTRL_REGWEN_OFFSET);
Tests: T4 T5 T29
2435 1/1 addr_hit[10] = (reg_addr == CLKMGR_IO_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T29
2436 1/1 addr_hit[11] = (reg_addr == CLKMGR_IO_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T29
2437 1/1 addr_hit[12] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T29
2438 1/1 addr_hit[13] = (reg_addr == CLKMGR_IO_DIV2_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T29
2439 1/1 addr_hit[14] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T29
2440 1/1 addr_hit[15] = (reg_addr == CLKMGR_IO_DIV4_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T29
2441 1/1 addr_hit[16] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T29
2442 1/1 addr_hit[17] = (reg_addr == CLKMGR_MAIN_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T29
2443 1/1 addr_hit[18] = (reg_addr == CLKMGR_USB_MEAS_CTRL_EN_OFFSET);
Tests: T4 T5 T29
2444 1/1 addr_hit[19] = (reg_addr == CLKMGR_USB_MEAS_CTRL_SHADOWED_OFFSET);
Tests: T4 T5 T29
2445 1/1 addr_hit[20] = (reg_addr == CLKMGR_RECOV_ERR_CODE_OFFSET);
Tests: T4 T5 T29
2446 1/1 addr_hit[21] = (reg_addr == CLKMGR_FATAL_ERR_CODE_OFFSET);
Tests: T4 T5 T29
2447 end
2448
2449 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T4 T5 T29
2450
2451 // Check sub-word write is permitted
2452 always_comb begin
2453 1/1 wr_err = (reg_we &
Tests: T4 T5 T29
2454 ((addr_hit[ 0] & (|(CLKMGR_PERMIT[ 0] & ~reg_be))) |
2455 (addr_hit[ 1] & (|(CLKMGR_PERMIT[ 1] & ~reg_be))) |
2456 (addr_hit[ 2] & (|(CLKMGR_PERMIT[ 2] & ~reg_be))) |
2457 (addr_hit[ 3] & (|(CLKMGR_PERMIT[ 3] & ~reg_be))) |
2458 (addr_hit[ 4] & (|(CLKMGR_PERMIT[ 4] & ~reg_be))) |
2459 (addr_hit[ 5] & (|(CLKMGR_PERMIT[ 5] & ~reg_be))) |
2460 (addr_hit[ 6] & (|(CLKMGR_PERMIT[ 6] & ~reg_be))) |
2461 (addr_hit[ 7] & (|(CLKMGR_PERMIT[ 7] & ~reg_be))) |
2462 (addr_hit[ 8] & (|(CLKMGR_PERMIT[ 8] & ~reg_be))) |
2463 (addr_hit[ 9] & (|(CLKMGR_PERMIT[ 9] & ~reg_be))) |
2464 (addr_hit[10] & (|(CLKMGR_PERMIT[10] & ~reg_be))) |
2465 (addr_hit[11] & (|(CLKMGR_PERMIT[11] & ~reg_be))) |
2466 (addr_hit[12] & (|(CLKMGR_PERMIT[12] & ~reg_be))) |
2467 (addr_hit[13] & (|(CLKMGR_PERMIT[13] & ~reg_be))) |
2468 (addr_hit[14] & (|(CLKMGR_PERMIT[14] & ~reg_be))) |
2469 (addr_hit[15] & (|(CLKMGR_PERMIT[15] & ~reg_be))) |
2470 (addr_hit[16] & (|(CLKMGR_PERMIT[16] & ~reg_be))) |
2471 (addr_hit[17] & (|(CLKMGR_PERMIT[17] & ~reg_be))) |
2472 (addr_hit[18] & (|(CLKMGR_PERMIT[18] & ~reg_be))) |
2473 (addr_hit[19] & (|(CLKMGR_PERMIT[19] & ~reg_be))) |
2474 (addr_hit[20] & (|(CLKMGR_PERMIT[20] & ~reg_be))) |
2475 (addr_hit[21] & (|(CLKMGR_PERMIT[21] & ~reg_be)))));
2476 end
2477
2478 // Generate write-enables
2479 1/1 assign alert_test_we = addr_hit[0] & reg_we & !reg_error;
Tests: T4 T5 T29
2480
2481 1/1 assign alert_test_recov_fault_wd = reg_wdata[0];
Tests: T4 T5 T29
2482
2483 1/1 assign alert_test_fatal_fault_wd = reg_wdata[1];
Tests: T4 T5 T29
2484 1/1 assign extclk_ctrl_regwen_we = addr_hit[1] & reg_we & !reg_error;
Tests: T4 T5 T29
2485
2486 1/1 assign extclk_ctrl_regwen_wd = reg_wdata[0];
Tests: T4 T5 T29
2487 1/1 assign extclk_ctrl_we = addr_hit[2] & reg_we & !reg_error;
Tests: T4 T5 T29
2488
2489 1/1 assign extclk_ctrl_sel_wd = reg_wdata[3:0];
Tests: T4 T5 T29
2490
2491 1/1 assign extclk_ctrl_hi_speed_sel_wd = reg_wdata[7:4];
Tests: T4 T5 T29
2492 1/1 assign extclk_status_re = addr_hit[3] & reg_re & !reg_error;
Tests: T4 T5 T29
2493 1/1 assign jitter_regwen_we = addr_hit[4] & reg_we & !reg_error;
Tests: T4 T5 T29
2494
2495 1/1 assign jitter_regwen_wd = reg_wdata[0];
Tests: T4 T5 T29
2496 1/1 assign jitter_enable_we = addr_hit[5] & reg_we & !reg_error;
Tests: T4 T5 T29
2497
2498 1/1 assign jitter_enable_wd = reg_wdata[3:0];
Tests: T4 T5 T29
2499 1/1 assign clk_enables_we = addr_hit[6] & reg_we & !reg_error;
Tests: T4 T5 T29
2500
2501 1/1 assign clk_enables_clk_io_div4_peri_en_wd = reg_wdata[0];
Tests: T4 T5 T29
2502
2503 1/1 assign clk_enables_clk_io_div2_peri_en_wd = reg_wdata[1];
Tests: T4 T5 T29
2504
2505 1/1 assign clk_enables_clk_io_peri_en_wd = reg_wdata[2];
Tests: T4 T5 T29
2506
2507 1/1 assign clk_enables_clk_usb_peri_en_wd = reg_wdata[3];
Tests: T4 T5 T29
2508 1/1 assign clk_hints_we = addr_hit[7] & reg_we & !reg_error;
Tests: T4 T5 T29
2509
2510 1/1 assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0];
Tests: T4 T5 T29
2511
2512 1/1 assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1];
Tests: T4 T5 T29
2513
2514 1/1 assign clk_hints_clk_main_kmac_hint_wd = reg_wdata[2];
Tests: T4 T5 T29
2515
2516 1/1 assign clk_hints_clk_main_otbn_hint_wd = reg_wdata[3];
Tests: T4 T5 T29
2517 1/1 assign measure_ctrl_regwen_we = addr_hit[9] & reg_we & !reg_error;
Tests: T4 T5 T29
2518
2519 1/1 assign measure_ctrl_regwen_wd = reg_wdata[0];
Tests: T4 T5 T29
2520 1/1 assign io_meas_ctrl_en_we = addr_hit[10] & reg_we & !reg_error;
Tests: T4 T5 T29
2521
2522 1/1 assign io_meas_ctrl_shadowed_re = addr_hit[11] & reg_re & !reg_error;
Tests: T4 T5 T29
2523 1/1 assign io_meas_ctrl_shadowed_we = addr_hit[11] & reg_we & !reg_error;
Tests: T4 T5 T29
2524
2525
2526 1/1 assign io_div2_meas_ctrl_en_we = addr_hit[12] & reg_we & !reg_error;
Tests: T4 T5 T29
2527
2528 1/1 assign io_div2_meas_ctrl_shadowed_re = addr_hit[13] & reg_re & !reg_error;
Tests: T4 T5 T29
2529 1/1 assign io_div2_meas_ctrl_shadowed_we = addr_hit[13] & reg_we & !reg_error;
Tests: T4 T5 T29
2530
2531
2532 1/1 assign io_div4_meas_ctrl_en_we = addr_hit[14] & reg_we & !reg_error;
Tests: T4 T5 T29
2533
2534 1/1 assign io_div4_meas_ctrl_shadowed_re = addr_hit[15] & reg_re & !reg_error;
Tests: T4 T5 T29
2535 1/1 assign io_div4_meas_ctrl_shadowed_we = addr_hit[15] & reg_we & !reg_error;
Tests: T4 T5 T29
2536
2537
2538 1/1 assign main_meas_ctrl_en_we = addr_hit[16] & reg_we & !reg_error;
Tests: T4 T5 T29
2539
2540 1/1 assign main_meas_ctrl_shadowed_re = addr_hit[17] & reg_re & !reg_error;
Tests: T4 T5 T29
2541 1/1 assign main_meas_ctrl_shadowed_we = addr_hit[17] & reg_we & !reg_error;
Tests: T4 T5 T29
2542
2543
2544 1/1 assign usb_meas_ctrl_en_we = addr_hit[18] & reg_we & !reg_error;
Tests: T4 T5 T29
2545
2546 1/1 assign usb_meas_ctrl_shadowed_re = addr_hit[19] & reg_re & !reg_error;
Tests: T4 T5 T29
2547 1/1 assign usb_meas_ctrl_shadowed_we = addr_hit[19] & reg_we & !reg_error;
Tests: T4 T5 T29
2548
2549
2550 1/1 assign recov_err_code_we = addr_hit[20] & reg_we & !reg_error;
Tests: T4 T5 T29
2551
2552 1/1 assign recov_err_code_shadow_update_err_wd = reg_wdata[0];
Tests: T4 T5 T29
2553
2554 1/1 assign recov_err_code_io_measure_err_wd = reg_wdata[1];
Tests: T4 T5 T29
2555
2556 1/1 assign recov_err_code_io_div2_measure_err_wd = reg_wdata[2];
Tests: T4 T5 T29
2557
2558 1/1 assign recov_err_code_io_div4_measure_err_wd = reg_wdata[3];
Tests: T4 T5 T29
2559
2560 1/1 assign recov_err_code_main_measure_err_wd = reg_wdata[4];
Tests: T4 T5 T29
2561
2562 1/1 assign recov_err_code_usb_measure_err_wd = reg_wdata[5];
Tests: T4 T5 T29
2563
2564 1/1 assign recov_err_code_io_timeout_err_wd = reg_wdata[6];
Tests: T4 T5 T29
2565
2566 1/1 assign recov_err_code_io_div2_timeout_err_wd = reg_wdata[7];
Tests: T4 T5 T29
2567
2568 1/1 assign recov_err_code_io_div4_timeout_err_wd = reg_wdata[8];
Tests: T4 T5 T29
2569
2570 1/1 assign recov_err_code_main_timeout_err_wd = reg_wdata[9];
Tests: T4 T5 T29
2571
2572 1/1 assign recov_err_code_usb_timeout_err_wd = reg_wdata[10];
Tests: T4 T5 T29
2573
2574 // Assign write-enables to checker logic vector.
2575 always_comb begin
2576 1/1 reg_we_check = '0;
Tests: T4 T5 T29
2577 1/1 reg_we_check[0] = alert_test_we;
Tests: T4 T5 T29
2578 1/1 reg_we_check[1] = extclk_ctrl_regwen_we;
Tests: T4 T5 T29
2579 1/1 reg_we_check[2] = extclk_ctrl_gated_we;
Tests: T4 T5 T29
2580 1/1 reg_we_check[3] = 1'b0;
Tests: T4 T5 T29
2581 1/1 reg_we_check[4] = jitter_regwen_we;
Tests: T4 T5 T29
2582 1/1 reg_we_check[5] = jitter_enable_we;
Tests: T4 T5 T29
2583 1/1 reg_we_check[6] = clk_enables_we;
Tests: T4 T5 T29
2584 1/1 reg_we_check[7] = clk_hints_we;
Tests: T4 T5 T29
2585 1/1 reg_we_check[8] = 1'b0;
Tests: T4 T5 T29
2586 1/1 reg_we_check[9] = measure_ctrl_regwen_we;
Tests: T4 T5 T29
2587 1/1 reg_we_check[10] = io_meas_ctrl_en_we;
Tests: T4 T5 T29
2588 1/1 reg_we_check[11] = io_meas_ctrl_shadowed_we;
Tests: T4 T5 T29
2589 1/1 reg_we_check[12] = io_div2_meas_ctrl_en_we;
Tests: T4 T5 T29
2590 1/1 reg_we_check[13] = io_div2_meas_ctrl_shadowed_we;
Tests: T4 T5 T29
2591 1/1 reg_we_check[14] = io_div4_meas_ctrl_en_we;
Tests: T4 T5 T29
2592 1/1 reg_we_check[15] = io_div4_meas_ctrl_shadowed_we;
Tests: T4 T5 T29
2593 1/1 reg_we_check[16] = main_meas_ctrl_en_we;
Tests: T4 T5 T29
2594 1/1 reg_we_check[17] = main_meas_ctrl_shadowed_we;
Tests: T4 T5 T29
2595 1/1 reg_we_check[18] = usb_meas_ctrl_en_we;
Tests: T4 T5 T29
2596 1/1 reg_we_check[19] = usb_meas_ctrl_shadowed_we;
Tests: T4 T5 T29
2597 1/1 reg_we_check[20] = recov_err_code_we;
Tests: T4 T5 T29
2598 1/1 reg_we_check[21] = 1'b0;
Tests: T4 T5 T29
2599 end
2600
2601 // Read data return
2602 always_comb begin
2603 1/1 reg_rdata_next = '0;
Tests: T4 T5 T6
2604 1/1 unique case (1'b1)
Tests: T4 T5 T6
2605 addr_hit[0]: begin
2606 1/1 reg_rdata_next[0] = '0;
Tests: T4 T29 T30
2607 1/1 reg_rdata_next[1] = '0;
Tests: T4 T29 T30
2608 end
2609
2610 addr_hit[1]: begin
2611 1/1 reg_rdata_next[0] = extclk_ctrl_regwen_qs;
Tests: T4 T5 T29
2612 end
2613
2614 addr_hit[2]: begin
2615 1/1 reg_rdata_next[3:0] = extclk_ctrl_sel_qs;
Tests: T4 T5 T29
2616 1/1 reg_rdata_next[7:4] = extclk_ctrl_hi_speed_sel_qs;
Tests: T4 T5 T29
2617 end
2618
2619 addr_hit[3]: begin
2620 1/1 reg_rdata_next[3:0] = extclk_status_qs;
Tests: T4 T5 T29
2621 end
2622
2623 addr_hit[4]: begin
2624 1/1 reg_rdata_next[0] = jitter_regwen_qs;
Tests: T4 T29 T30
2625 end
2626
2627 addr_hit[5]: begin
2628 1/1 reg_rdata_next[3:0] = jitter_enable_qs;
Tests: T4 T29 T30
2629 end
2630
2631 addr_hit[6]: begin
2632 1/1 reg_rdata_next[0] = clk_enables_clk_io_div4_peri_en_qs;
Tests: T4 T5 T29
2633 1/1 reg_rdata_next[1] = clk_enables_clk_io_div2_peri_en_qs;
Tests: T4 T5 T29
2634 1/1 reg_rdata_next[2] = clk_enables_clk_io_peri_en_qs;
Tests: T4 T5 T29
2635 1/1 reg_rdata_next[3] = clk_enables_clk_usb_peri_en_qs;
Tests: T4 T5 T29
2636 end
2637
2638 addr_hit[7]: begin
2639 1/1 reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
Tests: T4 T29 T30
2640 1/1 reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
Tests: T4 T29 T30
2641 1/1 reg_rdata_next[2] = clk_hints_clk_main_kmac_hint_qs;
Tests: T4 T29 T30
2642 1/1 reg_rdata_next[3] = clk_hints_clk_main_otbn_hint_qs;
Tests: T4 T29 T30
2643 end
2644
2645 addr_hit[8]: begin
2646 1/1 reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
Tests: T4 T29 T30
2647 1/1 reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
Tests: T4 T29 T30
2648 1/1 reg_rdata_next[2] = clk_hints_status_clk_main_kmac_val_qs;
Tests: T4 T29 T30
2649 1/1 reg_rdata_next[3] = clk_hints_status_clk_main_otbn_val_qs;
Tests: T4 T29 T30
2650 end
2651
2652 addr_hit[9]: begin
2653 1/1 reg_rdata_next[0] = measure_ctrl_regwen_qs;
Tests: T4 T6 T29
2654 end
2655
2656 addr_hit[10]: begin
2657 1/1 reg_rdata_next = DW'(io_meas_ctrl_en_qs);
Tests: T4 T5 T29
2658 end
2659 addr_hit[11]: begin
2660 1/1 reg_rdata_next = DW'(io_meas_ctrl_shadowed_qs);
Tests: T4 T5 T29
2661 end
2662 addr_hit[12]: begin
2663 1/1 reg_rdata_next = DW'(io_div2_meas_ctrl_en_qs);
Tests: T4 T5 T29
2664 end
2665 addr_hit[13]: begin
2666 1/1 reg_rdata_next = DW'(io_div2_meas_ctrl_shadowed_qs);
Tests: T4 T5 T29
2667 end
2668 addr_hit[14]: begin
2669 1/1 reg_rdata_next = DW'(io_div4_meas_ctrl_en_qs);
Tests: T4 T5 T29
2670 end
2671 addr_hit[15]: begin
2672 1/1 reg_rdata_next = DW'(io_div4_meas_ctrl_shadowed_qs);
Tests: T4 T29 T30
2673 end
2674 addr_hit[16]: begin
2675 1/1 reg_rdata_next = DW'(main_meas_ctrl_en_qs);
Tests: T4 T29 T30
2676 end
2677 addr_hit[17]: begin
2678 1/1 reg_rdata_next = DW'(main_meas_ctrl_shadowed_qs);
Tests: T4 T5 T29
2679 end
2680 addr_hit[18]: begin
2681 1/1 reg_rdata_next = DW'(usb_meas_ctrl_en_qs);
Tests: T4 T29 T30
2682 end
2683 addr_hit[19]: begin
2684 1/1 reg_rdata_next = DW'(usb_meas_ctrl_shadowed_qs);
Tests: T4 T5 T29
2685 end
2686 addr_hit[20]: begin
2687 1/1 reg_rdata_next[0] = recov_err_code_shadow_update_err_qs;
Tests: T4 T5 T29
2688 1/1 reg_rdata_next[1] = recov_err_code_io_measure_err_qs;
Tests: T4 T5 T29
2689 1/1 reg_rdata_next[2] = recov_err_code_io_div2_measure_err_qs;
Tests: T4 T5 T29
2690 1/1 reg_rdata_next[3] = recov_err_code_io_div4_measure_err_qs;
Tests: T4 T5 T29
2691 1/1 reg_rdata_next[4] = recov_err_code_main_measure_err_qs;
Tests: T4 T5 T29
2692 1/1 reg_rdata_next[5] = recov_err_code_usb_measure_err_qs;
Tests: T4 T5 T29
2693 1/1 reg_rdata_next[6] = recov_err_code_io_timeout_err_qs;
Tests: T4 T5 T29
2694 1/1 reg_rdata_next[7] = recov_err_code_io_div2_timeout_err_qs;
Tests: T4 T5 T29
2695 1/1 reg_rdata_next[8] = recov_err_code_io_div4_timeout_err_qs;
Tests: T4 T5 T29
2696 1/1 reg_rdata_next[9] = recov_err_code_main_timeout_err_qs;
Tests: T4 T5 T29
2697 1/1 reg_rdata_next[10] = recov_err_code_usb_timeout_err_qs;
Tests: T4 T5 T29
2698 end
2699
2700 addr_hit[21]: begin
2701 1/1 reg_rdata_next[0] = fatal_err_code_reg_intg_qs;
Tests: T4 T5 T29
2702 1/1 reg_rdata_next[1] = fatal_err_code_idle_cnt_qs;
Tests: T4 T5 T29
2703 1/1 reg_rdata_next[2] = fatal_err_code_shadow_storage_err_qs;
Tests: T4 T5 T29
2704 end
2705
2706 default: begin
2707 reg_rdata_next = '1;
2708 end
2709 endcase
2710 end
2711
2712 // shadow busy
2713 logic shadow_busy;
2714 logic rst_done;
2715 logic shadow_rst_done;
2716 always_ff @(posedge clk_i or negedge rst_ni) begin
2717 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
2718 1/1 rst_done <= '0;
Tests: T4 T5 T6
2719 end else begin
2720 1/1 rst_done <= 1'b1;
Tests: T4 T5 T6
2721 end
2722 end
2723
2724 always_ff @(posedge clk_i or negedge rst_shadowed_ni) begin
2725 1/1 if (!rst_shadowed_ni) begin
Tests: T4 T5 T6
2726 1/1 shadow_rst_done <= '0;
Tests: T4 T5 T6
2727 end else begin
2728 1/1 shadow_rst_done <= 1'b1;
Tests: T4 T5 T6
2729 end
2730 end
2731
2732 // both shadow and normal resets have been released
2733 1/1 assign shadow_busy = ~(rst_done & shadow_rst_done);
Tests: T4 T5 T6
2734
2735 // Collect up storage and update errors
2736 1/1 assign shadowed_storage_err_o = |{
Tests: T87 T88 T89
2737 io_meas_ctrl_shadowed_hi_storage_err,
2738 io_meas_ctrl_shadowed_lo_storage_err,
2739 io_div2_meas_ctrl_shadowed_hi_storage_err,
2740 io_div2_meas_ctrl_shadowed_lo_storage_err,
2741 io_div4_meas_ctrl_shadowed_hi_storage_err,
2742 io_div4_meas_ctrl_shadowed_lo_storage_err,
2743 main_meas_ctrl_shadowed_hi_storage_err,
2744 main_meas_ctrl_shadowed_lo_storage_err,
2745 usb_meas_ctrl_shadowed_hi_storage_err,
2746 usb_meas_ctrl_shadowed_lo_storage_err
2747 };
2748 1/1 assign shadowed_update_err_o = |{
Tests: T87 T88 T89
2749 io_meas_ctrl_shadowed_hi_update_err,
2750 io_meas_ctrl_shadowed_lo_update_err,
2751 io_div2_meas_ctrl_shadowed_hi_update_err,
2752 io_div2_meas_ctrl_shadowed_lo_update_err,
2753 io_div4_meas_ctrl_shadowed_hi_update_err,
2754 io_div4_meas_ctrl_shadowed_lo_update_err,
2755 main_meas_ctrl_shadowed_hi_update_err,
2756 main_meas_ctrl_shadowed_lo_update_err,
2757 usb_meas_ctrl_shadowed_hi_update_err,
2758 usb_meas_ctrl_shadowed_lo_update_err
2759 };
2760
2761 // register busy
2762 logic reg_busy_sel;
2763 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T4 T5 T6
2764 always_comb begin
2765 1/1 reg_busy_sel = '0;
Tests: T4 T5 T29
2766 1/1 unique case (1'b1)
Tests: T4 T5 T29
2767 addr_hit[10]: begin
2768 1/1 reg_busy_sel = io_meas_ctrl_en_busy;
Tests: T4 T5 T29
2769 end
2770 addr_hit[11]: begin
2771 1/1 reg_busy_sel = io_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2772 end
2773 addr_hit[12]: begin
2774 1/1 reg_busy_sel = io_div2_meas_ctrl_en_busy;
Tests: T4 T5 T29
2775 end
2776 addr_hit[13]: begin
2777 1/1 reg_busy_sel = io_div2_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2778 end
2779 addr_hit[14]: begin
2780 1/1 reg_busy_sel = io_div4_meas_ctrl_en_busy;
Tests: T4 T5 T29
2781 end
2782 addr_hit[15]: begin
2783 1/1 reg_busy_sel = io_div4_meas_ctrl_shadowed_busy;
Tests: T4 T29 T30
2784 end
2785 addr_hit[16]: begin
2786 1/1 reg_busy_sel = main_meas_ctrl_en_busy;
Tests: T4 T29 T30
2787 end
2788 addr_hit[17]: begin
2789 1/1 reg_busy_sel = main_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2790 end
2791 addr_hit[18]: begin
2792 1/1 reg_busy_sel = usb_meas_ctrl_en_busy;
Tests: T4 T29 T30
2793 end
2794 addr_hit[19]: begin
2795 1/1 reg_busy_sel = usb_meas_ctrl_shadowed_busy;
Tests: T4 T5 T29
2796 end
2797 default: begin
2798 reg_busy_sel = '0;
2799 end
2800 endcase
2801 end
2802
2803
2804 // Unused signal tieoff
2805
2806 // wdata / byte enable are not always fully used
2807 // add a blanket unused statement to handle lint waivers
2808 logic unused_wdata;
2809 logic unused_be;
2810 1/1 assign unused_wdata = ^reg_wdata;
Tests: T4 T5 T29
2811 1/1 assign unused_be = ^reg_be;
Tests: T4 T5 T29