Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72109756 1 T4 3318 T5 1836 T6 2132
auto[1] 276714 1 T6 120 T27 60 T29 396


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72075834 1 T4 3318 T5 1836 T6 2186
auto[1] 310636 1 T6 66 T27 450 T29 226


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72051608 1 T4 3318 T5 1836 T6 2152
auto[1] 334862 1 T6 100 T27 556 T29 336


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 70985888 1 T4 3318 T5 1836 T6 1940
auto[1] 1400582 1 T6 312 T27 3316 T29 2660


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 53401386 1 T4 3318 T5 162 T6 2252
auto[1] 18985084 1 T5 1674 T27 392 T30 2184


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 51966240 1 T4 3318 T5 162 T6 1880
auto[0] auto[0] auto[0] auto[0] auto[1] 18748416 1 T5 1674 T27 20 T30 2184
auto[0] auto[0] auto[0] auto[1] auto[0] 22674 1 T6 4 T32 32 T42 164
auto[0] auto[0] auto[0] auto[1] auto[1] 5644 1 T32 4 T42 38 T112 36
auto[0] auto[0] auto[1] auto[0] auto[0] 1010732 1 T6 206 T27 2596 T29 2204
auto[0] auto[0] auto[1] auto[0] auto[1] 156392 1 T27 336 T32 214 T42 112
auto[0] auto[0] auto[1] auto[1] auto[0] 32128 1 T6 22 T29 86 T32 76
auto[0] auto[0] auto[1] auto[1] auto[1] 8338 1 T32 52 T43 46 T111 70
auto[0] auto[1] auto[0] auto[0] auto[0] 60030 1 T6 2 T42 6 T111 28
auto[0] auto[1] auto[0] auto[0] auto[1] 1112 1 T112 10 T205 2 T70 50
auto[0] auto[1] auto[0] auto[1] auto[0] 10020 1 T6 38 T42 62 T25 68
auto[0] auto[1] auto[0] auto[1] auto[1] 2890 1 T112 48 T205 40 T70 54
auto[0] auto[1] auto[1] auto[0] auto[0] 8332 1 T27 52 T29 64 T32 28
auto[0] auto[1] auto[1] auto[0] auto[1] 1532 1 T27 36 T32 6 T75 8
auto[0] auto[1] auto[1] auto[1] auto[0] 13756 1 T29 52 T32 86 T111 58
auto[0] auto[1] auto[1] auto[1] auto[1] 3372 1 T32 40 T75 68 T70 66
auto[1] auto[0] auto[0] auto[0] auto[0] 24448 1 T6 16 T27 74 T29 10
auto[1] auto[0] auto[0] auto[0] auto[1] 2794 1 T32 2 T42 36 T112 18
auto[1] auto[0] auto[0] auto[1] auto[0] 26392 1 T29 72 T32 158 T42 200
auto[1] auto[0] auto[0] auto[1] auto[1] 6330 1 T32 66 T42 52 T112 74
auto[1] auto[0] auto[1] auto[0] auto[0] 18172 1 T6 2 T27 120 T29 30
auto[1] auto[0] auto[1] auto[0] auto[1] 4526 1 T75 34 T113 10 T206 42
auto[1] auto[0] auto[1] auto[1] auto[0] 33648 1 T6 56 T29 114 T110 118
auto[1] auto[0] auto[1] auto[1] auto[1] 8960 1 T75 112 T113 66 T25 62
auto[1] auto[1] auto[0] auto[0] auto[0] 64572 1 T27 186 T32 2 T42 102
auto[1] auto[1] auto[0] auto[0] auto[1] 4826 1 T32 8 T42 40 T72 40
auto[1] auto[1] auto[0] auto[1] auto[0] 30408 1 T32 38 T42 134 T43 76
auto[1] auto[1] auto[0] auto[1] auto[1] 9092 1 T32 36 T42 156 T112 64
auto[1] auto[1] auto[1] auto[0] auto[0] 29384 1 T6 26 T27 116 T29 38
auto[1] auto[1] auto[1] auto[0] auto[1] 8248 1 T32 8 T42 28 T43 4
auto[1] auto[1] auto[1] auto[1] auto[0] 50450 1 T27 60 T29 72 T32 164
auto[1] auto[1] auto[1] auto[1] auto[1] 12612 1 T43 112 T113 52 T171 64

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