Group : clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::fatal_err_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
idle_cnt_cp 2 0 2 100.00 100 1 1 2
reg_integ_cp 2 0 2 100.00 100 1 1 2
shadow_storage_cp 2 0 2 100.00 100 1 1 2


Summary for Variable idle_cnt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for idle_cnt_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2910 1 T4 1 T5 1 T6 1
auto[1] 360 1 T62 80 T63 80 T65 80


Summary for Variable reg_integ_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for reg_integ_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2860 1 T4 1 T5 1 T6 1
auto[1] 410 1 T62 20 T63 20 T65 20


Summary for Variable shadow_storage_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for shadow_storage_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 2910 1 T4 1 T5 1 T6 1
auto[1] 360 1 T78 7 T79 8 T80 6