Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72457896 1 T4 3668 T5 2732 T6 3260
auto[1] 274108 1 T5 366 T32 1166 T34 60


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72426604 1 T4 3668 T5 2690 T6 3260
auto[1] 305400 1 T5 408 T32 558 T33 128


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 72366662 1 T4 3668 T5 2706 T6 3260
auto[1] 365342 1 T5 392 T32 716 T33 174


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 70955062 1 T4 3668 T5 472 T6 3260
auto[1] 1776942 1 T5 2626 T32 364 T33 3150


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 51901222 1 T4 3650 T5 2798 T6 2940
auto[1] 20830782 1 T4 18 T5 300 T6 320


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 50457828 1 T4 3650 T5 254 T6 2940
auto[0] auto[0] auto[0] auto[0] auto[1] 20212262 1 T4 18 T6 320 T31 2074
auto[0] auto[0] auto[0] auto[1] auto[0] 22956 1 T5 26 T32 330 T35 38
auto[0] auto[0] auto[0] auto[1] auto[1] 5734 1 T32 130 T20 34 T21 8
auto[0] auto[0] auto[1] auto[0] auto[0] 1006430 1 T5 2106 T32 166 T33 2642
auto[0] auto[0] auto[1] auto[0] auto[1] 540972 1 T5 150 T33 364 T35 1508
auto[0] auto[0] auto[1] auto[1] auto[0] 31154 1 T5 12 T32 30 T35 44
auto[0] auto[0] auto[1] auto[1] auto[1] 7986 1 T5 30 T35 4 T76 18
auto[0] auto[1] auto[0] auto[0] auto[0] 46386 1 T5 18 T33 16 T20 6
auto[0] auto[1] auto[0] auto[0] auto[1] 1348 1 T21 6 T182 16 T183 16
auto[0] auto[1] auto[0] auto[1] auto[0] 8564 1 T5 58 T20 58 T85 140
auto[0] auto[1] auto[0] auto[1] auto[1] 1982 1 T21 66 T183 66 T17 54
auto[0] auto[1] auto[1] auto[0] auto[0] 6272 1 T32 2 T34 24 T35 2
auto[0] auto[1] auto[1] auto[0] auto[1] 1670 1 T5 10 T21 8 T88 12
auto[0] auto[1] auto[1] auto[1] auto[0] 12686 1 T32 100 T35 56 T19 124
auto[0] auto[1] auto[1] auto[1] auto[1] 2432 1 T5 42 T21 90 T13 56
auto[1] auto[0] auto[0] auto[0] auto[0] 39788 1 T5 64 T32 20 T34 34
auto[1] auto[0] auto[0] auto[0] auto[1] 3010 1 T20 4 T21 64 T149 68
auto[1] auto[0] auto[0] auto[1] auto[0] 27010 1 T32 174 T19 66 T20 148
auto[1] auto[0] auto[0] auto[1] auto[1] 4980 1 T20 62 T149 70 T91 74
auto[1] auto[0] auto[1] auto[0] auto[0] 19750 1 T5 48 T32 2 T33 46
auto[1] auto[0] auto[1] auto[0] auto[1] 5262 1 T33 16 T21 12 T26 22
auto[1] auto[0] auto[1] auto[1] auto[0] 33070 1 T32 64 T35 286 T19 56
auto[1] auto[0] auto[1] auto[1] auto[1] 8412 1 T21 72 T26 60 T88 60
auto[1] auto[1] auto[0] auto[0] auto[0] 76730 1 T5 10 T32 118 T33 30
auto[1] auto[1] auto[0] auto[0] auto[1] 4720 1 T20 18 T85 16 T87 50
auto[1] auto[1] auto[0] auto[1] auto[0] 32502 1 T5 42 T32 338 T35 106
auto[1] auto[1] auto[0] auto[1] auto[1] 9262 1 T20 70 T85 62 T91 84
auto[1] auto[1] auto[1] auto[0] auto[0] 28422 1 T5 60 T33 66 T34 22
auto[1] auto[1] auto[1] auto[0] auto[1] 7046 1 T5 12 T33 16 T35 2
auto[1] auto[1] auto[1] auto[1] auto[0] 51674 1 T5 100 T34 60 T35 62
auto[1] auto[1] auto[1] auto[1] auto[1] 13704 1 T5 56 T35 54 T76 48

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