Unified Coverage Report :: Group :: clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv

---

Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
byp_req_cp	2	0	2	100.00	100	1	1	2
csr_low_speed_cp	2	0	2	100.00	100	1	1	2
csr_sel_cp	2	0	2	100.00	100	1	1	2
hw_debug_en_cp	2	0	2	100.00	100	1	1	2
scanmode_cp	2	0	2	100.00	100	1	1	2

Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
extclk_cross	32	0	32	100.00	100	1	1	0

Summary for Variable byp_req_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for byp_req_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72597460

1

T4

3034

T5

3324

T6

2614

auto[1]

295588

1

T4

764

T30

484

T31

192

---

Summary for Variable csr_low_speed_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_low_speed_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72593780

1

T4

3422

T5

3324

T6

2614

auto[1]

299268

1

T4

376

T30

388

T31

162

---

Summary for Variable csr_sel_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for csr_sel_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72539472

1

T4

3214

T5

3324

T6

2614

auto[1]

353576

1

T4

584

T30

256

T31

102

---

Summary for Variable hw_debug_en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hw_debug_en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

71034382

1

T4

504

T5

3324

T6

2614

auto[1]

1858666

1

T4

3294

T30

1888

T31

286

---

Summary for Variable scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for scanmode_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49199710

1

T4

3522

T5

3198

T6

2482

auto[1]

23693338

1

T4

276

T5

126

T6

132

---

Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for extclk_cross

Bins

csr_sel_cp

csr_low_speed_cp

hw_debug_en_cp

byp_req_cp

scanmode_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

47527710

1

T4

216

T5

3198

T6

2482

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

23270548

1

T4

84

T5

126

T6

132

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

21772

1

T4

48

T30

72

T31

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5248

1

T30

24

T43

20

T24

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

1254296

1

T4

2448

T30

1778

T31

130

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

341536

1

T4

54

T32

236

T87

84

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

38926

1

T4

150

T30

34

T31

34

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8804

1

T4

12

T55

22

T155

28

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

29882

1

T30

18

T43

4

T20

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

1388

1

T30

30

T61

2

T24

10

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8872

1

T30

64

T43

48

T20

48

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2152

1

T30

64

T61

54

T24

68

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

7520

1

T4

44

T30

16

T31

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1900

1

T32

32

T155

76

T185

8

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

14810

1

T4

158

T31

58

T87

108

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4108

1

T155

84

T185

50

T186

60

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

19466

1

T4

22

T32

36

T87

14

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

2716

1

T87

8

T58

24

T43

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

22930

1

T4

52

T56

68

T58

52

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5102

1

T43

66

T26

72

T187

56

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

20048

1

T4

66

T30

2

T32

58

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5510

1

T32

36

T61

30

T24

36

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

38926

1

T4

270

T30

58

T58

70

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10242

1

T61

46

T55

54

T155

86

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

70682

1

T4

40

T30

28

T31

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

3988

1

T4

42

T61

8

T43

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

34378

1

T30

168

T31

38

T87

46

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

7548

1

T43

64

T26

88

T155

60

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32258

1

T4

8

T31

2

T32

62

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8012

1

T4

10

T87

16

T20

28

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

57234

1

T31

60

T87

42

T58

138

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14536

1

T4

74

T20

50

T55

114