Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 65976032 1 T4 3374 T5 3166 T6 2116
auto[1] 258968 1 T5 840 T32 192 T33 90


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 65938100 1 T4 3374 T5 3546 T6 2116
auto[1] 296900 1 T5 460 T32 182 T33 70


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 65904760 1 T4 3374 T5 3130 T6 2116
auto[1] 330240 1 T5 876 T32 284 T33 70


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 64996200 1 T4 3374 T5 972 T6 2116
auto[1] 1238800 1 T5 3034 T32 2614 T34 1674


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 47199196 1 T4 3350 T5 3744 T6 2092
auto[1] 19035804 1 T4 24 T5 262 T6 24


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 45934432 1 T4 3350 T5 538 T6 2092
auto[0] auto[0] auto[0] auto[0] auto[1] 18789720 1 T4 24 T5 80 T6 24
auto[0] auto[0] auto[0] auto[1] auto[0] 19098 1 T5 22 T33 34 T34 22
auto[0] auto[0] auto[0] auto[1] auto[1] 5174 1 T34 20 T119 76 T25 4
auto[0] auto[0] auto[1] auto[0] auto[0] 840802 1 T5 2212 T32 142 T34 1356
auto[0] auto[0] auto[1] auto[0] auto[1] 175420 1 T5 60 T32 2186 T34 106
auto[0] auto[0] auto[1] auto[1] auto[0] 31326 1 T5 142 T32 46 T34 6
auto[0] auto[0] auto[1] auto[1] auto[1] 6648 1 T5 6 T32 6 T34 14
auto[0] auto[1] auto[0] auto[0] auto[0] 64240 1 T5 8 T59 8 T90 26
auto[0] auto[1] auto[0] auto[0] auto[1] 1332 1 T119 6 T61 20 T17 62
auto[0] auto[1] auto[0] auto[1] auto[0] 7468 1 T5 62 T93 50 T26 66
auto[0] auto[1] auto[0] auto[1] auto[1] 2572 1 T119 116 T61 70 T196 80
auto[0] auto[1] auto[1] auto[0] auto[0] 7444 1 T32 44 T71 34 T59 10
auto[0] auto[1] auto[1] auto[0] auto[1] 1714 1 T71 16 T61 20 T82 12
auto[0] auto[1] auto[1] auto[1] auto[0] 13894 1 T87 174 T61 70 T105 52
auto[0] auto[1] auto[1] auto[1] auto[1] 3476 1 T71 52 T61 64 T18 40
auto[1] auto[0] auto[0] auto[0] auto[0] 42590 1 T5 68 T32 58 T34 18
auto[1] auto[0] auto[0] auto[0] auto[1] 2956 1 T5 54 T119 30 T93 36
auto[1] auto[0] auto[0] auto[1] auto[0] 22698 1 T5 98 T34 48 T71 56
auto[1] auto[0] auto[0] auto[1] auto[1] 5342 1 T65 84 T197 70 T198 38
auto[1] auto[0] auto[1] auto[0] auto[0] 16612 1 T5 28 T32 12 T34 16
auto[1] auto[0] auto[1] auto[0] auto[1] 5032 1 T5 10 T34 22 T59 8
auto[1] auto[0] auto[1] auto[1] auto[0] 31954 1 T5 176 T32 76 T34 44
auto[1] auto[0] auto[1] auto[1] auto[1] 8296 1 T5 52 T34 58 T87 140
auto[1] auto[1] auto[0] auto[0] auto[0] 56246 1 T5 42 T32 36 T33 14
auto[1] auto[1] auto[0] auto[0] auto[1] 3958 1 T34 22 T119 48 T93 34
auto[1] auto[1] auto[0] auto[1] auto[0] 31588 1 T33 56 T58 62 T119 240
auto[1] auto[1] auto[0] auto[1] auto[1] 6786 1 T34 54 T119 220 T93 66
auto[1] auto[1] auto[1] auto[0] auto[0] 27040 1 T5 66 T34 52 T71 56
auto[1] auto[1] auto[1] auto[0] auto[1] 6494 1 T32 38 T71 8 T59 22
auto[1] auto[1] auto[1] auto[1] auto[0] 51764 1 T5 282 T71 208 T53 78
auto[1] auto[1] auto[1] auto[1] auto[1] 10884 1 T32 64 T71 60 T90 58

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