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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80


Total test records in report: 963
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T805 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3624122197 Sep 18 06:14:18 AM UTC 24 Sep 18 06:14:52 AM UTC 24 3962024767 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3537899141 Sep 18 06:14:04 AM UTC 24 Sep 18 06:14:54 AM UTC 24 3666786186 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3330798462 Sep 18 06:14:18 AM UTC 24 Sep 18 06:14:58 AM UTC 24 4420145966 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.546466597 Sep 18 06:14:05 AM UTC 24 Sep 18 06:15:34 AM UTC 24 9356000239 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.2889091346 Sep 18 06:14:05 AM UTC 24 Sep 18 06:15:40 AM UTC 24 15962290692 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.882410836 Sep 18 06:14:31 AM UTC 24 Sep 18 06:16:06 AM UTC 24 14134906179 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.18169717 Sep 18 06:14:18 AM UTC 24 Sep 18 06:16:16 AM UTC 24 5681777719 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.2503127669 Sep 18 06:13:38 AM UTC 24 Sep 18 06:16:51 AM UTC 24 41313619295 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3689692658 Sep 18 06:09:05 AM UTC 24 Sep 18 06:09:08 AM UTC 24 73256330 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2343801114 Sep 18 06:09:05 AM UTC 24 Sep 18 06:09:09 AM UTC 24 158487251 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.2200230600 Sep 18 06:09:08 AM UTC 24 Sep 18 06:09:12 AM UTC 24 38175580 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.4063895739 Sep 18 06:09:10 AM UTC 24 Sep 18 06:09:12 AM UTC 24 14360357 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.129799866 Sep 18 06:09:10 AM UTC 24 Sep 18 06:09:12 AM UTC 24 21927137 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.955064324 Sep 18 06:09:10 AM UTC 24 Sep 18 06:09:14 AM UTC 24 346205116 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1245752957 Sep 18 06:09:12 AM UTC 24 Sep 18 06:09:15 AM UTC 24 22552779 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.4021374287 Sep 18 06:09:12 AM UTC 24 Sep 18 06:09:15 AM UTC 24 106555610 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4174627594 Sep 18 06:09:12 AM UTC 24 Sep 18 06:09:15 AM UTC 24 19423573 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.238762463 Sep 18 06:09:12 AM UTC 24 Sep 18 06:09:15 AM UTC 24 61652234 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1092768964 Sep 18 06:09:13 AM UTC 24 Sep 18 06:09:17 AM UTC 24 167281914 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.1456914407 Sep 18 06:09:16 AM UTC 24 Sep 18 06:09:18 AM UTC 24 28936790 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1761269470 Sep 18 06:09:16 AM UTC 24 Sep 18 06:09:18 AM UTC 24 29765778 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.57209510 Sep 18 06:09:15 AM UTC 24 Sep 18 06:09:18 AM UTC 24 61739250 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3707792670 Sep 18 06:09:14 AM UTC 24 Sep 18 06:09:18 AM UTC 24 145776967 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.2208422658 Sep 18 06:09:16 AM UTC 24 Sep 18 06:09:18 AM UTC 24 20014391 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1176069238 Sep 18 06:09:17 AM UTC 24 Sep 18 06:09:20 AM UTC 24 67824116 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.818599772 Sep 18 06:09:15 AM UTC 24 Sep 18 06:09:21 AM UTC 24 354333218 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1823910659 Sep 18 06:09:19 AM UTC 24 Sep 18 06:09:21 AM UTC 24 42989247 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2738456007 Sep 18 06:09:19 AM UTC 24 Sep 18 06:09:22 AM UTC 24 40778127 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1574348766 Sep 18 06:09:19 AM UTC 24 Sep 18 06:09:22 AM UTC 24 100042464 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2070606162 Sep 18 06:09:19 AM UTC 24 Sep 18 06:09:23 AM UTC 24 289870988 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.2058965354 Sep 18 06:09:21 AM UTC 24 Sep 18 06:09:23 AM UTC 24 14403278 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2839838338 Sep 18 06:09:21 AM UTC 24 Sep 18 06:09:23 AM UTC 24 17321585 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.2268019930 Sep 18 06:09:21 AM UTC 24 Sep 18 06:09:23 AM UTC 24 52320142 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.360602347 Sep 18 06:09:12 AM UTC 24 Sep 18 06:09:23 AM UTC 24 263450398 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3411515886 Sep 18 06:09:21 AM UTC 24 Sep 18 06:09:24 AM UTC 24 53843976 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.2922518887 Sep 18 06:09:21 AM UTC 24 Sep 18 06:09:25 AM UTC 24 101635306 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3319202434 Sep 18 06:09:22 AM UTC 24 Sep 18 06:09:25 AM UTC 24 29625152 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3770299424 Sep 18 06:09:23 AM UTC 24 Sep 18 06:09:25 AM UTC 24 68215211 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.2555635119 Sep 18 06:09:24 AM UTC 24 Sep 18 06:09:26 AM UTC 24 16264839 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3913733235 Sep 18 06:09:23 AM UTC 24 Sep 18 06:09:26 AM UTC 24 77018155 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1614963759 Sep 18 06:09:24 AM UTC 24 Sep 18 06:09:26 AM UTC 24 29246824 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.108351717 Sep 18 06:09:22 AM UTC 24 Sep 18 06:09:26 AM UTC 24 70254185 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3300583229 Sep 18 06:09:16 AM UTC 24 Sep 18 06:09:26 AM UTC 24 931986282 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2911315441 Sep 18 06:09:24 AM UTC 24 Sep 18 06:09:27 AM UTC 24 114880908 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.4138467820 Sep 18 06:09:25 AM UTC 24 Sep 18 06:09:27 AM UTC 24 53317700 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3615964058 Sep 18 06:09:24 AM UTC 24 Sep 18 06:09:27 AM UTC 24 80497847 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.439137733 Sep 18 06:09:24 AM UTC 24 Sep 18 06:09:28 AM UTC 24 242976682 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.289183891 Sep 18 06:09:36 AM UTC 24 Sep 18 06:09:39 AM UTC 24 191994329 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1269781609 Sep 18 06:09:26 AM UTC 24 Sep 18 06:09:29 AM UTC 24 84432901 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2632323781 Sep 18 06:09:26 AM UTC 24 Sep 18 06:09:29 AM UTC 24 26881470 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3355459532 Sep 18 06:09:27 AM UTC 24 Sep 18 06:09:30 AM UTC 24 54974122 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1907141767 Sep 18 06:09:27 AM UTC 24 Sep 18 06:09:30 AM UTC 24 112413816 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.2971417122 Sep 18 06:09:29 AM UTC 24 Sep 18 06:09:31 AM UTC 24 13871997 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.762604619 Sep 18 06:09:29 AM UTC 24 Sep 18 06:09:31 AM UTC 24 15066939 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3466220049 Sep 18 06:09:29 AM UTC 24 Sep 18 06:09:31 AM UTC 24 22304556 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2015892584 Sep 18 06:09:27 AM UTC 24 Sep 18 06:09:32 AM UTC 24 102325415 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2564193698 Sep 18 06:09:27 AM UTC 24 Sep 18 06:09:32 AM UTC 24 120217179 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.502144759 Sep 18 06:09:27 AM UTC 24 Sep 18 06:09:33 AM UTC 24 49836326 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.23460548 Sep 18 06:09:30 AM UTC 24 Sep 18 06:09:33 AM UTC 24 88388839 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.913141282 Sep 18 06:09:26 AM UTC 24 Sep 18 06:09:33 AM UTC 24 207267860 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.45010112 Sep 18 06:09:30 AM UTC 24 Sep 18 06:09:34 AM UTC 24 124974598 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3669759462 Sep 18 06:09:22 AM UTC 24 Sep 18 06:09:34 AM UTC 24 1391966542 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.4214438272 Sep 18 06:09:31 AM UTC 24 Sep 18 06:09:34 AM UTC 24 205109069 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.417167755 Sep 18 06:09:33 AM UTC 24 Sep 18 06:09:35 AM UTC 24 11233707 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.230728044 Sep 18 06:09:32 AM UTC 24 Sep 18 06:09:35 AM UTC 24 73399738 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.27527192 Sep 18 06:09:33 AM UTC 24 Sep 18 06:09:36 AM UTC 24 23242376 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.181638562 Sep 18 06:09:32 AM UTC 24 Sep 18 06:09:36 AM UTC 24 93151501 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3505048402 Sep 18 06:09:33 AM UTC 24 Sep 18 06:09:36 AM UTC 24 27836890 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.719907997 Sep 18 06:09:33 AM UTC 24 Sep 18 06:09:36 AM UTC 24 38657277 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3768531101 Sep 18 06:09:32 AM UTC 24 Sep 18 06:09:37 AM UTC 24 100296031 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.2165558762 Sep 18 06:09:36 AM UTC 24 Sep 18 06:09:38 AM UTC 24 18840499 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.2279067084 Sep 18 06:09:36 AM UTC 24 Sep 18 06:09:38 AM UTC 24 50550593 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.459959758 Sep 18 06:09:32 AM UTC 24 Sep 18 06:09:38 AM UTC 24 317604458 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1903348545 Sep 18 06:09:35 AM UTC 24 Sep 18 06:09:39 AM UTC 24 144683503 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2049493066 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:39 AM UTC 24 26385417 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.2371716876 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:39 AM UTC 24 17943180 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1322294717 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:40 AM UTC 24 58986057 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1970938252 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:40 AM UTC 24 37122928 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1253340966 Sep 18 06:09:35 AM UTC 24 Sep 18 06:09:40 AM UTC 24 151991747 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.278167170 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:40 AM UTC 24 148459927 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3546095654 Sep 18 06:09:36 AM UTC 24 Sep 18 06:09:41 AM UTC 24 133242060 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2841787670 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:41 AM UTC 24 123388706 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1498078798 Sep 18 06:09:39 AM UTC 24 Sep 18 06:09:41 AM UTC 24 49993972 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.210737699 Sep 18 06:09:39 AM UTC 24 Sep 18 06:09:41 AM UTC 24 75111919 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.693948242 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:42 AM UTC 24 88322252 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.4261228579 Sep 18 06:09:29 AM UTC 24 Sep 18 06:09:42 AM UTC 24 520526098 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.402268346 Sep 18 06:09:39 AM UTC 24 Sep 18 06:09:42 AM UTC 24 93910415 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.56088146 Sep 18 06:09:39 AM UTC 24 Sep 18 06:09:43 AM UTC 24 166097205 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.4102089101 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:43 AM UTC 24 14673715 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.3421695299 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:43 AM UTC 24 20940497 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4196473450 Sep 18 06:09:37 AM UTC 24 Sep 18 06:09:43 AM UTC 24 320926013 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1544167231 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:44 AM UTC 24 138159838 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.1157929737 Sep 18 06:09:42 AM UTC 24 Sep 18 06:09:44 AM UTC 24 18123271 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.793414393 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:44 AM UTC 24 181286806 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2481708015 Sep 18 06:09:42 AM UTC 24 Sep 18 06:09:44 AM UTC 24 19792806 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.236173807 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:45 AM UTC 24 142312310 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3078700032 Sep 18 06:09:42 AM UTC 24 Sep 18 06:09:45 AM UTC 24 38951627 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2697774355 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:45 AM UTC 24 465698548 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1873345168 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:58 AM UTC 24 81425218 ps
T866 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.1971045043 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:45 AM UTC 24 209640123 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.969000557 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:45 AM UTC 24 120389321 ps
T867 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.3931413949 Sep 18 06:09:41 AM UTC 24 Sep 18 06:09:45 AM UTC 24 115050105 ps
T868 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.1147476134 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:45 AM UTC 24 35752425 ps
T869 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3361482147 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:46 AM UTC 24 72909886 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2595448603 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:46 AM UTC 24 56327165 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1437104515 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:46 AM UTC 24 65121724 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.933143975 Sep 18 06:09:42 AM UTC 24 Sep 18 06:09:47 AM UTC 24 189615007 ps
T870 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.860756165 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:48 AM UTC 24 14216193 ps
T871 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.157081984 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:48 AM UTC 24 453109915 ps
T872 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2359113231 Sep 18 06:09:45 AM UTC 24 Sep 18 06:09:48 AM UTC 24 23555018 ps
T873 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2503922961 Sep 18 06:09:45 AM UTC 24 Sep 18 06:09:48 AM UTC 24 75341883 ps
T874 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1663117552 Sep 18 06:09:45 AM UTC 24 Sep 18 06:09:48 AM UTC 24 180180649 ps
T875 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.802067022 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:58 AM UTC 24 64694511 ps
T876 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3154077309 Sep 18 06:09:45 AM UTC 24 Sep 18 06:09:48 AM UTC 24 43302775 ps
T877 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.454572756 Sep 18 06:09:43 AM UTC 24 Sep 18 06:09:48 AM UTC 24 670204133 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2309138758 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:49 AM UTC 24 115810971 ps
T878 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.522266850 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:49 AM UTC 24 16559663 ps
T879 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2005384713 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:49 AM UTC 24 117131025 ps
T880 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.2886242537 Sep 18 06:09:47 AM UTC 24 Sep 18 06:09:49 AM UTC 24 24276322 ps
T881 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2397505477 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:49 AM UTC 24 59694293 ps
T882 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.425064265 Sep 18 06:09:47 AM UTC 24 Sep 18 06:09:50 AM UTC 24 128391437 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1864700305 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:50 AM UTC 24 224372506 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2104308831 Sep 18 06:09:47 AM UTC 24 Sep 18 06:09:50 AM UTC 24 102935923 ps
T883 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.3837943556 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:50 AM UTC 24 41089117 ps
T884 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3201136102 Sep 18 06:09:46 AM UTC 24 Sep 18 06:09:51 AM UTC 24 291158355 ps
T885 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.530927176 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:51 AM UTC 24 34529564 ps
T886 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.3126912980 Sep 18 06:09:47 AM UTC 24 Sep 18 06:09:51 AM UTC 24 77183488 ps
T887 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2660075855 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:52 AM UTC 24 159987769 ps
T888 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.4288752767 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:52 AM UTC 24 47050103 ps
T889 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2801339640 Sep 18 06:09:47 AM UTC 24 Sep 18 06:09:52 AM UTC 24 310601630 ps
T890 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.786319445 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:52 AM UTC 24 28549350 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3884705114 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:52 AM UTC 24 105448800 ps
T891 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.975542858 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:52 AM UTC 24 16422709 ps
T892 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3486228390 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:53 AM UTC 24 33563460 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3359233520 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:53 AM UTC 24 133767850 ps
T893 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.72947286 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:53 AM UTC 24 14943151 ps
T894 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2955379764 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:53 AM UTC 24 64996025 ps
T895 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.75515175 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:59 AM UTC 24 65627001 ps
T896 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.531775678 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:53 AM UTC 24 121804179 ps
T897 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3617683178 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:58 AM UTC 24 40348907 ps
T898 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.1301008512 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:53 AM UTC 24 44353933 ps
T899 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2752477054 Sep 18 06:09:49 AM UTC 24 Sep 18 06:09:54 AM UTC 24 143105929 ps
T900 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3467534817 Sep 18 06:09:52 AM UTC 24 Sep 18 06:09:54 AM UTC 24 91967051 ps
T901 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.1295548298 Sep 18 06:09:52 AM UTC 24 Sep 18 06:09:54 AM UTC 24 75704723 ps
T902 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3073769729 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:54 AM UTC 24 112294917 ps
T903 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4011836977 Sep 18 06:09:50 AM UTC 24 Sep 18 06:09:54 AM UTC 24 224172876 ps
T904 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2263704524 Sep 18 06:09:52 AM UTC 24 Sep 18 06:09:54 AM UTC 24 38641715 ps
T905 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.104397271 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:55 AM UTC 24 25875536 ps
T906 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.2014531242 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:55 AM UTC 24 36340660 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2989780889 Sep 18 06:09:52 AM UTC 24 Sep 18 06:09:55 AM UTC 24 136135827 ps
T907 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2961497749 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:55 AM UTC 24 73051941 ps
T908 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3273468677 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:56 AM UTC 24 104170258 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1275073720 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:56 AM UTC 24 63301570 ps
T909 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.2822327218 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:56 AM UTC 24 30281247 ps
T910 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1988043597 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:57 AM UTC 24 38596626 ps
T911 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3405851036 Sep 18 06:09:52 AM UTC 24 Sep 18 06:09:57 AM UTC 24 493528039 ps
T912 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.3584899997 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:57 AM UTC 24 48820695 ps
T913 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1751296159 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:57 AM UTC 24 22233141 ps
T914 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.771487696 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:57 AM UTC 24 25194538 ps
T915 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.836282364 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:58 AM UTC 24 11429440 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3091323209 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:58 AM UTC 24 169340100 ps
T916 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1974809034 Sep 18 06:09:53 AM UTC 24 Sep 18 06:09:58 AM UTC 24 507022327 ps
T917 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.3207736087 Sep 18 06:09:57 AM UTC 24 Sep 18 06:09:59 AM UTC 24 17941721 ps
T918 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3545706868 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:58 AM UTC 24 22367070 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.4210981250 Sep 18 06:09:54 AM UTC 24 Sep 18 06:09:58 AM UTC 24 150544905 ps
T919 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1675002309 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:58 AM UTC 24 106689201 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3915185885 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:59 AM UTC 24 99748765 ps
T920 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.1163769374 Sep 18 06:09:57 AM UTC 24 Sep 18 06:09:59 AM UTC 24 17734015 ps
T921 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2424449358 Sep 18 06:09:56 AM UTC 24 Sep 18 06:09:59 AM UTC 24 128552143 ps
T922 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.4174824921 Sep 18 06:09:56 AM UTC 24 Sep 18 06:10:00 AM UTC 24 194867175 ps
T923 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3675695219 Sep 18 06:09:57 AM UTC 24 Sep 18 06:10:00 AM UTC 24 52249890 ps
T924 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.2366053252 Sep 18 06:09:59 AM UTC 24 Sep 18 06:10:00 AM UTC 24 10505958 ps
T925 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.2676349792 Sep 18 06:09:59 AM UTC 24 Sep 18 06:10:01 AM UTC 24 42917640 ps
T926 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.4203834989 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:01 AM UTC 24 120922820 ps
T927 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.839116770 Sep 18 06:09:57 AM UTC 24 Sep 18 06:10:01 AM UTC 24 104156054 ps
T928 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.387599189 Sep 18 06:09:59 AM UTC 24 Sep 18 06:10:01 AM UTC 24 97130425 ps
T929 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.118705436 Sep 18 06:09:59 AM UTC 24 Sep 18 06:10:01 AM UTC 24 84153135 ps
T930 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2334644849 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:01 AM UTC 24 74611028 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3685386562 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:02 AM UTC 24 198298097 ps
T931 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.391812573 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:02 AM UTC 24 108882042 ps
T932 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.3197773632 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 36142432 ps
T933 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.4259351915 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 13802244 ps
T934 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.3518060034 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 12996100 ps
T935 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.2910428623 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 14593883 ps
T936 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.860391323 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 32410553 ps
T937 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.291578183 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 42398790 ps
T938 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.2180833243 Sep 18 06:10:00 AM UTC 24 Sep 18 06:10:02 AM UTC 24 23121955 ps
T939 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.986771903 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:02 AM UTC 24 504070445 ps
T940 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.1122266291 Sep 18 06:09:58 AM UTC 24 Sep 18 06:10:02 AM UTC 24 198680835 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3196700408 Sep 18 06:09:57 AM UTC 24 Sep 18 06:10:02 AM UTC 24 445469574 ps
T941 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.2094755712 Sep 18 06:10:02 AM UTC 24 Sep 18 06:10:04 AM UTC 24 35143175 ps
T942 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.3043704025 Sep 18 06:10:02 AM UTC 24 Sep 18 06:10:04 AM UTC 24 50174445 ps
T943 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.329037830 Sep 18 06:10:02 AM UTC 24 Sep 18 06:10:04 AM UTC 24 21857665 ps
T944 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.2250229522 Sep 18 06:10:01 AM UTC 24 Sep 18 06:10:04 AM UTC 24 12101061 ps
T945 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2431561811 Sep 18 06:10:02 AM UTC 24 Sep 18 06:10:04 AM UTC 24 11867773 ps
T946 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.1033100378 Sep 18 06:10:01 AM UTC 24 Sep 18 06:10:04 AM UTC 24 16246743 ps
T947 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.3377825675 Sep 18 06:10:01 AM UTC 24 Sep 18 06:10:04 AM UTC 24 120881097 ps
T948 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.2214683950 Sep 18 06:10:02 AM UTC 24 Sep 18 06:10:04 AM UTC 24 20076402 ps
T949 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.3099696208 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:04 AM UTC 24 16577174 ps
T950 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3943152085 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:04 AM UTC 24 20424255 ps
T951 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.1291554105 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 11574109 ps
T952 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1440715043 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 15169245 ps
T953 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.2021730384 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 40227897 ps
T954 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.2116233652 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 18128316 ps
T955 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.525559994 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 13193555 ps
T956 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.3056928478 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 12575216 ps
T957 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2210391640 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 15273907 ps
T958 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3100051320 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 13046581 ps
T959 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.2617821633 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 30789961 ps
T960 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.1633330148 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 42850816 ps
T961 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.506936355 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 12281922 ps
T962 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.1264931000 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 61968024 ps
T963 /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.2199488600 Sep 18 06:10:03 AM UTC 24 Sep 18 06:10:05 AM UTC 24 73971251 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_handshake_intersig_mubi.904188664
Short name T34
Test name
Test status
Simulation time 70561900 ps
CPU time 1.1 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904188664 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_handshake_intersig_mubi.904188664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency.249571995
Short name T10
Test name
Test status
Simulation time 1638683557 ps
CPU time 9.64 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249571995 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.249571995
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all_with_rand_reset.103131384
Short name T17
Test name
Test status
Simulation time 6939186007 ps
CPU time 36.35 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:11:21 AM UTC 24
Peak memory 220584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103131384 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.103131384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_smoke.2915405888
Short name T4
Test name
Test status
Simulation time 68640998 ps
CPU time 1.24 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2915405888 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.2915405888
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_regwen.1144837580
Short name T20
Test name
Test status
Simulation time 731270481 ps
CPU time 5.72 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:50 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144837580 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.1144837580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors_with_csr_rw.3707792670
Short name T98
Test name
Test status
Simulation time 145776967 ps
CPU time 3.85 seconds
Started Sep 18 06:09:14 AM UTC 24
Finished Sep 18 06:09:18 AM UTC 24
Peak memory 212852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3707792670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_
errors_with_csr_rw.3707792670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_sec_cm.2571668000
Short name T57
Test name
Test status
Simulation time 235639996 ps
CPU time 2.23 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 242568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571668000 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.2571668000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_idle_intersig_mubi.2862075538
Short name T130
Test name
Test status
Simulation time 26171015 ps
CPU time 1.39 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:49 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862075538 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.2862075538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_clk_status.3290922317
Short name T31
Test name
Test status
Simulation time 19991070 ps
CPU time 0.98 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290922317 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3290922317
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_ctrl_intersig_mubi.3311051759
Short name T119
Test name
Test status
Simulation time 451127252 ps
CPU time 2.26 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311051759
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_ctrl_intersig_mubi.3311051759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors.1907141767
Short name T124
Test name
Test status
Simulation time 112413816 ps
CPU time 2.21 seconds
Started Sep 18 06:09:27 AM UTC 24
Finished Sep 18 06:09:30 AM UTC 24
Peak memory 212380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907141
767 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.1907141767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_intg_err.4196473450
Short name T136
Test name
Test status
Simulation time 320926013 ps
CPU time 4.68 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:43 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196473450 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.4196473450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all_with_rand_reset.3515794749
Short name T15
Test name
Test status
Simulation time 2956580097 ps
CPU time 30.91 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:11:18 AM UTC 24
Peak memory 220428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515794749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.3515794749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_clk_byp_req_intersig_mubi.1039727517
Short name T32
Test name
Test status
Simulation time 18424475 ps
CPU time 0.98 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039727517
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_clk_byp_req_intersig_mubi.1039727517
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_regwen.2385039653
Short name T28
Test name
Test status
Simulation time 1150295416 ps
CPU time 5.58 seconds
Started Sep 18 06:10:48 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 211068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385039653 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.2385039653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_stress_all.1074614620
Short name T18
Test name
Test status
Simulation time 8564126711 ps
CPU time 35.83 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 211044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074614620 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all.1074614620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_alert_test.3513102564
Short name T70
Test name
Test status
Simulation time 16082834 ps
CPU time 0.95 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513102564 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.3513102564
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all_with_rand_reset.82242021
Short name T681
Test name
Test status
Simulation time 12708451938 ps
CPU time 119.59 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:13:47 AM UTC 24
Peak memory 226732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82242021 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.clkmgr_stress_all_with_rand_reset.82242021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_regwen.3875010240
Short name T7
Test name
Test status
Simulation time 993593570 ps
CPU time 5.51 seconds
Started Sep 18 06:11:59 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875010240 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_regwen.3875010240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_intg_err.933143975
Short name T138
Test name
Test status
Simulation time 189615007 ps
CPU time 4.33 seconds
Started Sep 18 06:09:42 AM UTC 24
Finished Sep 18 06:09:47 AM UTC 24
Peak memory 211960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933143975 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.933143975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors.3915185885
Short name T156
Test name
Test status
Simulation time 99748765 ps
CPU time 1.96 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:59 AM UTC 24
Peak memory 228540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915185
885 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.3915185885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_extclk.2491791906
Short name T5
Test name
Test status
Simulation time 48854913 ps
CPU time 1.2 seconds
Started Sep 18 06:10:40 AM UTC 24
Finished Sep 18 06:10:42 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491791906 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_extclk.2491791906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_idle_intersig_mubi.1881942199
Short name T56
Test name
Test status
Simulation time 71132782 ps
CPU time 1.2 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881942199 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.1881942199
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_handshake_intersig_mubi.1641520015
Short name T87
Test name
Test status
Simulation time 29013181 ps
CPU time 1.3 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641520015 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_handshake_intersig_mubi.1641520015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_peri.3055957810
Short name T6
Test name
Test status
Simulation time 23153872 ps
CPU time 0.89 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:43 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3055957810 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.3055957810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors.2595448603
Short name T148
Test name
Test status
Simulation time 56327165 ps
CPU time 1.99 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:46 AM UTC 24
Peak memory 211468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595448
603 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.2595448603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors.2309138758
Short name T153
Test name
Test status
Simulation time 115810971 ps
CPU time 1.88 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:49 AM UTC 24
Peak memory 221140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309138
758 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.2309138758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_intg_err.4210981250
Short name T133
Test name
Test status
Simulation time 150544905 ps
CPU time 2.87 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210981250 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.4210981250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all.3179151475
Short name T113
Test name
Test status
Simulation time 4140494446 ps
CPU time 17.6 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 210980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179151475 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_stress_all.3179151475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_aliasing.4174627594
Short name T96
Test name
Test status
Simulation time 19423573 ps
CPU time 1.65 seconds
Started Sep 18 06:09:12 AM UTC 24
Finished Sep 18 06:09:15 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174627594 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.4174627594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_bit_bash.360602347
Short name T823
Test name
Test status
Simulation time 263450398 ps
CPU time 9.76 seconds
Started Sep 18 06:09:12 AM UTC 24
Finished Sep 18 06:09:23 AM UTC 24
Peak memory 212304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360602347 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.360602347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_hw_reset.129799866
Short name T134
Test name
Test status
Simulation time 21927137 ps
CPU time 1.28 seconds
Started Sep 18 06:09:10 AM UTC 24
Finished Sep 18 06:09:12 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129799866 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.129799866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_mem_rw_with_rand_reset.1245752957
Short name T814
Test name
Test status
Simulation time 22552779 ps
CPU time 1.35 seconds
Started Sep 18 06:09:12 AM UTC 24
Finished Sep 18 06:09:15 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1245752957 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.clkmgr_csr_mem_rw_with_rand_reset.1245752957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_csr_rw.4021374287
Short name T815
Test name
Test status
Simulation time 106555610 ps
CPU time 1.61 seconds
Started Sep 18 06:09:12 AM UTC 24
Finished Sep 18 06:09:15 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021374287 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.4021374287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_intr_test.4063895739
Short name T813
Test name
Test status
Simulation time 14360357 ps
CPU time 1.06 seconds
Started Sep 18 06:09:10 AM UTC 24
Finished Sep 18 06:09:12 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063895739 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_intr_test.4063895739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_same_csr_outstanding.238762463
Short name T97
Test name
Test status
Simulation time 61652234 ps
CPU time 1.91 seconds
Started Sep 18 06:09:12 AM UTC 24
Finished Sep 18 06:09:15 AM UTC 24
Peak memory 211724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387
62463 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.238762463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors.3689692658
Short name T120
Test name
Test status
Simulation time 73256330 ps
CPU time 2.35 seconds
Started Sep 18 06:09:05 AM UTC 24
Finished Sep 18 06:09:08 AM UTC 24
Peak memory 212512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689692
658 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.3689692658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_shadow_reg_errors_with_csr_rw.2343801114
Short name T95
Test name
Test status
Simulation time 158487251 ps
CPU time 2.88 seconds
Started Sep 18 06:09:05 AM UTC 24
Finished Sep 18 06:09:09 AM UTC 24
Peak memory 212664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2343801114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_
errors_with_csr_rw.2343801114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_errors.2200230600
Short name T812
Test name
Test status
Simulation time 38175580 ps
CPU time 2.98 seconds
Started Sep 18 06:09:08 AM UTC 24
Finished Sep 18 06:09:12 AM UTC 24
Peak memory 212676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200230600 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2200230600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/0.clkmgr_tl_intg_err.955064324
Short name T127
Test name
Test status
Simulation time 346205116 ps
CPU time 3.02 seconds
Started Sep 18 06:09:10 AM UTC 24
Finished Sep 18 06:09:14 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955064324 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.955064324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_aliasing.1176069238
Short name T818
Test name
Test status
Simulation time 67824116 ps
CPU time 1.93 seconds
Started Sep 18 06:09:17 AM UTC 24
Finished Sep 18 06:09:20 AM UTC 24
Peak memory 211844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176069238 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_aliasing.1176069238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_bit_bash.3300583229
Short name T829
Test name
Test status
Simulation time 931986282 ps
CPU time 9.16 seconds
Started Sep 18 06:09:16 AM UTC 24
Finished Sep 18 06:09:26 AM UTC 24
Peak memory 212224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300583229 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_bit_bash.3300583229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_hw_reset.1761269470
Short name T817
Test name
Test status
Simulation time 29765778 ps
CPU time 1.19 seconds
Started Sep 18 06:09:16 AM UTC 24
Finished Sep 18 06:09:18 AM UTC 24
Peak memory 212128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761269470 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_hw_reset.1761269470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_mem_rw_with_rand_reset.1823910659
Short name T820
Test name
Test status
Simulation time 42989247 ps
CPU time 1.77 seconds
Started Sep 18 06:09:19 AM UTC 24
Finished Sep 18 06:09:21 AM UTC 24
Peak memory 211692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1823910659 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 1.clkmgr_csr_mem_rw_with_rand_reset.1823910659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_csr_rw.2208422658
Short name T99
Test name
Test status
Simulation time 20014391 ps
CPU time 1.35 seconds
Started Sep 18 06:09:16 AM UTC 24
Finished Sep 18 06:09:18 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208422658 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.2208422658
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_intr_test.1456914407
Short name T816
Test name
Test status
Simulation time 28936790 ps
CPU time 1.11 seconds
Started Sep 18 06:09:16 AM UTC 24
Finished Sep 18 06:09:18 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456914407 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_intr_test.1456914407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_same_csr_outstanding.2738456007
Short name T100
Test name
Test status
Simulation time 40778127 ps
CPU time 1.91 seconds
Started Sep 18 06:09:19 AM UTC 24
Finished Sep 18 06:09:22 AM UTC 24
Peak memory 211916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738
456007 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.2738456007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_shadow_reg_errors.1092768964
Short name T121
Test name
Test status
Simulation time 167281914 ps
CPU time 2.51 seconds
Started Sep 18 06:09:13 AM UTC 24
Finished Sep 18 06:09:17 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092768
964 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.1092768964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_errors.818599772
Short name T819
Test name
Test status
Simulation time 354333218 ps
CPU time 4.9 seconds
Started Sep 18 06:09:15 AM UTC 24
Finished Sep 18 06:09:21 AM UTC 24
Peak memory 212412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818599772 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.818599772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/1.clkmgr_tl_intg_err.57209510
Short name T128
Test name
Test status
Simulation time 61739250 ps
CPU time 2.43 seconds
Started Sep 18 06:09:15 AM UTC 24
Finished Sep 18 06:09:18 AM UTC 24
Peak memory 212340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57209510 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.57209510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_mem_rw_with_rand_reset.2359113231
Short name T872
Test name
Test status
Simulation time 23555018 ps
CPU time 1.45 seconds
Started Sep 18 06:09:45 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2359113231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.clkmgr_csr_mem_rw_with_rand_reset.2359113231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_csr_rw.1663117552
Short name T874
Test name
Test status
Simulation time 180180649 ps
CPU time 1.89 seconds
Started Sep 18 06:09:45 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663117552 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_csr_rw.1663117552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_intr_test.1147476134
Short name T868
Test name
Test status
Simulation time 35752425 ps
CPU time 1.09 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147476134 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_intr_test.1147476134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_same_csr_outstanding.3154077309
Short name T876
Test name
Test status
Simulation time 43302775 ps
CPU time 2.11 seconds
Started Sep 18 06:09:45 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 212620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154
077309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_same_csr_outstanding.3154077309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_shadow_reg_errors_with_csr_rw.454572756
Short name T877
Test name
Test status
Simulation time 670204133 ps
CPU time 4.23 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 229084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=454572756 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_
errors_with_csr_rw.454572756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_errors.157081984
Short name T871
Test name
Test status
Simulation time 453109915 ps
CPU time 3.47 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 212428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157081984 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.157081984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/10.clkmgr_tl_intg_err.1437104515
Short name T193
Test name
Test status
Simulation time 65121724 ps
CPU time 1.89 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:46 AM UTC 24
Peak memory 211892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437104515 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.1437104515
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_mem_rw_with_rand_reset.2005384713
Short name T879
Test name
Test status
Simulation time 117131025 ps
CPU time 2.06 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:49 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2005384713 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.clkmgr_csr_mem_rw_with_rand_reset.2005384713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_csr_rw.522266850
Short name T878
Test name
Test status
Simulation time 16559663 ps
CPU time 1.05 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:49 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522266850 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_csr_rw.522266850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_intr_test.860756165
Short name T870
Test name
Test status
Simulation time 14216193 ps
CPU time 0.91 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 211332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860756165 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_intr_test.860756165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_same_csr_outstanding.2397505477
Short name T881
Test name
Test status
Simulation time 59694293 ps
CPU time 2.14 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:49 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397
505477 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_same_csr_outstanding.2397505477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors.2503922961
Short name T873
Test name
Test status
Simulation time 75341883 ps
CPU time 1.54 seconds
Started Sep 18 06:09:45 AM UTC 24
Finished Sep 18 06:09:48 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503922
961 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.2503922961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_shadow_reg_errors_with_csr_rw.3201136102
Short name T884
Test name
Test status
Simulation time 291158355 ps
CPU time 4.03 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:51 AM UTC 24
Peak memory 212656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3201136102 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg
_errors_with_csr_rw.3201136102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_errors.3837943556
Short name T883
Test name
Test status
Simulation time 41089117 ps
CPU time 3.32 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:50 AM UTC 24
Peak memory 212612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837943556 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.3837943556
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/11.clkmgr_tl_intg_err.1864700305
Short name T141
Test name
Test status
Simulation time 224372506 ps
CPU time 3.11 seconds
Started Sep 18 06:09:46 AM UTC 24
Finished Sep 18 06:09:50 AM UTC 24
Peak memory 212296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864700305 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.1864700305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_mem_rw_with_rand_reset.786319445
Short name T890
Test name
Test status
Simulation time 28549350 ps
CPU time 2.07 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=786319445 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 12.clkmgr_csr_mem_rw_with_rand_reset.786319445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_csr_rw.425064265
Short name T882
Test name
Test status
Simulation time 128391437 ps
CPU time 1.64 seconds
Started Sep 18 06:09:47 AM UTC 24
Finished Sep 18 06:09:50 AM UTC 24
Peak memory 211648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425064265 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_csr_rw.425064265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_intr_test.2886242537
Short name T880
Test name
Test status
Simulation time 24276322 ps
CPU time 0.94 seconds
Started Sep 18 06:09:47 AM UTC 24
Finished Sep 18 06:09:49 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886242537 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_intr_test.2886242537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_same_csr_outstanding.2660075855
Short name T887
Test name
Test status
Simulation time 159987769 ps
CPU time 1.87 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 211868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660
075855 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_same_csr_outstanding.2660075855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_shadow_reg_errors_with_csr_rw.2801339640
Short name T889
Test name
Test status
Simulation time 310601630 ps
CPU time 3.72 seconds
Started Sep 18 06:09:47 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 221952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2801339640 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg
_errors_with_csr_rw.2801339640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_errors.3126912980
Short name T886
Test name
Test status
Simulation time 77183488 ps
CPU time 3.23 seconds
Started Sep 18 06:09:47 AM UTC 24
Finished Sep 18 06:09:51 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126912980 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.3126912980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/12.clkmgr_tl_intg_err.2104308831
Short name T132
Test name
Test status
Simulation time 102935923 ps
CPU time 1.88 seconds
Started Sep 18 06:09:47 AM UTC 24
Finished Sep 18 06:09:50 AM UTC 24
Peak memory 211848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104308831 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.2104308831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_mem_rw_with_rand_reset.531775678
Short name T896
Test name
Test status
Simulation time 121804179 ps
CPU time 2.05 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 212228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=531775678 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.clkmgr_csr_mem_rw_with_rand_reset.531775678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_csr_rw.975542858
Short name T891
Test name
Test status
Simulation time 16422709 ps
CPU time 0.93 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 212180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975542858 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_csr_rw.975542858
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_intr_test.530927176
Short name T885
Test name
Test status
Simulation time 34529564 ps
CPU time 1.01 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:51 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530927176 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_intr_test.530927176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_same_csr_outstanding.3486228390
Short name T892
Test name
Test status
Simulation time 33563460 ps
CPU time 1.5 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486
228390 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_same_csr_outstanding.3486228390
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors.3884705114
Short name T160
Test name
Test status
Simulation time 105448800 ps
CPU time 2.03 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 212596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884705
114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.3884705114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_shadow_reg_errors_with_csr_rw.2752477054
Short name T899
Test name
Test status
Simulation time 143105929 ps
CPU time 3.91 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2752477054 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg
_errors_with_csr_rw.2752477054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_errors.4288752767
Short name T888
Test name
Test status
Simulation time 47050103 ps
CPU time 1.76 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:52 AM UTC 24
Peak memory 211908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288752767 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.4288752767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/13.clkmgr_tl_intg_err.3359233520
Short name T194
Test name
Test status
Simulation time 133767850 ps
CPU time 2.64 seconds
Started Sep 18 06:09:49 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 212572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359233520 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.3359233520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_mem_rw_with_rand_reset.2263704524
Short name T904
Test name
Test status
Simulation time 38641715 ps
CPU time 1.81 seconds
Started Sep 18 06:09:52 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2263704524 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.clkmgr_csr_mem_rw_with_rand_reset.2263704524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_csr_rw.1295548298
Short name T901
Test name
Test status
Simulation time 75704723 ps
CPU time 1.46 seconds
Started Sep 18 06:09:52 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295548298 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_csr_rw.1295548298
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_intr_test.72947286
Short name T893
Test name
Test status
Simulation time 14943151 ps
CPU time 1.08 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72947286 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_intr_test.72947286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_same_csr_outstanding.3467534817
Short name T900
Test name
Test status
Simulation time 91967051 ps
CPU time 1.4 seconds
Started Sep 18 06:09:52 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467
534817 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_same_csr_outstanding.3467534817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors.2955379764
Short name T894
Test name
Test status
Simulation time 64996025 ps
CPU time 1.46 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 211596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955379
764 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.2955379764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_shadow_reg_errors_with_csr_rw.4011836977
Short name T903
Test name
Test status
Simulation time 224172876 ps
CPU time 2.58 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 221936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=4011836977 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg
_errors_with_csr_rw.4011836977
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_errors.1301008512
Short name T898
Test name
Test status
Simulation time 44353933 ps
CPU time 1.7 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:53 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301008512 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.1301008512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/14.clkmgr_tl_intg_err.3073769729
Short name T902
Test name
Test status
Simulation time 112294917 ps
CPU time 2.37 seconds
Started Sep 18 06:09:50 AM UTC 24
Finished Sep 18 06:09:54 AM UTC 24
Peak memory 212564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073769729 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.3073769729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_mem_rw_with_rand_reset.2961497749
Short name T907
Test name
Test status
Simulation time 73051941 ps
CPU time 1.35 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:55 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=2961497749 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.clkmgr_csr_mem_rw_with_rand_reset.2961497749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_csr_rw.2014531242
Short name T906
Test name
Test status
Simulation time 36340660 ps
CPU time 1.28 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:55 AM UTC 24
Peak memory 212192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014531242 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_csr_rw.2014531242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_intr_test.104397271
Short name T905
Test name
Test status
Simulation time 25875536 ps
CPU time 1.04 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:55 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104397271 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_intr_test.104397271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_same_csr_outstanding.3273468677
Short name T908
Test name
Test status
Simulation time 104170258 ps
CPU time 1.79 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:56 AM UTC 24
Peak memory 211868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273
468677 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_same_csr_outstanding.3273468677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors.2989780889
Short name T154
Test name
Test status
Simulation time 136135827 ps
CPU time 2.63 seconds
Started Sep 18 06:09:52 AM UTC 24
Finished Sep 18 06:09:55 AM UTC 24
Peak memory 221948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989780
889 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.2989780889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_shadow_reg_errors_with_csr_rw.3405851036
Short name T911
Test name
Test status
Simulation time 493528039 ps
CPU time 3.97 seconds
Started Sep 18 06:09:52 AM UTC 24
Finished Sep 18 06:09:57 AM UTC 24
Peak memory 222020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3405851036 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg
_errors_with_csr_rw.3405851036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_errors.3584899997
Short name T912
Test name
Test status
Simulation time 48820695 ps
CPU time 2.98 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:57 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584899997 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.3584899997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/15.clkmgr_tl_intg_err.1974809034
Short name T916
Test name
Test status
Simulation time 507022327 ps
CPU time 3.93 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1974809034 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.1974809034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_mem_rw_with_rand_reset.3617683178
Short name T897
Test name
Test status
Simulation time 40348907 ps
CPU time 2.48 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 212492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3617683178 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.clkmgr_csr_mem_rw_with_rand_reset.3617683178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_csr_rw.1988043597
Short name T910
Test name
Test status
Simulation time 38596626 ps
CPU time 1.26 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:57 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988043597 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_csr_rw.1988043597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_intr_test.2822327218
Short name T909
Test name
Test status
Simulation time 30281247 ps
CPU time 1.02 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:56 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822327218 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_intr_test.2822327218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_same_csr_outstanding.1751296159
Short name T913
Test name
Test status
Simulation time 22233141 ps
CPU time 1.39 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:57 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751
296159 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_same_csr_outstanding.1751296159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors.1275073720
Short name T157
Test name
Test status
Simulation time 63301570 ps
CPU time 1.96 seconds
Started Sep 18 06:09:53 AM UTC 24
Finished Sep 18 06:09:56 AM UTC 24
Peak memory 211528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275073
720 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.1275073720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_shadow_reg_errors_with_csr_rw.1873345168
Short name T155
Test name
Test status
Simulation time 81425218 ps
CPU time 2.61 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 222020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1873345168 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg
_errors_with_csr_rw.1873345168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/16.clkmgr_tl_errors.771487696
Short name T914
Test name
Test status
Simulation time 25194538 ps
CPU time 2.25 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:57 AM UTC 24
Peak memory 212632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771487696 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.771487696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_mem_rw_with_rand_reset.1675002309
Short name T919
Test name
Test status
Simulation time 106689201 ps
CPU time 1.48 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 211640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1675002309 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.clkmgr_csr_mem_rw_with_rand_reset.1675002309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_csr_rw.802067022
Short name T875
Test name
Test status
Simulation time 64694511 ps
CPU time 1.35 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 211884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802067022 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_csr_rw.802067022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_intr_test.836282364
Short name T915
Test name
Test status
Simulation time 11429440 ps
CPU time 0.94 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836282364 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_intr_test.836282364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_same_csr_outstanding.3545706868
Short name T918
Test name
Test status
Simulation time 22367070 ps
CPU time 1.11 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545
706868 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_same_csr_outstanding.3545706868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors.3091323209
Short name T162
Test name
Test status
Simulation time 169340100 ps
CPU time 2.26 seconds
Started Sep 18 06:09:54 AM UTC 24
Finished Sep 18 06:09:58 AM UTC 24
Peak memory 212452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091323
209 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.3091323209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_shadow_reg_errors_with_csr_rw.2424449358
Short name T921
Test name
Test status
Simulation time 128552143 ps
CPU time 2.79 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:59 AM UTC 24
Peak memory 212724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2424449358 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg
_errors_with_csr_rw.2424449358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_errors.75515175
Short name T895
Test name
Test status
Simulation time 65627001 ps
CPU time 2.84 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:09:59 AM UTC 24
Peak memory 212496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75515175 -assert nopostpr
oc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.75515175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/17.clkmgr_tl_intg_err.4174824921
Short name T922
Test name
Test status
Simulation time 194867175 ps
CPU time 3.46 seconds
Started Sep 18 06:09:56 AM UTC 24
Finished Sep 18 06:10:00 AM UTC 24
Peak memory 212560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174824921 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.4174824921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_mem_rw_with_rand_reset.986771903
Short name T939
Test name
Test status
Simulation time 504070445 ps
CPU time 2.85 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=986771903 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 18.clkmgr_csr_mem_rw_with_rand_reset.986771903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_csr_rw.3207736087
Short name T917
Test name
Test status
Simulation time 17941721 ps
CPU time 1.05 seconds
Started Sep 18 06:09:57 AM UTC 24
Finished Sep 18 06:09:59 AM UTC 24
Peak memory 211712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207736087 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_csr_rw.3207736087
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_intr_test.1163769374
Short name T920
Test name
Test status
Simulation time 17734015 ps
CPU time 0.84 seconds
Started Sep 18 06:09:57 AM UTC 24
Finished Sep 18 06:09:59 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163769374 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_intr_test.1163769374
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_same_csr_outstanding.4203834989
Short name T926
Test name
Test status
Simulation time 120922820 ps
CPU time 1.81 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203
834989 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_same_csr_outstanding.4203834989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_shadow_reg_errors_with_csr_rw.839116770
Short name T927
Test name
Test status
Simulation time 104156054 ps
CPU time 3.07 seconds
Started Sep 18 06:09:57 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 222280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=839116770 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_
errors_with_csr_rw.839116770
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_errors.3675695219
Short name T923
Test name
Test status
Simulation time 52249890 ps
CPU time 2.11 seconds
Started Sep 18 06:09:57 AM UTC 24
Finished Sep 18 06:10:00 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675695219 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.3675695219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/18.clkmgr_tl_intg_err.3196700408
Short name T139
Test name
Test status
Simulation time 445469574 ps
CPU time 4.3 seconds
Started Sep 18 06:09:57 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196700408 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.3196700408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_mem_rw_with_rand_reset.118705436
Short name T929
Test name
Test status
Simulation time 84153135 ps
CPU time 1.66 seconds
Started Sep 18 06:09:59 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 211956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=118705436 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.clkmgr_csr_mem_rw_with_rand_reset.118705436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_csr_rw.2676349792
Short name T925
Test name
Test status
Simulation time 42917640 ps
CPU time 1.31 seconds
Started Sep 18 06:09:59 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 211656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676349792 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_csr_rw.2676349792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_intr_test.2366053252
Short name T924
Test name
Test status
Simulation time 10505958 ps
CPU time 0.76 seconds
Started Sep 18 06:09:59 AM UTC 24
Finished Sep 18 06:10:00 AM UTC 24
Peak memory 211220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366053252 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_intr_test.2366053252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_same_csr_outstanding.387599189
Short name T928
Test name
Test status
Simulation time 97130425 ps
CPU time 1.6 seconds
Started Sep 18 06:09:59 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 211956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3875
99189 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_same_csr_outstanding.387599189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors.3685386562
Short name T158
Test name
Test status
Simulation time 198298097 ps
CPU time 2.21 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 212720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685386
562 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.3685386562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_shadow_reg_errors_with_csr_rw.391812573
Short name T931
Test name
Test status
Simulation time 108882042 ps
CPU time 2.19 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 212640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=391812573 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_
errors_with_csr_rw.391812573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_errors.1122266291
Short name T940
Test name
Test status
Simulation time 198680835 ps
CPU time 2.96 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122266291 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.1122266291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/19.clkmgr_tl_intg_err.2334644849
Short name T930
Test name
Test status
Simulation time 74611028 ps
CPU time 1.98 seconds
Started Sep 18 06:09:58 AM UTC 24
Finished Sep 18 06:10:01 AM UTC 24
Peak memory 211896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334644849 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.2334644849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_aliasing.108351717
Short name T828
Test name
Test status
Simulation time 70254185 ps
CPU time 2.9 seconds
Started Sep 18 06:09:22 AM UTC 24
Finished Sep 18 06:09:26 AM UTC 24
Peak memory 212504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108351717 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_aliasing.108351717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_bit_bash.3669759462
Short name T842
Test name
Test status
Simulation time 1391966542 ps
CPU time 10.51 seconds
Started Sep 18 06:09:22 AM UTC 24
Finished Sep 18 06:09:34 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669759462 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_bit_bash.3669759462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_hw_reset.2839838338
Short name T822
Test name
Test status
Simulation time 17321585 ps
CPU time 1.17 seconds
Started Sep 18 06:09:21 AM UTC 24
Finished Sep 18 06:09:23 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839838338 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_hw_reset.2839838338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_mem_rw_with_rand_reset.3770299424
Short name T825
Test name
Test status
Simulation time 68215211 ps
CPU time 2.03 seconds
Started Sep 18 06:09:23 AM UTC 24
Finished Sep 18 06:09:25 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3770299424 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 2.clkmgr_csr_mem_rw_with_rand_reset.3770299424
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_csr_rw.2268019930
Short name T102
Test name
Test status
Simulation time 52320142 ps
CPU time 1.16 seconds
Started Sep 18 06:09:21 AM UTC 24
Finished Sep 18 06:09:23 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268019930 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.2268019930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_intr_test.2058965354
Short name T821
Test name
Test status
Simulation time 14403278 ps
CPU time 1.04 seconds
Started Sep 18 06:09:21 AM UTC 24
Finished Sep 18 06:09:23 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058965354 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_intr_test.2058965354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_same_csr_outstanding.3319202434
Short name T103
Test name
Test status
Simulation time 29625152 ps
CPU time 1.59 seconds
Started Sep 18 06:09:22 AM UTC 24
Finished Sep 18 06:09:25 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319
202434 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.3319202434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors.1574348766
Short name T123
Test name
Test status
Simulation time 100042464 ps
CPU time 2.02 seconds
Started Sep 18 06:09:19 AM UTC 24
Finished Sep 18 06:09:22 AM UTC 24
Peak memory 212576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574348
766 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.1574348766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_shadow_reg_errors_with_csr_rw.2070606162
Short name T101
Test name
Test status
Simulation time 289870988 ps
CPU time 2.92 seconds
Started Sep 18 06:09:19 AM UTC 24
Finished Sep 18 06:09:23 AM UTC 24
Peak memory 221948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2070606162 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_
errors_with_csr_rw.2070606162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_errors.2922518887
Short name T824
Test name
Test status
Simulation time 101635306 ps
CPU time 3.13 seconds
Started Sep 18 06:09:21 AM UTC 24
Finished Sep 18 06:09:25 AM UTC 24
Peak memory 212320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922518887 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.2922518887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/2.clkmgr_tl_intg_err.3411515886
Short name T129
Test name
Test status
Simulation time 53843976 ps
CPU time 2.32 seconds
Started Sep 18 06:09:21 AM UTC 24
Finished Sep 18 06:09:24 AM UTC 24
Peak memory 212116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411515886 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.3411515886
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/20.clkmgr_intr_test.860391323
Short name T936
Test name
Test status
Simulation time 32410553 ps
CPU time 1.05 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860391323 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_intr_test.860391323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/21.clkmgr_intr_test.3197773632
Short name T932
Test name
Test status
Simulation time 36142432 ps
CPU time 0.94 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197773632 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_intr_test.3197773632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/22.clkmgr_intr_test.2910428623
Short name T935
Test name
Test status
Simulation time 14593883 ps
CPU time 0.96 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910428623 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_intr_test.2910428623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/23.clkmgr_intr_test.4259351915
Short name T933
Test name
Test status
Simulation time 13802244 ps
CPU time 0.91 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259351915 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_intr_test.4259351915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/24.clkmgr_intr_test.291578183
Short name T937
Test name
Test status
Simulation time 42398790 ps
CPU time 0.92 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291578183 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_intr_test.291578183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/25.clkmgr_intr_test.3518060034
Short name T934
Test name
Test status
Simulation time 12996100 ps
CPU time 0.79 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518060034 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.clkmgr_intr_test.3518060034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/26.clkmgr_intr_test.2180833243
Short name T938
Test name
Test status
Simulation time 23121955 ps
CPU time 0.88 seconds
Started Sep 18 06:10:00 AM UTC 24
Finished Sep 18 06:10:02 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180833243 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.clkmgr_intr_test.2180833243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/27.clkmgr_intr_test.1033100378
Short name T946
Test name
Test status
Simulation time 16246743 ps
CPU time 1 seconds
Started Sep 18 06:10:01 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033100378 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.clkmgr_intr_test.1033100378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/28.clkmgr_intr_test.3377825675
Short name T947
Test name
Test status
Simulation time 120881097 ps
CPU time 0.98 seconds
Started Sep 18 06:10:01 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377825675 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.clkmgr_intr_test.3377825675
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/29.clkmgr_intr_test.2250229522
Short name T944
Test name
Test status
Simulation time 12101061 ps
CPU time 0.92 seconds
Started Sep 18 06:10:01 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250229522 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.clkmgr_intr_test.2250229522
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_aliasing.2632323781
Short name T833
Test name
Test status
Simulation time 26881470 ps
CPU time 2.12 seconds
Started Sep 18 06:09:26 AM UTC 24
Finished Sep 18 06:09:29 AM UTC 24
Peak memory 212312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632323781 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_aliasing.2632323781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_bit_bash.913141282
Short name T840
Test name
Test status
Simulation time 207267860 ps
CPU time 6.26 seconds
Started Sep 18 06:09:26 AM UTC 24
Finished Sep 18 06:09:33 AM UTC 24
Peak memory 212348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913141282 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_bit_bash.913141282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_hw_reset.1614963759
Short name T827
Test name
Test status
Simulation time 29246824 ps
CPU time 1.27 seconds
Started Sep 18 06:09:24 AM UTC 24
Finished Sep 18 06:09:26 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614963759 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_hw_reset.1614963759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_mem_rw_with_rand_reset.3355459532
Short name T834
Test name
Test status
Simulation time 54974122 ps
CPU time 1.8 seconds
Started Sep 18 06:09:27 AM UTC 24
Finished Sep 18 06:09:30 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3355459532 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.clkmgr_csr_mem_rw_with_rand_reset.3355459532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_csr_rw.4138467820
Short name T104
Test name
Test status
Simulation time 53317700 ps
CPU time 1.34 seconds
Started Sep 18 06:09:25 AM UTC 24
Finished Sep 18 06:09:27 AM UTC 24
Peak memory 212124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138467820 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.4138467820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_intr_test.2555635119
Short name T826
Test name
Test status
Simulation time 16264839 ps
CPU time 1.04 seconds
Started Sep 18 06:09:24 AM UTC 24
Finished Sep 18 06:09:26 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2555635119 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_intr_test.2555635119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_same_csr_outstanding.1269781609
Short name T832
Test name
Test status
Simulation time 84432901 ps
CPU time 1.9 seconds
Started Sep 18 06:09:26 AM UTC 24
Finished Sep 18 06:09:29 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269
781609 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.1269781609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors.3913733235
Short name T122
Test name
Test status
Simulation time 77018155 ps
CPU time 2.39 seconds
Started Sep 18 06:09:23 AM UTC 24
Finished Sep 18 06:09:26 AM UTC 24
Peak memory 212704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913733
235 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.3913733235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_shadow_reg_errors_with_csr_rw.3615964058
Short name T125
Test name
Test status
Simulation time 80497847 ps
CPU time 2.68 seconds
Started Sep 18 06:09:24 AM UTC 24
Finished Sep 18 06:09:27 AM UTC 24
Peak memory 212584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3615964058 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_
errors_with_csr_rw.3615964058
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_errors.439137733
Short name T830
Test name
Test status
Simulation time 242976682 ps
CPU time 3.44 seconds
Started Sep 18 06:09:24 AM UTC 24
Finished Sep 18 06:09:28 AM UTC 24
Peak memory 212488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439137733 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.439137733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/3.clkmgr_tl_intg_err.2911315441
Short name T195
Test name
Test status
Simulation time 114880908 ps
CPU time 2.4 seconds
Started Sep 18 06:09:24 AM UTC 24
Finished Sep 18 06:09:27 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911315441 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.2911315441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/30.clkmgr_intr_test.3043704025
Short name T942
Test name
Test status
Simulation time 50174445 ps
CPU time 0.78 seconds
Started Sep 18 06:10:02 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043704025 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.clkmgr_intr_test.3043704025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/31.clkmgr_intr_test.329037830
Short name T943
Test name
Test status
Simulation time 21857665 ps
CPU time 0.85 seconds
Started Sep 18 06:10:02 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329037830 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.clkmgr_intr_test.329037830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/32.clkmgr_intr_test.2214683950
Short name T948
Test name
Test status
Simulation time 20076402 ps
CPU time 1.02 seconds
Started Sep 18 06:10:02 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214683950 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.clkmgr_intr_test.2214683950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/33.clkmgr_intr_test.2431561811
Short name T945
Test name
Test status
Simulation time 11867773 ps
CPU time 0.81 seconds
Started Sep 18 06:10:02 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431561811 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.clkmgr_intr_test.2431561811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/34.clkmgr_intr_test.2094755712
Short name T941
Test name
Test status
Simulation time 35143175 ps
CPU time 0.72 seconds
Started Sep 18 06:10:02 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094755712 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.clkmgr_intr_test.2094755712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/35.clkmgr_intr_test.3943152085
Short name T950
Test name
Test status
Simulation time 20424255 ps
CPU time 0.65 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943152085 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.clkmgr_intr_test.3943152085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/36.clkmgr_intr_test.3099696208
Short name T949
Test name
Test status
Simulation time 16577174 ps
CPU time 0.67 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:04 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099696208 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.clkmgr_intr_test.3099696208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/37.clkmgr_intr_test.1291554105
Short name T951
Test name
Test status
Simulation time 11574109 ps
CPU time 0.74 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291554105 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.clkmgr_intr_test.1291554105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/38.clkmgr_intr_test.2021730384
Short name T953
Test name
Test status
Simulation time 40227897 ps
CPU time 0.78 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021730384 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.clkmgr_intr_test.2021730384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/39.clkmgr_intr_test.2116233652
Short name T954
Test name
Test status
Simulation time 18128316 ps
CPU time 0.82 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116233652 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.clkmgr_intr_test.2116233652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_aliasing.45010112
Short name T841
Test name
Test status
Simulation time 124974598 ps
CPU time 2.99 seconds
Started Sep 18 06:09:30 AM UTC 24
Finished Sep 18 06:09:34 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45010112 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_aliasing.45010112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_bit_bash.4261228579
Short name T857
Test name
Test status
Simulation time 520526098 ps
CPU time 11.93 seconds
Started Sep 18 06:09:29 AM UTC 24
Finished Sep 18 06:09:42 AM UTC 24
Peak memory 212464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261228579 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_bit_bash.4261228579
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_hw_reset.3466220049
Short name T837
Test name
Test status
Simulation time 22304556 ps
CPU time 1.32 seconds
Started Sep 18 06:09:29 AM UTC 24
Finished Sep 18 06:09:31 AM UTC 24
Peak memory 211708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrument
ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466220049 -asse
rt nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_hw_reset.3466220049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_mem_rw_with_rand_reset.4214438272
Short name T843
Test name
Test status
Simulation time 205109069 ps
CPU time 2.02 seconds
Started Sep 18 06:09:31 AM UTC 24
Finished Sep 18 06:09:34 AM UTC 24
Peak memory 212420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=4214438272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.clkmgr_csr_mem_rw_with_rand_reset.4214438272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_csr_rw.762604619
Short name T836
Test name
Test status
Simulation time 15066939 ps
CPU time 1.23 seconds
Started Sep 18 06:09:29 AM UTC 24
Finished Sep 18 06:09:31 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762604619 -assert nopo
stproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.762604619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_intr_test.2971417122
Short name T835
Test name
Test status
Simulation time 13871997 ps
CPU time 1.07 seconds
Started Sep 18 06:09:29 AM UTC 24
Finished Sep 18 06:09:31 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971417122 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_intr_test.2971417122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_same_csr_outstanding.23460548
Short name T839
Test name
Test status
Simulation time 88388839 ps
CPU time 1.75 seconds
Started Sep 18 06:09:30 AM UTC 24
Finished Sep 18 06:09:33 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346
0548 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.23460548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_shadow_reg_errors_with_csr_rw.2015892584
Short name T144
Test name
Test status
Simulation time 102325415 ps
CPU time 3.83 seconds
Started Sep 18 06:09:27 AM UTC 24
Finished Sep 18 06:09:32 AM UTC 24
Peak memory 221952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2015892584 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_
errors_with_csr_rw.2015892584
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_errors.502144759
Short name T838
Test name
Test status
Simulation time 49836326 ps
CPU time 4.16 seconds
Started Sep 18 06:09:27 AM UTC 24
Finished Sep 18 06:09:33 AM UTC 24
Peak memory 212416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502144759 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.502144759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/4.clkmgr_tl_intg_err.2564193698
Short name T131
Test name
Test status
Simulation time 120217179 ps
CPU time 3.98 seconds
Started Sep 18 06:09:27 AM UTC 24
Finished Sep 18 06:09:32 AM UTC 24
Peak memory 212452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564193698 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.2564193698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/40.clkmgr_intr_test.1440715043
Short name T952
Test name
Test status
Simulation time 15169245 ps
CPU time 0.76 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440715043 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.clkmgr_intr_test.1440715043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/40.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/41.clkmgr_intr_test.525559994
Short name T955
Test name
Test status
Simulation time 13193555 ps
CPU time 0.93 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525559994 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.clkmgr_intr_test.525559994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/42.clkmgr_intr_test.3056928478
Short name T956
Test name
Test status
Simulation time 12575216 ps
CPU time 0.86 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056928478 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.clkmgr_intr_test.3056928478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/43.clkmgr_intr_test.3100051320
Short name T958
Test name
Test status
Simulation time 13046581 ps
CPU time 0.93 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100051320 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.clkmgr_intr_test.3100051320
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/44.clkmgr_intr_test.1264931000
Short name T962
Test name
Test status
Simulation time 61968024 ps
CPU time 1.06 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1264931000 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.clkmgr_intr_test.1264931000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/45.clkmgr_intr_test.1633330148
Short name T960
Test name
Test status
Simulation time 42850816 ps
CPU time 0.86 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633330148 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.clkmgr_intr_test.1633330148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/46.clkmgr_intr_test.2210391640
Short name T957
Test name
Test status
Simulation time 15273907 ps
CPU time 0.72 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210391640 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.clkmgr_intr_test.2210391640
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/47.clkmgr_intr_test.2617821633
Short name T959
Test name
Test status
Simulation time 30789961 ps
CPU time 0.82 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617821633 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.clkmgr_intr_test.2617821633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/48.clkmgr_intr_test.2199488600
Short name T963
Test name
Test status
Simulation time 73971251 ps
CPU time 1.05 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199488600 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.clkmgr_intr_test.2199488600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/49.clkmgr_intr_test.506936355
Short name T961
Test name
Test status
Simulation time 12281922 ps
CPU time 0.74 seconds
Started Sep 18 06:10:03 AM UTC 24
Finished Sep 18 06:10:05 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506936355 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.clkmgr_intr_test.506936355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_mem_rw_with_rand_reset.3505048402
Short name T846
Test name
Test status
Simulation time 27836890 ps
CPU time 1.44 seconds
Started Sep 18 06:09:33 AM UTC 24
Finished Sep 18 06:09:36 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3505048402 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.clkmgr_csr_mem_rw_with_rand_reset.3505048402
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_csr_rw.27527192
Short name T845
Test name
Test status
Simulation time 23242376 ps
CPU time 1.38 seconds
Started Sep 18 06:09:33 AM UTC 24
Finished Sep 18 06:09:36 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27527192 -assert nopos
tproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_csr_rw.27527192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_intr_test.417167755
Short name T844
Test name
Test status
Simulation time 11233707 ps
CPU time 1.07 seconds
Started Sep 18 06:09:33 AM UTC 24
Finished Sep 18 06:09:35 AM UTC 24
Peak memory 211272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417167755 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_intr_test.417167755
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_same_csr_outstanding.719907997
Short name T847
Test name
Test status
Simulation time 38657277 ps
CPU time 1.86 seconds
Started Sep 18 06:09:33 AM UTC 24
Finished Sep 18 06:09:36 AM UTC 24
Peak memory 211772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7199
07997 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_same_csr_outstanding.719907997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors.230728044
Short name T126
Test name
Test status
Simulation time 73399738 ps
CPU time 2.37 seconds
Started Sep 18 06:09:32 AM UTC 24
Finished Sep 18 06:09:35 AM UTC 24
Peak memory 212604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307280
44 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.230728044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_shadow_reg_errors_with_csr_rw.3768531101
Short name T145
Test name
Test status
Simulation time 100296031 ps
CPU time 3.64 seconds
Started Sep 18 06:09:32 AM UTC 24
Finished Sep 18 06:09:37 AM UTC 24
Peak memory 222172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=3768531101 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_
errors_with_csr_rw.3768531101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_errors.459959758
Short name T850
Test name
Test status
Simulation time 317604458 ps
CPU time 5.25 seconds
Started Sep 18 06:09:32 AM UTC 24
Finished Sep 18 06:09:38 AM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459959758 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.459959758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/5.clkmgr_tl_intg_err.181638562
Short name T135
Test name
Test status
Simulation time 93151501 ps
CPU time 2.46 seconds
Started Sep 18 06:09:32 AM UTC 24
Finished Sep 18 06:09:36 AM UTC 24
Peak memory 212616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181638562 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.181638562
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_mem_rw_with_rand_reset.1970938252
Short name T854
Test name
Test status
Simulation time 37122928 ps
CPU time 1.74 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:40 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1970938252 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 6.clkmgr_csr_mem_rw_with_rand_reset.1970938252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_csr_rw.2279067084
Short name T849
Test name
Test status
Simulation time 50550593 ps
CPU time 1.46 seconds
Started Sep 18 06:09:36 AM UTC 24
Finished Sep 18 06:09:38 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279067084 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_csr_rw.2279067084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_intr_test.2165558762
Short name T848
Test name
Test status
Simulation time 18840499 ps
CPU time 1.07 seconds
Started Sep 18 06:09:36 AM UTC 24
Finished Sep 18 06:09:38 AM UTC 24
Peak memory 211328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165558762 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_intr_test.2165558762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_same_csr_outstanding.1322294717
Short name T853
Test name
Test status
Simulation time 58986057 ps
CPU time 1.73 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:40 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322
294717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_same_csr_outstanding.1322294717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors.1903348545
Short name T146
Test name
Test status
Simulation time 144683503 ps
CPU time 2.35 seconds
Started Sep 18 06:09:35 AM UTC 24
Finished Sep 18 06:09:39 AM UTC 24
Peak memory 212640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903348
545 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.1903348545
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_shadow_reg_errors_with_csr_rw.1253340966
Short name T149
Test name
Test status
Simulation time 151991747 ps
CPU time 3.56 seconds
Started Sep 18 06:09:35 AM UTC 24
Finished Sep 18 06:09:40 AM UTC 24
Peak memory 229096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=1253340966 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_
errors_with_csr_rw.1253340966
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_errors.289183891
Short name T831
Test name
Test status
Simulation time 191994329 ps
CPU time 2.98 seconds
Started Sep 18 06:09:36 AM UTC 24
Finished Sep 18 06:09:39 AM UTC 24
Peak memory 212364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289183891 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.289183891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/6.clkmgr_tl_intg_err.3546095654
Short name T140
Test name
Test status
Simulation time 133242060 ps
CPU time 4.12 seconds
Started Sep 18 06:09:36 AM UTC 24
Finished Sep 18 06:09:41 AM UTC 24
Peak memory 212440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546095654 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.3546095654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_mem_rw_with_rand_reset.402268346
Short name T858
Test name
Test status
Simulation time 93910415 ps
CPU time 2.02 seconds
Started Sep 18 06:09:39 AM UTC 24
Finished Sep 18 06:09:42 AM UTC 24
Peak memory 212360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=402268346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 7.clkmgr_csr_mem_rw_with_rand_reset.402268346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_csr_rw.2371716876
Short name T852
Test name
Test status
Simulation time 17943180 ps
CPU time 1.04 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:39 AM UTC 24
Peak memory 211652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371716876 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_csr_rw.2371716876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_intr_test.2049493066
Short name T851
Test name
Test status
Simulation time 26385417 ps
CPU time 1.01 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:39 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049493066 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_intr_test.2049493066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_same_csr_outstanding.1498078798
Short name T855
Test name
Test status
Simulation time 49993972 ps
CPU time 1.56 seconds
Started Sep 18 06:09:39 AM UTC 24
Finished Sep 18 06:09:41 AM UTC 24
Peak memory 211716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498
078798 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_same_csr_outstanding.1498078798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors.278167170
Short name T152
Test name
Test status
Simulation time 148459927 ps
CPU time 1.95 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:40 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781671
70 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.278167170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_shadow_reg_errors_with_csr_rw.2841787670
Short name T161
Test name
Test status
Simulation time 123388706 ps
CPU time 2.55 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:41 AM UTC 24
Peak memory 222020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=2841787670 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_
errors_with_csr_rw.2841787670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/7.clkmgr_tl_errors.693948242
Short name T856
Test name
Test status
Simulation time 88322252 ps
CPU time 3.41 seconds
Started Sep 18 06:09:37 AM UTC 24
Finished Sep 18 06:09:42 AM UTC 24
Peak memory 212448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693948242 -assert nopostp
roc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.693948242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_mem_rw_with_rand_reset.1544167231
Short name T861
Test name
Test status
Simulation time 138159838 ps
CPU time 2.14 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:44 AM UTC 24
Peak memory 212292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=1544167231 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.clkmgr_csr_mem_rw_with_rand_reset.1544167231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_csr_rw.3421695299
Short name T860
Test name
Test status
Simulation time 20940497 ps
CPU time 1.15 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:43 AM UTC 24
Peak memory 211588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421695299 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_csr_rw.3421695299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_intr_test.4102089101
Short name T859
Test name
Test status
Simulation time 14673715 ps
CPU time 1.05 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:43 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102089101 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_intr_test.4102089101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_same_csr_outstanding.2697774355
Short name T865
Test name
Test status
Simulation time 465698548 ps
CPU time 2.84 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 212372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697
774355 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_same_csr_outstanding.2697774355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors.210737699
Short name T150
Test name
Test status
Simulation time 75111919 ps
CPU time 1.46 seconds
Started Sep 18 06:09:39 AM UTC 24
Finished Sep 18 06:09:41 AM UTC 24
Peak memory 211592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107376
99 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.210737699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_shadow_reg_errors_with_csr_rw.56088146
Short name T151
Test name
Test status
Simulation time 166097205 ps
CPU time 2.53 seconds
Started Sep 18 06:09:39 AM UTC 24
Finished Sep 18 06:09:43 AM UTC 24
Peak memory 222008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=56088146 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_er
rors_with_csr_rw.56088146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_errors.1971045043
Short name T866
Test name
Test status
Simulation time 209640123 ps
CPU time 3.16 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 212636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971045043 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.1971045043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/8.clkmgr_tl_intg_err.793414393
Short name T137
Test name
Test status
Simulation time 181286806 ps
CPU time 2.35 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:44 AM UTC 24
Peak memory 212624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793414393 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.793414393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_mem_rw_with_rand_reset.3361482147
Short name T869
Test name
Test status
Simulation time 72909886 ps
CPU time 1.52 seconds
Started Sep 18 06:09:43 AM UTC 24
Finished Sep 18 06:09:46 AM UTC 24
Peak memory 211704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/
tools/sim.tcl +ntb_random_seed=3361482147 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.clkmgr_csr_mem_rw_with_rand_reset.3361482147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_csr_rw.2481708015
Short name T863
Test name
Test status
Simulation time 19792806 ps
CPU time 1.08 seconds
Started Sep 18 06:09:42 AM UTC 24
Finished Sep 18 06:09:44 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481708015 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_csr_rw.2481708015
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_intr_test.1157929737
Short name T862
Test name
Test status
Simulation time 18123271 ps
CPU time 1.04 seconds
Started Sep 18 06:09:42 AM UTC 24
Finished Sep 18 06:09:44 AM UTC 24
Peak memory 211268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_intr_test +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157929737 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_intr_test.1157929737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_same_csr_outstanding.3078700032
Short name T864
Test name
Test status
Simulation time 38951627 ps
CPU time 1.64 seconds
Started Sep 18 06:09:42 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 211916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078
700032 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_same_csr_outstanding.3078700032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors.969000557
Short name T147
Test name
Test status
Simulation time 120389321 ps
CPU time 3.04 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 228648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9690005
57 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.969000557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_shadow_reg_errors_with_csr_rw.236173807
Short name T159
Test name
Test status
Simulation time 142312310 ps
CPU time 2.53 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 212980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interru
pts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_
seed=236173807 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_e
rrors_with_csr_rw.236173807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top/9.clkmgr_tl_errors.3931413949
Short name T867
Test name
Test status
Simulation time 115050105 ps
CPU time 3.07 seconds
Started Sep 18 06:09:41 AM UTC 24
Finished Sep 18 06:09:45 AM UTC 24
Peak memory 212684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931413949 -assert nopost
proc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.3931413949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_div_intersig_mubi.1123933018
Short name T71
Test name
Test status
Simulation time 57214961 ps
CPU time 1.25 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123933018 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_div_intersig_mubi.1123933018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_frequency_timeout.2138387136
Short name T1
Test name
Test status
Simulation time 668922945 ps
CPU time 3.12 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 210632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138387136 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.2138387136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_idle_intersig_mubi.1483786622
Short name T29
Test name
Test status
Simulation time 28453440 ps
CPU time 0.82 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483786622 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.1483786622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_lc_ctrl_intersig_mubi.2038203931
Short name T33
Test name
Test status
Simulation time 24082283 ps
CPU time 1.15 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038203931
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_lc_ctrl_intersig_mubi.2038203931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_stress_all.3792950694
Short name T37
Test name
Test status
Simulation time 5406403353 ps
CPU time 42.52 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:11:28 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792950694 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all.3792950694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/0.clkmgr_trans.4277835464
Short name T30
Test name
Test status
Simulation time 79144754 ps
CPU time 0.92 seconds
Started Sep 18 06:10:42 AM UTC 24
Finished Sep 18 06:10:44 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277835464 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.4277835464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/0.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_alert_test.1376988759
Short name T60
Test name
Test status
Simulation time 64406657 ps
CPU time 1 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 210860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1376988759 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.1376988759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_clk_status.1338061672
Short name T35
Test name
Test status
Simulation time 16289987 ps
CPU time 0.73 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338061672 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.1338061672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_div_intersig_mubi.777575337
Short name T58
Test name
Test status
Simulation time 16175727 ps
CPU time 0.96 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777575337 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_div_intersig_mubi.777575337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_extclk.1163026649
Short name T53
Test name
Test status
Simulation time 15082269 ps
CPU time 1.01 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163026649 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_extclk.1163026649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency.4016756444
Short name T9
Test name
Test status
Simulation time 962699633 ps
CPU time 5.17 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:50 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4016756444 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.4016756444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_frequency_timeout.4003966775
Short name T68
Test name
Test status
Simulation time 1829056015 ps
CPU time 10.26 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 210572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003966775 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.4003966775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_lc_clk_byp_req_intersig_mubi.193937787
Short name T59
Test name
Test status
Simulation time 59511289 ps
CPU time 1.15 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:47 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193937787 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_lc_clk_byp_req_intersig_mubi.193937787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_peri.2892436759
Short name T52
Test name
Test status
Simulation time 24684034 ps
CPU time 0.86 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892436759 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.2892436759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_regwen.3891782750
Short name T2
Test name
Test status
Simulation time 92674053 ps
CPU time 1.33 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:48 AM UTC 24
Peak memory 210048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891782750 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.3891782750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_sec_cm.3446626901
Short name T89
Test name
Test status
Simulation time 164130233 ps
CPU time 2.18 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:48 AM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446626901 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.3446626901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_smoke.330834944
Short name T55
Test name
Test status
Simulation time 25339337 ps
CPU time 1.36 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330834944 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.330834944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/1.clkmgr_trans.7530266
Short name T54
Test name
Test status
Simulation time 51864136 ps
CPU time 1.05 seconds
Started Sep 18 06:10:44 AM UTC 24
Finished Sep 18 06:10:46 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7530266 -assert nopostproc +UVM_TESTNAME=clkmg
r_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.7530266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/1.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_alert_test.2936115512
Short name T259
Test name
Test status
Simulation time 70808574 ps
CPU time 0.94 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936115512 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_alert_test.2936115512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_handshake_intersig_mubi.832710712
Short name T258
Test name
Test status
Simulation time 45794835 ps
CPU time 0.87 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832710712 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_handshake_intersig_mubi.832710712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_clk_status.976187155
Short name T191
Test name
Test status
Simulation time 34459415 ps
CPU time 0.7 seconds
Started Sep 18 06:11:28 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976187155 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_clk_status.976187155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_div_intersig_mubi.3537062597
Short name T256
Test name
Test status
Simulation time 24064258 ps
CPU time 0.75 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537062597 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_div_intersig_mubi.3537062597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_extclk.605732816
Short name T196
Test name
Test status
Simulation time 110968207 ps
CPU time 1.31 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:37 AM UTC 24
Peak memory 208928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605732816 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_extclk.605732816
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency.2931120970
Short name T264
Test name
Test status
Simulation time 2296535692 ps
CPU time 9.02 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:50 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931120970 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency.2931120970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_frequency_timeout.1346585316
Short name T242
Test name
Test status
Simulation time 740216119 ps
CPU time 4.25 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:40 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346585316 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_frequency_timeout.1346585316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_idle_intersig_mubi.324571996
Short name T237
Test name
Test status
Simulation time 352402653 ps
CPU time 1.95 seconds
Started Sep 18 06:11:29 AM UTC 24
Finished Sep 18 06:11:32 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324571996 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_idle_intersig_mubi.324571996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_clk_byp_req_intersig_mubi.1270886748
Short name T254
Test name
Test status
Simulation time 214077047 ps
CPU time 1.3 seconds
Started Sep 18 06:11:31 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270886748
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_clk_byp_req_intersig_mubi.1270886748
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_lc_ctrl_intersig_mubi.2581136987
Short name T253
Test name
Test status
Simulation time 89586832 ps
CPU time 1.22 seconds
Started Sep 18 06:11:31 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581136987
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_lc_ctrl_intersig_mubi.2581136987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_peri.2568825240
Short name T231
Test name
Test status
Simulation time 36121885 ps
CPU time 0.87 seconds
Started Sep 18 06:11:28 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568825240 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_peri.2568825240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_regwen.3285667155
Short name T172
Test name
Test status
Simulation time 221792195 ps
CPU time 1.79 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:48 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285667155 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_regwen.3285667155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_smoke.480856949
Short name T247
Test name
Test status
Simulation time 21236347 ps
CPU time 0.81 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480856949 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_smoke.480856949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all.162372151
Short name T167
Test name
Test status
Simulation time 1582782171 ps
CPU time 7.16 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:54 AM UTC 24
Peak memory 210876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162372151 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_stress_all.162372151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_stress_all_with_rand_reset.3283487983
Short name T200
Test name
Test status
Simulation time 2742953791 ps
CPU time 46.66 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 227584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283487983 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.clkmgr_stress_all_with_rand_reset.3283487983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/10.clkmgr_trans.3308226263
Short name T233
Test name
Test status
Simulation time 33923236 ps
CPU time 0.93 seconds
Started Sep 18 06:11:28 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308226263 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.clkmgr_trans.3308226263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/10.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_alert_test.2016720404
Short name T186
Test name
Test status
Simulation time 37769889 ps
CPU time 0.83 seconds
Started Sep 18 06:11:42 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016720404 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_alert_test.2016720404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_handshake_intersig_mubi.2253258919
Short name T107
Test name
Test status
Simulation time 38724821 ps
CPU time 0.88 seconds
Started Sep 18 06:11:38 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253258919 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_handshake_intersig_mubi.2253258919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_clk_status.40747001
Short name T244
Test name
Test status
Simulation time 34061569 ps
CPU time 0.66 seconds
Started Sep 18 06:11:37 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40747001 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_clk_status.40747001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_div_intersig_mubi.2001953200
Short name T248
Test name
Test status
Simulation time 25865531 ps
CPU time 0.83 seconds
Started Sep 18 06:11:39 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001953200 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_div_intersig_mubi.2001953200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_extclk.480584255
Short name T239
Test name
Test status
Simulation time 123034016 ps
CPU time 0.95 seconds
Started Sep 18 06:11:33 AM UTC 24
Finished Sep 18 06:11:36 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480584255 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_extclk.480584255
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency.2105665381
Short name T42
Test name
Test status
Simulation time 1882467616 ps
CPU time 14.65 seconds
Started Sep 18 06:11:33 AM UTC 24
Finished Sep 18 06:11:50 AM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105665381 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency.2105665381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_frequency_timeout.1903271931
Short name T243
Test name
Test status
Simulation time 1116557385 ps
CPU time 5.25 seconds
Started Sep 18 06:11:34 AM UTC 24
Finished Sep 18 06:11:41 AM UTC 24
Peak memory 209924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903271931 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_frequency_timeout.1903271931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_idle_intersig_mubi.3386149363
Short name T249
Test name
Test status
Simulation time 156978770 ps
CPU time 1.31 seconds
Started Sep 18 06:11:37 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 207856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386149363 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_idle_intersig_mubi.3386149363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_clk_byp_req_intersig_mubi.194184111
Short name T252
Test name
Test status
Simulation time 108628759 ps
CPU time 1.05 seconds
Started Sep 18 06:11:38 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194184111 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_clk_byp_req_intersig_mubi.194184111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_lc_ctrl_intersig_mubi.4039122615
Short name T245
Test name
Test status
Simulation time 17948811 ps
CPU time 0.74 seconds
Started Sep 18 06:11:37 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039122615
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_lc_ctrl_intersig_mubi.4039122615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_peri.4275334931
Short name T238
Test name
Test status
Simulation time 15219985 ps
CPU time 0.67 seconds
Started Sep 18 06:11:34 AM UTC 24
Finished Sep 18 06:11:36 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275334931 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_peri.4275334931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_regwen.2696154950
Short name T250
Test name
Test status
Simulation time 106655147 ps
CPU time 1 seconds
Started Sep 18 06:11:40 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 208500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696154950 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_regwen.2696154950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_smoke.1338870202
Short name T177
Test name
Test status
Simulation time 22525913 ps
CPU time 0.9 seconds
Started Sep 18 06:11:32 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338870202 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_smoke.1338870202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all.848479592
Short name T164
Test name
Test status
Simulation time 5359400772 ps
CPU time 23.33 seconds
Started Sep 18 06:11:42 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848479592 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_stress_all.848479592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_stress_all_with_rand_reset.3056678099
Short name T73
Test name
Test status
Simulation time 4894236504 ps
CPU time 28.2 seconds
Started Sep 18 06:11:40 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 220392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056678099 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.clkmgr_stress_all_with_rand_reset.3056678099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/11.clkmgr_trans.1899561307
Short name T246
Test name
Test status
Simulation time 65631711 ps
CPU time 0.91 seconds
Started Sep 18 06:11:37 AM UTC 24
Finished Sep 18 06:11:42 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899561307 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.clkmgr_trans.1899561307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/11.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_alert_test.2950455581
Short name T268
Test name
Test status
Simulation time 16369390 ps
CPU time 0.69 seconds
Started Sep 18 06:11:46 AM UTC 24
Finished Sep 18 06:11:51 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950455581 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_alert_test.2950455581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_handshake_intersig_mubi.4153384413
Short name T260
Test name
Test status
Simulation time 30083076 ps
CPU time 0.87 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153384413 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_handshake_intersig_mubi.4153384413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_clk_status.2879088887
Short name T192
Test name
Test status
Simulation time 27133215 ps
CPU time 0.8 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879088887 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_clk_status.2879088887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_div_intersig_mubi.3152197771
Short name T257
Test name
Test status
Simulation time 23875218 ps
CPU time 0.71 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152197771 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_div_intersig_mubi.3152197771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_extclk.1598818708
Short name T269
Test name
Test status
Simulation time 71485285 ps
CPU time 0.94 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:51 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598818708 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_extclk.1598818708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency.3363477037
Short name T301
Test name
Test status
Simulation time 1076349876 ps
CPU time 5.4 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363477037 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency.3363477037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_frequency_timeout.731459538
Short name T307
Test name
Test status
Simulation time 1098629556 ps
CPU time 6.22 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:58 AM UTC 24
Peak memory 210708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731459538 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_frequency_timeout.731459538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_idle_intersig_mubi.2954050549
Short name T255
Test name
Test status
Simulation time 25134711 ps
CPU time 0.87 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954050549 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_idle_intersig_mubi.2954050549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_clk_byp_req_intersig_mubi.3448735929
Short name T261
Test name
Test status
Simulation time 33304123 ps
CPU time 0.96 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448735929
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_clk_byp_req_intersig_mubi.3448735929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_lc_ctrl_intersig_mubi.229288744
Short name T262
Test name
Test status
Simulation time 22535950 ps
CPU time 1.03 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:47 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229288744 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_lc_ctrl_intersig_mubi.229288744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_peri.3427562140
Short name T273
Test name
Test status
Simulation time 54177558 ps
CPU time 0.8 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:52 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427562140 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_peri.3427562140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_regwen.2038498133
Short name T263
Test name
Test status
Simulation time 274436756 ps
CPU time 2.03 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:49 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038498133 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_regwen.2038498133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_smoke.1030392869
Short name T266
Test name
Test status
Simulation time 18830442 ps
CPU time 0.79 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:51 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030392869 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_smoke.1030392869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_stress_all.1658613799
Short name T308
Test name
Test status
Simulation time 2857641025 ps
CPU time 11.18 seconds
Started Sep 18 06:11:45 AM UTC 24
Finished Sep 18 06:11:58 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658613799 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_stress_all.1658613799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/12.clkmgr_trans.295183602
Short name T279
Test name
Test status
Simulation time 73255762 ps
CPU time 0.97 seconds
Started Sep 18 06:11:43 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295183602 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.clkmgr_trans.295183602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/12.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_alert_test.338829924
Short name T284
Test name
Test status
Simulation time 156893445 ps
CPU time 1.31 seconds
Started Sep 18 06:11:50 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338829924 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_alert_test.338829924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_handshake_intersig_mubi.4233508391
Short name T277
Test name
Test status
Simulation time 53146307 ps
CPU time 0.97 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233508391 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_handshake_intersig_mubi.4233508391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_clk_status.1335287280
Short name T271
Test name
Test status
Simulation time 23155116 ps
CPU time 0.74 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:52 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335287280 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_clk_status.1335287280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_div_intersig_mubi.1526339974
Short name T276
Test name
Test status
Simulation time 55833622 ps
CPU time 0.89 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526339974 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_div_intersig_mubi.1526339974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_extclk.2445804705
Short name T267
Test name
Test status
Simulation time 18570477 ps
CPU time 0.92 seconds
Started Sep 18 06:11:46 AM UTC 24
Finished Sep 18 06:11:51 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445804705 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_extclk.2445804705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency.4237272104
Short name T323
Test name
Test status
Simulation time 1155067941 ps
CPU time 9.73 seconds
Started Sep 18 06:11:48 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237272104 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency.4237272104
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_frequency_timeout.625391830
Short name T306
Test name
Test status
Simulation time 738232138 ps
CPU time 5.69 seconds
Started Sep 18 06:11:48 AM UTC 24
Finished Sep 18 06:11:58 AM UTC 24
Peak memory 210768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625391830 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_frequency_timeout.625391830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_idle_intersig_mubi.3704809989
Short name T278
Test name
Test status
Simulation time 112768875 ps
CPU time 1.21 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704809989 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_idle_intersig_mubi.3704809989
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_clk_byp_req_intersig_mubi.2616715537
Short name T281
Test name
Test status
Simulation time 92739301 ps
CPU time 1.27 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616715537
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_clk_byp_req_intersig_mubi.2616715537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_lc_ctrl_intersig_mubi.963346008
Short name T274
Test name
Test status
Simulation time 25775596 ps
CPU time 1.04 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963346008 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_lc_ctrl_intersig_mubi.963346008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_peri.2936058452
Short name T282
Test name
Test status
Simulation time 34628740 ps
CPU time 0.88 seconds
Started Sep 18 06:11:48 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936058452 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_peri.2936058452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_regwen.4235945168
Short name T287
Test name
Test status
Simulation time 862393916 ps
CPU time 2.96 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:55 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235945168 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_regwen.4235945168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_smoke.2628025813
Short name T270
Test name
Test status
Simulation time 15521999 ps
CPU time 0.79 seconds
Started Sep 18 06:11:46 AM UTC 24
Finished Sep 18 06:11:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628025813 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_smoke.2628025813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all.1340218167
Short name T311
Test name
Test status
Simulation time 1063344002 ps
CPU time 8.68 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:59 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340218167 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_stress_all.1340218167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_stress_all_with_rand_reset.11863743
Short name T74
Test name
Test status
Simulation time 4110002290 ps
CPU time 20.16 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:12:11 AM UTC 24
Peak memory 220508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11863743 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.clkmgr_stress_all_with_rand_reset.11863743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/13.clkmgr_trans.4009307305
Short name T272
Test name
Test status
Simulation time 16532409 ps
CPU time 0.84 seconds
Started Sep 18 06:11:49 AM UTC 24
Finished Sep 18 06:11:52 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4009307305 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.clkmgr_trans.4009307305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/13.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_alert_test.2854152688
Short name T295
Test name
Test status
Simulation time 45072916 ps
CPU time 1.03 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854152688 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_alert_test.2854152688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_handshake_intersig_mubi.321225264
Short name T108
Test name
Test status
Simulation time 45722006 ps
CPU time 1.1 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:56 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321225264 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_handshake_intersig_mubi.321225264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_clk_status.2010406308
Short name T289
Test name
Test status
Simulation time 45458139 ps
CPU time 0.76 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:56 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010406308 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_clk_status.2010406308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_div_intersig_mubi.2897608698
Short name T297
Test name
Test status
Simulation time 55533589 ps
CPU time 1.29 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897608698 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_div_intersig_mubi.2897608698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_extclk.470354504
Short name T283
Test name
Test status
Simulation time 52398778 ps
CPU time 1.16 seconds
Started Sep 18 06:11:50 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470354504 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_extclk.470354504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency.609723591
Short name T334
Test name
Test status
Simulation time 1520124327 ps
CPU time 12.56 seconds
Started Sep 18 06:11:52 AM UTC 24
Finished Sep 18 06:12:05 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609723591 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency.609723591
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_frequency_timeout.2070859018
Short name T310
Test name
Test status
Simulation time 1104554032 ps
CPU time 5.88 seconds
Started Sep 18 06:11:52 AM UTC 24
Finished Sep 18 06:11:59 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070859018 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_frequency_timeout.2070859018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_idle_intersig_mubi.1665980760
Short name T290
Test name
Test status
Simulation time 31791125 ps
CPU time 0.92 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:56 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665980760 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_idle_intersig_mubi.1665980760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_clk_byp_req_intersig_mubi.757474003
Short name T291
Test name
Test status
Simulation time 18086601 ps
CPU time 0.86 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:56 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757474003 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_clk_byp_req_intersig_mubi.757474003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_lc_ctrl_intersig_mubi.4190362881
Short name T294
Test name
Test status
Simulation time 49241536 ps
CPU time 1.18 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190362881
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_lc_ctrl_intersig_mubi.4190362881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_peri.3276217215
Short name T285
Test name
Test status
Simulation time 38720873 ps
CPU time 0.7 seconds
Started Sep 18 06:11:52 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276217215 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_peri.3276217215
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_regwen.2699821074
Short name T174
Test name
Test status
Simulation time 2069971258 ps
CPU time 7.22 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:12:03 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699821074 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_regwen.2699821074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_smoke.1221908674
Short name T280
Test name
Test status
Simulation time 28551915 ps
CPU time 0.86 seconds
Started Sep 18 06:11:50 AM UTC 24
Finished Sep 18 06:11:53 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221908674 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_smoke.1221908674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all.1411141491
Short name T331
Test name
Test status
Simulation time 2397866060 ps
CPU time 8.5 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:12:04 AM UTC 24
Peak memory 210944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411141491 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_stress_all.1411141491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_stress_all_with_rand_reset.205348849
Short name T116
Test name
Test status
Simulation time 2811856629 ps
CPU time 49.25 seconds
Started Sep 18 06:11:54 AM UTC 24
Finished Sep 18 06:12:45 AM UTC 24
Peak memory 220540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205348849 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 14.clkmgr_stress_all_with_rand_reset.205348849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/14.clkmgr_trans.1184352630
Short name T286
Test name
Test status
Simulation time 109987957 ps
CPU time 1.2 seconds
Started Sep 18 06:11:52 AM UTC 24
Finished Sep 18 06:11:54 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184352630 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.clkmgr_trans.1184352630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/14.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_alert_test.1201412750
Short name T314
Test name
Test status
Simulation time 104518649 ps
CPU time 0.98 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:00 AM UTC 24
Peak memory 209728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201412750 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_alert_test.1201412750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_handshake_intersig_mubi.91485825
Short name T109
Test name
Test status
Simulation time 16415082 ps
CPU time 0.75 seconds
Started Sep 18 06:11:56 AM UTC 24
Finished Sep 18 06:11:58 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91485825 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_handshake_intersig_mubi.91485825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_clk_status.971385613
Short name T299
Test name
Test status
Simulation time 39483003 ps
CPU time 1 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971385613 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_clk_status.971385613
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_div_intersig_mubi.587836497
Short name T309
Test name
Test status
Simulation time 20062811 ps
CPU time 1.05 seconds
Started Sep 18 06:11:56 AM UTC 24
Finished Sep 18 06:11:58 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587836497 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_div_intersig_mubi.587836497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_extclk.3391809183
Short name T296
Test name
Test status
Simulation time 22886651 ps
CPU time 1.01 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391809183 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_extclk.3391809183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency.830640085
Short name T317
Test name
Test status
Simulation time 1058404215 ps
CPU time 5.7 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:12:01 AM UTC 24
Peak memory 210852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830640085 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency.830640085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_frequency_timeout.2459008551
Short name T305
Test name
Test status
Simulation time 151376332 ps
CPU time 1.46 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459008551 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_frequency_timeout.2459008551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_idle_intersig_mubi.4096405069
Short name T303
Test name
Test status
Simulation time 101633580 ps
CPU time 1.17 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096405069 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_idle_intersig_mubi.4096405069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_clk_byp_req_intersig_mubi.406308985
Short name T300
Test name
Test status
Simulation time 18751512 ps
CPU time 0.93 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406308985 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_clk_byp_req_intersig_mubi.406308985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_lc_ctrl_intersig_mubi.3565589342
Short name T304
Test name
Test status
Simulation time 22938366 ps
CPU time 1.17 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565589342
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_lc_ctrl_intersig_mubi.3565589342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_peri.2991089783
Short name T298
Test name
Test status
Simulation time 26692011 ps
CPU time 1.03 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991089783 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_peri.2991089783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_regwen.377441975
Short name T324
Test name
Test status
Simulation time 1170377603 ps
CPU time 4.59 seconds
Started Sep 18 06:11:56 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377441975 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_regwen.377441975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_smoke.1583322512
Short name T168
Test name
Test status
Simulation time 67392131 ps
CPU time 1.1 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583322512 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_smoke.1583322512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all.1147722980
Short name T444
Test name
Test status
Simulation time 7376125577 ps
CPU time 32.38 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147722980 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_stress_all.1147722980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_stress_all_with_rand_reset.2471421345
Short name T668
Test name
Test status
Simulation time 13910636530 ps
CPU time 96.23 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471421345 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.clkmgr_stress_all_with_rand_reset.2471421345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/15.clkmgr_trans.382430797
Short name T302
Test name
Test status
Simulation time 47083468 ps
CPU time 1.23 seconds
Started Sep 18 06:11:55 AM UTC 24
Finished Sep 18 06:11:57 AM UTC 24
Peak memory 210332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382430797 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.clkmgr_trans.382430797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/15.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_alert_test.2004116990
Short name T326
Test name
Test status
Simulation time 20712664 ps
CPU time 0.96 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2004116990 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_alert_test.2004116990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_handshake_intersig_mubi.38421621
Short name T322
Test name
Test status
Simulation time 23321076 ps
CPU time 1.01 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38421621 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_handshake_intersig_mubi.38421621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_clk_status.60215934
Short name T318
Test name
Test status
Simulation time 22011624 ps
CPU time 0.99 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60215934 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_clk_status.60215934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_div_intersig_mubi.4270115269
Short name T325
Test name
Test status
Simulation time 102223685 ps
CPU time 1.33 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270115269 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_div_intersig_mubi.4270115269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_extclk.3871376570
Short name T316
Test name
Test status
Simulation time 23075523 ps
CPU time 0.94 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:01 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871376570 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_extclk.3871376570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency.1520548156
Short name T333
Test name
Test status
Simulation time 1270177778 ps
CPU time 5.65 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:05 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520548156 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency.1520548156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_frequency_timeout.3023617535
Short name T357
Test name
Test status
Simulation time 2320185905 ps
CPU time 10.04 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3023617535 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_frequency_timeout.3023617535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_idle_intersig_mubi.866150654
Short name T292
Test name
Test status
Simulation time 81090011 ps
CPU time 1.33 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866150654 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_idle_intersig_mubi.866150654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_clk_byp_req_intersig_mubi.89110581
Short name T320
Test name
Test status
Simulation time 33330549 ps
CPU time 1.1 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89110581 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_clk_byp_req_intersig_mubi.89110581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_lc_ctrl_intersig_mubi.1344863331
Short name T321
Test name
Test status
Simulation time 29125259 ps
CPU time 1.12 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344863331
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_lc_ctrl_intersig_mubi.1344863331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_peri.1646805867
Short name T315
Test name
Test status
Simulation time 20051289 ps
CPU time 0.83 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:01 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646805867 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_peri.1646805867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_smoke.3131214135
Short name T312
Test name
Test status
Simulation time 29710349 ps
CPU time 0.85 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:00 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131214135 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_smoke.3131214135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all.1224246622
Short name T480
Test name
Test status
Simulation time 9720307986 ps
CPU time 38.56 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:40 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224246622 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_stress_all.1224246622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_stress_all_with_rand_reset.3895982495
Short name T478
Test name
Test status
Simulation time 5961225113 ps
CPU time 37.15 seconds
Started Sep 18 06:11:59 AM UTC 24
Finished Sep 18 06:12:38 AM UTC 24
Peak memory 224708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895982495 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.clkmgr_stress_all_with_rand_reset.3895982495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/16.clkmgr_trans.1604428656
Short name T319
Test name
Test status
Simulation time 62341152 ps
CPU time 1.36 seconds
Started Sep 18 06:11:58 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604428656 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.clkmgr_trans.1604428656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/16.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_alert_test.2154129112
Short name T335
Test name
Test status
Simulation time 71325939 ps
CPU time 1 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154129112 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_alert_test.2154129112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_handshake_intersig_mubi.2572724024
Short name T110
Test name
Test status
Simulation time 43894108 ps
CPU time 1.22 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572724024 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_handshake_intersig_mubi.2572724024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_clk_status.1544626610
Short name T330
Test name
Test status
Simulation time 174716706 ps
CPU time 1.24 seconds
Started Sep 18 06:12:01 AM UTC 24
Finished Sep 18 06:12:04 AM UTC 24
Peak memory 208268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544626610 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_clk_status.1544626610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_div_intersig_mubi.2831981423
Short name T339
Test name
Test status
Simulation time 70702773 ps
CPU time 1.31 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831981423 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_div_intersig_mubi.2831981423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_extclk.437330368
Short name T275
Test name
Test status
Simulation time 12221384 ps
CPU time 0.83 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437330368 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_extclk.437330368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency.2168987478
Short name T343
Test name
Test status
Simulation time 802708324 ps
CPU time 4.95 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168987478 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency.2168987478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_frequency_timeout.3357242442
Short name T346
Test name
Test status
Simulation time 1105247677 ps
CPU time 5.83 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:07 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357242442 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_frequency_timeout.3357242442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_idle_intersig_mubi.1465312688
Short name T328
Test name
Test status
Simulation time 45262042 ps
CPU time 1.14 seconds
Started Sep 18 06:12:01 AM UTC 24
Finished Sep 18 06:12:04 AM UTC 24
Peak memory 208188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465312688 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_idle_intersig_mubi.1465312688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_clk_byp_req_intersig_mubi.1612050880
Short name T329
Test name
Test status
Simulation time 48830549 ps
CPU time 1.11 seconds
Started Sep 18 06:12:01 AM UTC 24
Finished Sep 18 06:12:04 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612050880
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_clk_byp_req_intersig_mubi.1612050880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_lc_ctrl_intersig_mubi.1091832271
Short name T332
Test name
Test status
Simulation time 28780693 ps
CPU time 1.02 seconds
Started Sep 18 06:12:01 AM UTC 24
Finished Sep 18 06:12:04 AM UTC 24
Peak memory 210720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091832271
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_lc_ctrl_intersig_mubi.1091832271
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_peri.2819472315
Short name T288
Test name
Test status
Simulation time 32720578 ps
CPU time 1.01 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819472315 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_peri.2819472315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_regwen.1146488806
Short name T351
Test name
Test status
Simulation time 1007408348 ps
CPU time 3.87 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:09 AM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146488806 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_regwen.1146488806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_smoke.3751152082
Short name T293
Test name
Test status
Simulation time 41725001 ps
CPU time 1 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:02 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751152082 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_smoke.3751152082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all.4117858503
Short name T396
Test name
Test status
Simulation time 1595470174 ps
CPU time 12.97 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:18 AM UTC 24
Peak memory 210848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117858503 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_stress_all.4117858503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_stress_all_with_rand_reset.3554731308
Short name T618
Test name
Test status
Simulation time 5261876012 ps
CPU time 72.24 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:13:18 AM UTC 24
Peak memory 220100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554731308 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.clkmgr_stress_all_with_rand_reset.3554731308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/17.clkmgr_trans.4175614293
Short name T327
Test name
Test status
Simulation time 108527042 ps
CPU time 1.39 seconds
Started Sep 18 06:12:00 AM UTC 24
Finished Sep 18 06:12:03 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175614293 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.clkmgr_trans.4175614293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/17.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_alert_test.2401943221
Short name T349
Test name
Test status
Simulation time 49730084 ps
CPU time 1.09 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:08 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401943221 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_alert_test.2401943221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_handshake_intersig_mubi.30845197
Short name T111
Test name
Test status
Simulation time 50094369 ps
CPU time 1.17 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:07 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30845197 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_handshake_intersig_mubi.30845197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_clk_status.2939953440
Short name T342
Test name
Test status
Simulation time 15297442 ps
CPU time 0.87 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939953440 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_clk_status.2939953440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_div_intersig_mubi.1824633572
Short name T347
Test name
Test status
Simulation time 16854641 ps
CPU time 0.81 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:08 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824633572 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_div_intersig_mubi.1824633572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_extclk.956738701
Short name T338
Test name
Test status
Simulation time 74540321 ps
CPU time 1.12 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956738701 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_extclk.956738701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency.1929353885
Short name T360
Test name
Test status
Simulation time 997248613 ps
CPU time 5.36 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929353885 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency.1929353885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_frequency_timeout.3243424571
Short name T354
Test name
Test status
Simulation time 502074188 ps
CPU time 4.46 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243424571 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_frequency_timeout.3243424571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_idle_intersig_mubi.3927089917
Short name T344
Test name
Test status
Simulation time 63988289 ps
CPU time 1.01 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927089917 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_idle_intersig_mubi.3927089917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_clk_byp_req_intersig_mubi.2432090344
Short name T341
Test name
Test status
Simulation time 21732324 ps
CPU time 0.8 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432090344
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_clk_byp_req_intersig_mubi.2432090344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_lc_ctrl_intersig_mubi.3416163761
Short name T345
Test name
Test status
Simulation time 52606552 ps
CPU time 1.05 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416163761
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_lc_ctrl_intersig_mubi.3416163761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_peri.3223237574
Short name T340
Test name
Test status
Simulation time 59279537 ps
CPU time 1.19 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223237574 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_peri.3223237574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_regwen.2704799225
Short name T175
Test name
Test status
Simulation time 777446947 ps
CPU time 5.05 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:12 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704799225 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_regwen.2704799225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_smoke.4123473481
Short name T163
Test name
Test status
Simulation time 24983752 ps
CPU time 1.12 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123473481 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_smoke.4123473481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all.3152535902
Short name T463
Test name
Test status
Simulation time 5601781762 ps
CPU time 26.7 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152535902 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_stress_all.3152535902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_stress_all_with_rand_reset.4248370811
Short name T671
Test name
Test status
Simulation time 8753724728 ps
CPU time 88.62 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 220552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248370811 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.clkmgr_stress_all_with_rand_reset.4248370811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/18.clkmgr_trans.1174723222
Short name T336
Test name
Test status
Simulation time 20383107 ps
CPU time 0.86 seconds
Started Sep 18 06:12:04 AM UTC 24
Finished Sep 18 06:12:06 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174723222 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.clkmgr_trans.1174723222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/18.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_alert_test.698174088
Short name T358
Test name
Test status
Simulation time 24290811 ps
CPU time 1.11 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698174088 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_alert_test.698174088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_handshake_intersig_mubi.536039268
Short name T112
Test name
Test status
Simulation time 81495637 ps
CPU time 1.28 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536039268 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_handshake_intersig_mubi.536039268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_clk_status.467975712
Short name T352
Test name
Test status
Simulation time 16482070 ps
CPU time 0.81 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467975712 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_clk_status.467975712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_div_intersig_mubi.3842388301
Short name T356
Test name
Test status
Simulation time 45994647 ps
CPU time 1 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842388301 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_div_intersig_mubi.3842388301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_extclk.1872433974
Short name T348
Test name
Test status
Simulation time 22690968 ps
CPU time 0.83 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:08 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872433974 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_extclk.1872433974
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency.1677762673
Short name T400
Test name
Test status
Simulation time 1762659077 ps
CPU time 13.85 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:21 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677762673 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency.1677762673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_frequency_timeout.4238882993
Short name T363
Test name
Test status
Simulation time 140534751 ps
CPU time 1.79 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:11 AM UTC 24
Peak memory 210372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4238882993 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_frequency_timeout.4238882993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_idle_intersig_mubi.4047743295
Short name T359
Test name
Test status
Simulation time 222164729 ps
CPU time 1.51 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047743295 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_idle_intersig_mubi.4047743295
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_clk_byp_req_intersig_mubi.1475526337
Short name T355
Test name
Test status
Simulation time 19118262 ps
CPU time 0.85 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475526337
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_clk_byp_req_intersig_mubi.1475526337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_lc_ctrl_intersig_mubi.2027325686
Short name T361
Test name
Test status
Simulation time 111383342 ps
CPU time 1.51 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:11 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027325686
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_lc_ctrl_intersig_mubi.2027325686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_peri.1894932089
Short name T353
Test name
Test status
Simulation time 56332490 ps
CPU time 0.95 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894932089 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_peri.1894932089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_regwen.522921838
Short name T365
Test name
Test status
Simulation time 425196472 ps
CPU time 2.49 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:12 AM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522921838 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_regwen.522921838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_smoke.1938905024
Short name T350
Test name
Test status
Simulation time 54824372 ps
CPU time 1.11 seconds
Started Sep 18 06:12:06 AM UTC 24
Finished Sep 18 06:12:08 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938905024 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_smoke.1938905024
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all.3447355117
Short name T506
Test name
Test status
Simulation time 7305110105 ps
CPU time 35.83 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:45 AM UTC 24
Peak memory 211136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447355117 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_stress_all.3447355117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_stress_all_with_rand_reset.703799601
Short name T199
Test name
Test status
Simulation time 8417264721 ps
CPU time 46.67 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:56 AM UTC 24
Peak memory 227520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703799601 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.clkmgr_stress_all_with_rand_reset.703799601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/19.clkmgr_trans.4181334725
Short name T362
Test name
Test status
Simulation time 95179352 ps
CPU time 1.71 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:11 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4181334725 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.clkmgr_trans.4181334725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/19.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_alert_test.2521171778
Short name T23
Test name
Test status
Simulation time 41872386 ps
CPU time 1.1 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:10:51 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521171778 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.2521171778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_handshake_intersig_mubi.51210177
Short name T25
Test name
Test status
Simulation time 85795662 ps
CPU time 1.65 seconds
Started Sep 18 06:10:48 AM UTC 24
Finished Sep 18 06:10:51 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51210177 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_handshake_intersig_mubi.51210177
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_clk_status.989663742
Short name T92
Test name
Test status
Simulation time 14783597 ps
CPU time 0.92 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:49 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989663742 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.989663742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_div_intersig_mubi.639705678
Short name T22
Test name
Test status
Simulation time 21824408 ps
CPU time 1.22 seconds
Started Sep 18 06:10:48 AM UTC 24
Finished Sep 18 06:10:51 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639705678 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_div_intersig_mubi.639705678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_extclk.3456218756
Short name T94
Test name
Test status
Simulation time 66536555 ps
CPU time 1.46 seconds
Started Sep 18 06:10:46 AM UTC 24
Finished Sep 18 06:10:49 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456218756 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_extclk.3456218756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency.3242466354
Short name T12
Test name
Test status
Simulation time 1875427919 ps
CPU time 15.29 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:11:03 AM UTC 24
Peak memory 210868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3242466354 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.3242466354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_frequency_timeout.3858175822
Short name T51
Test name
Test status
Simulation time 737994604 ps
CPU time 7.13 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858175822 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.3858175822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_clk_byp_req_intersig_mubi.2866474314
Short name T176
Test name
Test status
Simulation time 91918803 ps
CPU time 1.24 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:49 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866474314
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_clk_byp_req_intersig_mubi.2866474314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_lc_ctrl_intersig_mubi.3592531174
Short name T93
Test name
Test status
Simulation time 90788537 ps
CPU time 1.15 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:49 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592531174
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_lc_ctrl_intersig_mubi.3592531174
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_peri.1201068257
Short name T91
Test name
Test status
Simulation time 19043323 ps
CPU time 0.93 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:48 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201068257 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.1201068257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_sec_cm.362493736
Short name T62
Test name
Test status
Simulation time 282139125 ps
CPU time 3.32 seconds
Started Sep 18 06:10:48 AM UTC 24
Finished Sep 18 06:10:53 AM UTC 24
Peak memory 242760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362493736 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.362493736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_smoke.821931522
Short name T88
Test name
Test status
Simulation time 80467187 ps
CPU time 1.54 seconds
Started Sep 18 06:10:45 AM UTC 24
Finished Sep 18 06:10:48 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821931522 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.821931522
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all.2967851377
Short name T38
Test name
Test status
Simulation time 8207242821 ps
CPU time 42.9 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:11:33 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967851377 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all.2967851377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_stress_all_with_rand_reset.2152293442
Short name T72
Test name
Test status
Simulation time 5695043516 ps
CPU time 61.71 seconds
Started Sep 18 06:10:48 AM UTC 24
Finished Sep 18 06:11:52 AM UTC 24
Peak memory 220596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152293442 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2152293442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/2.clkmgr_trans.4105744547
Short name T21
Test name
Test status
Simulation time 567764608 ps
CPU time 2.84 seconds
Started Sep 18 06:10:47 AM UTC 24
Finished Sep 18 06:10:50 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105744547 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.4105744547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/2.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_alert_test.1697277250
Short name T371
Test name
Test status
Simulation time 14141388 ps
CPU time 0.78 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 210644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697277250 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_alert_test.1697277250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_handshake_intersig_mubi.2853538700
Short name T372
Test name
Test status
Simulation time 53278344 ps
CPU time 0.97 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853538700 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_handshake_intersig_mubi.2853538700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_clk_status.3597079261
Short name T366
Test name
Test status
Simulation time 22524308 ps
CPU time 0.74 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597079261 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_clk_status.3597079261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_div_intersig_mubi.3313288341
Short name T370
Test name
Test status
Simulation time 18298123 ps
CPU time 0.87 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313288341 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_div_intersig_mubi.3313288341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_extclk.1184111132
Short name T364
Test name
Test status
Simulation time 77912925 ps
CPU time 1.35 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:11 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1184111132 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_extclk.1184111132
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency.2663956785
Short name T337
Test name
Test status
Simulation time 1597268963 ps
CPU time 7.92 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663956785 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency.2663956785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_frequency_timeout.1060403593
Short name T390
Test name
Test status
Simulation time 1114325390 ps
CPU time 4.91 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060403593 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_frequency_timeout.1060403593
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_idle_intersig_mubi.2530538279
Short name T377
Test name
Test status
Simulation time 186738423 ps
CPU time 1.48 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2530538279 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_idle_intersig_mubi.2530538279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_clk_byp_req_intersig_mubi.2194854467
Short name T375
Test name
Test status
Simulation time 64117742 ps
CPU time 1.37 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194854467
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_clk_byp_req_intersig_mubi.2194854467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_lc_ctrl_intersig_mubi.2559299963
Short name T373
Test name
Test status
Simulation time 81415468 ps
CPU time 1.16 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559299963
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_lc_ctrl_intersig_mubi.2559299963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_peri.686714644
Short name T368
Test name
Test status
Simulation time 17210970 ps
CPU time 1 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686714644 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_peri.686714644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_regwen.1736312811
Short name T389
Test name
Test status
Simulation time 1161891554 ps
CPU time 4.58 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736312811 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_regwen.1736312811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_smoke.627989276
Short name T165
Test name
Test status
Simulation time 23621508 ps
CPU time 0.92 seconds
Started Sep 18 06:12:08 AM UTC 24
Finished Sep 18 06:12:10 AM UTC 24
Peak memory 208096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627989276 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_smoke.627989276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all.2225977210
Short name T117
Test name
Test status
Simulation time 11858538674 ps
CPU time 88.33 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:13:41 AM UTC 24
Peak memory 211164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225977210 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_stress_all.2225977210
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_stress_all_with_rand_reset.3840480371
Short name T646
Test name
Test status
Simulation time 14001823171 ps
CPU time 72.54 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:13:25 AM UTC 24
Peak memory 220588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840480371 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 20.clkmgr_stress_all_with_rand_reset.3840480371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/20.clkmgr_trans.367981619
Short name T369
Test name
Test status
Simulation time 19744951 ps
CPU time 1.11 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367981619 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.clkmgr_trans.367981619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/20.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_alert_test.1889584429
Short name T388
Test name
Test status
Simulation time 21571349 ps
CPU time 0.94 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889584429 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_alert_test.1889584429
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_handshake_intersig_mubi.1456032799
Short name T384
Test name
Test status
Simulation time 35844303 ps
CPU time 1.21 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456032799 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_handshake_intersig_mubi.1456032799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_clk_status.280105736
Short name T380
Test name
Test status
Simulation time 18004659 ps
CPU time 0.91 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280105736 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_clk_status.280105736
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_div_intersig_mubi.407972649
Short name T383
Test name
Test status
Simulation time 16377719 ps
CPU time 1.19 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407972649 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_div_intersig_mubi.407972649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_extclk.3774672984
Short name T374
Test name
Test status
Simulation time 24441204 ps
CPU time 1.01 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 208368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774672984 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_extclk.3774672984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency.3198812950
Short name T378
Test name
Test status
Simulation time 202392771 ps
CPU time 2.3 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198812950 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency.3198812950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_frequency_timeout.705926036
Short name T417
Test name
Test status
Simulation time 1098545285 ps
CPU time 8.85 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:23 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705926036 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_frequency_timeout.705926036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_idle_intersig_mubi.3917991930
Short name T386
Test name
Test status
Simulation time 87116566 ps
CPU time 1.57 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:16 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917991930 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_idle_intersig_mubi.3917991930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_clk_byp_req_intersig_mubi.1769992999
Short name T382
Test name
Test status
Simulation time 81258907 ps
CPU time 1.2 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769992999
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_clk_byp_req_intersig_mubi.1769992999
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_lc_ctrl_intersig_mubi.1331720821
Short name T381
Test name
Test status
Simulation time 23278252 ps
CPU time 1.1 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331720821
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_lc_ctrl_intersig_mubi.1331720821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_peri.3700484304
Short name T379
Test name
Test status
Simulation time 19142396 ps
CPU time 0.95 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:15 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3700484304 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_peri.3700484304
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_regwen.587419457
Short name T398
Test name
Test status
Simulation time 838263051 ps
CPU time 5.29 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:19 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587419457 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_regwen.587419457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_smoke.780923647
Short name T376
Test name
Test status
Simulation time 15058861 ps
CPU time 1.08 seconds
Started Sep 18 06:12:11 AM UTC 24
Finished Sep 18 06:12:13 AM UTC 24
Peak memory 210300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780923647 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_smoke.780923647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_stress_all_with_rand_reset.2826088533
Short name T614
Test name
Test status
Simulation time 9157996310 ps
CPU time 58.87 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:13:14 AM UTC 24
Peak memory 220492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826088533 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 21.clkmgr_stress_all_with_rand_reset.2826088533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/21.clkmgr_trans.721944286
Short name T385
Test name
Test status
Simulation time 262407773 ps
CPU time 1.75 seconds
Started Sep 18 06:12:13 AM UTC 24
Finished Sep 18 06:12:16 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721944286 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.clkmgr_trans.721944286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/21.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_alert_test.4256049547
Short name T414
Test name
Test status
Simulation time 24980312 ps
CPU time 1.09 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256049547 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_alert_test.4256049547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_handshake_intersig_mubi.3106930308
Short name T416
Test name
Test status
Simulation time 82074190 ps
CPU time 1.53 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106930308 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_handshake_intersig_mubi.3106930308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_clk_status.291050462
Short name T393
Test name
Test status
Simulation time 17761290 ps
CPU time 0.97 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291050462 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_clk_status.291050462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_div_intersig_mubi.1664002139
Short name T410
Test name
Test status
Simulation time 49834134 ps
CPU time 1.21 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664002139 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_div_intersig_mubi.1664002139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_extclk.2098428892
Short name T367
Test name
Test status
Simulation time 93985098 ps
CPU time 1.69 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098428892 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_extclk.2098428892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency.3520608946
Short name T397
Test name
Test status
Simulation time 197474331 ps
CPU time 2.5 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:18 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520608946 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency.3520608946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_frequency_timeout.2945461850
Short name T427
Test name
Test status
Simulation time 1823467625 ps
CPU time 9.61 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:26 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945461850 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_frequency_timeout.2945461850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_idle_intersig_mubi.2087864431
Short name T387
Test name
Test status
Simulation time 64877183 ps
CPU time 1.46 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087864431 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_idle_intersig_mubi.2087864431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_clk_byp_req_intersig_mubi.2612174992
Short name T405
Test name
Test status
Simulation time 16075404 ps
CPU time 1.08 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612174992
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_clk_byp_req_intersig_mubi.2612174992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_lc_ctrl_intersig_mubi.1991145870
Short name T395
Test name
Test status
Simulation time 26528346 ps
CPU time 1.04 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991145870
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_lc_ctrl_intersig_mubi.1991145870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_peri.4250925064
Short name T391
Test name
Test status
Simulation time 20911509 ps
CPU time 0.96 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250925064 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_peri.4250925064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_regwen.734380577
Short name T418
Test name
Test status
Simulation time 214790337 ps
CPU time 1.96 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:23 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734380577 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_regwen.734380577
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_smoke.1469932710
Short name T392
Test name
Test status
Simulation time 34253023 ps
CPU time 1.11 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469932710 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_smoke.1469932710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all.373623238
Short name T522
Test name
Test status
Simulation time 4891481723 ps
CPU time 26.52 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373623238 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_stress_all.373623238
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_stress_all_with_rand_reset.1860233496
Short name T644
Test name
Test status
Simulation time 4622877846 ps
CPU time 62.77 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:13:24 AM UTC 24
Peak memory 224636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860233496 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 22.clkmgr_stress_all_with_rand_reset.1860233496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/22.clkmgr_trans.3139940681
Short name T394
Test name
Test status
Simulation time 71722607 ps
CPU time 1.09 seconds
Started Sep 18 06:12:15 AM UTC 24
Finished Sep 18 06:12:17 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139940681 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.clkmgr_trans.3139940681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/22.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_alert_test.1304607131
Short name T415
Test name
Test status
Simulation time 73258631 ps
CPU time 1.01 seconds
Started Sep 18 06:12:20 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304607131 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_alert_test.1304607131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_handshake_intersig_mubi.2029863541
Short name T408
Test name
Test status
Simulation time 15943660 ps
CPU time 1.09 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029863541 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_handshake_intersig_mubi.2029863541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_clk_status.2772045605
Short name T402
Test name
Test status
Simulation time 13493231 ps
CPU time 0.84 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772045605 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_clk_status.2772045605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_div_intersig_mubi.2237167969
Short name T407
Test name
Test status
Simulation time 34976564 ps
CPU time 0.93 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237167969 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_div_intersig_mubi.2237167969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_extclk.3074224502
Short name T412
Test name
Test status
Simulation time 20714910 ps
CPU time 1.08 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074224502 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_extclk.3074224502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency.1770258967
Short name T419
Test name
Test status
Simulation time 336714853 ps
CPU time 2.41 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:23 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770258967 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency.1770258967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_frequency_timeout.4040639682
Short name T461
Test name
Test status
Simulation time 1699316058 ps
CPU time 13.21 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 210892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040639682 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_frequency_timeout.4040639682
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_idle_intersig_mubi.3849381768
Short name T409
Test name
Test status
Simulation time 94641840 ps
CPU time 1.24 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849381768 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_idle_intersig_mubi.3849381768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_clk_byp_req_intersig_mubi.2756719285
Short name T406
Test name
Test status
Simulation time 45876521 ps
CPU time 0.96 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756719285
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_clk_byp_req_intersig_mubi.2756719285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_lc_ctrl_intersig_mubi.1746067525
Short name T411
Test name
Test status
Simulation time 35420764 ps
CPU time 1.29 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746067525
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_lc_ctrl_intersig_mubi.1746067525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_peri.3034253139
Short name T401
Test name
Test status
Simulation time 14616646 ps
CPU time 0.77 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:21 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034253139 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_peri.3034253139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_regwen.479488337
Short name T413
Test name
Test status
Simulation time 66031991 ps
CPU time 1.21 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479488337 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_regwen.479488337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_smoke.1843302125
Short name T166
Test name
Test status
Simulation time 22097055 ps
CPU time 1.2 seconds
Started Sep 18 06:12:17 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843302125 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_smoke.1843302125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all.83927619
Short name T535
Test name
Test status
Simulation time 3820316831 ps
CPU time 30.16 seconds
Started Sep 18 06:12:20 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 211112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83927619 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_stress_all.83927619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_stress_all_with_rand_reset.3349113718
Short name T530
Test name
Test status
Simulation time 1697617226 ps
CPU time 28.4 seconds
Started Sep 18 06:12:20 AM UTC 24
Finished Sep 18 06:12:50 AM UTC 24
Peak memory 227608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349113718 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 23.clkmgr_stress_all_with_rand_reset.3349113718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/23.clkmgr_trans.3757557069
Short name T403
Test name
Test status
Simulation time 29352517 ps
CPU time 1.07 seconds
Started Sep 18 06:12:19 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757557069 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.clkmgr_trans.3757557069
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/23.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_alert_test.1673602458
Short name T433
Test name
Test status
Simulation time 27249168 ps
CPU time 1.14 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:27 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673602458 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_alert_test.1673602458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_handshake_intersig_mubi.1032670398
Short name T431
Test name
Test status
Simulation time 27692439 ps
CPU time 1.03 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:26 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032670398 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_handshake_intersig_mubi.1032670398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_clk_status.720750481
Short name T424
Test name
Test status
Simulation time 39187202 ps
CPU time 1.02 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720750481 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_clk_status.720750481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_div_intersig_mubi.1621138102
Short name T429
Test name
Test status
Simulation time 17843790 ps
CPU time 0.75 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:26 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621138102 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_div_intersig_mubi.1621138102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_extclk.1676414550
Short name T422
Test name
Test status
Simulation time 17603668 ps
CPU time 0.96 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676414550 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_extclk.1676414550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency.1057223112
Short name T501
Test name
Test status
Simulation time 2238530776 ps
CPU time 18.38 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057223112 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency.1057223112
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_frequency_timeout.2848267218
Short name T459
Test name
Test status
Simulation time 1701373805 ps
CPU time 9.78 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848267218 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_frequency_timeout.2848267218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_idle_intersig_mubi.1859984048
Short name T430
Test name
Test status
Simulation time 56649844 ps
CPU time 1.13 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:26 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859984048 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_idle_intersig_mubi.1859984048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_clk_byp_req_intersig_mubi.430737053
Short name T425
Test name
Test status
Simulation time 24830201 ps
CPU time 0.95 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430737053 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_clk_byp_req_intersig_mubi.430737053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_lc_ctrl_intersig_mubi.3724966479
Short name T428
Test name
Test status
Simulation time 61363746 ps
CPU time 0.88 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:26 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724966479
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_lc_ctrl_intersig_mubi.3724966479
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_peri.3915755476
Short name T420
Test name
Test status
Simulation time 27904796 ps
CPU time 0.75 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915755476 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_peri.3915755476
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_regwen.1751402965
Short name T440
Test name
Test status
Simulation time 664208907 ps
CPU time 4.25 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:30 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751402965 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_regwen.1751402965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_smoke.78616008
Short name T423
Test name
Test status
Simulation time 26446362 ps
CPU time 1.1 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78616008 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_smoke.78616008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all.1904582252
Short name T617
Test name
Test status
Simulation time 9612053521 ps
CPU time 50.67 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:13:17 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904582252 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_stress_all.1904582252
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_stress_all_with_rand_reset.2091109060
Short name T443
Test name
Test status
Simulation time 527477457 ps
CPU time 5.7 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:31 AM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091109060 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 24.clkmgr_stress_all_with_rand_reset.2091109060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/24.clkmgr_trans.2986553926
Short name T426
Test name
Test status
Simulation time 101837144 ps
CPU time 1.37 seconds
Started Sep 18 06:12:23 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986553926 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.clkmgr_trans.2986553926
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/24.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_alert_test.1525150961
Short name T450
Test name
Test status
Simulation time 12002435 ps
CPU time 0.95 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525150961 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_alert_test.1525150961
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_handshake_intersig_mubi.1265767573
Short name T448
Test name
Test status
Simulation time 37372306 ps
CPU time 1.02 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265767573 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_handshake_intersig_mubi.1265767573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_clk_status.1433827844
Short name T437
Test name
Test status
Simulation time 19192997 ps
CPU time 1.08 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:29 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433827844 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_clk_status.1433827844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_div_intersig_mubi.548622338
Short name T453
Test name
Test status
Simulation time 75066736 ps
CPU time 1.42 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548622338 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_div_intersig_mubi.548622338
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_extclk.2780807824
Short name T432
Test name
Test status
Simulation time 21244546 ps
CPU time 0.78 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:27 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780807824 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_extclk.2780807824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency.3517398066
Short name T464
Test name
Test status
Simulation time 2411739475 ps
CPU time 8.73 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:35 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517398066 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency.3517398066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_frequency_timeout.2904634147
Short name T466
Test name
Test status
Simulation time 1340920732 ps
CPU time 10.32 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904634147 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_frequency_timeout.2904634147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_idle_intersig_mubi.3204029061
Short name T439
Test name
Test status
Simulation time 68327713 ps
CPU time 1.22 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:29 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204029061 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_idle_intersig_mubi.3204029061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_clk_byp_req_intersig_mubi.421863879
Short name T452
Test name
Test status
Simulation time 116021561 ps
CPU time 1.4 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=421863879 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_clk_byp_req_intersig_mubi.421863879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_lc_ctrl_intersig_mubi.492385061
Short name T447
Test name
Test status
Simulation time 17368725 ps
CPU time 1.04 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492385061 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_lc_ctrl_intersig_mubi.492385061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_peri.199227030
Short name T434
Test name
Test status
Simulation time 15438172 ps
CPU time 0.95 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:27 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199227030 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_peri.199227030
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_regwen.1320908998
Short name T457
Test name
Test status
Simulation time 1020931950 ps
CPU time 4.76 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 211056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320908998 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_regwen.1320908998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_smoke.539960518
Short name T435
Test name
Test status
Simulation time 54087794 ps
CPU time 1.33 seconds
Started Sep 18 06:12:25 AM UTC 24
Finished Sep 18 06:12:27 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539960518 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_smoke.539960518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all.4232936779
Short name T503
Test name
Test status
Simulation time 2875958857 ps
CPU time 15.08 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:44 AM UTC 24
Peak memory 211076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232936779 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_stress_all.4232936779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_stress_all_with_rand_reset.843757757
Short name T675
Test name
Test status
Simulation time 4765680168 ps
CPU time 65.05 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:13:37 AM UTC 24
Peak memory 227408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843757757 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 25.clkmgr_stress_all_with_rand_reset.843757757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/25.clkmgr_trans.2087599628
Short name T438
Test name
Test status
Simulation time 21986455 ps
CPU time 1.27 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:29 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087599628 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.clkmgr_trans.2087599628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/25.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_alert_test.161062502
Short name T469
Test name
Test status
Simulation time 33691214 ps
CPU time 1.13 seconds
Started Sep 18 06:12:33 AM UTC 24
Finished Sep 18 06:12:37 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161062502 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_alert_test.161062502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_handshake_intersig_mubi.4153350330
Short name T455
Test name
Test status
Simulation time 23910480 ps
CPU time 1.09 seconds
Started Sep 18 06:12:30 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153350330 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_handshake_intersig_mubi.4153350330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_clk_status.408283759
Short name T441
Test name
Test status
Simulation time 38492593 ps
CPU time 0.99 seconds
Started Sep 18 06:12:29 AM UTC 24
Finished Sep 18 06:12:31 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408283759 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_clk_status.408283759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_div_intersig_mubi.562009904
Short name T456
Test name
Test status
Simulation time 44200258 ps
CPU time 1.28 seconds
Started Sep 18 06:12:31 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562009904 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_div_intersig_mubi.562009904
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_extclk.3258887541
Short name T458
Test name
Test status
Simulation time 83466537 ps
CPU time 1.47 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258887541 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_extclk.3258887541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency.726713080
Short name T462
Test name
Test status
Simulation time 194539982 ps
CPU time 2.27 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726713080 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency.726713080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_frequency_timeout.3004664953
Short name T479
Test name
Test status
Simulation time 1337371200 ps
CPU time 10.04 seconds
Started Sep 18 06:12:29 AM UTC 24
Finished Sep 18 06:12:40 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004664953 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_frequency_timeout.3004664953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_idle_intersig_mubi.609810862
Short name T442
Test name
Test status
Simulation time 18535267 ps
CPU time 1.12 seconds
Started Sep 18 06:12:29 AM UTC 24
Finished Sep 18 06:12:31 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609810862 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_idle_intersig_mubi.609810862
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_clk_byp_req_intersig_mubi.1811781031
Short name T449
Test name
Test status
Simulation time 33063996 ps
CPU time 0.79 seconds
Started Sep 18 06:12:30 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811781031
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_clk_byp_req_intersig_mubi.1811781031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_lc_ctrl_intersig_mubi.2088958718
Short name T454
Test name
Test status
Simulation time 29673246 ps
CPU time 1.15 seconds
Started Sep 18 06:12:30 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088958718
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_lc_ctrl_intersig_mubi.2088958718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_peri.3174345146
Short name T446
Test name
Test status
Simulation time 19345701 ps
CPU time 1.1 seconds
Started Sep 18 06:12:29 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174345146 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_peri.3174345146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_regwen.1804297787
Short name T460
Test name
Test status
Simulation time 204589481 ps
CPU time 2.15 seconds
Started Sep 18 06:12:31 AM UTC 24
Finished Sep 18 06:12:34 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804297787 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_regwen.1804297787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_smoke.2011192879
Short name T451
Test name
Test status
Simulation time 14742756 ps
CPU time 0.99 seconds
Started Sep 18 06:12:27 AM UTC 24
Finished Sep 18 06:12:33 AM UTC 24
Peak memory 208400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011192879 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_smoke.2011192879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all.1016408217
Short name T502
Test name
Test status
Simulation time 2454467647 ps
CPU time 9.95 seconds
Started Sep 18 06:12:32 AM UTC 24
Finished Sep 18 06:12:43 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016408217 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_stress_all.1016408217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_stress_all_with_rand_reset.3670351921
Short name T180
Test name
Test status
Simulation time 1182088744 ps
CPU time 15.05 seconds
Started Sep 18 06:12:32 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 220608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670351921 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 26.clkmgr_stress_all_with_rand_reset.3670351921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/26.clkmgr_trans.338992946
Short name T445
Test name
Test status
Simulation time 37309470 ps
CPU time 1.04 seconds
Started Sep 18 06:12:29 AM UTC 24
Finished Sep 18 06:12:32 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338992946 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.clkmgr_trans.338992946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/26.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_alert_test.2334975205
Short name T474
Test name
Test status
Simulation time 38869496 ps
CPU time 0.87 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:38 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334975205 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_alert_test.2334975205
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_handshake_intersig_mubi.3603397628
Short name T473
Test name
Test status
Simulation time 86304705 ps
CPU time 1.24 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:37 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603397628 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_handshake_intersig_mubi.3603397628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_clk_status.648353268
Short name T421
Test name
Test status
Simulation time 16407348 ps
CPU time 0.8 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:35 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648353268 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_clk_status.648353268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_div_intersig_mubi.3200835335
Short name T471
Test name
Test status
Simulation time 49318078 ps
CPU time 1.03 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:37 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200835335 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_div_intersig_mubi.3200835335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_extclk.2706251438
Short name T467
Test name
Test status
Simulation time 36003364 ps
CPU time 1.02 seconds
Started Sep 18 06:12:33 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706251438 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_extclk.2706251438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency.712783508
Short name T525
Test name
Test status
Simulation time 2367723348 ps
CPU time 13.74 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:49 AM UTC 24
Peak memory 210992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712783508 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency.712783508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_frequency_timeout.757337642
Short name T504
Test name
Test status
Simulation time 1957319253 ps
CPU time 8 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:44 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757337642 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_frequency_timeout.757337642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_idle_intersig_mubi.3978901404
Short name T470
Test name
Test status
Simulation time 15291571 ps
CPU time 0.97 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:37 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978901404 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_idle_intersig_mubi.3978901404
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_clk_byp_req_intersig_mubi.2820119958
Short name T465
Test name
Test status
Simulation time 20358962 ps
CPU time 0.92 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820119958
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_clk_byp_req_intersig_mubi.2820119958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_lc_ctrl_intersig_mubi.1373768902
Short name T472
Test name
Test status
Simulation time 22513080 ps
CPU time 1.21 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:37 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373768902
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_lc_ctrl_intersig_mubi.1373768902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_peri.3413918924
Short name T468
Test name
Test status
Simulation time 17595665 ps
CPU time 0.92 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413918924 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_peri.3413918924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_regwen.342064243
Short name T475
Test name
Test status
Simulation time 181287227 ps
CPU time 1.23 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:38 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342064243 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_regwen.342064243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_smoke.2375431882
Short name T399
Test name
Test status
Simulation time 17821994 ps
CPU time 0.85 seconds
Started Sep 18 06:12:33 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375431882 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_smoke.2375431882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all.3056952892
Short name T596
Test name
Test status
Simulation time 3790160766 ps
CPU time 27.36 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:13:05 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056952892 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_stress_all.3056952892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_stress_all_with_rand_reset.2834751306
Short name T661
Test name
Test status
Simulation time 3469600872 ps
CPU time 55.12 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:13:33 AM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834751306 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 27.clkmgr_stress_all_with_rand_reset.2834751306
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/27.clkmgr_trans.361327
Short name T404
Test name
Test status
Simulation time 13472730 ps
CPU time 0.75 seconds
Started Sep 18 06:12:34 AM UTC 24
Finished Sep 18 06:12:36 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361327 -assert nopostproc +UVM_TESTNAME=clkmgr
_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.clkmgr_trans.361327
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/27.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_alert_test.613331312
Short name T481
Test name
Test status
Simulation time 28790960 ps
CPU time 0.7 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613331312 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_alert_test.613331312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_handshake_intersig_mubi.614490878
Short name T486
Test name
Test status
Simulation time 13601111 ps
CPU time 1.08 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614490878 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_handshake_intersig_mubi.614490878
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_clk_status.1852222342
Short name T487
Test name
Test status
Simulation time 14618761 ps
CPU time 0.96 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852222342 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_clk_status.1852222342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_div_intersig_mubi.3002649096
Short name T483
Test name
Test status
Simulation time 18665086 ps
CPU time 0.87 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002649096 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_div_intersig_mubi.3002649096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_extclk.2909155282
Short name T477
Test name
Test status
Simulation time 37955136 ps
CPU time 1.17 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:38 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909155282 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_extclk.2909155282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency.1320299747
Short name T529
Test name
Test status
Simulation time 2249088406 ps
CPU time 12.67 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:50 AM UTC 24
Peak memory 210936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320299747 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency.1320299747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_frequency_timeout.4188907819
Short name T533
Test name
Test status
Simulation time 1335587524 ps
CPU time 10.4 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:51 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188907819 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_frequency_timeout.4188907819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_idle_intersig_mubi.1360695934
Short name T488
Test name
Test status
Simulation time 45808452 ps
CPU time 0.98 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360695934 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_idle_intersig_mubi.1360695934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_clk_byp_req_intersig_mubi.337559739
Short name T484
Test name
Test status
Simulation time 62790584 ps
CPU time 0.9 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337559739 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_clk_byp_req_intersig_mubi.337559739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_lc_ctrl_intersig_mubi.4179537341
Short name T491
Test name
Test status
Simulation time 49486871 ps
CPU time 0.98 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179537341
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_lc_ctrl_intersig_mubi.4179537341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_peri.496087439
Short name T485
Test name
Test status
Simulation time 16783722 ps
CPU time 1.04 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=496087439 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_peri.496087439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_regwen.2180015580
Short name T490
Test name
Test status
Simulation time 68241537 ps
CPU time 1.12 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180015580 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_regwen.2180015580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_smoke.68471607
Short name T476
Test name
Test status
Simulation time 112500639 ps
CPU time 1.14 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:38 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68471607 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_smoke.68471607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all.2984465349
Short name T616
Test name
Test status
Simulation time 4905744938 ps
CPU time 36.08 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:13:17 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984465349 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_stress_all.2984465349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_stress_all_with_rand_reset.3314773839
Short name T619
Test name
Test status
Simulation time 4601957840 ps
CPU time 37.93 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:13:19 AM UTC 24
Peak memory 224644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314773839 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 28.clkmgr_stress_all_with_rand_reset.3314773839
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/28.clkmgr_trans.1233922720
Short name T489
Test name
Test status
Simulation time 45644901 ps
CPU time 1.1 seconds
Started Sep 18 06:12:36 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233922720 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.clkmgr_trans.1233922720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/28.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_alert_test.233229312
Short name T510
Test name
Test status
Simulation time 20905282 ps
CPU time 0.77 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233229312 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_alert_test.233229312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_handshake_intersig_mubi.1918359097
Short name T508
Test name
Test status
Simulation time 13396070 ps
CPU time 0.84 seconds
Started Sep 18 06:12:42 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918359097 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_handshake_intersig_mubi.1918359097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_clk_status.1552004967
Short name T496
Test name
Test status
Simulation time 19349189 ps
CPU time 0.83 seconds
Started Sep 18 06:12:40 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552004967 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_clk_status.1552004967
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_div_intersig_mubi.2237651941
Short name T507
Test name
Test status
Simulation time 24778023 ps
CPU time 0.78 seconds
Started Sep 18 06:12:42 AM UTC 24
Finished Sep 18 06:12:46 AM UTC 24
Peak memory 208824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237651941 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_div_intersig_mubi.2237651941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_extclk.1457121833
Short name T494
Test name
Test status
Simulation time 20269601 ps
CPU time 1.03 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457121833 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_extclk.1457121833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency.3431823311
Short name T528
Test name
Test status
Simulation time 1932990335 ps
CPU time 9.05 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:50 AM UTC 24
Peak memory 210544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3431823311 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency.3431823311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_frequency_timeout.58202159
Short name T505
Test name
Test status
Simulation time 877484824 ps
CPU time 3.88 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:45 AM UTC 24
Peak memory 210440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58202159 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_frequency_timeout.58202159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_idle_intersig_mubi.2465410566
Short name T500
Test name
Test status
Simulation time 25043277 ps
CPU time 0.97 seconds
Started Sep 18 06:12:40 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2465410566 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_idle_intersig_mubi.2465410566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_clk_byp_req_intersig_mubi.1329205835
Short name T499
Test name
Test status
Simulation time 39552046 ps
CPU time 0.79 seconds
Started Sep 18 06:12:40 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329205835
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_clk_byp_req_intersig_mubi.1329205835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_lc_ctrl_intersig_mubi.4003532727
Short name T498
Test name
Test status
Simulation time 25485671 ps
CPU time 0.84 seconds
Started Sep 18 06:12:40 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003532727
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_lc_ctrl_intersig_mubi.4003532727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_peri.787836423
Short name T492
Test name
Test status
Simulation time 28628434 ps
CPU time 0.87 seconds
Started Sep 18 06:12:39 AM UTC 24
Finished Sep 18 06:12:41 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=787836423 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_peri.787836423
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_regwen.1728962146
Short name T526
Test name
Test status
Simulation time 928489637 ps
CPU time 3.65 seconds
Started Sep 18 06:12:42 AM UTC 24
Finished Sep 18 06:12:49 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728962146 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_regwen.1728962146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_smoke.3858951379
Short name T495
Test name
Test status
Simulation time 19591695 ps
CPU time 1.22 seconds
Started Sep 18 06:12:38 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858951379 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_smoke.3858951379
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all.3983138299
Short name T655
Test name
Test status
Simulation time 12294273168 ps
CPU time 41.87 seconds
Started Sep 18 06:12:42 AM UTC 24
Finished Sep 18 06:13:28 AM UTC 24
Peak memory 211096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983138299 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_stress_all.3983138299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_stress_all_with_rand_reset.731649694
Short name T181
Test name
Test status
Simulation time 1238297221 ps
CPU time 9.5 seconds
Started Sep 18 06:12:42 AM UTC 24
Finished Sep 18 06:12:55 AM UTC 24
Peak memory 219204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731649694 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 29.clkmgr_stress_all_with_rand_reset.731649694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/29.clkmgr_trans.23275377
Short name T497
Test name
Test status
Simulation time 29624409 ps
CPU time 1.09 seconds
Started Sep 18 06:12:39 AM UTC 24
Finished Sep 18 06:12:42 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23275377 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.clkmgr_trans.23275377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/29.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_alert_test.1843898871
Short name T64
Test name
Test status
Simulation time 43620586 ps
CPU time 1.29 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:10:54 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843898871 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.1843898871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_handshake_intersig_mubi.756677868
Short name T61
Test name
Test status
Simulation time 53605493 ps
CPU time 1.34 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756677868 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_handshake_intersig_mubi.756677868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_clk_status.3429138232
Short name T187
Test name
Test status
Simulation time 26789624 ps
CPU time 1.08 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429138232 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.3429138232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_div_intersig_mubi.1825243437
Short name T65
Test name
Test status
Simulation time 110512723 ps
CPU time 1.81 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:10:54 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825243437 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_div_intersig_mubi.1825243437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_extclk.513618588
Short name T26
Test name
Test status
Simulation time 92726887 ps
CPU time 1.49 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:10:51 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513618588 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_extclk.513618588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency.4015867703
Short name T11
Test name
Test status
Simulation time 1277837204 ps
CPU time 12.35 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:11:02 AM UTC 24
Peak memory 210784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015867703 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.4015867703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_frequency_timeout.4068210825
Short name T40
Test name
Test status
Simulation time 371626013 ps
CPU time 2.17 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068210825 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.4068210825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_idle_intersig_mubi.2832199630
Short name T142
Test name
Test status
Simulation time 18803469 ps
CPU time 1.08 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 209772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832199630 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.2832199630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_clk_byp_req_intersig_mubi.1443634352
Short name T205
Test name
Test status
Simulation time 19512664 ps
CPU time 0.97 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443634352
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_clk_byp_req_intersig_mubi.1443634352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_lc_ctrl_intersig_mubi.3140258551
Short name T203
Test name
Test status
Simulation time 57094526 ps
CPU time 1.13 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140258551
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_lc_ctrl_intersig_mubi.3140258551
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_peri.2289328768
Short name T27
Test name
Test status
Simulation time 18110163 ps
CPU time 1.06 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289328768 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.2289328768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_regwen.303090726
Short name T41
Test name
Test status
Simulation time 132183305 ps
CPU time 1.81 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:10:54 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303090726 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.303090726
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_sec_cm.457783152
Short name T67
Test name
Test status
Simulation time 178172457 ps
CPU time 2.53 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 242564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457783152 -assert nop
ostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.457783152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_smoke.1966440017
Short name T24
Test name
Test status
Simulation time 22468457 ps
CPU time 1.2 seconds
Started Sep 18 06:10:49 AM UTC 24
Finished Sep 18 06:10:51 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966440017 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.1966440017
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all.2775203968
Short name T69
Test name
Test status
Simulation time 705355848 ps
CPU time 5.12 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775203968 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all.2775203968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_stress_all_with_rand_reset.3091706342
Short name T77
Test name
Test status
Simulation time 15182185946 ps
CPU time 91.54 seconds
Started Sep 18 06:10:51 AM UTC 24
Finished Sep 18 06:12:25 AM UTC 24
Peak memory 220536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091706342 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.3091706342
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/3.clkmgr_trans.2417886111
Short name T206
Test name
Test status
Simulation time 50717623 ps
CPU time 1.26 seconds
Started Sep 18 06:10:50 AM UTC 24
Finished Sep 18 06:10:52 AM UTC 24
Peak memory 210448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417886111 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2417886111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/3.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_alert_test.1994408784
Short name T521
Test name
Test status
Simulation time 42571189 ps
CPU time 0.95 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994408784 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_alert_test.1994408784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_handshake_intersig_mubi.1310062815
Short name T517
Test name
Test status
Simulation time 35704727 ps
CPU time 0.87 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310062815 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_handshake_intersig_mubi.1310062815
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_clk_status.1316807097
Short name T516
Test name
Test status
Simulation time 137682405 ps
CPU time 0.99 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316807097 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_clk_status.1316807097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_div_intersig_mubi.1072913570
Short name T519
Test name
Test status
Simulation time 63668922 ps
CPU time 1.04 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072913570 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_div_intersig_mubi.1072913570
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_extclk.585542001
Short name T514
Test name
Test status
Simulation time 26268043 ps
CPU time 1.05 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585542001 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_extclk.585542001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency.3656034890
Short name T524
Test name
Test status
Simulation time 320745285 ps
CPU time 2.32 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:49 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656034890 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency.3656034890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_frequency_timeout.1938483902
Short name T531
Test name
Test status
Simulation time 885932610 ps
CPU time 3.78 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:50 AM UTC 24
Peak memory 210764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938483902 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_frequency_timeout.1938483902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_idle_intersig_mubi.3071441513
Short name T518
Test name
Test status
Simulation time 80947277 ps
CPU time 1.07 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071441513 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_idle_intersig_mubi.3071441513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_clk_byp_req_intersig_mubi.3986195301
Short name T523
Test name
Test status
Simulation time 52337293 ps
CPU time 1.19 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986195301
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_clk_byp_req_intersig_mubi.3986195301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_lc_ctrl_intersig_mubi.3869889389
Short name T513
Test name
Test status
Simulation time 30303329 ps
CPU time 0.78 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869889389
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_lc_ctrl_intersig_mubi.3869889389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_peri.2129411669
Short name T512
Test name
Test status
Simulation time 31248210 ps
CPU time 0.89 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129411669 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_peri.2129411669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_regwen.3680786421
Short name T527
Test name
Test status
Simulation time 754462768 ps
CPU time 2.96 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:50 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680786421 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_regwen.3680786421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_smoke.232831524
Short name T511
Test name
Test status
Simulation time 51490691 ps
CPU time 0.93 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232831524 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_smoke.232831524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all.3752180580
Short name T645
Test name
Test status
Simulation time 11951543521 ps
CPU time 37.69 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:13:25 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752180580 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_stress_all.3752180580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_stress_all_with_rand_reset.2960647709
Short name T692
Test name
Test status
Simulation time 11123357189 ps
CPU time 64.62 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 220588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960647709 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 30.clkmgr_stress_all_with_rand_reset.2960647709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/30.clkmgr_trans.643727438
Short name T515
Test name
Test status
Simulation time 23136977 ps
CPU time 0.94 seconds
Started Sep 18 06:12:45 AM UTC 24
Finished Sep 18 06:12:47 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643727438 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.clkmgr_trans.643727438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/30.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_alert_test.3254236489
Short name T493
Test name
Test status
Simulation time 42798108 ps
CPU time 0.8 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254236489 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_alert_test.3254236489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_handshake_intersig_mubi.3033169332
Short name T540
Test name
Test status
Simulation time 21155771 ps
CPU time 0.88 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033169332 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_handshake_intersig_mubi.3033169332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_clk_status.2912512329
Short name T534
Test name
Test status
Simulation time 32749221 ps
CPU time 0.66 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 206812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912512329 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_clk_status.2912512329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_div_intersig_mubi.244242033
Short name T542
Test name
Test status
Simulation time 60826550 ps
CPU time 1.04 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244242033 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_div_intersig_mubi.244242033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_extclk.3645473690
Short name T532
Test name
Test status
Simulation time 16662798 ps
CPU time 0.77 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:51 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645473690 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_extclk.3645473690
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency.3214209621
Short name T567
Test name
Test status
Simulation time 799334069 ps
CPU time 7.14 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214209621 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency.3214209621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_frequency_timeout.1812889782
Short name T548
Test name
Test status
Simulation time 505548126 ps
CPU time 3.21 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:54 AM UTC 24
Peak memory 210824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812889782 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_frequency_timeout.1812889782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_idle_intersig_mubi.3977732226
Short name T537
Test name
Test status
Simulation time 42154592 ps
CPU time 0.87 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977732226 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_idle_intersig_mubi.3977732226
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_clk_byp_req_intersig_mubi.2285964129
Short name T539
Test name
Test status
Simulation time 24360067 ps
CPU time 0.81 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285964129
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_clk_byp_req_intersig_mubi.2285964129
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_lc_ctrl_intersig_mubi.2982116646
Short name T543
Test name
Test status
Simulation time 86730030 ps
CPU time 1.13 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982116646
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_lc_ctrl_intersig_mubi.2982116646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_peri.2699718418
Short name T536
Test name
Test status
Simulation time 35587318 ps
CPU time 0.84 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 209140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699718418 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_peri.2699718418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_regwen.3411104468
Short name T541
Test name
Test status
Simulation time 205132731 ps
CPU time 1.44 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:53 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411104468 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_regwen.3411104468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_smoke.3562934280
Short name T520
Test name
Test status
Simulation time 68390458 ps
CPU time 0.92 seconds
Started Sep 18 06:12:46 AM UTC 24
Finished Sep 18 06:12:48 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562934280 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_smoke.3562934280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all.325396684
Short name T573
Test name
Test status
Simulation time 2371170292 ps
CPU time 10.01 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:13:01 AM UTC 24
Peak memory 211024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325396684 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_stress_all.325396684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_stress_all_with_rand_reset.1737866272
Short name T648
Test name
Test status
Simulation time 2071010152 ps
CPU time 34.79 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:13:26 AM UTC 24
Peak memory 220464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737866272 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 31.clkmgr_stress_all_with_rand_reset.1737866272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/31.clkmgr_trans.2142153450
Short name T538
Test name
Test status
Simulation time 29554107 ps
CPU time 0.98 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142153450 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.clkmgr_trans.2142153450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/31.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_alert_test.254697984
Short name T552
Test name
Test status
Simulation time 14152867 ps
CPU time 0.71 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254697984 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_alert_test.254697984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_handshake_intersig_mubi.724191945
Short name T550
Test name
Test status
Simulation time 38335055 ps
CPU time 0.76 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724191945 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_handshake_intersig_mubi.724191945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_clk_status.794695076
Short name T544
Test name
Test status
Simulation time 23043619 ps
CPU time 0.7 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794695076 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_clk_status.794695076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_div_intersig_mubi.190954222
Short name T551
Test name
Test status
Simulation time 13681939 ps
CPU time 0.75 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190954222 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_div_intersig_mubi.190954222
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_extclk.4043546409
Short name T482
Test name
Test status
Simulation time 29725817 ps
CPU time 0.77 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043546409 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_extclk.4043546409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency.248326230
Short name T572
Test name
Test status
Simulation time 1981728835 ps
CPU time 9.26 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:13:01 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248326230 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency.248326230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_frequency_timeout.104528694
Short name T547
Test name
Test status
Simulation time 279265241 ps
CPU time 1.78 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:53 AM UTC 24
Peak memory 210252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104528694 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_frequency_timeout.104528694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_idle_intersig_mubi.3446316146
Short name T557
Test name
Test status
Simulation time 190987779 ps
CPU time 1.41 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446316146 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_idle_intersig_mubi.3446316146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_clk_byp_req_intersig_mubi.607854847
Short name T549
Test name
Test status
Simulation time 18240525 ps
CPU time 0.73 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607854847 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_clk_byp_req_intersig_mubi.607854847
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_lc_ctrl_intersig_mubi.2416016709
Short name T553
Test name
Test status
Simulation time 134381902 ps
CPU time 1.13 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416016709
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_lc_ctrl_intersig_mubi.2416016709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_peri.4129955294
Short name T545
Test name
Test status
Simulation time 103656837 ps
CPU time 0.93 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:53 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129955294 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_peri.4129955294
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_regwen.2353278263
Short name T8
Test name
Test status
Simulation time 1217434219 ps
CPU time 6.57 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353278263 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_regwen.2353278263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_smoke.1094590673
Short name T509
Test name
Test status
Simulation time 14928502 ps
CPU time 0.83 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094590673 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_smoke.1094590673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all.79201020
Short name T613
Test name
Test status
Simulation time 2130887956 ps
CPU time 15.95 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:13:12 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79201020 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_stress_all.79201020
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_stress_all_with_rand_reset.1773192703
Short name T182
Test name
Test status
Simulation time 4396504176 ps
CPU time 35.64 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:13:32 AM UTC 24
Peak memory 220616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773192703 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 32.clkmgr_stress_all_with_rand_reset.1773192703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/32.clkmgr_trans.1573123468
Short name T546
Test name
Test status
Simulation time 111563111 ps
CPU time 1.06 seconds
Started Sep 18 06:12:50 AM UTC 24
Finished Sep 18 06:12:53 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573123468 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.clkmgr_trans.1573123468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/32.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_alert_test.1179271654
Short name T561
Test name
Test status
Simulation time 27914774 ps
CPU time 0.85 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179271654 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_alert_test.1179271654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_handshake_intersig_mubi.3224232783
Short name T566
Test name
Test status
Simulation time 22744567 ps
CPU time 1.12 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224232783 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_handshake_intersig_mubi.3224232783
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_clk_status.502533241
Short name T554
Test name
Test status
Simulation time 31978881 ps
CPU time 0.71 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502533241 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_clk_status.502533241
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_div_intersig_mubi.1427554103
Short name T565
Test name
Test status
Simulation time 118395218 ps
CPU time 1.09 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 210524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1427554103 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_div_intersig_mubi.1427554103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_extclk.487602187
Short name T555
Test name
Test status
Simulation time 81867526 ps
CPU time 0.99 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=487602187 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_extclk.487602187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency.3324838364
Short name T571
Test name
Test status
Simulation time 683282151 ps
CPU time 4.23 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:13:01 AM UTC 24
Peak memory 210792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324838364 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency.3324838364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_frequency_timeout.2241283606
Short name T570
Test name
Test status
Simulation time 254836777 ps
CPU time 2.45 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:59 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2241283606 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_frequency_timeout.2241283606
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_idle_intersig_mubi.1970135980
Short name T564
Test name
Test status
Simulation time 135164485 ps
CPU time 1.25 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970135980 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_idle_intersig_mubi.1970135980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_clk_byp_req_intersig_mubi.1766513331
Short name T568
Test name
Test status
Simulation time 200305712 ps
CPU time 1.46 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766513331
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_clk_byp_req_intersig_mubi.1766513331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_lc_ctrl_intersig_mubi.3426795010
Short name T560
Test name
Test status
Simulation time 31025333 ps
CPU time 1.06 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426795010
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_lc_ctrl_intersig_mubi.3426795010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_peri.3111666332
Short name T556
Test name
Test status
Simulation time 37996584 ps
CPU time 0.97 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111666332 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_peri.3111666332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_regwen.3474984921
Short name T578
Test name
Test status
Simulation time 1539813358 ps
CPU time 5.31 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474984921 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_regwen.3474984921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_smoke.1001612819
Short name T559
Test name
Test status
Simulation time 37608892 ps
CPU time 1.16 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:57 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001612819 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_smoke.1001612819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all.1975233322
Short name T682
Test name
Test status
Simulation time 7063356603 ps
CPU time 52.19 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:13:49 AM UTC 24
Peak memory 211160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975233322 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_stress_all.1975233322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_stress_all_with_rand_reset.3256040830
Short name T663
Test name
Test status
Simulation time 2706335818 ps
CPU time 37.01 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:13:34 AM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256040830 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 33.clkmgr_stress_all_with_rand_reset.3256040830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/33.clkmgr_trans.1075614716
Short name T563
Test name
Test status
Simulation time 79707689 ps
CPU time 1.29 seconds
Started Sep 18 06:12:55 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075614716 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.clkmgr_trans.1075614716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/33.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_alert_test.1213606975
Short name T583
Test name
Test status
Simulation time 31449553 ps
CPU time 0.79 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 210548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213606975 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_alert_test.1213606975
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_handshake_intersig_mubi.3711840985
Short name T579
Test name
Test status
Simulation time 15034069 ps
CPU time 0.77 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711840985 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_handshake_intersig_mubi.3711840985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_clk_status.3548755249
Short name T576
Test name
Test status
Simulation time 72811960 ps
CPU time 0.92 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548755249 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_clk_status.3548755249
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_div_intersig_mubi.3963881558
Short name T585
Test name
Test status
Simulation time 15847077 ps
CPU time 1.01 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963881558 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_div_intersig_mubi.3963881558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_extclk.1008557744
Short name T569
Test name
Test status
Simulation time 53660753 ps
CPU time 1.25 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008557744 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_extclk.1008557744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency.339309435
Short name T606
Test name
Test status
Simulation time 1520399213 ps
CPU time 12.09 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:13:09 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339309435 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency.339309435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_frequency_timeout.280714482
Short name T612
Test name
Test status
Simulation time 1455288546 ps
CPU time 10.71 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:12 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280714482 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_frequency_timeout.280714482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_idle_intersig_mubi.445676157
Short name T577
Test name
Test status
Simulation time 18149317 ps
CPU time 0.83 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445676157 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_idle_intersig_mubi.445676157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_clk_byp_req_intersig_mubi.2608743490
Short name T580
Test name
Test status
Simulation time 16164487 ps
CPU time 0.92 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2608743490
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_clk_byp_req_intersig_mubi.2608743490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_lc_ctrl_intersig_mubi.646552773
Short name T575
Test name
Test status
Simulation time 43529463 ps
CPU time 0.83 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646552773 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_lc_ctrl_intersig_mubi.646552773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_peri.538005885
Short name T574
Test name
Test status
Simulation time 12731572 ps
CPU time 0.72 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538005885 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_peri.538005885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_regwen.2807485312
Short name T597
Test name
Test status
Simulation time 672820633 ps
CPU time 4.71 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:06 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807485312 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_regwen.2807485312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_smoke.241695572
Short name T562
Test name
Test status
Simulation time 27960128 ps
CPU time 0.88 seconds
Started Sep 18 06:12:56 AM UTC 24
Finished Sep 18 06:12:58 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241695572 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_smoke.241695572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all.2410125413
Short name T632
Test name
Test status
Simulation time 5721615979 ps
CPU time 20.91 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410125413 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_stress_all.2410125413
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_stress_all_with_rand_reset.3060636269
Short name T787
Test name
Test status
Simulation time 14240257361 ps
CPU time 82.1 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:14:24 AM UTC 24
Peak memory 221440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3060636269 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 34.clkmgr_stress_all_with_rand_reset.3060636269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/34.clkmgr_trans.1743391072
Short name T584
Test name
Test status
Simulation time 121917482 ps
CPU time 1.25 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743391072 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.clkmgr_trans.1743391072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/34.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_alert_test.335761281
Short name T599
Test name
Test status
Simulation time 12682735 ps
CPU time 0.94 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335761281 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_alert_test.335761281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_handshake_intersig_mubi.603972406
Short name T594
Test name
Test status
Simulation time 142895085 ps
CPU time 1.12 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603972406 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_handshake_intersig_mubi.603972406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_clk_status.3359803392
Short name T592
Test name
Test status
Simulation time 23539835 ps
CPU time 0.9 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359803392 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_clk_status.3359803392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_div_intersig_mubi.1292341843
Short name T593
Test name
Test status
Simulation time 39344069 ps
CPU time 1.01 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292341843 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_div_intersig_mubi.1292341843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_extclk.477618334
Short name T582
Test name
Test status
Simulation time 19724209 ps
CPU time 0.75 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477618334 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_extclk.477618334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency.118004583
Short name T607
Test name
Test status
Simulation time 1042426131 ps
CPU time 8.4 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:10 AM UTC 24
Peak memory 210476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118004583 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency.118004583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_frequency_timeout.691621417
Short name T611
Test name
Test status
Simulation time 2441263577 ps
CPU time 9.95 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:12 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691621417 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_frequency_timeout.691621417
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_idle_intersig_mubi.4194934435
Short name T595
Test name
Test status
Simulation time 66381692 ps
CPU time 1.17 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194934435 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_idle_intersig_mubi.4194934435
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_clk_byp_req_intersig_mubi.3952376037
Short name T588
Test name
Test status
Simulation time 19181273 ps
CPU time 0.77 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952376037
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_clk_byp_req_intersig_mubi.3952376037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_lc_ctrl_intersig_mubi.1129446396
Short name T589
Test name
Test status
Simulation time 26978343 ps
CPU time 0.79 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129446396
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_lc_ctrl_intersig_mubi.1129446396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_peri.19670019
Short name T587
Test name
Test status
Simulation time 15314117 ps
CPU time 0.75 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:02 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19670019 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_1
7/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_peri.19670019
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_regwen.2701126819
Short name T600
Test name
Test status
Simulation time 122666858 ps
CPU time 1.05 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701126819 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_regwen.2701126819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_smoke.2959707571
Short name T590
Test name
Test status
Simulation time 74762951 ps
CPU time 1.17 seconds
Started Sep 18 06:13:00 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959707571 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_smoke.2959707571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all.4287793159
Short name T654
Test name
Test status
Simulation time 4029960529 ps
CPU time 21.95 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:28 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287793159 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_stress_all.4287793159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_stress_all_with_rand_reset.2268682267
Short name T790
Test name
Test status
Simulation time 12733385097 ps
CPU time 78.37 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:14:25 AM UTC 24
Peak memory 227456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268682267 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 35.clkmgr_stress_all_with_rand_reset.2268682267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/35.clkmgr_trans.3567569722
Short name T591
Test name
Test status
Simulation time 103066963 ps
CPU time 1.05 seconds
Started Sep 18 06:13:01 AM UTC 24
Finished Sep 18 06:13:03 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567569722 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.clkmgr_trans.3567569722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/35.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_extclk.1925983786
Short name T598
Test name
Test status
Simulation time 20124144 ps
CPU time 0.78 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925983786 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_extclk.1925983786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency.1825870281
Short name T615
Test name
Test status
Simulation time 1397356680 ps
CPU time 9.31 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:15 AM UTC 24
Peak memory 210856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825870281 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency.1825870281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_frequency_timeout.2847455012
Short name T605
Test name
Test status
Simulation time 139601939 ps
CPU time 1.47 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:08 AM UTC 24
Peak memory 210312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847455012 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_frequency_timeout.2847455012
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_lc_clk_byp_req_intersig_mubi.3018846063
Short name T602
Test name
Test status
Simulation time 49353106 ps
CPU time 0.93 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018846063
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_lc_clk_byp_req_intersig_mubi.3018846063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_peri.761339332
Short name T601
Test name
Test status
Simulation time 48941737 ps
CPU time 0.87 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761339332 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_peri.761339332
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_smoke.4185655737
Short name T604
Test name
Test status
Simulation time 66408807 ps
CPU time 1.42 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185655737 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_smoke.4185655737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/36.clkmgr_trans.410719308
Short name T603
Test name
Test status
Simulation time 78784607 ps
CPU time 1.15 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:07 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410719308 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.clkmgr_trans.410719308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/36.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_alert_test.886636119
Short name T622
Test name
Test status
Simulation time 17452432 ps
CPU time 0.69 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:21 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886636119 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_alert_test.886636119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_handshake_intersig_mubi.1173128652
Short name T630
Test name
Test status
Simulation time 77267734 ps
CPU time 0.94 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173128652 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_handshake_intersig_mubi.1173128652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_clk_status.1136699646
Short name T639
Test name
Test status
Simulation time 14665613 ps
CPU time 0.94 seconds
Started Sep 18 06:13:07 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136699646 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_clk_status.1136699646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_div_intersig_mubi.2509876580
Short name T621
Test name
Test status
Simulation time 21576464 ps
CPU time 0.81 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:21 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2509876580 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_div_intersig_mubi.2509876580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_extclk.1650492414
Short name T609
Test name
Test status
Simulation time 35956375 ps
CPU time 0.85 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:10 AM UTC 24
Peak memory 208420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650492414 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_extclk.1650492414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency.3137200807
Short name T620
Test name
Test status
Simulation time 2135171974 ps
CPU time 9.4 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:19 AM UTC 24
Peak memory 211000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137200807 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency.3137200807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_frequency_timeout.641389037
Short name T581
Test name
Test status
Simulation time 978252502 ps
CPU time 7.3 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:17 AM UTC 24
Peak memory 210532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641389037 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_frequency_timeout.641389037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_idle_intersig_mubi.2720898758
Short name T636
Test name
Test status
Simulation time 34002175 ps
CPU time 0.9 seconds
Started Sep 18 06:13:07 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720898758 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_idle_intersig_mubi.2720898758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_clk_byp_req_intersig_mubi.2911764386
Short name T628
Test name
Test status
Simulation time 48599559 ps
CPU time 0.87 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2911764386
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_clk_byp_req_intersig_mubi.2911764386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_lc_ctrl_intersig_mubi.2217222552
Short name T634
Test name
Test status
Simulation time 53680778 ps
CPU time 0.87 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217222552
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_lc_ctrl_intersig_mubi.2217222552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_peri.3642576885
Short name T608
Test name
Test status
Simulation time 20950402 ps
CPU time 0.65 seconds
Started Sep 18 06:13:06 AM UTC 24
Finished Sep 18 06:13:10 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642576885 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_peri.3642576885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_regwen.4197919549
Short name T643
Test name
Test status
Simulation time 621158199 ps
CPU time 3.1 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4197919549 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_regwen.4197919549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_smoke.1641712473
Short name T610
Test name
Test status
Simulation time 50914234 ps
CPU time 1.01 seconds
Started Sep 18 06:13:05 AM UTC 24
Finished Sep 18 06:13:11 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641712473 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_smoke.1641712473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all.2802827186
Short name T665
Test name
Test status
Simulation time 3004753423 ps
CPU time 15.14 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 211088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802827186 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_stress_all.2802827186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_stress_all_with_rand_reset.43536828
Short name T793
Test name
Test status
Simulation time 5416411137 ps
CPU time 68.22 seconds
Started Sep 18 06:13:09 AM UTC 24
Finished Sep 18 06:14:29 AM UTC 24
Peak memory 220684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43536828 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.clkmgr_stress_all_with_rand_reset.43536828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/37.clkmgr_trans.1187733969
Short name T633
Test name
Test status
Simulation time 23116111 ps
CPU time 0.79 seconds
Started Sep 18 06:13:07 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187733969 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.clkmgr_trans.1187733969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/37.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_alert_test.1782514496
Short name T635
Test name
Test status
Simulation time 56234112 ps
CPU time 0.85 seconds
Started Sep 18 06:13:19 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782514496 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_alert_test.1782514496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_handshake_intersig_mubi.2898485542
Short name T624
Test name
Test status
Simulation time 49104119 ps
CPU time 0.85 seconds
Started Sep 18 06:13:16 AM UTC 24
Finished Sep 18 06:13:21 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898485542 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_handshake_intersig_mubi.2898485542
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_clk_status.1691831309
Short name T627
Test name
Test status
Simulation time 45345611 ps
CPU time 0.73 seconds
Started Sep 18 06:13:13 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691831309 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_clk_status.1691831309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_div_intersig_mubi.294117328
Short name T637
Test name
Test status
Simulation time 39974896 ps
CPU time 0.89 seconds
Started Sep 18 06:13:17 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294117328 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_div_intersig_mubi.294117328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_extclk.2830302602
Short name T642
Test name
Test status
Simulation time 43570501 ps
CPU time 0.87 seconds
Started Sep 18 06:13:11 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 210212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2830302602 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_extclk.2830302602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency.2899346053
Short name T673
Test name
Test status
Simulation time 1874407471 ps
CPU time 13.97 seconds
Started Sep 18 06:13:11 AM UTC 24
Finished Sep 18 06:13:37 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899346053 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency.2899346053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_frequency_timeout.1232891743
Short name T658
Test name
Test status
Simulation time 2314259489 ps
CPU time 8.64 seconds
Started Sep 18 06:13:11 AM UTC 24
Finished Sep 18 06:13:31 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232891743 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_frequency_timeout.1232891743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_idle_intersig_mubi.3864378535
Short name T631
Test name
Test status
Simulation time 169656104 ps
CPU time 1.27 seconds
Started Sep 18 06:13:13 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864378535 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_idle_intersig_mubi.3864378535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_lc_ctrl_intersig_mubi.3662841094
Short name T649
Test name
Test status
Simulation time 29218487 ps
CPU time 0.73 seconds
Started Sep 18 06:13:14 AM UTC 24
Finished Sep 18 06:13:26 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662841094
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_lc_ctrl_intersig_mubi.3662841094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_peri.1345385378
Short name T650
Test name
Test status
Simulation time 43105395 ps
CPU time 0.75 seconds
Started Sep 18 06:13:11 AM UTC 24
Finished Sep 18 06:13:27 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345385378 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_peri.1345385378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_regwen.1698318676
Short name T647
Test name
Test status
Simulation time 1214393332 ps
CPU time 4.49 seconds
Started Sep 18 06:13:19 AM UTC 24
Finished Sep 18 06:13:26 AM UTC 24
Peak memory 210872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698318676 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_regwen.1698318676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_smoke.3917510902
Short name T641
Test name
Test status
Simulation time 36399495 ps
CPU time 0.88 seconds
Started Sep 18 06:13:11 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 210204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917510902 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_smoke.3917510902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all.911917976
Short name T680
Test name
Test status
Simulation time 4480125967 ps
CPU time 24.97 seconds
Started Sep 18 06:13:19 AM UTC 24
Finished Sep 18 06:13:47 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911917976 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_stress_all.911917976
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_stress_all_with_rand_reset.3905956302
Short name T709
Test name
Test status
Simulation time 4065787877 ps
CPU time 34.78 seconds
Started Sep 18 06:13:19 AM UTC 24
Finished Sep 18 06:13:56 AM UTC 24
Peak memory 227548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905956302 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 38.clkmgr_stress_all_with_rand_reset.3905956302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/38.clkmgr_trans.1647190938
Short name T626
Test name
Test status
Simulation time 26923057 ps
CPU time 0.87 seconds
Started Sep 18 06:13:13 AM UTC 24
Finished Sep 18 06:13:22 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647190938 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.clkmgr_trans.1647190938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/38.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_clk_status.295148813
Short name T651
Test name
Test status
Simulation time 14286947 ps
CPU time 0.72 seconds
Started Sep 18 06:13:25 AM UTC 24
Finished Sep 18 06:13:27 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295148813 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_clk_status.295148813
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_extclk.935851958
Short name T638
Test name
Test status
Simulation time 30312395 ps
CPU time 0.86 seconds
Started Sep 18 06:13:20 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935851958 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_extclk.935851958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency.1341085777
Short name T656
Test name
Test status
Simulation time 207629945 ps
CPU time 1.66 seconds
Started Sep 18 06:13:22 AM UTC 24
Finished Sep 18 06:13:28 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341085777 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency.1341085777
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_frequency_timeout.2742531776
Short name T662
Test name
Test status
Simulation time 383233537 ps
CPU time 2.28 seconds
Started Sep 18 06:13:22 AM UTC 24
Finished Sep 18 06:13:33 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742531776 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_frequency_timeout.2742531776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_idle_intersig_mubi.423870552
Short name T653
Test name
Test status
Simulation time 137396343 ps
CPU time 1.26 seconds
Started Sep 18 06:13:25 AM UTC 24
Finished Sep 18 06:13:28 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423870552 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_idle_intersig_mubi.423870552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_peri.1304554980
Short name T652
Test name
Test status
Simulation time 19316594 ps
CPU time 0.63 seconds
Started Sep 18 06:13:22 AM UTC 24
Finished Sep 18 06:13:27 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304554980 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_peri.1304554980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/39.clkmgr_smoke.1420255758
Short name T640
Test name
Test status
Simulation time 120115796 ps
CPU time 1.04 seconds
Started Sep 18 06:13:20 AM UTC 24
Finished Sep 18 06:13:23 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420255758 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.clkmgr_smoke.1420255758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/39.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_alert_test.3730378654
Short name T204
Test name
Test status
Simulation time 62566851 ps
CPU time 1.31 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730378654 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.3730378654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_handshake_intersig_mubi.2636434360
Short name T105
Test name
Test status
Simulation time 27752680 ps
CPU time 1.12 seconds
Started Sep 18 06:10:54 AM UTC 24
Finished Sep 18 06:10:56 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636434360 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_handshake_intersig_mubi.2636434360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_clk_status.2209848358
Short name T188
Test name
Test status
Simulation time 13240178 ps
CPU time 1.05 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209848358 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.2209848358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_div_intersig_mubi.3911366488
Short name T90
Test name
Test status
Simulation time 109219854 ps
CPU time 1.37 seconds
Started Sep 18 06:10:54 AM UTC 24
Finished Sep 18 06:10:57 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911366488 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_div_intersig_mubi.3911366488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_extclk.3340684498
Short name T169
Test name
Test status
Simulation time 25631365 ps
CPU time 1.27 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 210692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340684498 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_extclk.3340684498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency.1242162006
Short name T13
Test name
Test status
Simulation time 1882945264 ps
CPU time 15.16 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:11:09 AM UTC 24
Peak memory 210912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242162006 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.1242162006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_frequency_timeout.1871007375
Short name T44
Test name
Test status
Simulation time 2444860846 ps
CPU time 10.43 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:11:04 AM UTC 24
Peak memory 210904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871007375 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.1871007375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_idle_intersig_mubi.1848072643
Short name T201
Test name
Test status
Simulation time 20709024 ps
CPU time 1.03 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848072643 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.1848072643
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_clk_byp_req_intersig_mubi.748616394
Short name T207
Test name
Test status
Simulation time 14837269 ps
CPU time 0.98 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748616394 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_clk_byp_req_intersig_mubi.748616394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_lc_ctrl_intersig_mubi.641442267
Short name T208
Test name
Test status
Simulation time 47135253 ps
CPU time 1.23 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641442267 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_lc_ctrl_intersig_mubi.641442267
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_peri.3598472263
Short name T66
Test name
Test status
Simulation time 43002285 ps
CPU time 1.05 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598472263 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.3598472263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_regwen.1944905459
Short name T3
Test name
Test status
Simulation time 198907086 ps
CPU time 1.52 seconds
Started Sep 18 06:10:54 AM UTC 24
Finished Sep 18 06:10:57 AM UTC 24
Peak memory 210732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944905459 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.1944905459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_sec_cm.3550487507
Short name T19
Test name
Test status
Simulation time 381114165 ps
CPU time 3.07 seconds
Started Sep 18 06:10:54 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 242560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550487507 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.3550487507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_smoke.2033084347
Short name T63
Test name
Test status
Simulation time 16410620 ps
CPU time 0.96 seconds
Started Sep 18 06:10:52 AM UTC 24
Finished Sep 18 06:10:53 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033084347 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.2033084347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all.1380563945
Short name T436
Test name
Test status
Simulation time 12407481324 ps
CPU time 90.42 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:12:28 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380563945 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all.1380563945
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_stress_all_with_rand_reset.2785357488
Short name T178
Test name
Test status
Simulation time 6898099343 ps
CPU time 97.66 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:12:35 AM UTC 24
Peak memory 220604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785357488 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.2785357488
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/4.clkmgr_trans.2878541091
Short name T209
Test name
Test status
Simulation time 96351215 ps
CPU time 1.42 seconds
Started Sep 18 06:10:53 AM UTC 24
Finished Sep 18 06:10:55 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878541091 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.2878541091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/4.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/40.clkmgr_alert_test.724723364
Short name T659
Test name
Test status
Simulation time 107983094 ps
CPU time 0.91 seconds
Started Sep 18 06:13:29 AM UTC 24
Finished Sep 18 06:13:32 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724723364 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_alert_test.724723364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/40.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/40.clkmgr_regwen.820778098
Short name T664
Test name
Test status
Simulation time 788024723 ps
CPU time 4.28 seconds
Started Sep 18 06:13:29 AM UTC 24
Finished Sep 18 06:13:35 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820778098 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_regwen.820778098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/40.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/40.clkmgr_stress_all.4206463965
Short name T676
Test name
Test status
Simulation time 2891793404 ps
CPU time 9.99 seconds
Started Sep 18 06:13:29 AM UTC 24
Finished Sep 18 06:13:41 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206463965 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.clkmgr_stress_all.4206463965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/40.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_alert_test.1980675692
Short name T686
Test name
Test status
Simulation time 29781487 ps
CPU time 0.73 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980675692 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_alert_test.1980675692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_handshake_intersig_mubi.1739133569
Short name T669
Test name
Test status
Simulation time 22288265 ps
CPU time 0.75 seconds
Started Sep 18 06:13:33 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739133569 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_handshake_intersig_mubi.1739133569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_clk_status.1529172111
Short name T666
Test name
Test status
Simulation time 15141208 ps
CPU time 0.63 seconds
Started Sep 18 06:13:33 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 208160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529172111 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_clk_status.1529172111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_div_intersig_mubi.1452736037
Short name T670
Test name
Test status
Simulation time 19760676 ps
CPU time 0.69 seconds
Started Sep 18 06:13:35 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1452736037 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_div_intersig_mubi.1452736037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_extclk.884817985
Short name T657
Test name
Test status
Simulation time 12800300 ps
CPU time 0.65 seconds
Started Sep 18 06:13:29 AM UTC 24
Finished Sep 18 06:13:31 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884817985 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_extclk.884817985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_idle_intersig_mubi.3258066526
Short name T667
Test name
Test status
Simulation time 20004732 ps
CPU time 0.75 seconds
Started Sep 18 06:13:33 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 208248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258066526 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_idle_intersig_mubi.3258066526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_clk_byp_req_intersig_mubi.3545171789
Short name T674
Test name
Test status
Simulation time 164064104 ps
CPU time 1.12 seconds
Started Sep 18 06:13:33 AM UTC 24
Finished Sep 18 06:13:37 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545171789
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_clk_byp_req_intersig_mubi.3545171789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_lc_ctrl_intersig_mubi.3484996179
Short name T672
Test name
Test status
Simulation time 118041129 ps
CPU time 0.97 seconds
Started Sep 18 06:13:33 AM UTC 24
Finished Sep 18 06:13:36 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484996179
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_lc_ctrl_intersig_mubi.3484996179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_peri.2978995388
Short name T677
Test name
Test status
Simulation time 17589850 ps
CPU time 0.67 seconds
Started Sep 18 06:13:32 AM UTC 24
Finished Sep 18 06:13:47 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978995388 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_peri.2978995388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_regwen.3054336090
Short name T705
Test name
Test status
Simulation time 927654341 ps
CPU time 3.54 seconds
Started Sep 18 06:13:36 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054336090 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_regwen.3054336090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_smoke.688200099
Short name T660
Test name
Test status
Simulation time 85007000 ps
CPU time 0.94 seconds
Started Sep 18 06:13:29 AM UTC 24
Finished Sep 18 06:13:32 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688200099 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_smoke.688200099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all.379538415
Short name T714
Test name
Test status
Simulation time 5744047264 ps
CPU time 17.25 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:14:04 AM UTC 24
Peak memory 211028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379538415 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_stress_all.379538415
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_stress_all_with_rand_reset.2503127669
Short name T811
Test name
Test status
Simulation time 41313619295 ps
CPU time 183.3 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:16:51 AM UTC 24
Peak memory 230340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503127669 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 41.clkmgr_stress_all_with_rand_reset.2503127669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/41.clkmgr_trans.1444047054
Short name T678
Test name
Test status
Simulation time 109821703 ps
CPU time 0.86 seconds
Started Sep 18 06:13:32 AM UTC 24
Finished Sep 18 06:13:47 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444047054 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.clkmgr_trans.1444047054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/41.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_alert_test.718488938
Short name T691
Test name
Test status
Simulation time 22411150 ps
CPU time 0.72 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718488938 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_alert_test.718488938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_handshake_intersig_mubi.4069898746
Short name T707
Test name
Test status
Simulation time 30675574 ps
CPU time 0.85 seconds
Started Sep 18 06:13:46 AM UTC 24
Finished Sep 18 06:13:55 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069898746 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_handshake_intersig_mubi.4069898746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_clk_status.2870237388
Short name T688
Test name
Test status
Simulation time 15692269 ps
CPU time 0.67 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870237388 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_clk_status.2870237388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_div_intersig_mubi.184197619
Short name T625
Test name
Test status
Simulation time 49748881 ps
CPU time 0.77 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184197619 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_div_intersig_mubi.184197619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_extclk.1491780728
Short name T685
Test name
Test status
Simulation time 13322644 ps
CPU time 0.66 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491780728 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_extclk.1491780728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency.32689022
Short name T713
Test name
Test status
Simulation time 1283237941 ps
CPU time 10.03 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:14:00 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32689022 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency.32689022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_frequency_timeout.3742246260
Short name T706
Test name
Test status
Simulation time 617305972 ps
CPU time 3.95 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:54 AM UTC 24
Peak memory 210636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742246260 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_frequency_timeout.3742246260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_idle_intersig_mubi.620657884
Short name T690
Test name
Test status
Simulation time 21912815 ps
CPU time 0.74 seconds
Started Sep 18 06:13:39 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620657884 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_idle_intersig_mubi.620657884
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_clk_byp_req_intersig_mubi.431762481
Short name T684
Test name
Test status
Simulation time 12975174 ps
CPU time 0.63 seconds
Started Sep 18 06:13:43 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431762481 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_clk_byp_req_intersig_mubi.431762481
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_lc_ctrl_intersig_mubi.60170856
Short name T683
Test name
Test status
Simulation time 26797299 ps
CPU time 0.75 seconds
Started Sep 18 06:13:43 AM UTC 24
Finished Sep 18 06:13:50 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60170856 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_lc_ctrl_intersig_mubi.60170856
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_peri.3758936083
Short name T687
Test name
Test status
Simulation time 35728636 ps
CPU time 0.69 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758936083 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_peri.3758936083
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_regwen.2646740004
Short name T708
Test name
Test status
Simulation time 1297026491 ps
CPU time 4.76 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:56 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646740004 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_regwen.2646740004
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_smoke.2703202830
Short name T679
Test name
Test status
Simulation time 32417499 ps
CPU time 0.76 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:47 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703202830 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_smoke.2703202830
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all.1006950869
Short name T759
Test name
Test status
Simulation time 5995044690 ps
CPU time 24.73 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:14:16 AM UTC 24
Peak memory 211036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006950869 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_stress_all.1006950869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_stress_all_with_rand_reset.2268815070
Short name T792
Test name
Test status
Simulation time 10452062718 ps
CPU time 36.83 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:14:28 AM UTC 24
Peak memory 220740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268815070 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 42.clkmgr_stress_all_with_rand_reset.2268815070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/42.clkmgr_trans.1364410699
Short name T689
Test name
Test status
Simulation time 57854980 ps
CPU time 0.95 seconds
Started Sep 18 06:13:38 AM UTC 24
Finished Sep 18 06:13:51 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364410699 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.clkmgr_trans.1364410699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/42.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_alert_test.2957850587
Short name T702
Test name
Test status
Simulation time 68976083 ps
CPU time 0.82 seconds
Started Sep 18 06:13:51 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957850587 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_alert_test.2957850587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_handshake_intersig_mubi.3580974038
Short name T697
Test name
Test status
Simulation time 23058870 ps
CPU time 0.78 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580974038 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_handshake_intersig_mubi.3580974038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_clk_status.3368721742
Short name T696
Test name
Test status
Simulation time 15413332 ps
CPU time 0.79 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368721742 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_clk_status.3368721742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_div_intersig_mubi.160828979
Short name T703
Test name
Test status
Simulation time 81417356 ps
CPU time 0.9 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160828979 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_div_intersig_mubi.160828979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_extclk.593525211
Short name T693
Test name
Test status
Simulation time 20439031 ps
CPU time 0.74 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593525211 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_extclk.593525211
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency.2429106016
Short name T711
Test name
Test status
Simulation time 1652061382 ps
CPU time 6.95 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:58 AM UTC 24
Peak memory 210600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429106016 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency.2429106016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_frequency_timeout.66626351
Short name T712
Test name
Test status
Simulation time 1952623885 ps
CPU time 7.98 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:14:00 AM UTC 24
Peak memory 210824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=66626351 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_frequency_timeout.66626351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_idle_intersig_mubi.635213360
Short name T701
Test name
Test status
Simulation time 51921696 ps
CPU time 1.08 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635213360 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_idle_intersig_mubi.635213360
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_clk_byp_req_intersig_mubi.2001518850
Short name T698
Test name
Test status
Simulation time 93505288 ps
CPU time 0.87 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001518850
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_clk_byp_req_intersig_mubi.2001518850
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_lc_ctrl_intersig_mubi.3830056983
Short name T699
Test name
Test status
Simulation time 87499792 ps
CPU time 0.96 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3830056983
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_lc_ctrl_intersig_mubi.3830056983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_peri.3630056700
Short name T623
Test name
Test status
Simulation time 47608088 ps
CPU time 0.77 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630056700 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_peri.3630056700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_regwen.1067977308
Short name T710
Test name
Test status
Simulation time 1062716632 ps
CPU time 6.08 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:58 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067977308 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_regwen.1067977308
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_smoke.3676433446
Short name T629
Test name
Test status
Simulation time 48103984 ps
CPU time 0.8 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676433446 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_smoke.3676433446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all.39943202
Short name T763
Test name
Test status
Simulation time 5371327908 ps
CPU time 27.05 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 210964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39943202 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_stress_all.39943202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_stress_all_with_rand_reset.1398001114
Short name T804
Test name
Test status
Simulation time 5104329229 ps
CPU time 56.18 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:14:49 AM UTC 24
Peak memory 224708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398001114 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 43.clkmgr_stress_all_with_rand_reset.1398001114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/43.clkmgr_trans.2422200578
Short name T695
Test name
Test status
Simulation time 18820137 ps
CPU time 0.72 seconds
Started Sep 18 06:13:50 AM UTC 24
Finished Sep 18 06:13:52 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422200578 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.clkmgr_trans.2422200578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/43.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_alert_test.2788410744
Short name T722
Test name
Test status
Simulation time 41796636 ps
CPU time 0.75 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2788410744 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_alert_test.2788410744
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_handshake_intersig_mubi.1742248116
Short name T723
Test name
Test status
Simulation time 78874717 ps
CPU time 0.96 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742248116 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_handshake_intersig_mubi.1742248116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_clk_status.127230685
Short name T716
Test name
Test status
Simulation time 17270486 ps
CPU time 0.66 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127230685 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_clk_status.127230685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_div_intersig_mubi.4185441708
Short name T719
Test name
Test status
Simulation time 18168490 ps
CPU time 0.71 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185441708 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_div_intersig_mubi.4185441708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_extclk.417859489
Short name T700
Test name
Test status
Simulation time 19721847 ps
CPU time 0.74 seconds
Started Sep 18 06:13:51 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417859489 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_extclk.417859489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency.64573119
Short name T758
Test name
Test status
Simulation time 1970035165 ps
CPU time 7.96 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:13 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64573119 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency.64573119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_frequency_timeout.376545667
Short name T757
Test name
Test status
Simulation time 974934014 ps
CPU time 7.24 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:12 AM UTC 24
Peak memory 210472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376545667 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_frequency_timeout.376545667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_idle_intersig_mubi.3969211659
Short name T733
Test name
Test status
Simulation time 272855986 ps
CPU time 1.48 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969211659 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_idle_intersig_mubi.3969211659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_clk_byp_req_intersig_mubi.1629442137
Short name T721
Test name
Test status
Simulation time 40084437 ps
CPU time 0.83 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629442137
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_clk_byp_req_intersig_mubi.1629442137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_lc_ctrl_intersig_mubi.3569304168
Short name T718
Test name
Test status
Simulation time 23091477 ps
CPU time 0.79 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569304168
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_lc_ctrl_intersig_mubi.3569304168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_peri.1594102659
Short name T715
Test name
Test status
Simulation time 20207511 ps
CPU time 0.68 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594102659 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_peri.1594102659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_regwen.1955206373
Short name T753
Test name
Test status
Simulation time 451685429 ps
CPU time 2.78 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:08 AM UTC 24
Peak memory 210596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955206373 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_regwen.1955206373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_smoke.3137122195
Short name T704
Test name
Test status
Simulation time 42004886 ps
CPU time 0.93 seconds
Started Sep 18 06:13:51 AM UTC 24
Finished Sep 18 06:13:53 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137122195 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_smoke.3137122195
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all.3800625699
Short name T794
Test name
Test status
Simulation time 3634211173 ps
CPU time 25.25 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:31 AM UTC 24
Peak memory 211168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800625699 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_stress_all.3800625699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_stress_all_with_rand_reset.3537899141
Short name T115
Test name
Test status
Simulation time 3666786186 ps
CPU time 48.28 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:54 AM UTC 24
Peak memory 220592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537899141 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 44.clkmgr_stress_all_with_rand_reset.3537899141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/44.clkmgr_trans.874702796
Short name T717
Test name
Test status
Simulation time 37590432 ps
CPU time 0.85 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874702796 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.clkmgr_trans.874702796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/44.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_alert_test.314365536
Short name T741
Test name
Test status
Simulation time 13506276 ps
CPU time 0.72 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 210796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314365536 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_alert_test.314365536
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_handshake_intersig_mubi.3721494774
Short name T731
Test name
Test status
Simulation time 53511873 ps
CPU time 0.83 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721494774 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_handshake_intersig_mubi.3721494774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_clk_status.2483063311
Short name T726
Test name
Test status
Simulation time 25554957 ps
CPU time 0.65 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483063311 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_clk_status.2483063311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_div_intersig_mubi.1516804141
Short name T740
Test name
Test status
Simulation time 60260518 ps
CPU time 0.89 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516804141 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_div_intersig_mubi.1516804141
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_extclk.2871997351
Short name T725
Test name
Test status
Simulation time 26864622 ps
CPU time 0.81 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871997351 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_extclk.2871997351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency.1639788869
Short name T761
Test name
Test status
Simulation time 1637698892 ps
CPU time 12.17 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:18 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639788869 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency.1639788869
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_frequency_timeout.3890761573
Short name T756
Test name
Test status
Simulation time 1106667471 ps
CPU time 5.72 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:11 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890761573 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_frequency_timeout.3890761573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_idle_intersig_mubi.2570641506
Short name T732
Test name
Test status
Simulation time 45401698 ps
CPU time 0.95 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570641506 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_idle_intersig_mubi.2570641506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_clk_byp_req_intersig_mubi.1083540257
Short name T729
Test name
Test status
Simulation time 46974030 ps
CPU time 0.77 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083540257
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_clk_byp_req_intersig_mubi.1083540257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_lc_ctrl_intersig_mubi.3606062703
Short name T728
Test name
Test status
Simulation time 12626620 ps
CPU time 0.69 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 210712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606062703
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_lc_ctrl_intersig_mubi.3606062703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_peri.780999530
Short name T727
Test name
Test status
Simulation time 37567020 ps
CPU time 0.78 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780999530 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_peri.780999530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_regwen.636357037
Short name T752
Test name
Test status
Simulation time 224913039 ps
CPU time 1.39 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636357037 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_regwen.636357037
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_smoke.3189871314
Short name T724
Test name
Test status
Simulation time 18301378 ps
CPU time 0.75 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189871314 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_smoke.3189871314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all.2916699382
Short name T114
Test name
Test status
Simulation time 10396224282 ps
CPU time 41.63 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:48 AM UTC 24
Peak memory 210976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916699382 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_stress_all.2916699382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_stress_all_with_rand_reset.546466597
Short name T807
Test name
Test status
Simulation time 9356000239 ps
CPU time 87.14 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:15:34 AM UTC 24
Peak memory 220740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546466597 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 45.clkmgr_stress_all_with_rand_reset.546466597
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/45.clkmgr_trans.2210241678
Short name T730
Test name
Test status
Simulation time 80353736 ps
CPU time 1.02 seconds
Started Sep 18 06:14:04 AM UTC 24
Finished Sep 18 06:14:06 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2210241678 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.clkmgr_trans.2210241678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/45.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_alert_test.360530667
Short name T765
Test name
Test status
Simulation time 16473770 ps
CPU time 0.76 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360530667 -assert no
postproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_alert_test.360530667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_handshake_intersig_mubi.4066929496
Short name T750
Test name
Test status
Simulation time 44966627 ps
CPU time 0.86 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066929496 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_handshake_intersig_mubi.4066929496
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_clk_status.623977785
Short name T745
Test name
Test status
Simulation time 28690767 ps
CPU time 0.8 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623977785 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_clk_status.623977785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_div_intersig_mubi.4097590220
Short name T747
Test name
Test status
Simulation time 21413116 ps
CPU time 0.77 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097590220 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_div_intersig_mubi.4097590220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_extclk.1534551410
Short name T744
Test name
Test status
Simulation time 59045011 ps
CPU time 0.88 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534551410 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_extclk.1534551410
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency.3928095197
Short name T755
Test name
Test status
Simulation time 1060290025 ps
CPU time 5 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:11 AM UTC 24
Peak memory 210852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928095197 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency.3928095197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_frequency_timeout.2624015485
Short name T760
Test name
Test status
Simulation time 1694355993 ps
CPU time 11.44 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:18 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2624015485 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_frequency_timeout.2624015485
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_idle_intersig_mubi.2009244917
Short name T749
Test name
Test status
Simulation time 43134112 ps
CPU time 0.94 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 210528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009244917 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_idle_intersig_mubi.2009244917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_clk_byp_req_intersig_mubi.3858647412
Short name T746
Test name
Test status
Simulation time 26558561 ps
CPU time 0.77 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858647412
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_clk_byp_req_intersig_mubi.3858647412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_lc_ctrl_intersig_mubi.843476334
Short name T751
Test name
Test status
Simulation time 106467332 ps
CPU time 1.05 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 210672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843476334 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_lc_ctrl_intersig_mubi.843476334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_peri.3449916575
Short name T743
Test name
Test status
Simulation time 40269226 ps
CPU time 0.86 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 210536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449916575 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_peri.3449916575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_regwen.3920669446
Short name T754
Test name
Test status
Simulation time 965079820 ps
CPU time 3.25 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:09 AM UTC 24
Peak memory 211000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920669446 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_regwen.3920669446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_smoke.2854807006
Short name T742
Test name
Test status
Simulation time 29404895 ps
CPU time 0.8 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854807006 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_smoke.2854807006
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all.1914750610
Short name T801
Test name
Test status
Simulation time 9550177496 ps
CPU time 33.32 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:40 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914750610 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_stress_all.1914750610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_stress_all_with_rand_reset.2889091346
Short name T808
Test name
Test status
Simulation time 15962290692 ps
CPU time 93.16 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:15:40 AM UTC 24
Peak memory 220660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889091346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 46.clkmgr_stress_all_with_rand_reset.2889091346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/46.clkmgr_trans.1482448181
Short name T748
Test name
Test status
Simulation time 27774528 ps
CPU time 0.9 seconds
Started Sep 18 06:14:05 AM UTC 24
Finished Sep 18 06:14:07 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482448181 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.clkmgr_trans.1482448181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/46.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_alert_test.2348039256
Short name T694
Test name
Test status
Simulation time 60606957 ps
CPU time 0.96 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348039256 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_alert_test.2348039256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_handshake_intersig_mubi.3325556602
Short name T734
Test name
Test status
Simulation time 51349803 ps
CPU time 0.78 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325556602 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_handshake_intersig_mubi.3325556602
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_clk_status.1491095735
Short name T766
Test name
Test status
Simulation time 21951601 ps
CPU time 0.66 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491095735 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_clk_status.1491095735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_div_intersig_mubi.3972176938
Short name T735
Test name
Test status
Simulation time 25687819 ps
CPU time 0.82 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972176938 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_div_intersig_mubi.3972176938
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_extclk.3296690719
Short name T762
Test name
Test status
Simulation time 15324329 ps
CPU time 0.7 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296690719 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_extclk.3296690719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency.3198853498
Short name T785
Test name
Test status
Simulation time 963607166 ps
CPU time 4.79 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:23 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198853498 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency.3198853498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_frequency_timeout.1091360434
Short name T791
Test name
Test status
Simulation time 1947050423 ps
CPU time 9.26 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:28 AM UTC 24
Peak memory 209988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091360434 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_frequency_timeout.1091360434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_idle_intersig_mubi.1666444262
Short name T768
Test name
Test status
Simulation time 37021530 ps
CPU time 0.73 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666444262 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_idle_intersig_mubi.1666444262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_clk_byp_req_intersig_mubi.4150336550
Short name T770
Test name
Test status
Simulation time 21960638 ps
CPU time 0.81 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150336550
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_clk_byp_req_intersig_mubi.4150336550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_lc_ctrl_intersig_mubi.1950982712
Short name T769
Test name
Test status
Simulation time 44584564 ps
CPU time 0.91 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950982712
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_lc_ctrl_intersig_mubi.1950982712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_peri.1109239152
Short name T767
Test name
Test status
Simulation time 18062216 ps
CPU time 0.7 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109239152 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_peri.1109239152
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_regwen.624859420
Short name T783
Test name
Test status
Simulation time 491341713 ps
CPU time 3.18 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:22 AM UTC 24
Peak memory 210592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=624859420 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_regwen.624859420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_smoke.1041467764
Short name T764
Test name
Test status
Simulation time 56386307 ps
CPU time 0.85 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041467764 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_smoke.1041467764
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all.3330798462
Short name T806
Test name
Test status
Simulation time 4420145966 ps
CPU time 39.17 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:58 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330798462 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_stress_all.3330798462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_stress_all_with_rand_reset.562247082
Short name T802
Test name
Test status
Simulation time 2480200633 ps
CPU time 22.48 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:41 AM UTC 24
Peak memory 220608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562247082 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 47.clkmgr_stress_all_with_rand_reset.562247082
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/47.clkmgr_trans.1581030434
Short name T771
Test name
Test status
Simulation time 110286159 ps
CPU time 1.11 seconds
Started Sep 18 06:14:17 AM UTC 24
Finished Sep 18 06:14:19 AM UTC 24
Peak memory 209212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581030434 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.clkmgr_trans.1581030434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/47.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_alert_test.4079359234
Short name T720
Test name
Test status
Simulation time 73636474 ps
CPU time 0.82 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079359234 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_alert_test.4079359234
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_handshake_intersig_mubi.2098228492
Short name T739
Test name
Test status
Simulation time 21232775 ps
CPU time 0.79 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098228492 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_handshake_intersig_mubi.2098228492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_clk_status.914036948
Short name T738
Test name
Test status
Simulation time 19881101 ps
CPU time 0.73 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914036948 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_clk_status.914036948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_div_intersig_mubi.743146633
Short name T779
Test name
Test status
Simulation time 44739450 ps
CPU time 1.09 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743146633 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_div_intersig_mubi.743146633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_extclk.35154656
Short name T736
Test name
Test status
Simulation time 44741514 ps
CPU time 0.8 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35154656 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_extclk.35154656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency.4260587261
Short name T786
Test name
Test status
Simulation time 562113766 ps
CPU time 4.61 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:24 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260587261 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency.4260587261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_frequency_timeout.1522719560
Short name T788
Test name
Test status
Simulation time 1352935281 ps
CPU time 5.47 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:24 AM UTC 24
Peak memory 210700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522719560 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_frequency_timeout.1522719560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_idle_intersig_mubi.1082844200
Short name T586
Test name
Test status
Simulation time 21531650 ps
CPU time 0.89 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082844200 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_idle_intersig_mubi.1082844200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_clk_byp_req_intersig_mubi.1309134242
Short name T775
Test name
Test status
Simulation time 79129251 ps
CPU time 0.96 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309134242
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_clk_byp_req_intersig_mubi.1309134242
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_lc_ctrl_intersig_mubi.1266184142
Short name T777
Test name
Test status
Simulation time 68011566 ps
CPU time 1.04 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266184142
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_lc_ctrl_intersig_mubi.1266184142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_peri.1612552957
Short name T737
Test name
Test status
Simulation time 17253481 ps
CPU time 0.72 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612552957 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_peri.1612552957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_regwen.1858526240
Short name T789
Test name
Test status
Simulation time 993545998 ps
CPU time 5.59 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:25 AM UTC 24
Peak memory 210804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858526240 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_regwen.1858526240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_smoke.3207559605
Short name T773
Test name
Test status
Simulation time 51586149 ps
CPU time 0.89 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207559605 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_smoke.3207559605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all.3624122197
Short name T805
Test name
Test status
Simulation time 3962024767 ps
CPU time 32.93 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:52 AM UTC 24
Peak memory 210908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624122197 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_stress_all.3624122197
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_stress_all_with_rand_reset.18169717
Short name T810
Test name
Test status
Simulation time 5681777719 ps
CPU time 115.57 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:16:16 AM UTC 24
Peak memory 225608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18169717 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.clkmgr_stress_all_with_rand_reset.18169717
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/48.clkmgr_trans.4109739811
Short name T772
Test name
Test status
Simulation time 17222064 ps
CPU time 0.72 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109739811 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.clkmgr_trans.4109739811
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/48.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_alert_test.1149817879
Short name T797
Test name
Test status
Simulation time 46923527 ps
CPU time 0.77 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:33 AM UTC 24
Peak memory 210668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149817879 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_alert_test.1149817879
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_handshake_intersig_mubi.781655334
Short name T796
Test name
Test status
Simulation time 44464697 ps
CPU time 0.84 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:32 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781655334 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_handshake_intersig_mubi.781655334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_clk_status.2120083696
Short name T776
Test name
Test status
Simulation time 14248035 ps
CPU time 0.65 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120083696 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_clk_status.2120083696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_div_intersig_mubi.930266733
Short name T798
Test name
Test status
Simulation time 119252892 ps
CPU time 1.08 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:33 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930266733 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_div_intersig_mubi.930266733
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_extclk.1465895628
Short name T774
Test name
Test status
Simulation time 22019174 ps
CPU time 0.79 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465895628 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_extclk.1465895628
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency.3608199463
Short name T782
Test name
Test status
Simulation time 269899338 ps
CPU time 1.51 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:21 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608199463 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency.3608199463
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_frequency_timeout.283978477
Short name T784
Test name
Test status
Simulation time 390492720 ps
CPU time 2.66 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:22 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283978477 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_frequency_timeout.283978477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_idle_intersig_mubi.1998149224
Short name T781
Test name
Test status
Simulation time 120892126 ps
CPU time 1.21 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:21 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998149224 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_idle_intersig_mubi.1998149224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_clk_byp_req_intersig_mubi.2139398705
Short name T799
Test name
Test status
Simulation time 219638278 ps
CPU time 1.43 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:33 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139398705
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_clk_byp_req_intersig_mubi.2139398705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_lc_ctrl_intersig_mubi.1062608313
Short name T795
Test name
Test status
Simulation time 46838922 ps
CPU time 0.88 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:32 AM UTC 24
Peak memory 210736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062608313
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_lc_ctrl_intersig_mubi.1062608313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_peri.4001675175
Short name T778
Test name
Test status
Simulation time 20248442 ps
CPU time 0.79 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001675175 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_peri.4001675175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_regwen.2715894705
Short name T800
Test name
Test status
Simulation time 314735810 ps
CPU time 1.72 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:33 AM UTC 24
Peak memory 208604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715894705 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_regwen.2715894705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_smoke.1940655397
Short name T558
Test name
Test status
Simulation time 17831960 ps
CPU time 0.81 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940655397 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_smoke.1940655397
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all.1979925983
Short name T803
Test name
Test status
Simulation time 2020276268 ps
CPU time 15.41 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:14:47 AM UTC 24
Peak memory 211108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979925983 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_stress_all.1979925983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_stress_all_with_rand_reset.882410836
Short name T809
Test name
Test status
Simulation time 14134906179 ps
CPU time 92.95 seconds
Started Sep 18 06:14:31 AM UTC 24
Finished Sep 18 06:16:06 AM UTC 24
Peak memory 220544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882410836 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 49.clkmgr_stress_all_with_rand_reset.882410836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/49.clkmgr_trans.109888414
Short name T780
Test name
Test status
Simulation time 30119187 ps
CPU time 0.91 seconds
Started Sep 18 06:14:18 AM UTC 24
Finished Sep 18 06:14:20 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109888414 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.clkmgr_trans.109888414
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/49.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_alert_test.4126745107
Short name T216
Test name
Test status
Simulation time 43543128 ps
CPU time 1.19 seconds
Started Sep 18 06:10:58 AM UTC 24
Finished Sep 18 06:11:00 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126745107 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.4126745107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_handshake_intersig_mubi.4074878968
Short name T214
Test name
Test status
Simulation time 23027754 ps
CPU time 1.08 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074878968 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_handshake_intersig_mubi.4074878968
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_clk_status.1237819581
Short name T189
Test name
Test status
Simulation time 41447760 ps
CPU time 1.15 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237819581 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.1237819581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_div_intersig_mubi.1524428908
Short name T198
Test name
Test status
Simulation time 25820747 ps
CPU time 0.86 seconds
Started Sep 18 06:10:57 AM UTC 24
Finished Sep 18 06:10:59 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524428908 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_div_intersig_mubi.1524428908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_extclk.476742756
Short name T210
Test name
Test status
Simulation time 16159979 ps
CPU time 0.99 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476742756 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_extclk.476742756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency.4106466749
Short name T118
Test name
Test status
Simulation time 206092367 ps
CPU time 2.46 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:59 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106466749 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.4106466749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_frequency_timeout.4062595599
Short name T46
Test name
Test status
Simulation time 2083079731 ps
CPU time 8.37 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:11:05 AM UTC 24
Peak memory 210832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062595599 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.4062595599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_idle_intersig_mubi.1153424263
Short name T202
Test name
Test status
Simulation time 20246254 ps
CPU time 0.97 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153424263 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.1153424263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_clk_byp_req_intersig_mubi.3266233745
Short name T170
Test name
Test status
Simulation time 16486812 ps
CPU time 1.04 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266233745
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_clk_byp_req_intersig_mubi.3266233745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_lc_ctrl_intersig_mubi.1531619928
Short name T197
Test name
Test status
Simulation time 71494161 ps
CPU time 1.31 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1531619928
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_lc_ctrl_intersig_mubi.1531619928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_peri.598742868
Short name T212
Test name
Test status
Simulation time 22695331 ps
CPU time 0.91 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598742868 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.598742868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_regwen.2315218667
Short name T43
Test name
Test status
Simulation time 918804678 ps
CPU time 3.85 seconds
Started Sep 18 06:10:58 AM UTC 24
Finished Sep 18 06:11:02 AM UTC 24
Peak memory 210996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315218667 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2315218667
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_smoke.3567620018
Short name T211
Test name
Test status
Simulation time 18211157 ps
CPU time 1.1 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567620018 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.3567620018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all.401134798
Short name T14
Test name
Test status
Simulation time 3808430501 ps
CPU time 15.6 seconds
Started Sep 18 06:10:58 AM UTC 24
Finished Sep 18 06:11:14 AM UTC 24
Peak memory 210968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401134798 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all.401134798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_stress_all_with_rand_reset.1688281549
Short name T79
Test name
Test status
Simulation time 13626694397 ps
CPU time 89.91 seconds
Started Sep 18 06:10:58 AM UTC 24
Finished Sep 18 06:12:29 AM UTC 24
Peak memory 220540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688281549 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.1688281549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/5.clkmgr_trans.1352818944
Short name T213
Test name
Test status
Simulation time 31479814 ps
CPU time 1.17 seconds
Started Sep 18 06:10:56 AM UTC 24
Finished Sep 18 06:10:58 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352818944 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.1352818944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/5.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_alert_test.1900597927
Short name T221
Test name
Test status
Simulation time 26040141 ps
CPU time 0.91 seconds
Started Sep 18 06:11:01 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900597927 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.1900597927
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_extclk.1318101639
Short name T184
Test name
Test status
Simulation time 16942555 ps
CPU time 0.88 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318101639 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_extclk.1318101639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency.2278695209
Short name T36
Test name
Test status
Simulation time 1359137037 ps
CPU time 6.42 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:27 AM UTC 24
Peak memory 210724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278695209 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.2278695209
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_frequency_timeout.276153544
Short name T45
Test name
Test status
Simulation time 1167146756 ps
CPU time 4.22 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:04 AM UTC 24
Peak memory 210760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276153544 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.276153544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_peri.3793980303
Short name T215
Test name
Test status
Simulation time 52696065 ps
CPU time 1.34 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:01 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793980303 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.3793980303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_regwen.1401049354
Short name T229
Test name
Test status
Simulation time 972927081 ps
CPU time 3.63 seconds
Started Sep 18 06:11:00 AM UTC 24
Finished Sep 18 06:11:28 AM UTC 24
Peak memory 210932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401049354 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.1401049354
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_smoke.36907442
Short name T218
Test name
Test status
Simulation time 77306318 ps
CPU time 1.12 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:11 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36907442 -assert nopostproc +UVM_TESTNAME=clkm
gr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_
17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.36907442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all.3254623344
Short name T313
Test name
Test status
Simulation time 6239343308 ps
CPU time 35.05 seconds
Started Sep 18 06:11:01 AM UTC 24
Finished Sep 18 06:12:00 AM UTC 24
Peak memory 211000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254623344 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all.3254623344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_stress_all_with_rand_reset.386489504
Short name T179
Test name
Test status
Simulation time 12475841515 ps
CPU time 74.41 seconds
Started Sep 18 06:11:00 AM UTC 24
Finished Sep 18 06:12:40 AM UTC 24
Peak memory 227476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386489504 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.386489504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/6.clkmgr_trans.2440691187
Short name T217
Test name
Test status
Simulation time 26242452 ps
CPU time 1.05 seconds
Started Sep 18 06:10:59 AM UTC 24
Finished Sep 18 06:11:11 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440691187 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.2440691187
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/6.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_handshake_intersig_mubi.1619711339
Short name T84
Test name
Test status
Simulation time 22316955 ps
CPU time 0.86 seconds
Started Sep 18 06:11:06 AM UTC 24
Finished Sep 18 06:11:21 AM UTC 24
Peak memory 208672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619711339 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_handshake_intersig_mubi.1619711339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_clk_status.1816517616
Short name T49
Test name
Test status
Simulation time 15053239 ps
CPU time 0.68 seconds
Started Sep 18 06:11:05 AM UTC 24
Finished Sep 18 06:11:07 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816517616 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.1816517616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_div_intersig_mubi.263018920
Short name T226
Test name
Test status
Simulation time 15780120 ps
CPU time 0.84 seconds
Started Sep 18 06:11:07 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263018920 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_div_intersig_mubi.263018920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_extclk.2623154430
Short name T219
Test name
Test status
Simulation time 18751280 ps
CPU time 0.82 seconds
Started Sep 18 06:11:03 AM UTC 24
Finished Sep 18 06:11:16 AM UTC 24
Peak memory 210728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623154430 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_extclk.2623154430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_extclk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency.3902792827
Short name T39
Test name
Test status
Simulation time 1999087817 ps
CPU time 15.77 seconds
Started Sep 18 06:11:03 AM UTC 24
Finished Sep 18 06:11:37 AM UTC 24
Peak memory 210864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902792827 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3902792827
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_frequency_timeout.391628758
Short name T228
Test name
Test status
Simulation time 1578855260 ps
CPU time 11.77 seconds
Started Sep 18 06:11:03 AM UTC 24
Finished Sep 18 06:11:27 AM UTC 24
Peak memory 210828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391628758 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.391628758
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_idle_intersig_mubi.2641912262
Short name T83
Test name
Test status
Simulation time 24379429 ps
CPU time 0.87 seconds
Started Sep 18 06:11:06 AM UTC 24
Finished Sep 18 06:11:21 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641912262 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.2641912262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_clk_byp_req_intersig_mubi.1139457400
Short name T82
Test name
Test status
Simulation time 17526457 ps
CPU time 0.85 seconds
Started Sep 18 06:11:06 AM UTC 24
Finished Sep 18 06:11:21 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139457400
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_clk_byp_req_intersig_mubi.1139457400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_lc_ctrl_intersig_mubi.3362541544
Short name T81
Test name
Test status
Simulation time 31536463 ps
CPU time 0.84 seconds
Started Sep 18 06:11:06 AM UTC 24
Finished Sep 18 06:11:21 AM UTC 24
Peak memory 208500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362541544
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_lc_ctrl_intersig_mubi.3362541544
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_peri.1471841905
Short name T47
Test name
Test status
Simulation time 13143113 ps
CPU time 0.64 seconds
Started Sep 18 06:11:04 AM UTC 24
Finished Sep 18 06:11:06 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471841905 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1471841905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_regwen.1159779484
Short name T230
Test name
Test status
Simulation time 997605302 ps
CPU time 3.63 seconds
Started Sep 18 06:11:07 AM UTC 24
Finished Sep 18 06:11:29 AM UTC 24
Peak memory 210704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159779484 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.1159779484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_smoke.1005640616
Short name T48
Test name
Test status
Simulation time 28223665 ps
CPU time 0.94 seconds
Started Sep 18 06:11:02 AM UTC 24
Finished Sep 18 06:11:07 AM UTC 24
Peak memory 208540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005640616 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.1005640616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all.1435401701
Short name T241
Test name
Test status
Simulation time 2487850329 ps
CPU time 17.17 seconds
Started Sep 18 06:11:10 AM UTC 24
Finished Sep 18 06:11:38 AM UTC 24
Peak memory 211040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435401701 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all.1435401701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_stress_all_with_rand_reset.12993716
Short name T76
Test name
Test status
Simulation time 7905969578 ps
CPU time 67.98 seconds
Started Sep 18 06:11:08 AM UTC 24
Finished Sep 18 06:12:24 AM UTC 24
Peak memory 220664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12993716 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.12993716
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/7.clkmgr_trans.2695624917
Short name T50
Test name
Test status
Simulation time 38430477 ps
CPU time 1.08 seconds
Started Sep 18 06:11:05 AM UTC 24
Finished Sep 18 06:11:07 AM UTC 24
Peak memory 210604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695624917 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.2695624917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/7.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_alert_test.2957306171
Short name T225
Test name
Test status
Simulation time 16928368 ps
CPU time 0.9 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957306171 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.2957306171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_handshake_intersig_mubi.971631225
Short name T222
Test name
Test status
Simulation time 15262963 ps
CPU time 0.85 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971631225 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_handshake_intersig_mubi.971631225
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_clk_status.4257248814
Short name T85
Test name
Test status
Simulation time 31609936 ps
CPU time 0.79 seconds
Started Sep 18 06:11:17 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 208384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257248814 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.4257248814
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_div_intersig_mubi.512288841
Short name T224
Test name
Test status
Simulation time 23175324 ps
CPU time 1.01 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512288841 -ass
ert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_div_intersig_mubi.512288841
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency.2125053068
Short name T16
Test name
Test status
Simulation time 858796289 ps
CPU time 3.95 seconds
Started Sep 18 06:11:13 AM UTC 24
Finished Sep 18 06:11:19 AM UTC 24
Peak memory 210660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125053068 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.2125053068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_frequency_timeout.1308114489
Short name T80
Test name
Test status
Simulation time 1017048069 ps
CPU time 4.32 seconds
Started Sep 18 06:11:15 AM UTC 24
Finished Sep 18 06:11:20 AM UTC 24
Peak memory 210696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308114489 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.1308114489
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_idle_intersig_mubi.2339069243
Short name T183
Test name
Test status
Simulation time 52834615 ps
CPU time 1.03 seconds
Started Sep 18 06:11:19 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 208532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339069243 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.2339069243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_clk_byp_req_intersig_mubi.4053233161
Short name T223
Test name
Test status
Simulation time 60944880 ps
CPU time 0.89 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053233161
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_clk_byp_req_intersig_mubi.4053233161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_lc_ctrl_intersig_mubi.1897607071
Short name T86
Test name
Test status
Simulation time 23079832 ps
CPU time 0.83 seconds
Started Sep 18 06:11:20 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 208552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897607071
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_lc_ctrl_intersig_mubi.1897607071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_peri.1896325889
Short name T220
Test name
Test status
Simulation time 39546888 ps
CPU time 0.75 seconds
Started Sep 18 06:11:15 AM UTC 24
Finished Sep 18 06:11:16 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896325889 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.1896325889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_regwen.609570608
Short name T171
Test name
Test status
Simulation time 881866299 ps
CPU time 4.9 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:30 AM UTC 24
Peak memory 210808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609570608 -assert nopostproc +UVM_TESTNAME=clk
mgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.609570608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all.2764667440
Short name T265
Test name
Test status
Simulation time 6521489565 ps
CPU time 25.71 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:11:51 AM UTC 24
Peak memory 210972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764667440 -asser
t nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all.2764667440
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_stress_all_with_rand_reset.3796593857
Short name T78
Test name
Test status
Simulation time 11505239360 ps
CPU time 61.35 seconds
Started Sep 18 06:11:21 AM UTC 24
Finished Sep 18 06:12:27 AM UTC 24
Peak memory 220588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796593857 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.3796593857
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/8.clkmgr_trans.2178338430
Short name T185
Test name
Test status
Simulation time 118161370 ps
CPU time 1.14 seconds
Started Sep 18 06:11:17 AM UTC 24
Finished Sep 18 06:11:22 AM UTC 24
Peak memory 210356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178338430 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
9_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.2178338430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/8.clkmgr_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_alert_test.3882519031
Short name T240
Test name
Test status
Simulation time 90293132 ps
CPU time 1.08 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:36 AM UTC 24
Peak memory 210800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentatio
n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882519031 -assert n
opostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.3882519031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_handshake_intersig_mubi.3203981153
Short name T106
Test name
Test status
Simulation time 18477764 ps
CPU time 0.89 seconds
Started Sep 18 06:11:23 AM UTC 24
Finished Sep 18 06:11:26 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiHand +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203981153 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_handshake_intersig_mubi.3203981153
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_clk_handshake_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_clk_status.3563717913
Short name T190
Test name
Test status
Simulation time 40808943 ps
CPU time 0.7 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563717913 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.3563717913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_clk_status/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_div_intersig_mubi.2126616196
Short name T227
Test name
Test status
Simulation time 43124447 ps
CPU time 0.88 seconds
Started Sep 18 06:11:25 AM UTC 24
Finished Sep 18 06:11:27 AM UTC 24
Peak memory 208612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiDiv +do_clear_all_interrupts=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126616196 -as
sert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_div_intersig_mubi.2126616196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_div_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_frequency.2112778482
Short name T143
Test name
Test status
Simulation time 322180887 ps
CPU time 3.06 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:33 AM UTC 24
Peak memory 210656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2112778482 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.2112778482
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_frequency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_idle_intersig_mubi.2653738416
Short name T236
Test name
Test status
Simulation time 36055142 ps
CPU time 1.19 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:32 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653738416 -a
ssert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.2653738416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_clk_byp_req_intersig_mubi.2578034352
Short name T234
Test name
Test status
Simulation time 25370250 ps
CPU time 0.82 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcHand +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578034352
-assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_clk_byp_req_intersig_mubi.2578034352
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_lc_clk_byp_req_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_lc_ctrl_intersig_mubi.990809600
Short name T235
Test name
Test status
Simulation time 38449878 ps
CPU time 0.85 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +clkmgr_mubi_mode=ClkmgrMubiLcCtrl +do_clear_all_interrupts=0 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990809600 -
assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_extclk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_lc_ctrl_intersig_mubi.990809600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_peri.3002217262
Short name T232
Test name
Test status
Simulation time 20474497 ps
CPU time 0.81 seconds
Started Sep 18 06:11:22 AM UTC 24
Finished Sep 18 06:11:31 AM UTC 24
Peak memory 208548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002217262 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09
_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.3002217262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_peri/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_regwen.3228308099
Short name T173
Test name
Test status
Simulation time 1510353515 ps
CPU time 5.58 seconds
Started Sep 18 06:11:26 AM UTC 24
Finished Sep 18 06:11:56 AM UTC 24
Peak memory 211064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT
ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228308099 -assert nopostproc +UVM_TESTNAME=cl
kmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.3228308099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all.147137799
Short name T251
Test name
Test status
Simulation time 161138675 ps
CPU time 1.45 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:11:43 AM UTC 24
Peak memory 210664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +do_clear_all_interrupts=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147137799 -assert
nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all.147137799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default/9.clkmgr_stress_all_with_rand_reset.2041968346
Short name T75
Test name
Test status
Simulation time 10251923665 ps
CPU time 40.48 seconds
Started Sep 18 06:11:27 AM UTC 24
Finished Sep 18 06:12:22 AM UTC 24
Peak memory 220728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor
kspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041968346 -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.2041968346
Directory /workspaces/repo/scratch/os_regression_2024_09_17/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest
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