Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
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Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76268358 1 T4 1514 T5 3802 T6 3668
auto[1] 268074 1 T4 70 T6 634 T28 444


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76275888 1 T4 1584 T5 3802 T6 3888
auto[1] 260544 1 T6 414 T28 402 T30 90


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 76217162 1 T4 1584 T5 3802 T6 3668
auto[1] 319270 1 T6 634 T28 422 T30 186


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74376100 1 T4 62 T5 3802 T6 4178
auto[1] 2160332 1 T4 1522 T6 124 T28 1012


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57748640 1 T4 1562 T5 3284 T6 4130
auto[1] 18787792 1 T4 22 T5 518 T6 172


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 55835370 1 T4 40 T5 3284 T6 3160
auto[0] auto[0] auto[0] auto[0] auto[1] 18319968 1 T4 22 T5 518 T6 132
auto[0] auto[0] auto[0] auto[1] auto[0] 19980 1 T6 186 T28 46 T130 138
auto[0] auto[0] auto[0] auto[1] auto[1] 5370 1 T28 6 T49 40 T56 16
auto[0] auto[0] auto[1] auto[0] auto[0] 1536454 1 T4 1452 T6 80 T28 660
auto[0] auto[0] auto[1] auto[0] auto[1] 393472 1 T82 62 T129 138 T130 74
auto[0] auto[0] auto[1] auto[1] auto[0] 32832 1 T4 70 T28 20 T130 56
auto[0] auto[0] auto[1] auto[1] auto[1] 7760 1 T82 28 T130 12 T53 16
auto[0] auto[1] auto[0] auto[0] auto[0] 28454 1 T6 36 T28 30 T130 14
auto[0] auto[1] auto[0] auto[0] auto[1] 1088 1 T28 16 T207 8 T176 32
auto[0] auto[1] auto[0] auto[1] auto[0] 8296 1 T6 74 T130 72 T142 206
auto[0] auto[1] auto[0] auto[1] auto[1] 2278 1 T28 70 T208 82 T18 80
auto[0] auto[1] auto[1] auto[0] auto[0] 7284 1 T28 58 T130 30 T142 28
auto[0] auto[1] auto[1] auto[0] auto[1] 2278 1 T53 2 T182 50 T60 2
auto[0] auto[1] auto[1] auto[1] auto[0] 13190 1 T28 68 T130 72 T51 38
auto[0] auto[1] auto[1] auto[1] auto[1] 3088 1 T53 58 T60 48 T100 60
auto[1] auto[0] auto[0] auto[0] auto[0] 28966 1 T6 72 T30 42 T129 28
auto[1] auto[0] auto[0] auto[0] auto[1] 3128 1 T28 22 T49 2 T54 46
auto[1] auto[0] auto[0] auto[1] auto[0] 23140 1 T6 258 T130 252 T143 50
auto[1] auto[0] auto[0] auto[1] auto[1] 5996 1 T28 66 T49 42 T56 40
auto[1] auto[0] auto[1] auto[0] auto[0] 17934 1 T28 112 T30 54 T129 38
auto[1] auto[0] auto[1] auto[0] auto[1] 4106 1 T130 22 T142 32 T37 10
auto[1] auto[0] auto[1] auto[1] auto[0] 34112 1 T28 62 T130 136 T142 186
auto[1] auto[0] auto[1] auto[1] auto[1] 7300 1 T130 82 T37 78 T173 48
auto[1] auto[1] auto[0] auto[0] auto[0] 49974 1 T6 104 T28 22 T130 70
auto[1] auto[1] auto[0] auto[0] auto[1] 3644 1 T6 40 T142 16 T49 24
auto[1] auto[1] auto[0] auto[1] auto[0] 33266 1 T6 116 T28 106 T130 140
auto[1] auto[1] auto[0] auto[1] auto[1] 7182 1 T49 118 T182 76 T60 46
auto[1] auto[1] auto[1] auto[0] auto[0] 28236 1 T6 44 T28 32 T30 90
auto[1] auto[1] auto[1] auto[0] auto[1] 8002 1 T82 16 T54 50 T209 40
auto[1] auto[1] auto[1] auto[1] auto[0] 51152 1 T130 122 T142 102 T49 66
auto[1] auto[1] auto[1] auto[1] auto[1] 13132 1 T82 78 T54 138 T37 94

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