Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67079638 1 T4 4058 T5 1972 T6 2956
auto[1] 278178 1 T4 714 T32 58 T34 76


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67056340 1 T4 4374 T5 1972 T6 2956
auto[1] 301476 1 T4 398 T34 182 T69 692


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 67025390 1 T4 3962 T5 1972 T6 2956
auto[1] 332426 1 T4 810 T32 72 T34 86


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 65733876 1 T4 786 T5 1972 T6 2956
auto[1] 1623940 1 T4 3986 T69 1790 T70 2898


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 49421024 1 T4 4220 T5 1972 T6 326
auto[1] 17936792 1 T4 552 T6 2630 T31 168


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 48048582 1 T4 282 T5 1972 T6 326
auto[0] auto[0] auto[0] auto[0] auto[1] 17416746 1 T4 150 T6 2630 T31 168
auto[0] auto[0] auto[0] auto[1] auto[0] 23876 1 T4 36 T32 4 T34 8
auto[0] auto[0] auto[0] auto[1] auto[1] 4800 1 T4 2 T69 44 T71 2
auto[0] auto[0] auto[1] auto[0] auto[0] 946992 1 T4 3216 T69 904 T70 1906
auto[0] auto[0] auto[1] auto[0] auto[1] 443630 1 T4 172 T70 324 T106 2012
auto[0] auto[0] auto[1] auto[1] auto[0] 34002 1 T4 84 T69 212 T70 50
auto[0] auto[0] auto[1] auto[1] auto[1] 8752 1 T70 16 T139 68 T122 10
auto[0] auto[1] auto[0] auto[0] auto[0] 60584 1 T34 66 T69 30 T105 18
auto[0] auto[1] auto[0] auto[0] auto[1] 1180 1 T112 14 T138 2 T185 24
auto[0] auto[1] auto[0] auto[1] auto[0] 8706 1 T34 68 T112 42 T186 56
auto[0] auto[1] auto[0] auto[1] auto[1] 2802 1 T112 54 T138 38 T185 40
auto[0] auto[1] auto[1] auto[0] auto[0] 7570 1 T69 20 T70 8 T71 16
auto[0] auto[1] auto[1] auto[0] auto[1] 1514 1 T4 20 T70 26 T187 2
auto[0] auto[1] auto[1] auto[1] auto[0] 12396 1 T69 64 T70 64 T71 64
auto[0] auto[1] auto[1] auto[1] auto[1] 3258 1 T187 62 T188 50 T18 62
auto[1] auto[0] auto[0] auto[0] auto[0] 27346 1 T4 10 T32 18 T34 38
auto[1] auto[0] auto[0] auto[0] auto[1] 2838 1 T4 34 T47 10 T139 12
auto[1] auto[0] auto[0] auto[1] auto[0] 23720 1 T4 56 T32 54 T69 74
auto[1] auto[0] auto[0] auto[1] auto[1] 5782 1 T4 50 T47 66 T139 68
auto[1] auto[0] auto[1] auto[0] auto[0] 19850 1 T4 72 T69 22 T70 118
auto[1] auto[0] auto[1] auto[0] auto[1] 5016 1 T4 38 T70 22 T138 16
auto[1] auto[0] auto[1] auto[1] auto[0] 34858 1 T4 172 T69 80 T70 86
auto[1] auto[0] auto[1] auto[1] auto[1] 9550 1 T70 42 T27 40 T189 126
auto[1] auto[1] auto[0] auto[0] auto[0] 59520 1 T4 34 T69 16 T70 12
auto[1] auto[1] auto[0] auto[0] auto[1] 3882 1 T4 8 T34 48 T69 74
auto[1] auto[1] auto[0] auto[1] auto[0] 35772 1 T4 46 T70 56 T71 170
auto[1] auto[1] auto[0] auto[1] auto[1] 7740 1 T4 78 T71 60 T112 56
auto[1] auto[1] auto[1] auto[0] auto[0] 27218 1 T4 22 T69 130 T70 32
auto[1] auto[1] auto[1] auto[0] auto[1] 7170 1 T70 78 T106 32 T139 4
auto[1] auto[1] auto[1] auto[1] auto[0] 50032 1 T4 190 T69 358 T70 74
auto[1] auto[1] auto[1] auto[1] auto[1] 12132 1 T70 52 T139 60 T122 54

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%