Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/clkmgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_clkmgr_env_0.1/clkmgr_env_cov.sv


Summary for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 32 0 32 100.00


Variables for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
byp_req_cp 2 0 2 100.00 100 1 1 2
csr_low_speed_cp 2 0 2 100.00 100 1 1 2
csr_sel_cp 2 0 2 100.00 100 1 1 2
hw_debug_en_cp 2 0 2 100.00 100 1 1 2
scanmode_cp 2 0 2 100.00 100 1 1 2


Crosses for Group clkmgr_env_pkg::clkmgr_env_cov::extclk_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
extclk_cross 32 0 32 100.00 100 1 1 0


Summary for Variable byp_req_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for byp_req_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74259154 1 T4 2272 T5 3150 T6 3308
auto[1] 295592 1 T24 62 T25 618 T26 530


Summary for Variable csr_low_speed_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_low_speed_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74240530 1 T4 2272 T5 3150 T6 3308
auto[1] 314216 1 T24 20 T25 350 T26 462


Summary for Variable csr_sel_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for csr_sel_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 74166554 1 T4 2272 T5 3150 T6 3308
auto[1] 388192 1 T24 106 T25 654 T26 502


Summary for Variable hw_debug_en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for hw_debug_en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 73416736 1 T4 2272 T5 3150 T6 3308
auto[1] 1138010 1 T24 2548 T26 3264 T29 3732


Summary for Variable scanmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for scanmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56034598 1 T4 2272 T5 2804 T6 3308
auto[1] 18520148 1 T5 346 T24 76 T25 596


Summary for Cross extclk_cross

Samples crossed: csr_sel_cp csr_low_speed_cp hw_debug_en_cp byp_req_cp scanmode_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 32 0 32 100.00


Automatically Generated Cross Bins for extclk_cross

Bins
csr_sel_cpcsr_low_speed_cphw_debug_en_cpbyp_req_cpscanmode_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] auto[0] auto[0] auto[0] 54884040 1 T4 2272 T5 2804 T6 3308
auto[0] auto[0] auto[0] auto[0] auto[1] 18266754 1 T5 346 T25 366 T27 1512
auto[0] auto[0] auto[0] auto[1] auto[0] 21896 1 T25 84 T30 18 T133 22
auto[0] auto[0] auto[0] auto[1] auto[1] 5992 1 T25 32 T30 4 T75 10
auto[0] auto[0] auto[1] auto[0] auto[0] 705108 1 T24 2372 T26 352 T29 550
auto[0] auto[0] auto[1] auto[0] auto[1] 167028 1 T24 76 T26 2338 T29 2592
auto[0] auto[0] auto[1] auto[1] auto[0] 36018 1 T24 10 T26 40 T29 60
auto[0] auto[0] auto[1] auto[1] auto[1] 8616 1 T26 14 T29 6 T166 14
auto[0] auto[1] auto[0] auto[0] auto[0] 30786 1 T134 8 T50 52 T204 56
auto[0] auto[1] auto[0] auto[0] auto[1] 1046 1 T170 44 T94 2 T205 8
auto[0] auto[1] auto[0] auto[1] auto[0] 9728 1 T50 62 T204 112 T41 50
auto[0] auto[1] auto[0] auto[1] auto[1] 2250 1 T94 66 T206 64 T207 44
auto[0] auto[1] auto[1] auto[0] auto[0] 7878 1 T26 10 T134 32 T21 102
auto[0] auto[1] auto[1] auto[0] auto[1] 1870 1 T26 2 T80 18 T92 18
auto[0] auto[1] auto[1] auto[1] auto[0] 13994 1 T26 40 T21 70 T91 56
auto[0] auto[1] auto[1] auto[1] auto[1] 3550 1 T26 56 T39 78 T208 78
auto[1] auto[0] auto[0] auto[0] auto[0] 33918 1 T24 8 T25 56 T26 14
auto[1] auto[0] auto[0] auto[0] auto[1] 3352 1 T25 14 T30 76 T75 2
auto[1] auto[0] auto[0] auto[1] auto[0] 23652 1 T25 128 T30 80 T133 124
auto[1] auto[0] auto[0] auto[1] auto[1] 6362 1 T25 106 T30 80 T75 44
auto[1] auto[0] auto[1] auto[0] auto[0] 23144 1 T24 26 T26 20 T29 4
auto[1] auto[0] auto[1] auto[0] auto[1] 5796 1 T26 30 T29 2 T133 20
auto[1] auto[0] auto[1] auto[1] auto[0] 40020 1 T24 52 T26 46 T29 118
auto[1] auto[0] auto[1] auto[1] auto[1] 8834 1 T26 38 T29 64 T133 54
auto[1] auto[1] auto[0] auto[0] auto[0] 79920 1 T24 8 T25 54 T26 12
auto[1] auto[1] auto[0] auto[0] auto[1] 5116 1 T25 28 T30 50 T134 20
auto[1] auto[1] auto[0] auto[1] auto[0] 33020 1 T25 218 T26 64 T29 104
auto[1] auto[1] auto[0] auto[1] auto[1] 8904 1 T25 50 T134 114 T209 72
auto[1] auto[1] auto[1] auto[0] auto[0] 33780 1 T24 12 T26 2 T29 50
auto[1] auto[1] auto[1] auto[0] auto[1] 9618 1 T26 44 T29 8 T79 8
auto[1] auto[1] auto[1] auto[1] auto[0] 57696 1 T26 50 T29 278 T30 386
auto[1] auto[1] auto[1] auto[1] auto[1] 15060 1 T26 182 T134 42 T21 62

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%