Unified Coverage Report :: Module

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=1,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_step_down_req_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_io_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clkmgr_byp.u_all_ack_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_idle_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=0,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_div_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_root_ctrl.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div4_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_div2_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_io_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_usb_peri_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_aes_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

SCORE	LINE
100.00	100.00

tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=6,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Line Coverage for Module : prim_mubi4_sync ( parameter NumCopies=1,AsyncOn=1,StabilityCheck=0,ResetValue=9 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_io_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div2_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_io_div4_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_main_meas.u_calib_rdy_sync

SCORE	LINE
100.00	100.00

tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : prim_mubi4_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	22064	22064	0	0
OutputsKnown_A	1602576168	1531050590	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	224324094	211537038	0	14184
gen_flops.gen_stable_chks.OutputDelay_A	517565015	492899428	0	16548
gen_flops.gen_stable_chks.OutputIfUnstable_A	517565015	129232	0	0
gen_no_flops.OutputDelay_A	860687059	826532347	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	22064	22064
T4	28	28
T5	28	28
T6	28	28
T27	28	28
T28	28	28
T29	28	28
T30	28	28
T31	28	28
T32	28	28
T33	28	28

OutputsKnown_A

Name	Attempts	Real Successes
Total	1602576168	1531050590
T4	246357	244137
T5	217259	214873
T6	52331	46632
T27	39312	37182
T28	58226	51363
T29	76427	73066
T30	165470	162712
T31	64145	61033
T32	86967	84536
T33	204009	203342

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	224324094	211537038	14184
T4	7902	7806	18
T5	9570	9426	18
T6	11760	10368	18
T27	6300	5910	18
T28	13398	11676	18
T29	17322	16488	18
T30	10404	10188	18
T31	7416	6996	18
T32	8040	7776	18
T33	12090	12024	18

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	517565015	492899428	16548
T4	95941	94916	21
T5	82331	81221	21
T6	14148	12478	21
T27	12172	11402	21
T28	15542	13545	21
T29	20535	19547	21
T30	60835	59627	21
T31	21648	20441	21
T32	30386	29445	21
T33	75438	75129	21

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	517565015	129232
T1	130473	0
T4	75248	12
T5	82331	199
T6	14148	72
T17	0	136
T23	0	49
T24	0	66
T25	0	57
T27	12172	44
T28	15542	71
T29	20535	195
T30	60835	170
T31	21648	56
T32	30386	76
T33	75438	298
T99	0	71
T100	0	12

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	860687059	826532347
T4	142514	141376
T5	125358	124187
T6	26423	23747
T27	20840	19831
T28	29286	26103
T29	38570	36992
T30	94231	92858
T31	35081	33557
T32	48541	47276
T33	116481	116150

Line Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T30 T31  | T5 T30 T31  | T5 T30 T31  | T5 T30 T31 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T30 T31

Cond Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_io_step_down_req_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	81234049	77382983	0	0
gen_flops.gen_stable_chks.OutputDelay_A	81234049	77376794	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	81234049	18363	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	81234049	77382983
T4	18059	17869
T5	15317	15114
T6	1980	1749
T27	1964	1843
T28	2144	1872
T29	2857	2722
T30	11103	10886
T31	3712	3508
T32	5362	5200
T33	13820	13768

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	81234049	77376794	2364
T4	18059	17866	3
T5	15317	15111	3
T6	1980	1746	3
T27	1964	1840	3
T28	2144	1869	3
T29	2857	2719	3
T30	11103	10883	3
T31	3712	3505	3
T32	5362	5197	3
T33	13820	13765	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	81234049	18363
T1	30639	0
T5	15317	50
T6	1980	0
T17	0	64
T23	0	22
T24	0	27
T25	0	17
T27	1964	0
T28	2144	0
T29	2857	0
T30	11103	46
T31	3712	15
T32	5362	15
T33	13820	118
T99	0	44

Line Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_div_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T30 T32  | T5 T30 T32  | T5 T30 T32  | T5 T30 T32 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T30 T32

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T32

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T32

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T32

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T32

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T32
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T32
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T32
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T32
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_io_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_stable_chks.OutputDelay_A	37387349	35256173	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	37387349	11110	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	37387349	11110
T1	49917	0
T5	1595	31
T6	1960	0
T17	0	33
T23	0	3
T24	0	22
T25	0	22
T27	1050	0
T28	2233	0
T29	2887	0
T30	1734	26
T31	1236	0
T32	1340	17
T33	2015	44
T99	0	12
T100	0	12

Line Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T5 T30 T31  | T5 T30 T31  | T5 T30 T31  | T5 T30 T31 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T5 T30 T31

Cond Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T30,T31

Branch Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T5,T30,T31
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clkmgr_byp.u_all_ack_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_stable_chks.OutputDelay_A	37387349	35256173	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	37387349	12920	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	37387349	12920
T1	49917	0
T5	1595	38
T6	1960	0
T17	0	39
T23	0	24
T24	0	17
T25	0	18
T27	1050	0
T28	2233	0
T29	2887	0
T30	1734	26
T31	1236	13
T32	1340	16
T33	2015	44
T99	0	15

Line Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	88363946	0	0
gen_no_flops.OutputDelay_A	90389067	88363946	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	88363946
T4	18812	18701
T5	15956	15873
T6	2062	1922
T27	2027	1973
T28	2233	2092
T29	2976	2893
T30	11566	11455
T31	3866	3754
T32	5586	5445
T33	14397	14371

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	90389067	88363946
T4	18812	18701
T5	15956	15873
T6	2062	1922
T27	2027	1973
T28	2233	2092
T29	2976	2893
T30	11566	11455
T31	3866	3754
T32	5586	5445
T33	14397	14371

Line Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	81234049	79339443	0	0
gen_no_flops.OutputDelay_A	81234049	79339443	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	81234049	79339443
T4	18059	17951
T5	15317	15238
T6	1980	1845
T27	1964	1911
T28	2144	2009
T29	2857	2777
T30	11103	10996
T31	3712	3604
T32	5362	5227
T33	13820	13795

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	81234049	79339443
T4	18059	17951
T5	15317	15238
T6	1980	1845
T27	1964	1911
T28	2144	2009
T29	2857	2777
T30	11103	10996
T31	3712	3604
T32	5362	5227
T33	13820	13795

Line Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	39845802	39845802	0	0
gen_no_flops.OutputDelay_A	39845802	39845802	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	39845802	39845802
T4	8976	8976
T5	8689	8689
T6	923	923
T27	956	956
T28	1005	1005
T29	1389	1389
T30	6230	6230
T31	1845	1845
T32	3019	3019
T33	7785	7785

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	39845802	39845802
T4	8976	8976
T5	8689	8689
T6	923	923
T27	956	956
T28	1005	1005
T29	1389	1389
T30	6230	6230
T31	1845	1845
T32	3019	3019
T33	7785	7785

Line Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	19922488	19922488	0	0
gen_no_flops.OutputDelay_A	19922488	19922488	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	19922488	19922488
T4	4488	4488
T5	4343	4343
T6	461	461
T27	478	478
T28	502	502
T29	694	694
T30	3113	3113
T31	922	922
T32	1509	1509
T33	3891	3891

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	19922488	19922488
T4	4488	4488
T5	4343	4343
T6	461	461
T27	478	478
T28	502	502
T29	694	694
T30	3113	3113
T31	922	922
T32	1509	1509
T33	3891	3891

Line Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_root_ctrl.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	43415291	42450440	0	0
gen_no_flops.OutputDelay_A	43415291	42450440	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	43415291	42450440
T4	9029	8976
T5	7659	7620
T6	989	922
T27	1007	981
T28	1072	1005
T29	1428	1389
T30	5551	5498
T31	1856	1802
T32	2681	2614
T33	6910	6898

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	43415291	42450440
T4	9029	8976
T5	7659	7620
T6	989	922
T27	1007	981
T28	1072	1005
T29	1428	1389
T30	5551	5498
T31	1856	1802
T32	2681	2614
T33	6910	6898

Line Coverage for Instance : tb.dut.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        6/6              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6

Assert Coverage for Instance : tb.dut.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div2_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_io_div4_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_main_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	124	1	1	100.00
ALWAYS	128	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



123                         end else begin : gen_no_stable_chks
124        1/1                assign mubi = mubi_sync;
           Tests:       T4 T5 T6 
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_usb_meas.u_calib_rdy_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_flops.gen_no_stable_chks.OutputDelay_A	37387349	35256173	0	2364

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_flops.gen_no_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	37387349	35256173	2364
T4	1317	1301	3
T5	1595	1571	3
T6	1960	1728	3
T27	1050	985	3
T28	2233	1946	3
T29	2887	2748	3
T30	1734	1698	3
T31	1236	1166	3
T32	1340	1296	3
T33	2015	2004	3

Line Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_div4_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_div2_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_io_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_usb_peri_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	37387349	35262516	0	0
gen_no_flops.OutputDelay_A	37387349	35262516	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	37387349	35262516
T4	1317	1304
T5	1595	1574
T6	1960	1731
T27	1050	988
T28	2233	1949
T29	2887	2751
T30	1734	1701
T31	1236	1169
T32	1340	1299
T33	2015	2007

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_flops.gen_stable_chks.OutputDelay_A	90389067	86252572	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	90389067	21659	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	90389067	86252572	2364
T4	18812	18612	3
T5	15956	15742	3
T6	2062	1819	3
T27	2027	1898	3
T28	2233	1946	3
T29	2976	2833	3
T30	11566	11337	3
T31	3866	3651	3
T32	5586	5414	3
T33	14397	14339	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	90389067	21659
T4	18812	3
T5	15956	20
T6	2062	19
T27	2027	9
T28	2233	17
T29	2976	53
T30	11566	21
T31	3866	5
T32	5586	8
T33	14397	16

Line Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_aes_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_no_flops.OutputDelay_A	90389067	86258783	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_flops.gen_stable_chks.OutputDelay_A	90389067	86252572	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	90389067	21873	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	90389067	86252572	2364
T4	18812	18612	3
T5	15956	15742	3
T6	2062	1819	3
T27	2027	1898	3
T28	2233	1946	3
T29	2976	2833	3
T30	11566	11337	3
T31	3866	3651	3
T32	5586	5414	3
T33	14397	14339	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	90389067	21873
T4	18812	3
T5	15956	28
T6	2062	16
T27	2027	9
T28	2233	17
T29	2976	47
T30	11566	13
T31	3866	9
T32	5586	5
T33	14397	20

Line Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_hmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_no_flops.OutputDelay_A	90389067	86258783	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_flops.gen_stable_chks.OutputDelay_A	90389067	86252572	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	90389067	21768	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	90389067	86252572	2364
T4	18812	18612	3
T5	15956	15742	3
T6	2062	1819	3
T27	2027	1898	3
T28	2233	1946	3
T29	2976	2833	3
T30	11566	11337	3
T31	3866	3651	3
T32	5586	5414	3
T33	14397	14339	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	90389067	21768
T4	18812	3
T5	15956	10
T6	2062	21
T27	2027	13
T28	2233	13
T29	2976	45
T30	11566	21
T31	3866	5
T32	5586	10
T33	14397	31

Line Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_kmac_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_no_flops.OutputDelay_A	90389067	86258783	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
CONT_ASSIGN	96	1	1	100.00
ALWAYS	117	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



95                              // hence this mux can be implemented behaviorally.
96         4/4                  assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
           Tests:       T4 T5 T6  | T4 T5 T6  | T4 T5 T6  | T4 T5 T6 
97                            end
98                      
99                      // Note regarding SVAs below:
100                     //
101                     // 1) Without the sampled rst_ni pre-condition, this may cause false assertion failures right after
102                     // a reset release, since the "disable iff" condition with the rst_ni is sampled in the "observed"
103                     // SV scheduler region after all assignments have been evaluated (see also LRM section 16.12, page
104                     // 423). This is a simulation artifact due to reset synchronization in RTL, which releases rst_ni
105                     // on the active clock edge. This causes the assertion to evaluate although the reset was actually
106                     // 0 when entering this simulation cycle.
107                     //
108                     // 2) Similarly to 1) there can be sampling mismatches of the lc_en_i signal since that signal may
109                     // originate from a different clock domain. I.e., in cases where the lc_en_i signal changes exactly
110                     // at the same time that the clk_i signal rises, the SVA will not pick up that change in that clock
111                     // cycle, whereas RTL will because SVAs sample values in the "preponed" region. To that end we make
112                     // use of an RTL helper variable to sample the lc_en_i signal, hence ensuring that there are no
113                     // sampling mismatches.
114                     `ifdef INC_ASSERT
115                           mubi4_t mubi_in_sva_q;
116                           always_ff @(posedge clk_i) begin
117        1/1                  mubi_in_sva_q <= mubi_i;
           Tests:       T4 T5 T6 
118                           end
119                           `ASSERT(OutputIfUnstable_A, sig_unstable |-> mubi_o == {NumCopies{reset_value}})
120                           `ASSERT(OutputDelay_A,
121                                   rst_ni |-> ##[3:4] sig_unstable || mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}})
122                     `endif
123                         end else begin : gen_no_stable_chks
124                           assign mubi = mubi_sync;
125                     `ifdef INC_ASSERT
126                           mubi4_t mubi_in_sva_q;
127                           always_ff @(posedge clk_i) begin
128                             mubi_in_sva_q <= mubi_i;
129                           end
130                           `ASSERT(OutputDelay_A,
131                                   rst_ni |-> ##3 (mubi_o == {NumCopies{$past(mubi_in_sva_q, 2)}} ||
132                                                   $past(mubi_in_sva_q, 2) != $past(mubi_in_sva_q, 1)))
133                     `endif
134                         end
135                       end else begin : gen_no_flops
136                     
137                         //VCS coverage off
138                         // pragma coverage off
139                     
140                         // This unused companion logic helps remove lint errors
141                         // for modules where clock and reset are used for assertions only
142                         // This logic will be removed for synthesis since it is unloaded.
143                         mubi4_t unused_logic;
144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145                           if (!rst_ni) begin
146                              unused_logic <= MuBi4False;
147                           end else begin
148                              unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155                         assign mubi = MuBi4Width'(mubi_i);
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Cond Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

Branch Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00
TERNARY	96	2	2	100.00



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        -1-  
                                                        ==>  
                                                        ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



96                 assign mubi[k] = (|sig_unstable_buf) ? reset_value[k] : mubi_q[k];
                                                        
           Warning: the following expressions can not be annotated
           -1- ((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? ...;

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_idle_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_flops.gen_stable_chks.OutputDelay_A	90389067	86252572	0	2364
gen_flops.gen_stable_chks.OutputIfUnstable_A	90389067	21539	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_flops.gen_stable_chks.OutputDelay_A

Name	Attempts	Real Successes	Incomplete
Total	90389067	86252572	2364
T4	18812	18612	3
T5	15956	15742	3
T6	2062	1819	3
T27	2027	1898	3
T28	2233	1946	3
T29	2976	2833	3
T30	11566	11337	3
T31	3866	3651	3
T32	5586	5414	3
T33	14397	14339	3

gen_flops.gen_stable_chks.OutputIfUnstable_A

Name	Attempts	Real Successes
Total	90389067	21539
T4	18812	3
T5	15956	22
T6	2062	16
T27	2027	13
T28	2233	24
T29	2976	50
T30	11566	17
T31	3866	9
T32	5586	5
T33	14397	25

Line Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00



144                         always_ff @(posedge clk_i or negedge rst_ni) begin
145        unreachable        if (!rst_ni) begin
146        unreachable           unused_logic <= MuBi4False;
147                           end else begin
148        unreachable           unused_logic <= mubi_i;
149                           end
150                         end
151                     
152                         //VCS coverage on
153                         // pragma coverage on
154                     
155        1/1              assign mubi = MuBi4Width'(mubi_i);
           Tests:       T4 T5 T6 
156                     
157                         `ASSERT(OutputDelay_A, mubi_o == {NumCopies{mubi_i}})
158                       end
159                     
160                       for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
161                         logic [MuBi4Width-1:0] mubi_out;
162                         for (genvar k = 0; k < MuBi4Width; k++) begin : gen_bits
163                           prim_buf u_prim_buf (
164                             .in_i(mubi[k]),
165                             .out_o(mubi_out[k])
166                           );
167                         end
168        1/1              assign mubi_o[j] = mubi4_t'(mubi_out);
           Tests:       T4 T5 T6

Assert Coverage for Instance : tb.dut.u_clk_main_otbn_trans.u_scanmode_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	788	788	0	0
OutputsKnown_A	90389067	86258783	0	0
gen_no_flops.OutputDelay_A	90389067	86258783	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes
Total	788	788
T4	1	1
T5	1	1
T6	1	1
T27	1	1
T28	1	1
T29	1	1
T30	1	1
T31	1	1
T32	1	1
T33	1	1

OutputsKnown_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes
Total	90389067	86258783
T4	18812	18615
T5	15956	15745
T6	2062	1822
T27	2027	1901
T28	2233	1949
T29	2976	2836
T30	11566	11340
T31	3866	3654
T32	5586	5417
T33	14397	14342

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_main_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div2_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_io_div4_root_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_usb_root_ctrl