Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	283355	1		T1	1346		T2	3159		T3	1
all_values[1]	283355	1		T1	1346		T2	3159		T3	1
all_values[2]	283355	1		T1	1346		T2	3159		T3	1
all_values[3]	283355	1		T1	1346		T2	3159		T3	1
all_values[4]	283355	1		T1	1346		T2	3159		T3	1
all_values[5]	283355	1		T1	1346		T2	3159		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	572913	1		T1	2692		T2	6322		T3	6
auto[1]	1127217	1		T1	5384		T2	12632		T5	10792

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	833046	1		T1	4039		T2	9478		T3	4
auto[1]	867084	1		T1	4037		T2	9476		T3	2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	283176	1		T1	1346		T2	3159		T3	1
all_values[0]	auto[1]	auto[1]	179	1		T212	8		T213	3		T214	3
all_values[1]	auto[0]	auto[1]	283194	1		T1	1346		T2	3159		T3	1
all_values[1]	auto[1]	auto[1]	161	1		T212	4		T213	4		T214	4
all_values[2]	auto[0]	auto[0]	1588	1		T2	1		T3	1		T4	2
all_values[2]	auto[0]	auto[1]	52	1		T213	1		T320	1		T322	4
all_values[2]	auto[1]	auto[0]	281660	1		T1	1346		T2	3158		T5	2698
all_values[2]	auto[1]	auto[1]	55	1		T212	1		T213	2		T214	3
all_values[3]	auto[0]	auto[0]	1598	1		T2	1		T3	1		T4	2
all_values[3]	auto[0]	auto[1]	49	1		T212	2		T213	2		T214	2
all_values[3]	auto[1]	auto[0]	87783	1		T1	1346		T2	1579		T5	898
all_values[3]	auto[1]	auto[1]	193925	1		T2	1579		T5	1800		T31	5121
all_values[4]	auto[0]	auto[0]	1110	1		T2	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	508	1		T4	1		T16	1		T18	1
all_values[4]	auto[1]	auto[0]	176142	1		T1	1		T2	1579		T5	1798
all_values[4]	auto[1]	auto[1]	105595	1		T1	1345		T2	1579		T5	900
all_values[5]	auto[0]	auto[0]	1511	1		T2	1		T3	1		T4	2
all_values[5]	auto[0]	auto[1]	127	1		T19	5		T32	1		T34	1
all_values[5]	auto[1]	auto[0]	281654	1		T1	1346		T2	3158		T5	2698
all_values[5]	auto[1]	auto[1]	63	1		T212	3		T213	2		T319	2