Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	242278	1		T1	657		T2	687		T3	8
auto[FlashEraseBank]	267294	1		T1	688		T2	892		T3	8

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	254460	1		T2	1579		T3	15		T4	1001
auto[FlashOpProgram]	234812	1		T1	1345		T3	1		T16	352
auto[FlashOpErase]	16300	1		T16	6		T6	1		T26	9
auto[FlashOpInvalid]	4000	1		T165	200		T89	200		T90	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	254460	1		T2	1579		T3	15		T4	1001
op[FlashOpProgram]	234812	1		T1	1345		T3	1		T16	352
op[FlashOpErase]	16300	1		T16	6		T6	1		T26	9
read_erase_read	624	1		T16	1		T26	1		T27	8
read_prog_read	776	1		T3	1		T17	1		T19	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	369508	1		T1	1147		T2	1579		T3	4
auto[FlashPartInfo]	136466	1		T1	196		T3	12		T4	253
auto[FlashPartInfo1]	826	1		T5	15		T18	64		T32	3
auto[FlashPartInfo2]	2772	1		T1	2		T4	8		T5	26

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	184095	1		T2	1579		T3	4		T4	740
auto[FlashPartData]	auto[FlashOpProgram]	177676	1		T1	1147		T17	1		T18	8192
auto[FlashPartData]	auto[FlashOpErase]	3821	1		T6	1		T27	32		T23	18
auto[FlashPartData]	auto[FlashOpInvalid]	3916	1		T165	196		T89	188		T90	198
auto[FlashPartInfo]	auto[FlashOpRead]	67801	1		T3	11		T4	253		T16	13
auto[FlashPartInfo]	auto[FlashOpProgram]	56133	1		T1	196		T3	1		T16	352
auto[FlashPartInfo]	auto[FlashOpErase]	12462	1		T16	6		T26	9		T27	20
auto[FlashPartInfo]	auto[FlashOpInvalid]	70	1		T165	4		T89	8		T91	2
auto[FlashPartInfo1]	auto[FlashOpRead]	650	1		T5	15		T18	32		T32	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T18	32		T73	32		T75	1
auto[FlashPartInfo1]	auto[FlashOpErase]	5	1		T89	1		T90	1		T91	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T89	2		T90	2		T91	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1914	1		T4	8		T5	26		T18	64
auto[FlashPartInfo2]	auto[FlashOpProgram]	838	1		T1	2		T18	64		T24	1
auto[FlashPartInfo2]	auto[FlashOpErase]	12	1		T75	1		T89	1		T201	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T89	2		T406	2		T407	2