Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
85.71	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	6	26	81.25

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	6	26	81.25	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	31519	1		T27	16		T65	424		T21	32
auto[1]	10	1		T33	1		T35	1		T332	1
auto[2]	30	1		T84	4		T97	8		T333	4
auto[3]	92	1		T3	1		T22	2		T55	8

---

Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7918	1		T27	4		T22	1		T65	106
evic_idx[1]	7920	1		T27	4		T65	106		T21	8
evic_idx[2]	7909	1		T3	1		T27	4		T65	106
evic_idx[3]	7904	1		T27	4		T22	1		T65	106

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30673	1		T65	424		T21	12		T55	8
evic_op[2]	330	1		T3	1		T22	2		T33	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	6	26	81.25	6

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[1]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2
[evic_idx[2]]	[evic_op[1]]	[auto[2]]	0	1	1
[evic_idx[3]]	[evic_op[1]]	[auto[1] - auto[2]]	--	--	2

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7659	1		T65	106		T21	3		T41	187
evic_idx[0]	evic_op[1]	auto[1]	1	1		T334	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	8	1		T55	2		T335	1		T336	2
evic_idx[0]	evic_op[2]	auto[0]	63	1		T21	4		T191	1		T167	7
evic_idx[0]	evic_op[2]	auto[1]	3	1		T33	1		T163	2		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T337	3		T338	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	18	1		T22	1		T162	1		T240	1
evic_idx[1]	evic_op[1]	auto[0]	7659	1		T65	106		T21	3		T41	187
evic_idx[1]	evic_op[1]	auto[3]	10	1		T55	2		T335	1		T336	4
evic_idx[1]	evic_op[2]	auto[0]	66	1		T21	4		T156	1		T167	7
evic_idx[1]	evic_op[2]	auto[1]	3	1		T332	1		T339	1		T340	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T341	1		T337	2		T342	1
evic_idx[1]	evic_op[2]	auto[3]	16	1		T162	1		T343	1		T344	1
evic_idx[2]	evic_op[1]	auto[0]	7660	1		T65	106		T21	3		T41	187
evic_idx[2]	evic_op[1]	auto[1]	1	1		T334	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	8	1		T55	2		T336	4		T334	1
evic_idx[2]	evic_op[2]	auto[0]	61	1		T21	4		T167	7		T228	8
evic_idx[2]	evic_op[2]	auto[1]	1	1		T35	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[2]	3	1		T341	1		T337	2		-	-
evic_idx[2]	evic_op[2]	auto[3]	13	1		T3	1		T36	1		T162	1
evic_idx[3]	evic_op[1]	auto[0]	7659	1		T65	106		T21	3		T41	187
evic_idx[3]	evic_op[1]	auto[3]	8	1		T55	2		T336	4		T334	1
evic_idx[3]	evic_op[2]	auto[0]	60	1		T21	4		T167	7		T228	8
evic_idx[3]	evic_op[2]	auto[1]	1	1		T296	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T341	1		T337	2		-	-
evic_idx[3]	evic_op[2]	auto[3]	11	1		T22	1		T162	1		T240	1