Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	18050	1		T325	2349		T326	15701		-	-
rd_lvl[2]	15003	1		T325	1143		T301	1390		T327	1308
rd_lvl[3]	17111	1		T57	820		T236	1416		T290	4806
rd_lvl[4]	34225	1		T57	815		T236	5270		T328	1342
rd_lvl[5]	15041	1		T31	2603		T57	81		T236	772
rd_lvl[6]	10686	1		T31	2518		T57	171		T236	51
rd_lvl[7]	2564	1		T5	1115		T57	80		T236	51
rd_lvl[8]	14450	1		T5	681		T57	52		T236	51
rd_lvl[9]	2715	1		T5	3		T29	168		T30	143
rd_lvl[10]	9629	1		T2	1235		T5	1		T57	3
rd_lvl[11]	6099	1		T2	344		T329	313		T30	174
rd_lvl[12]	8203	1		T328	75		T29	67		T330	622
rd_lvl[13]	3269	1		T57	105		T237	680		T331	457
rd_lvl[14]	9255	1		T28	197		T237	1146		T331	1248
rd_lvl[15]	4018	1		T28	93		T330	1		T299	472