Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	283355	1		T1	1346		T2	3159		T3	1
all_pins[1]	283355	1		T1	1346		T2	3159		T3	1
all_pins[2]	283355	1		T1	1346		T2	3159		T3	1
all_pins[3]	283355	1		T1	1346		T2	3159		T3	1
all_pins[4]	283355	1		T1	1346		T2	3159		T3	1
all_pins[5]	283355	1		T1	1346		T2	3159		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1412789	1		T1	6731		T2	15796		T3	6
values[0x1]	287341	1		T1	1345		T2	3158		T5	2701
transitions[0x0=>0x1]	260617	1		T1	1345		T2	3158		T5	2698
transitions[0x1=>0x0]	260601	1		T1	1345		T2	3158		T5	2698

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283176	1		T1	1346		T2	3159		T3	1
all_pins[0]	values[0x1]	179	1		T212	8		T213	3		T214	3
all_pins[0]	transitions[0x0=>0x1]	95	1		T212	4		T214	3		T318	1
all_pins[0]	transitions[0x1=>0x0]	77	1		T213	1		T214	4		T318	3
all_pins[1]	values[0x0]	283194	1		T1	1346		T2	3159		T3	1
all_pins[1]	values[0x1]	161	1		T212	4		T213	4		T214	4
all_pins[1]	transitions[0x0=>0x1]	127	1		T212	3		T213	3		T214	3
all_pins[1]	transitions[0x1=>0x0]	1946	1		T28	52		T347	1098		T348	20
all_pins[2]	values[0x0]	281375	1		T1	1346		T2	3159		T3	1
all_pins[2]	values[0x1]	1980	1		T28	52		T347	1098		T348	20
all_pins[2]	transitions[0x0=>0x1]	48	1		T212	1		T213	2		T214	2
all_pins[2]	transitions[0x1=>0x0]	170452	1		T2	1579		T5	1800		T31	5121
all_pins[3]	values[0x0]	110971	1		T1	1346		T2	1580		T3	1
all_pins[3]	values[0x1]	172384	1		T2	1579		T5	1800		T31	5121
all_pins[3]	transitions[0x0=>0x1]	147773	1		T2	1579		T5	1797		T31	4107
all_pins[3]	transitions[0x1=>0x0]	87963	1		T1	1345		T2	1579		T5	898
all_pins[4]	values[0x0]	170781	1		T1	1		T2	1580		T3	1
all_pins[4]	values[0x1]	112574	1		T1	1345		T2	1579		T5	901
all_pins[4]	transitions[0x0=>0x1]	112554	1		T1	1345		T2	1579		T5	901
all_pins[4]	transitions[0x1=>0x0]	43	1		T212	3		T213	2		T320	1
all_pins[5]	values[0x0]	283292	1		T1	1346		T2	3159		T3	1
all_pins[5]	values[0x1]	63	1		T212	3		T213	2		T319	2
all_pins[5]	transitions[0x0=>0x1]	20	1		T319	1		T320	1		T349	1
all_pins[5]	transitions[0x1=>0x0]	120	1		T212	4		T213	1		T214	3